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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / atombios_encoders.c
1 /*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31 #include <linux/backlight.h>
32
33 extern int atom_debug;
34
35 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
36
37 static u8
38 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
39 {
40 u8 backlight_level;
41 u32 bios_2_scratch;
42
43 if (rdev->family >= CHIP_R600)
44 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
45 else
46 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
47
48 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
49 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50
51 return backlight_level;
52 }
53
54 static void
55 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
56 u8 backlight_level)
57 {
58 u32 bios_2_scratch;
59
60 if (rdev->family >= CHIP_R600)
61 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
62 else
63 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
64
65 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
66 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
67 ATOM_S2_CURRENT_BL_LEVEL_MASK);
68
69 if (rdev->family >= CHIP_R600)
70 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
71 else
72 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
73 }
74
75 void
76 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
77 {
78 struct drm_encoder *encoder = &radeon_encoder->base;
79 struct drm_device *dev = radeon_encoder->base.dev;
80 struct radeon_device *rdev = dev->dev_private;
81 struct radeon_encoder_atom_dig *dig;
82 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
83 int index;
84
85 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
86 return;
87
88 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
89 radeon_encoder->enc_priv) {
90 dig = radeon_encoder->enc_priv;
91 dig->backlight_level = level;
92 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
93
94 switch (radeon_encoder->encoder_id) {
95 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
96 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
97 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
98 if (dig->backlight_level == 0) {
99 args.ucAction = ATOM_LCD_BLOFF;
100 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
101 } else {
102 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
103 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
104 args.ucAction = ATOM_LCD_BLON;
105 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
106 }
107 break;
108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
109 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
110 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
111 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
112 if (dig->backlight_level == 0)
113 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
114 else {
115 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
116 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
117 }
118 break;
119 default:
120 break;
121 }
122 }
123 }
124
125 static u8 radeon_atom_bl_level(struct backlight_device *bd)
126 {
127 u8 level;
128
129 /* Convert brightness to hardware level */
130 if (bd->props.brightness < 0)
131 level = 0;
132 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
133 level = RADEON_MAX_BL_LEVEL;
134 else
135 level = bd->props.brightness;
136
137 return level;
138 }
139
140 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
141 {
142 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
143 struct radeon_encoder *radeon_encoder = pdata->encoder;
144
145 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
146
147 return 0;
148 }
149
150 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
151 {
152 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
153 struct radeon_encoder *radeon_encoder = pdata->encoder;
154 struct drm_device *dev = radeon_encoder->base.dev;
155 struct radeon_device *rdev = dev->dev_private;
156
157 return radeon_atom_get_backlight_level_from_reg(rdev);
158 }
159
160 static const struct backlight_ops radeon_atom_backlight_ops = {
161 .get_brightness = radeon_atom_backlight_get_brightness,
162 .update_status = radeon_atom_backlight_update_status,
163 };
164
165 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
166 struct drm_connector *drm_connector)
167 {
168 struct drm_device *dev = radeon_encoder->base.dev;
169 struct radeon_device *rdev = dev->dev_private;
170 struct backlight_device *bd;
171 struct backlight_properties props;
172 struct radeon_backlight_privdata *pdata;
173 struct radeon_encoder_atom_dig *dig;
174 u8 backlight_level;
175
176 if (!radeon_encoder->enc_priv)
177 return;
178
179 if (!rdev->is_atom_bios)
180 return;
181
182 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
183 return;
184
185 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
186 if (!pdata) {
187 DRM_ERROR("Memory allocation failed\n");
188 goto error;
189 }
190
191 memset(&props, 0, sizeof(props));
192 props.max_brightness = RADEON_MAX_BL_LEVEL;
193 props.type = BACKLIGHT_RAW;
194 bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
195 pdata, &radeon_atom_backlight_ops, &props);
196 if (IS_ERR(bd)) {
197 DRM_ERROR("Backlight registration failed\n");
198 goto error;
199 }
200
201 pdata->encoder = radeon_encoder;
202
203 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
204
205 dig = radeon_encoder->enc_priv;
206 dig->bl_dev = bd;
207
208 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
209 bd->props.power = FB_BLANK_UNBLANK;
210 backlight_update_status(bd);
211
212 DRM_INFO("radeon atom DIG backlight initialized\n");
213
214 return;
215
216 error:
217 kfree(pdata);
218 return;
219 }
220
221 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
222 {
223 struct drm_device *dev = radeon_encoder->base.dev;
224 struct radeon_device *rdev = dev->dev_private;
225 struct backlight_device *bd = NULL;
226 struct radeon_encoder_atom_dig *dig;
227
228 if (!radeon_encoder->enc_priv)
229 return;
230
231 if (!rdev->is_atom_bios)
232 return;
233
234 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
235 return;
236
237 dig = radeon_encoder->enc_priv;
238 bd = dig->bl_dev;
239 dig->bl_dev = NULL;
240
241 if (bd) {
242 struct radeon_legacy_backlight_privdata *pdata;
243
244 pdata = bl_get_data(bd);
245 backlight_device_unregister(bd);
246 kfree(pdata);
247
248 DRM_INFO("radeon atom LVDS backlight unloaded\n");
249 }
250 }
251
252 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
253
254 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
255 {
256 }
257
258 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
259 {
260 }
261
262 #endif
263
264 /* evil but including atombios.h is much worse */
265 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
266 struct drm_display_mode *mode);
267
268
269 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
270 {
271 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
272 switch (radeon_encoder->encoder_id) {
273 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
274 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
275 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
276 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
277 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
278 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
279 case ENCODER_OBJECT_ID_INTERNAL_DDI:
280 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
281 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
282 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
284 return true;
285 default:
286 return false;
287 }
288 }
289
290 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
291 const struct drm_display_mode *mode,
292 struct drm_display_mode *adjusted_mode)
293 {
294 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
295 struct drm_device *dev = encoder->dev;
296 struct radeon_device *rdev = dev->dev_private;
297
298 /* set the active encoder to connector routing */
299 radeon_encoder_set_active_device(encoder);
300 drm_mode_set_crtcinfo(adjusted_mode, 0);
301
302 /* hw bug */
303 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
304 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
305 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
306
307 /* get the native mode for LVDS */
308 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
309 radeon_panel_mode_fixup(encoder, adjusted_mode);
310
311 /* get the native mode for TV */
312 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
313 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
314 if (tv_dac) {
315 if (tv_dac->tv_std == TV_STD_NTSC ||
316 tv_dac->tv_std == TV_STD_NTSC_J ||
317 tv_dac->tv_std == TV_STD_PAL_M)
318 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
319 else
320 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
321 }
322 }
323
324 if (ASIC_IS_DCE3(rdev) &&
325 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
326 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
327 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
328 radeon_dp_set_link_config(connector, mode);
329 }
330
331 return true;
332 }
333
334 static void
335 atombios_dac_setup(struct drm_encoder *encoder, int action)
336 {
337 struct drm_device *dev = encoder->dev;
338 struct radeon_device *rdev = dev->dev_private;
339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
341 int index = 0;
342 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
343
344 memset(&args, 0, sizeof(args));
345
346 switch (radeon_encoder->encoder_id) {
347 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
348 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
349 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
350 break;
351 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
352 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
353 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
354 break;
355 }
356
357 args.ucAction = action;
358
359 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
360 args.ucDacStandard = ATOM_DAC1_PS2;
361 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
362 args.ucDacStandard = ATOM_DAC1_CV;
363 else {
364 switch (dac_info->tv_std) {
365 case TV_STD_PAL:
366 case TV_STD_PAL_M:
367 case TV_STD_SCART_PAL:
368 case TV_STD_SECAM:
369 case TV_STD_PAL_CN:
370 args.ucDacStandard = ATOM_DAC1_PAL;
371 break;
372 case TV_STD_NTSC:
373 case TV_STD_NTSC_J:
374 case TV_STD_PAL_60:
375 default:
376 args.ucDacStandard = ATOM_DAC1_NTSC;
377 break;
378 }
379 }
380 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
381
382 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
383
384 }
385
386 static void
387 atombios_tv_setup(struct drm_encoder *encoder, int action)
388 {
389 struct drm_device *dev = encoder->dev;
390 struct radeon_device *rdev = dev->dev_private;
391 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
392 TV_ENCODER_CONTROL_PS_ALLOCATION args;
393 int index = 0;
394 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
395
396 memset(&args, 0, sizeof(args));
397
398 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
399
400 args.sTVEncoder.ucAction = action;
401
402 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
403 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
404 else {
405 switch (dac_info->tv_std) {
406 case TV_STD_NTSC:
407 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
408 break;
409 case TV_STD_PAL:
410 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
411 break;
412 case TV_STD_PAL_M:
413 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
414 break;
415 case TV_STD_PAL_60:
416 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
417 break;
418 case TV_STD_NTSC_J:
419 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
420 break;
421 case TV_STD_SCART_PAL:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
423 break;
424 case TV_STD_SECAM:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
426 break;
427 case TV_STD_PAL_CN:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
429 break;
430 default:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
432 break;
433 }
434 }
435
436 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
437
438 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
439
440 }
441
442 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
443 {
444 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
445 int bpc = 8;
446
447 if (connector)
448 bpc = radeon_get_monitor_bpc(connector);
449
450 switch (bpc) {
451 case 0:
452 return PANEL_BPC_UNDEFINE;
453 case 6:
454 return PANEL_6BIT_PER_COLOR;
455 case 8:
456 default:
457 return PANEL_8BIT_PER_COLOR;
458 case 10:
459 return PANEL_10BIT_PER_COLOR;
460 case 12:
461 return PANEL_12BIT_PER_COLOR;
462 case 16:
463 return PANEL_16BIT_PER_COLOR;
464 }
465 }
466
467
468 union dvo_encoder_control {
469 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
470 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
471 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
472 };
473
474 void
475 atombios_dvo_setup(struct drm_encoder *encoder, int action)
476 {
477 struct drm_device *dev = encoder->dev;
478 struct radeon_device *rdev = dev->dev_private;
479 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
480 union dvo_encoder_control args;
481 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
482 uint8_t frev, crev;
483
484 memset(&args, 0, sizeof(args));
485
486 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
487 return;
488
489 /* some R4xx chips have the wrong frev */
490 if (rdev->family <= CHIP_RV410)
491 frev = 1;
492
493 switch (frev) {
494 case 1:
495 switch (crev) {
496 case 1:
497 /* R4xx, R5xx */
498 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
499
500 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
501 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
502
503 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
504 break;
505 case 2:
506 /* RS600/690/740 */
507 args.dvo.sDVOEncoder.ucAction = action;
508 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
509 /* DFP1, CRT1, TV1 depending on the type of port */
510 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
511
512 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
513 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
514 break;
515 case 3:
516 /* R6xx */
517 args.dvo_v3.ucAction = action;
518 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
519 args.dvo_v3.ucDVOConfig = 0; /* XXX */
520 break;
521 default:
522 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
523 break;
524 }
525 break;
526 default:
527 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
528 break;
529 }
530
531 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
532 }
533
534 union lvds_encoder_control {
535 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
536 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
537 };
538
539 void
540 atombios_digital_setup(struct drm_encoder *encoder, int action)
541 {
542 struct drm_device *dev = encoder->dev;
543 struct radeon_device *rdev = dev->dev_private;
544 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
545 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
546 union lvds_encoder_control args;
547 int index = 0;
548 int hdmi_detected = 0;
549 uint8_t frev, crev;
550
551 if (!dig)
552 return;
553
554 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
555 hdmi_detected = 1;
556
557 memset(&args, 0, sizeof(args));
558
559 switch (radeon_encoder->encoder_id) {
560 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
561 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
562 break;
563 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
564 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
565 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
566 break;
567 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
568 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
569 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
570 else
571 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
572 break;
573 }
574
575 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
576 return;
577
578 switch (frev) {
579 case 1:
580 case 2:
581 switch (crev) {
582 case 1:
583 args.v1.ucMisc = 0;
584 args.v1.ucAction = action;
585 if (hdmi_detected)
586 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
587 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
588 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
589 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
590 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
591 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
592 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
593 } else {
594 if (dig->linkb)
595 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
596 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
597 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
598 /*if (pScrn->rgbBits == 8) */
599 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
600 }
601 break;
602 case 2:
603 case 3:
604 args.v2.ucMisc = 0;
605 args.v2.ucAction = action;
606 if (crev == 3) {
607 if (dig->coherent_mode)
608 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
609 }
610 if (hdmi_detected)
611 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
612 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
613 args.v2.ucTruncate = 0;
614 args.v2.ucSpatial = 0;
615 args.v2.ucTemporal = 0;
616 args.v2.ucFRC = 0;
617 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
618 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
619 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
620 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
621 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
622 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
623 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
624 }
625 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
626 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
627 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
628 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
629 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
630 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
631 }
632 } else {
633 if (dig->linkb)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
635 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
636 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
637 }
638 break;
639 default:
640 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
641 break;
642 }
643 break;
644 default:
645 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
646 break;
647 }
648
649 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
650 }
651
652 int
653 atombios_get_encoder_mode(struct drm_encoder *encoder)
654 {
655 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
656 struct drm_connector *connector;
657 struct radeon_connector *radeon_connector;
658 struct radeon_connector_atom_dig *dig_connector;
659
660 /* dp bridges are always DP */
661 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
662 return ATOM_ENCODER_MODE_DP;
663
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
667
668 connector = radeon_get_connector_for_encoder(encoder);
669 /* if we don't have an active device yet, just use one of
670 * the connectors tied to the encoder.
671 */
672 if (!connector)
673 connector = radeon_get_connector_for_encoder_init(encoder);
674 radeon_connector = to_radeon_connector(connector);
675
676 switch (connector->connector_type) {
677 case DRM_MODE_CONNECTOR_DVII:
678 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
679 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
680 radeon_audio)
681 return ATOM_ENCODER_MODE_HDMI;
682 else if (radeon_connector->use_digital)
683 return ATOM_ENCODER_MODE_DVI;
684 else
685 return ATOM_ENCODER_MODE_CRT;
686 break;
687 case DRM_MODE_CONNECTOR_DVID:
688 case DRM_MODE_CONNECTOR_HDMIA:
689 default:
690 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
691 radeon_audio)
692 return ATOM_ENCODER_MODE_HDMI;
693 else
694 return ATOM_ENCODER_MODE_DVI;
695 break;
696 case DRM_MODE_CONNECTOR_LVDS:
697 return ATOM_ENCODER_MODE_LVDS;
698 break;
699 case DRM_MODE_CONNECTOR_DisplayPort:
700 dig_connector = radeon_connector->con_priv;
701 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
702 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
703 return ATOM_ENCODER_MODE_DP;
704 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
705 radeon_audio)
706 return ATOM_ENCODER_MODE_HDMI;
707 else
708 return ATOM_ENCODER_MODE_DVI;
709 break;
710 case DRM_MODE_CONNECTOR_eDP:
711 return ATOM_ENCODER_MODE_DP;
712 case DRM_MODE_CONNECTOR_DVIA:
713 case DRM_MODE_CONNECTOR_VGA:
714 return ATOM_ENCODER_MODE_CRT;
715 break;
716 case DRM_MODE_CONNECTOR_Composite:
717 case DRM_MODE_CONNECTOR_SVIDEO:
718 case DRM_MODE_CONNECTOR_9PinDIN:
719 /* fix me */
720 return ATOM_ENCODER_MODE_TV;
721 /*return ATOM_ENCODER_MODE_CV;*/
722 break;
723 }
724 }
725
726 /*
727 * DIG Encoder/Transmitter Setup
728 *
729 * DCE 3.0/3.1
730 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
731 * Supports up to 3 digital outputs
732 * - 2 DIG encoder blocks.
733 * DIG1 can drive UNIPHY link A or link B
734 * DIG2 can drive UNIPHY link B or LVTMA
735 *
736 * DCE 3.2
737 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
738 * Supports up to 5 digital outputs
739 * - 2 DIG encoder blocks.
740 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
741 *
742 * DCE 4.0/5.0/6.0
743 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
744 * Supports up to 6 digital outputs
745 * - 6 DIG encoder blocks.
746 * - DIG to PHY mapping is hardcoded
747 * DIG1 drives UNIPHY0 link A, A+B
748 * DIG2 drives UNIPHY0 link B
749 * DIG3 drives UNIPHY1 link A, A+B
750 * DIG4 drives UNIPHY1 link B
751 * DIG5 drives UNIPHY2 link A, A+B
752 * DIG6 drives UNIPHY2 link B
753 *
754 * DCE 4.1
755 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
756 * Supports up to 6 digital outputs
757 * - 2 DIG encoder blocks.
758 * llano
759 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
760 * ontario
761 * DIG1 drives UNIPHY0/1/2 link A
762 * DIG2 drives UNIPHY0/1/2 link B
763 *
764 * Routing
765 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
766 * Examples:
767 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
768 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
769 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
770 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
771 */
772
773 union dig_encoder_control {
774 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
775 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
776 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
777 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
778 };
779
780 void
781 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
782 {
783 struct drm_device *dev = encoder->dev;
784 struct radeon_device *rdev = dev->dev_private;
785 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
786 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
787 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
788 union dig_encoder_control args;
789 int index = 0;
790 uint8_t frev, crev;
791 int dp_clock = 0;
792 int dp_lane_count = 0;
793 int hpd_id = RADEON_HPD_NONE;
794
795 if (connector) {
796 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
797 struct radeon_connector_atom_dig *dig_connector =
798 radeon_connector->con_priv;
799
800 dp_clock = dig_connector->dp_clock;
801 dp_lane_count = dig_connector->dp_lane_count;
802 hpd_id = radeon_connector->hpd.hpd;
803 }
804
805 /* no dig encoder assigned */
806 if (dig->dig_encoder == -1)
807 return;
808
809 memset(&args, 0, sizeof(args));
810
811 if (ASIC_IS_DCE4(rdev))
812 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
813 else {
814 if (dig->dig_encoder)
815 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
816 else
817 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
818 }
819
820 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
821 return;
822
823 switch (frev) {
824 case 1:
825 switch (crev) {
826 case 1:
827 args.v1.ucAction = action;
828 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
829 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
830 args.v3.ucPanelMode = panel_mode;
831 else
832 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
833
834 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
835 args.v1.ucLaneNum = dp_lane_count;
836 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
837 args.v1.ucLaneNum = 8;
838 else
839 args.v1.ucLaneNum = 4;
840
841 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
842 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
843 switch (radeon_encoder->encoder_id) {
844 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
845 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
846 break;
847 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
848 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
849 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
850 break;
851 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
852 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
853 break;
854 }
855 if (dig->linkb)
856 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
857 else
858 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
859 break;
860 case 2:
861 case 3:
862 args.v3.ucAction = action;
863 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
864 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
865 args.v3.ucPanelMode = panel_mode;
866 else
867 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
868
869 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
870 args.v3.ucLaneNum = dp_lane_count;
871 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
872 args.v3.ucLaneNum = 8;
873 else
874 args.v3.ucLaneNum = 4;
875
876 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
877 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
878 args.v3.acConfig.ucDigSel = dig->dig_encoder;
879 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
880 break;
881 case 4:
882 args.v4.ucAction = action;
883 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
884 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
885 args.v4.ucPanelMode = panel_mode;
886 else
887 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
888
889 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
890 args.v4.ucLaneNum = dp_lane_count;
891 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
892 args.v4.ucLaneNum = 8;
893 else
894 args.v4.ucLaneNum = 4;
895
896 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
897 if (dp_clock == 270000)
898 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
899 else if (dp_clock == 540000)
900 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
901 }
902 args.v4.acConfig.ucDigSel = dig->dig_encoder;
903 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
904 if (hpd_id == RADEON_HPD_NONE)
905 args.v4.ucHPD_ID = 0;
906 else
907 args.v4.ucHPD_ID = hpd_id + 1;
908 break;
909 default:
910 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
911 break;
912 }
913 break;
914 default:
915 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
916 break;
917 }
918
919 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
920
921 }
922
923 union dig_transmitter_control {
924 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
925 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
926 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
927 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
928 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
929 };
930
931 void
932 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
933 {
934 struct drm_device *dev = encoder->dev;
935 struct radeon_device *rdev = dev->dev_private;
936 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
938 struct drm_connector *connector;
939 union dig_transmitter_control args;
940 int index = 0;
941 uint8_t frev, crev;
942 bool is_dp = false;
943 int pll_id = 0;
944 int dp_clock = 0;
945 int dp_lane_count = 0;
946 int connector_object_id = 0;
947 int igp_lane_info = 0;
948 int dig_encoder = dig->dig_encoder;
949 int hpd_id = RADEON_HPD_NONE;
950
951 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
952 connector = radeon_get_connector_for_encoder_init(encoder);
953 /* just needed to avoid bailing in the encoder check. the encoder
954 * isn't used for init
955 */
956 dig_encoder = 0;
957 } else
958 connector = radeon_get_connector_for_encoder(encoder);
959
960 if (connector) {
961 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
962 struct radeon_connector_atom_dig *dig_connector =
963 radeon_connector->con_priv;
964
965 hpd_id = radeon_connector->hpd.hpd;
966 dp_clock = dig_connector->dp_clock;
967 dp_lane_count = dig_connector->dp_lane_count;
968 connector_object_id =
969 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
970 igp_lane_info = dig_connector->igp_lane_info;
971 }
972
973 if (encoder->crtc) {
974 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
975 pll_id = radeon_crtc->pll_id;
976 }
977
978 /* no dig encoder assigned */
979 if (dig_encoder == -1)
980 return;
981
982 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
983 is_dp = true;
984
985 memset(&args, 0, sizeof(args));
986
987 switch (radeon_encoder->encoder_id) {
988 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
989 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
990 break;
991 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
992 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
993 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
994 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
995 break;
996 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
997 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
998 break;
999 }
1000
1001 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1002 return;
1003
1004 switch (frev) {
1005 case 1:
1006 switch (crev) {
1007 case 1:
1008 args.v1.ucAction = action;
1009 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1010 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1011 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1012 args.v1.asMode.ucLaneSel = lane_num;
1013 args.v1.asMode.ucLaneSet = lane_set;
1014 } else {
1015 if (is_dp)
1016 args.v1.usPixelClock =
1017 cpu_to_le16(dp_clock / 10);
1018 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1019 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1020 else
1021 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1022 }
1023
1024 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1025
1026 if (dig_encoder)
1027 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1028 else
1029 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1030
1031 if ((rdev->flags & RADEON_IS_IGP) &&
1032 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1033 if (is_dp ||
1034 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1035 if (igp_lane_info & 0x1)
1036 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1037 else if (igp_lane_info & 0x2)
1038 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1039 else if (igp_lane_info & 0x4)
1040 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1041 else if (igp_lane_info & 0x8)
1042 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1043 } else {
1044 if (igp_lane_info & 0x3)
1045 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1046 else if (igp_lane_info & 0xc)
1047 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1048 }
1049 }
1050
1051 if (dig->linkb)
1052 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1053 else
1054 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1055
1056 if (is_dp)
1057 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1058 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1059 if (dig->coherent_mode)
1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1061 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1063 }
1064 break;
1065 case 2:
1066 args.v2.ucAction = action;
1067 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1068 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1069 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1070 args.v2.asMode.ucLaneSel = lane_num;
1071 args.v2.asMode.ucLaneSet = lane_set;
1072 } else {
1073 if (is_dp)
1074 args.v2.usPixelClock =
1075 cpu_to_le16(dp_clock / 10);
1076 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1077 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1078 else
1079 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1080 }
1081
1082 args.v2.acConfig.ucEncoderSel = dig_encoder;
1083 if (dig->linkb)
1084 args.v2.acConfig.ucLinkSel = 1;
1085
1086 switch (radeon_encoder->encoder_id) {
1087 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1088 args.v2.acConfig.ucTransmitterSel = 0;
1089 break;
1090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1091 args.v2.acConfig.ucTransmitterSel = 1;
1092 break;
1093 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1094 args.v2.acConfig.ucTransmitterSel = 2;
1095 break;
1096 }
1097
1098 if (is_dp) {
1099 args.v2.acConfig.fCoherentMode = 1;
1100 args.v2.acConfig.fDPConnector = 1;
1101 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1102 if (dig->coherent_mode)
1103 args.v2.acConfig.fCoherentMode = 1;
1104 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1105 args.v2.acConfig.fDualLinkConnector = 1;
1106 }
1107 break;
1108 case 3:
1109 args.v3.ucAction = action;
1110 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1111 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1112 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1113 args.v3.asMode.ucLaneSel = lane_num;
1114 args.v3.asMode.ucLaneSet = lane_set;
1115 } else {
1116 if (is_dp)
1117 args.v3.usPixelClock =
1118 cpu_to_le16(dp_clock / 10);
1119 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1120 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1121 else
1122 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1123 }
1124
1125 if (is_dp)
1126 args.v3.ucLaneNum = dp_lane_count;
1127 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1128 args.v3.ucLaneNum = 8;
1129 else
1130 args.v3.ucLaneNum = 4;
1131
1132 if (dig->linkb)
1133 args.v3.acConfig.ucLinkSel = 1;
1134 if (dig_encoder & 1)
1135 args.v3.acConfig.ucEncoderSel = 1;
1136
1137 /* Select the PLL for the PHY
1138 * DP PHY should be clocked from external src if there is
1139 * one.
1140 */
1141 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1142 if (is_dp && rdev->clock.dp_extclk)
1143 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1144 else
1145 args.v3.acConfig.ucRefClkSource = pll_id;
1146
1147 switch (radeon_encoder->encoder_id) {
1148 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1149 args.v3.acConfig.ucTransmitterSel = 0;
1150 break;
1151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1152 args.v3.acConfig.ucTransmitterSel = 1;
1153 break;
1154 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1155 args.v3.acConfig.ucTransmitterSel = 2;
1156 break;
1157 }
1158
1159 if (is_dp)
1160 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1161 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1162 if (dig->coherent_mode)
1163 args.v3.acConfig.fCoherentMode = 1;
1164 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1165 args.v3.acConfig.fDualLinkConnector = 1;
1166 }
1167 break;
1168 case 4:
1169 args.v4.ucAction = action;
1170 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1171 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1172 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1173 args.v4.asMode.ucLaneSel = lane_num;
1174 args.v4.asMode.ucLaneSet = lane_set;
1175 } else {
1176 if (is_dp)
1177 args.v4.usPixelClock =
1178 cpu_to_le16(dp_clock / 10);
1179 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1180 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1181 else
1182 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1183 }
1184
1185 if (is_dp)
1186 args.v4.ucLaneNum = dp_lane_count;
1187 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1188 args.v4.ucLaneNum = 8;
1189 else
1190 args.v4.ucLaneNum = 4;
1191
1192 if (dig->linkb)
1193 args.v4.acConfig.ucLinkSel = 1;
1194 if (dig_encoder & 1)
1195 args.v4.acConfig.ucEncoderSel = 1;
1196
1197 /* Select the PLL for the PHY
1198 * DP PHY should be clocked from external src if there is
1199 * one.
1200 */
1201 /* On DCE5 DCPLL usually generates the DP ref clock */
1202 if (is_dp) {
1203 if (rdev->clock.dp_extclk)
1204 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1205 else
1206 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1207 } else
1208 args.v4.acConfig.ucRefClkSource = pll_id;
1209
1210 switch (radeon_encoder->encoder_id) {
1211 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1212 args.v4.acConfig.ucTransmitterSel = 0;
1213 break;
1214 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1215 args.v4.acConfig.ucTransmitterSel = 1;
1216 break;
1217 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1218 args.v4.acConfig.ucTransmitterSel = 2;
1219 break;
1220 }
1221
1222 if (is_dp)
1223 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1224 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1225 if (dig->coherent_mode)
1226 args.v4.acConfig.fCoherentMode = 1;
1227 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1228 args.v4.acConfig.fDualLinkConnector = 1;
1229 }
1230 break;
1231 case 5:
1232 args.v5.ucAction = action;
1233 if (is_dp)
1234 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1235 else
1236 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1237
1238 switch (radeon_encoder->encoder_id) {
1239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1240 if (dig->linkb)
1241 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1242 else
1243 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1244 break;
1245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1246 if (dig->linkb)
1247 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1248 else
1249 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1250 break;
1251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1252 if (dig->linkb)
1253 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1254 else
1255 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1256 break;
1257 }
1258 if (is_dp)
1259 args.v5.ucLaneNum = dp_lane_count;
1260 else if (radeon_encoder->pixel_clock > 165000)
1261 args.v5.ucLaneNum = 8;
1262 else
1263 args.v5.ucLaneNum = 4;
1264 args.v5.ucConnObjId = connector_object_id;
1265 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1266
1267 if (is_dp && rdev->clock.dp_extclk)
1268 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1269 else
1270 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1271
1272 if (is_dp)
1273 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1274 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1275 if (dig->coherent_mode)
1276 args.v5.asConfig.ucCoherentMode = 1;
1277 }
1278 if (hpd_id == RADEON_HPD_NONE)
1279 args.v5.asConfig.ucHPDSel = 0;
1280 else
1281 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1282 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1283 args.v5.ucDPLaneSet = lane_set;
1284 break;
1285 default:
1286 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1287 break;
1288 }
1289 break;
1290 default:
1291 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1292 break;
1293 }
1294
1295 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1296 }
1297
1298 bool
1299 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1300 {
1301 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1302 struct drm_device *dev = radeon_connector->base.dev;
1303 struct radeon_device *rdev = dev->dev_private;
1304 union dig_transmitter_control args;
1305 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1306 uint8_t frev, crev;
1307
1308 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1309 goto done;
1310
1311 if (!ASIC_IS_DCE4(rdev))
1312 goto done;
1313
1314 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1315 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1316 goto done;
1317
1318 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1319 goto done;
1320
1321 memset(&args, 0, sizeof(args));
1322
1323 args.v1.ucAction = action;
1324
1325 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1326
1327 /* wait for the panel to power up */
1328 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1329 int i;
1330
1331 for (i = 0; i < 300; i++) {
1332 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1333 return true;
1334 mdelay(1);
1335 }
1336 return false;
1337 }
1338 done:
1339 return true;
1340 }
1341
1342 union external_encoder_control {
1343 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1344 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1345 };
1346
1347 static void
1348 atombios_external_encoder_setup(struct drm_encoder *encoder,
1349 struct drm_encoder *ext_encoder,
1350 int action)
1351 {
1352 struct drm_device *dev = encoder->dev;
1353 struct radeon_device *rdev = dev->dev_private;
1354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1355 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1356 union external_encoder_control args;
1357 struct drm_connector *connector;
1358 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1359 u8 frev, crev;
1360 int dp_clock = 0;
1361 int dp_lane_count = 0;
1362 int connector_object_id = 0;
1363 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1364
1365 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1366 connector = radeon_get_connector_for_encoder_init(encoder);
1367 else
1368 connector = radeon_get_connector_for_encoder(encoder);
1369
1370 if (connector) {
1371 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1372 struct radeon_connector_atom_dig *dig_connector =
1373 radeon_connector->con_priv;
1374
1375 dp_clock = dig_connector->dp_clock;
1376 dp_lane_count = dig_connector->dp_lane_count;
1377 connector_object_id =
1378 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1379 }
1380
1381 memset(&args, 0, sizeof(args));
1382
1383 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1384 return;
1385
1386 switch (frev) {
1387 case 1:
1388 /* no params on frev 1 */
1389 break;
1390 case 2:
1391 switch (crev) {
1392 case 1:
1393 case 2:
1394 args.v1.sDigEncoder.ucAction = action;
1395 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1396 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1397
1398 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1399 if (dp_clock == 270000)
1400 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1401 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1402 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1403 args.v1.sDigEncoder.ucLaneNum = 8;
1404 else
1405 args.v1.sDigEncoder.ucLaneNum = 4;
1406 break;
1407 case 3:
1408 args.v3.sExtEncoder.ucAction = action;
1409 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1410 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1411 else
1412 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1413 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1414
1415 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1416 if (dp_clock == 270000)
1417 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1418 else if (dp_clock == 540000)
1419 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1420 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1421 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1422 args.v3.sExtEncoder.ucLaneNum = 8;
1423 else
1424 args.v3.sExtEncoder.ucLaneNum = 4;
1425 switch (ext_enum) {
1426 case GRAPH_OBJECT_ENUM_ID1:
1427 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1428 break;
1429 case GRAPH_OBJECT_ENUM_ID2:
1430 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1431 break;
1432 case GRAPH_OBJECT_ENUM_ID3:
1433 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1434 break;
1435 }
1436 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1437 break;
1438 default:
1439 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1440 return;
1441 }
1442 break;
1443 default:
1444 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1445 return;
1446 }
1447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1448 }
1449
1450 static void
1451 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1452 {
1453 struct drm_device *dev = encoder->dev;
1454 struct radeon_device *rdev = dev->dev_private;
1455 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1456 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1457 ENABLE_YUV_PS_ALLOCATION args;
1458 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1459 uint32_t temp, reg;
1460
1461 memset(&args, 0, sizeof(args));
1462
1463 if (rdev->family >= CHIP_R600)
1464 reg = R600_BIOS_3_SCRATCH;
1465 else
1466 reg = RADEON_BIOS_3_SCRATCH;
1467
1468 /* XXX: fix up scratch reg handling */
1469 temp = RREG32(reg);
1470 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1471 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1472 (radeon_crtc->crtc_id << 18)));
1473 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1474 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1475 else
1476 WREG32(reg, 0);
1477
1478 if (enable)
1479 args.ucEnable = ATOM_ENABLE;
1480 args.ucCRTC = radeon_crtc->crtc_id;
1481
1482 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1483
1484 WREG32(reg, temp);
1485 }
1486
1487 static void
1488 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1489 {
1490 struct drm_device *dev = encoder->dev;
1491 struct radeon_device *rdev = dev->dev_private;
1492 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1493 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1494 int index = 0;
1495
1496 memset(&args, 0, sizeof(args));
1497
1498 switch (radeon_encoder->encoder_id) {
1499 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1500 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1501 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1502 break;
1503 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1504 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1505 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1506 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1507 break;
1508 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1509 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1510 break;
1511 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1512 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1513 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1514 else
1515 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1516 break;
1517 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1518 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1519 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1520 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1521 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1522 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1523 else
1524 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1525 break;
1526 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1527 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1528 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1529 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1530 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1531 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1532 else
1533 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1534 break;
1535 default:
1536 return;
1537 }
1538
1539 switch (mode) {
1540 case DRM_MODE_DPMS_ON:
1541 args.ucAction = ATOM_ENABLE;
1542 /* workaround for DVOOutputControl on some RS690 systems */
1543 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1544 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1545 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1546 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1547 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1548 } else
1549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1550 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1551 args.ucAction = ATOM_LCD_BLON;
1552 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1553 }
1554 break;
1555 case DRM_MODE_DPMS_STANDBY:
1556 case DRM_MODE_DPMS_SUSPEND:
1557 case DRM_MODE_DPMS_OFF:
1558 args.ucAction = ATOM_DISABLE;
1559 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1561 args.ucAction = ATOM_LCD_BLOFF;
1562 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1563 }
1564 break;
1565 }
1566 }
1567
1568 static void
1569 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1570 {
1571 struct drm_device *dev = encoder->dev;
1572 struct radeon_device *rdev = dev->dev_private;
1573 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1574 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1575 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1576 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1577 struct radeon_connector *radeon_connector = NULL;
1578 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1579
1580 if (connector) {
1581 radeon_connector = to_radeon_connector(connector);
1582 radeon_dig_connector = radeon_connector->con_priv;
1583 }
1584
1585 switch (mode) {
1586 case DRM_MODE_DPMS_ON:
1587 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1588 if (!connector)
1589 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1590 else
1591 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1592
1593 /* setup and enable the encoder */
1594 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1595 atombios_dig_encoder_setup(encoder,
1596 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1597 dig->panel_mode);
1598 if (ext_encoder) {
1599 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1600 atombios_external_encoder_setup(encoder, ext_encoder,
1601 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1602 }
1603 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1604 } else if (ASIC_IS_DCE4(rdev)) {
1605 /* setup and enable the encoder */
1606 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1607 /* enable the transmitter */
1608 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1609 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1610 } else {
1611 /* setup and enable the encoder and transmitter */
1612 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1613 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1614 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1615 /* some early dce3.2 boards have a bug in their transmitter control table */
1616 if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1617 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1618 }
1619 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1620 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1621 atombios_set_edp_panel_power(connector,
1622 ATOM_TRANSMITTER_ACTION_POWER_ON);
1623 radeon_dig_connector->edp_on = true;
1624 }
1625 radeon_dp_link_train(encoder, connector);
1626 if (ASIC_IS_DCE4(rdev))
1627 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1628 }
1629 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1630 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1631 break;
1632 case DRM_MODE_DPMS_STANDBY:
1633 case DRM_MODE_DPMS_SUSPEND:
1634 case DRM_MODE_DPMS_OFF:
1635 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1636 /* disable the transmitter */
1637 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1638 } else if (ASIC_IS_DCE4(rdev)) {
1639 /* disable the transmitter */
1640 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1641 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1642 } else {
1643 /* disable the encoder and transmitter */
1644 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1645 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1646 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1647 }
1648 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1649 if (ASIC_IS_DCE4(rdev))
1650 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1651 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1652 atombios_set_edp_panel_power(connector,
1653 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1654 radeon_dig_connector->edp_on = false;
1655 }
1656 }
1657 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1658 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1659 break;
1660 }
1661 }
1662
1663 static void
1664 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1665 struct drm_encoder *ext_encoder,
1666 int mode)
1667 {
1668 struct drm_device *dev = encoder->dev;
1669 struct radeon_device *rdev = dev->dev_private;
1670
1671 switch (mode) {
1672 case DRM_MODE_DPMS_ON:
1673 default:
1674 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1675 atombios_external_encoder_setup(encoder, ext_encoder,
1676 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1677 atombios_external_encoder_setup(encoder, ext_encoder,
1678 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1679 } else
1680 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1681 break;
1682 case DRM_MODE_DPMS_STANDBY:
1683 case DRM_MODE_DPMS_SUSPEND:
1684 case DRM_MODE_DPMS_OFF:
1685 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1686 atombios_external_encoder_setup(encoder, ext_encoder,
1687 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1688 atombios_external_encoder_setup(encoder, ext_encoder,
1689 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1690 } else
1691 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1692 break;
1693 }
1694 }
1695
1696 static void
1697 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1698 {
1699 struct drm_device *dev = encoder->dev;
1700 struct radeon_device *rdev = dev->dev_private;
1701 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1702 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1703
1704 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1705 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1706 radeon_encoder->active_device);
1707 switch (radeon_encoder->encoder_id) {
1708 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1709 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1710 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1711 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1712 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1713 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1714 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1715 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1716 radeon_atom_encoder_dpms_avivo(encoder, mode);
1717 break;
1718 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1719 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1720 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1721 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1722 radeon_atom_encoder_dpms_dig(encoder, mode);
1723 break;
1724 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1725 if (ASIC_IS_DCE5(rdev)) {
1726 switch (mode) {
1727 case DRM_MODE_DPMS_ON:
1728 atombios_dvo_setup(encoder, ATOM_ENABLE);
1729 break;
1730 case DRM_MODE_DPMS_STANDBY:
1731 case DRM_MODE_DPMS_SUSPEND:
1732 case DRM_MODE_DPMS_OFF:
1733 atombios_dvo_setup(encoder, ATOM_DISABLE);
1734 break;
1735 }
1736 } else if (ASIC_IS_DCE3(rdev))
1737 radeon_atom_encoder_dpms_dig(encoder, mode);
1738 else
1739 radeon_atom_encoder_dpms_avivo(encoder, mode);
1740 break;
1741 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1742 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1743 if (ASIC_IS_DCE5(rdev)) {
1744 switch (mode) {
1745 case DRM_MODE_DPMS_ON:
1746 atombios_dac_setup(encoder, ATOM_ENABLE);
1747 break;
1748 case DRM_MODE_DPMS_STANDBY:
1749 case DRM_MODE_DPMS_SUSPEND:
1750 case DRM_MODE_DPMS_OFF:
1751 atombios_dac_setup(encoder, ATOM_DISABLE);
1752 break;
1753 }
1754 } else
1755 radeon_atom_encoder_dpms_avivo(encoder, mode);
1756 break;
1757 default:
1758 return;
1759 }
1760
1761 if (ext_encoder)
1762 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1763
1764 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1765
1766 }
1767
1768 union crtc_source_param {
1769 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1770 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1771 };
1772
1773 static void
1774 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1775 {
1776 struct drm_device *dev = encoder->dev;
1777 struct radeon_device *rdev = dev->dev_private;
1778 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1779 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1780 union crtc_source_param args;
1781 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1782 uint8_t frev, crev;
1783 struct radeon_encoder_atom_dig *dig;
1784
1785 memset(&args, 0, sizeof(args));
1786
1787 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1788 return;
1789
1790 switch (frev) {
1791 case 1:
1792 switch (crev) {
1793 case 1:
1794 default:
1795 if (ASIC_IS_AVIVO(rdev))
1796 args.v1.ucCRTC = radeon_crtc->crtc_id;
1797 else {
1798 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1799 args.v1.ucCRTC = radeon_crtc->crtc_id;
1800 } else {
1801 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1802 }
1803 }
1804 switch (radeon_encoder->encoder_id) {
1805 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1806 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1807 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1808 break;
1809 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1810 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1811 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1812 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1813 else
1814 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1815 break;
1816 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1817 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1818 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1819 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1820 break;
1821 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1822 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1823 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1824 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1825 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1826 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1827 else
1828 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1829 break;
1830 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1831 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1832 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1833 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1834 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1835 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1836 else
1837 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1838 break;
1839 }
1840 break;
1841 case 2:
1842 args.v2.ucCRTC = radeon_crtc->crtc_id;
1843 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1844 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1845
1846 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1847 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1848 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1849 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1850 else
1851 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1852 } else
1853 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1854 switch (radeon_encoder->encoder_id) {
1855 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1856 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1857 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1858 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1859 dig = radeon_encoder->enc_priv;
1860 switch (dig->dig_encoder) {
1861 case 0:
1862 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1863 break;
1864 case 1:
1865 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1866 break;
1867 case 2:
1868 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1869 break;
1870 case 3:
1871 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1872 break;
1873 case 4:
1874 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1875 break;
1876 case 5:
1877 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1878 break;
1879 }
1880 break;
1881 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1882 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1883 break;
1884 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1885 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1886 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1887 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1888 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1889 else
1890 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1891 break;
1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1893 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1894 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1895 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1896 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1897 else
1898 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1899 break;
1900 }
1901 break;
1902 }
1903 break;
1904 default:
1905 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1906 return;
1907 }
1908
1909 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1910
1911 /* update scratch regs with new routing */
1912 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1913 }
1914
1915 static void
1916 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1917 struct drm_display_mode *mode)
1918 {
1919 struct drm_device *dev = encoder->dev;
1920 struct radeon_device *rdev = dev->dev_private;
1921 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1922 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1923
1924 /* Funky macbooks */
1925 if ((dev->pdev->device == 0x71C5) &&
1926 (dev->pdev->subsystem_vendor == 0x106b) &&
1927 (dev->pdev->subsystem_device == 0x0080)) {
1928 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1929 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1930
1931 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1932 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1933
1934 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1935 }
1936 }
1937
1938 /* set scaler clears this on some chips */
1939 if (ASIC_IS_AVIVO(rdev) &&
1940 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1941 if (ASIC_IS_DCE4(rdev)) {
1942 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1943 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1944 EVERGREEN_INTERLEAVE_EN);
1945 else
1946 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1947 } else {
1948 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1949 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1950 AVIVO_D1MODE_INTERLEAVE_EN);
1951 else
1952 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1953 }
1954 }
1955 }
1956
1957 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1958 {
1959 struct drm_device *dev = encoder->dev;
1960 struct radeon_device *rdev = dev->dev_private;
1961 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1962 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1963 struct drm_encoder *test_encoder;
1964 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1965 uint32_t dig_enc_in_use = 0;
1966
1967 if (ASIC_IS_DCE6(rdev)) {
1968 /* DCE6 */
1969 switch (radeon_encoder->encoder_id) {
1970 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1971 if (dig->linkb)
1972 return 1;
1973 else
1974 return 0;
1975 break;
1976 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1977 if (dig->linkb)
1978 return 3;
1979 else
1980 return 2;
1981 break;
1982 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1983 if (dig->linkb)
1984 return 5;
1985 else
1986 return 4;
1987 break;
1988 }
1989 } else if (ASIC_IS_DCE4(rdev)) {
1990 /* DCE4/5 */
1991 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
1992 /* ontario follows DCE4 */
1993 if (rdev->family == CHIP_PALM) {
1994 if (dig->linkb)
1995 return 1;
1996 else
1997 return 0;
1998 } else
1999 /* llano follows DCE3.2 */
2000 return radeon_crtc->crtc_id;
2001 } else {
2002 switch (radeon_encoder->encoder_id) {
2003 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2004 if (dig->linkb)
2005 return 1;
2006 else
2007 return 0;
2008 break;
2009 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2010 if (dig->linkb)
2011 return 3;
2012 else
2013 return 2;
2014 break;
2015 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2016 if (dig->linkb)
2017 return 5;
2018 else
2019 return 4;
2020 break;
2021 }
2022 }
2023 }
2024
2025 /* on DCE32 and encoder can driver any block so just crtc id */
2026 if (ASIC_IS_DCE32(rdev)) {
2027 return radeon_crtc->crtc_id;
2028 }
2029
2030 /* on DCE3 - LVTMA can only be driven by DIGB */
2031 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2032 struct radeon_encoder *radeon_test_encoder;
2033
2034 if (encoder == test_encoder)
2035 continue;
2036
2037 if (!radeon_encoder_is_digital(test_encoder))
2038 continue;
2039
2040 radeon_test_encoder = to_radeon_encoder(test_encoder);
2041 dig = radeon_test_encoder->enc_priv;
2042
2043 if (dig->dig_encoder >= 0)
2044 dig_enc_in_use |= (1 << dig->dig_encoder);
2045 }
2046
2047 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2048 if (dig_enc_in_use & 0x2)
2049 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2050 return 1;
2051 }
2052 if (!(dig_enc_in_use & 1))
2053 return 0;
2054 return 1;
2055 }
2056
2057 /* This only needs to be called once at startup */
2058 void
2059 radeon_atom_encoder_init(struct radeon_device *rdev)
2060 {
2061 struct drm_device *dev = rdev->ddev;
2062 struct drm_encoder *encoder;
2063
2064 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2065 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2066 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2067
2068 switch (radeon_encoder->encoder_id) {
2069 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2070 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2071 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2072 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2073 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2074 break;
2075 default:
2076 break;
2077 }
2078
2079 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2080 atombios_external_encoder_setup(encoder, ext_encoder,
2081 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2082 }
2083 }
2084
2085 static void
2086 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2087 struct drm_display_mode *mode,
2088 struct drm_display_mode *adjusted_mode)
2089 {
2090 struct drm_device *dev = encoder->dev;
2091 struct radeon_device *rdev = dev->dev_private;
2092 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2093
2094 radeon_encoder->pixel_clock = adjusted_mode->clock;
2095
2096 /* need to call this here rather than in prepare() since we need some crtc info */
2097 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2098
2099 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2100 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2101 atombios_yuv_setup(encoder, true);
2102 else
2103 atombios_yuv_setup(encoder, false);
2104 }
2105
2106 switch (radeon_encoder->encoder_id) {
2107 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2108 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2109 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2110 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2111 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2112 break;
2113 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2114 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2115 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2116 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2117 /* handled in dpms */
2118 break;
2119 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2120 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2121 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2122 atombios_dvo_setup(encoder, ATOM_ENABLE);
2123 break;
2124 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2126 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2128 atombios_dac_setup(encoder, ATOM_ENABLE);
2129 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2130 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2131 atombios_tv_setup(encoder, ATOM_ENABLE);
2132 else
2133 atombios_tv_setup(encoder, ATOM_DISABLE);
2134 }
2135 break;
2136 }
2137
2138 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2139
2140 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2141 r600_hdmi_enable(encoder);
2142 if (ASIC_IS_DCE6(rdev))
2143 ; /* TODO (use pointers instead of if-s?) */
2144 else if (ASIC_IS_DCE4(rdev))
2145 evergreen_hdmi_setmode(encoder, adjusted_mode);
2146 else
2147 r600_hdmi_setmode(encoder, adjusted_mode);
2148 }
2149 }
2150
2151 static bool
2152 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2153 {
2154 struct drm_device *dev = encoder->dev;
2155 struct radeon_device *rdev = dev->dev_private;
2156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2157 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2158
2159 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2160 ATOM_DEVICE_CV_SUPPORT |
2161 ATOM_DEVICE_CRT_SUPPORT)) {
2162 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2163 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2164 uint8_t frev, crev;
2165
2166 memset(&args, 0, sizeof(args));
2167
2168 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2169 return false;
2170
2171 args.sDacload.ucMisc = 0;
2172
2173 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2174 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2175 args.sDacload.ucDacType = ATOM_DAC_A;
2176 else
2177 args.sDacload.ucDacType = ATOM_DAC_B;
2178
2179 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2180 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2181 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2182 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2183 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2184 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2185 if (crev >= 3)
2186 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2187 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2188 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2189 if (crev >= 3)
2190 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2191 }
2192
2193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2194
2195 return true;
2196 } else
2197 return false;
2198 }
2199
2200 static enum drm_connector_status
2201 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2202 {
2203 struct drm_device *dev = encoder->dev;
2204 struct radeon_device *rdev = dev->dev_private;
2205 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2206 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2207 uint32_t bios_0_scratch;
2208
2209 if (!atombios_dac_load_detect(encoder, connector)) {
2210 DRM_DEBUG_KMS("detect returned false \n");
2211 return connector_status_unknown;
2212 }
2213
2214 if (rdev->family >= CHIP_R600)
2215 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2216 else
2217 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2218
2219 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2220 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2221 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2222 return connector_status_connected;
2223 }
2224 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2225 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2226 return connector_status_connected;
2227 }
2228 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2229 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2230 return connector_status_connected;
2231 }
2232 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2233 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2234 return connector_status_connected; /* CTV */
2235 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2236 return connector_status_connected; /* STV */
2237 }
2238 return connector_status_disconnected;
2239 }
2240
2241 static enum drm_connector_status
2242 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2243 {
2244 struct drm_device *dev = encoder->dev;
2245 struct radeon_device *rdev = dev->dev_private;
2246 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2247 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2248 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2249 u32 bios_0_scratch;
2250
2251 if (!ASIC_IS_DCE4(rdev))
2252 return connector_status_unknown;
2253
2254 if (!ext_encoder)
2255 return connector_status_unknown;
2256
2257 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2258 return connector_status_unknown;
2259
2260 /* load detect on the dp bridge */
2261 atombios_external_encoder_setup(encoder, ext_encoder,
2262 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2263
2264 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2265
2266 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2267 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2268 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2269 return connector_status_connected;
2270 }
2271 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2272 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2273 return connector_status_connected;
2274 }
2275 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2276 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2277 return connector_status_connected;
2278 }
2279 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2280 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2281 return connector_status_connected; /* CTV */
2282 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2283 return connector_status_connected; /* STV */
2284 }
2285 return connector_status_disconnected;
2286 }
2287
2288 void
2289 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2290 {
2291 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2292
2293 if (ext_encoder)
2294 /* ddc_setup on the dp bridge */
2295 atombios_external_encoder_setup(encoder, ext_encoder,
2296 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2297
2298 }
2299
2300 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2301 {
2302 struct radeon_device *rdev = encoder->dev->dev_private;
2303 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2304 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2305
2306 if ((radeon_encoder->active_device &
2307 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2308 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2309 ENCODER_OBJECT_ID_NONE)) {
2310 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2311 if (dig) {
2312 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2313 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2314 if (rdev->family >= CHIP_R600)
2315 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2316 else
2317 /* RS600/690/740 have only 1 afmt block */
2318 dig->afmt = rdev->mode_info.afmt[0];
2319 }
2320 }
2321 }
2322
2323 radeon_atom_output_lock(encoder, true);
2324
2325 if (connector) {
2326 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2327
2328 /* select the clock/data port if it uses a router */
2329 if (radeon_connector->router.cd_valid)
2330 radeon_router_select_cd_port(radeon_connector);
2331
2332 /* turn eDP panel on for mode set */
2333 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2334 atombios_set_edp_panel_power(connector,
2335 ATOM_TRANSMITTER_ACTION_POWER_ON);
2336 }
2337
2338 /* this is needed for the pll/ss setup to work correctly in some cases */
2339 atombios_set_encoder_crtc_source(encoder);
2340 }
2341
2342 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2343 {
2344 /* need to call this here as we need the crtc set up */
2345 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2346 radeon_atom_output_lock(encoder, false);
2347 }
2348
2349 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2350 {
2351 struct drm_device *dev = encoder->dev;
2352 struct radeon_device *rdev = dev->dev_private;
2353 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2354 struct radeon_encoder_atom_dig *dig;
2355
2356 /* check for pre-DCE3 cards with shared encoders;
2357 * can't really use the links individually, so don't disable
2358 * the encoder if it's in use by another connector
2359 */
2360 if (!ASIC_IS_DCE3(rdev)) {
2361 struct drm_encoder *other_encoder;
2362 struct radeon_encoder *other_radeon_encoder;
2363
2364 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2365 other_radeon_encoder = to_radeon_encoder(other_encoder);
2366 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2367 drm_helper_encoder_in_use(other_encoder))
2368 goto disable_done;
2369 }
2370 }
2371
2372 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2373
2374 switch (radeon_encoder->encoder_id) {
2375 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2376 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2377 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2378 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2379 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2380 break;
2381 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2383 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2385 /* handled in dpms */
2386 break;
2387 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2388 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2389 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2390 atombios_dvo_setup(encoder, ATOM_DISABLE);
2391 break;
2392 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2394 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2395 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2396 atombios_dac_setup(encoder, ATOM_DISABLE);
2397 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2398 atombios_tv_setup(encoder, ATOM_DISABLE);
2399 break;
2400 }
2401
2402 disable_done:
2403 if (radeon_encoder_is_digital(encoder)) {
2404 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2405 r600_hdmi_disable(encoder);
2406 dig = radeon_encoder->enc_priv;
2407 dig->dig_encoder = -1;
2408 }
2409 radeon_encoder->active_device = 0;
2410 }
2411
2412 /* these are handled by the primary encoders */
2413 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2414 {
2415
2416 }
2417
2418 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2419 {
2420
2421 }
2422
2423 static void
2424 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2425 struct drm_display_mode *mode,
2426 struct drm_display_mode *adjusted_mode)
2427 {
2428
2429 }
2430
2431 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2432 {
2433
2434 }
2435
2436 static void
2437 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2438 {
2439
2440 }
2441
2442 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2443 const struct drm_display_mode *mode,
2444 struct drm_display_mode *adjusted_mode)
2445 {
2446 return true;
2447 }
2448
2449 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2450 .dpms = radeon_atom_ext_dpms,
2451 .mode_fixup = radeon_atom_ext_mode_fixup,
2452 .prepare = radeon_atom_ext_prepare,
2453 .mode_set = radeon_atom_ext_mode_set,
2454 .commit = radeon_atom_ext_commit,
2455 .disable = radeon_atom_ext_disable,
2456 /* no detect for TMDS/LVDS yet */
2457 };
2458
2459 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2460 .dpms = radeon_atom_encoder_dpms,
2461 .mode_fixup = radeon_atom_mode_fixup,
2462 .prepare = radeon_atom_encoder_prepare,
2463 .mode_set = radeon_atom_encoder_mode_set,
2464 .commit = radeon_atom_encoder_commit,
2465 .disable = radeon_atom_encoder_disable,
2466 .detect = radeon_atom_dig_detect,
2467 };
2468
2469 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2470 .dpms = radeon_atom_encoder_dpms,
2471 .mode_fixup = radeon_atom_mode_fixup,
2472 .prepare = radeon_atom_encoder_prepare,
2473 .mode_set = radeon_atom_encoder_mode_set,
2474 .commit = radeon_atom_encoder_commit,
2475 .detect = radeon_atom_dac_detect,
2476 };
2477
2478 void radeon_enc_destroy(struct drm_encoder *encoder)
2479 {
2480 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2481 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2482 radeon_atom_backlight_exit(radeon_encoder);
2483 kfree(radeon_encoder->enc_priv);
2484 drm_encoder_cleanup(encoder);
2485 kfree(radeon_encoder);
2486 }
2487
2488 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2489 .destroy = radeon_enc_destroy,
2490 };
2491
2492 static struct radeon_encoder_atom_dac *
2493 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2494 {
2495 struct drm_device *dev = radeon_encoder->base.dev;
2496 struct radeon_device *rdev = dev->dev_private;
2497 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2498
2499 if (!dac)
2500 return NULL;
2501
2502 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2503 return dac;
2504 }
2505
2506 static struct radeon_encoder_atom_dig *
2507 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2508 {
2509 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2510 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2511
2512 if (!dig)
2513 return NULL;
2514
2515 /* coherent mode by default */
2516 dig->coherent_mode = true;
2517 dig->dig_encoder = -1;
2518
2519 if (encoder_enum == 2)
2520 dig->linkb = true;
2521 else
2522 dig->linkb = false;
2523
2524 return dig;
2525 }
2526
2527 void
2528 radeon_add_atom_encoder(struct drm_device *dev,
2529 uint32_t encoder_enum,
2530 uint32_t supported_device,
2531 u16 caps)
2532 {
2533 struct radeon_device *rdev = dev->dev_private;
2534 struct drm_encoder *encoder;
2535 struct radeon_encoder *radeon_encoder;
2536
2537 /* see if we already added it */
2538 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2539 radeon_encoder = to_radeon_encoder(encoder);
2540 if (radeon_encoder->encoder_enum == encoder_enum) {
2541 radeon_encoder->devices |= supported_device;
2542 return;
2543 }
2544
2545 }
2546
2547 /* add a new one */
2548 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2549 if (!radeon_encoder)
2550 return;
2551
2552 encoder = &radeon_encoder->base;
2553 switch (rdev->num_crtc) {
2554 case 1:
2555 encoder->possible_crtcs = 0x1;
2556 break;
2557 case 2:
2558 default:
2559 encoder->possible_crtcs = 0x3;
2560 break;
2561 case 4:
2562 encoder->possible_crtcs = 0xf;
2563 break;
2564 case 6:
2565 encoder->possible_crtcs = 0x3f;
2566 break;
2567 }
2568
2569 radeon_encoder->enc_priv = NULL;
2570
2571 radeon_encoder->encoder_enum = encoder_enum;
2572 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2573 radeon_encoder->devices = supported_device;
2574 radeon_encoder->rmx_type = RMX_OFF;
2575 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2576 radeon_encoder->is_ext_encoder = false;
2577 radeon_encoder->caps = caps;
2578
2579 switch (radeon_encoder->encoder_id) {
2580 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2581 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2582 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2583 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2584 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2585 radeon_encoder->rmx_type = RMX_FULL;
2586 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2587 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2588 } else {
2589 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2590 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2591 }
2592 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2593 break;
2594 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2595 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2596 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2597 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2598 break;
2599 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2600 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2601 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2602 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2603 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2604 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2605 break;
2606 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2607 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2608 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2610 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2611 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2612 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2613 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2614 radeon_encoder->rmx_type = RMX_FULL;
2615 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2616 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2617 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2618 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2619 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2620 } else {
2621 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2622 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2623 }
2624 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2625 break;
2626 case ENCODER_OBJECT_ID_SI170B:
2627 case ENCODER_OBJECT_ID_CH7303:
2628 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2629 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2630 case ENCODER_OBJECT_ID_TITFP513:
2631 case ENCODER_OBJECT_ID_VT1623:
2632 case ENCODER_OBJECT_ID_HDMI_SI1930:
2633 case ENCODER_OBJECT_ID_TRAVIS:
2634 case ENCODER_OBJECT_ID_NUTMEG:
2635 /* these are handled by the primary encoders */
2636 radeon_encoder->is_ext_encoder = true;
2637 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2638 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2639 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2640 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2641 else
2642 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2643 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2644 break;
2645 }
2646 }
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