2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
30 #include "radeon_audio.h"
32 #include <linux/backlight.h>
34 extern int atom_debug
;
37 radeon_atom_get_backlight_level_from_reg(struct radeon_device
*rdev
)
42 if (rdev
->family
>= CHIP_R600
)
43 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
45 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
47 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
50 return backlight_level
;
54 radeon_atom_set_backlight_level_to_reg(struct radeon_device
*rdev
,
59 if (rdev
->family
>= CHIP_R600
)
60 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
62 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
64 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
65 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
68 if (rdev
->family
>= CHIP_R600
)
69 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
71 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
75 atombios_get_backlight_level(struct radeon_encoder
*radeon_encoder
)
77 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
78 struct radeon_device
*rdev
= dev
->dev_private
;
80 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
83 return radeon_atom_get_backlight_level_from_reg(rdev
);
87 atombios_set_backlight_level(struct radeon_encoder
*radeon_encoder
, u8 level
)
89 struct drm_encoder
*encoder
= &radeon_encoder
->base
;
90 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
91 struct radeon_device
*rdev
= dev
->dev_private
;
92 struct radeon_encoder_atom_dig
*dig
;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
96 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
99 if ((radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
100 radeon_encoder
->enc_priv
) {
101 dig
= radeon_encoder
->enc_priv
;
102 dig
->backlight_level
= level
;
103 radeon_atom_set_backlight_level_to_reg(rdev
, dig
->backlight_level
);
105 switch (radeon_encoder
->encoder_id
) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
108 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
109 if (dig
->backlight_level
== 0) {
110 args
.ucAction
= ATOM_LCD_BLOFF
;
111 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
113 args
.ucAction
= ATOM_LCD_BL_BRIGHTNESS_CONTROL
;
114 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
115 args
.ucAction
= ATOM_LCD_BLON
;
116 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
123 if (dig
->backlight_level
== 0)
124 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
126 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
127 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
138 static u8
radeon_atom_bl_level(struct backlight_device
*bd
)
142 /* Convert brightness to hardware level */
143 if (bd
->props
.brightness
< 0)
145 else if (bd
->props
.brightness
> RADEON_MAX_BL_LEVEL
)
146 level
= RADEON_MAX_BL_LEVEL
;
148 level
= bd
->props
.brightness
;
153 static int radeon_atom_backlight_update_status(struct backlight_device
*bd
)
155 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
156 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
158 atombios_set_backlight_level(radeon_encoder
, radeon_atom_bl_level(bd
));
163 static int radeon_atom_backlight_get_brightness(struct backlight_device
*bd
)
165 struct radeon_backlight_privdata
*pdata
= bl_get_data(bd
);
166 struct radeon_encoder
*radeon_encoder
= pdata
->encoder
;
167 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
168 struct radeon_device
*rdev
= dev
->dev_private
;
170 return radeon_atom_get_backlight_level_from_reg(rdev
);
173 static const struct backlight_ops radeon_atom_backlight_ops
= {
174 .get_brightness
= radeon_atom_backlight_get_brightness
,
175 .update_status
= radeon_atom_backlight_update_status
,
178 void radeon_atom_backlight_init(struct radeon_encoder
*radeon_encoder
,
179 struct drm_connector
*drm_connector
)
181 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
182 struct radeon_device
*rdev
= dev
->dev_private
;
183 struct backlight_device
*bd
;
184 struct backlight_properties props
;
185 struct radeon_backlight_privdata
*pdata
;
186 struct radeon_encoder_atom_dig
*dig
;
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
192 if ((rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
193 (rdev
->pdev
->device
== 0x6741))
196 if (!radeon_encoder
->enc_priv
)
199 if (!rdev
->is_atom_bios
)
202 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
205 pdata
= kmalloc(sizeof(struct radeon_backlight_privdata
), GFP_KERNEL
);
207 DRM_ERROR("Memory allocation failed\n");
211 memset(&props
, 0, sizeof(props
));
212 props
.max_brightness
= RADEON_MAX_BL_LEVEL
;
213 props
.type
= BACKLIGHT_RAW
;
214 snprintf(bl_name
, sizeof(bl_name
),
215 "radeon_bl%d", dev
->primary
->index
);
216 bd
= backlight_device_register(bl_name
, drm_connector
->kdev
,
217 pdata
, &radeon_atom_backlight_ops
, &props
);
219 DRM_ERROR("Backlight registration failed\n");
223 pdata
->encoder
= radeon_encoder
;
225 dig
= radeon_encoder
->enc_priv
;
228 bd
->props
.brightness
= radeon_atom_backlight_get_brightness(bd
);
229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
234 if (bd
->props
.brightness
== 0)
235 bd
->props
.brightness
= RADEON_MAX_BL_LEVEL
;
236 bd
->props
.power
= FB_BLANK_UNBLANK
;
237 backlight_update_status(bd
);
239 DRM_INFO("radeon atom DIG backlight initialized\n");
248 static void radeon_atom_backlight_exit(struct radeon_encoder
*radeon_encoder
)
250 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
251 struct radeon_device
*rdev
= dev
->dev_private
;
252 struct backlight_device
*bd
= NULL
;
253 struct radeon_encoder_atom_dig
*dig
;
255 if (!radeon_encoder
->enc_priv
)
258 if (!rdev
->is_atom_bios
)
261 if (!(rdev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
264 dig
= radeon_encoder
->enc_priv
;
269 struct radeon_legacy_backlight_privdata
*pdata
;
271 pdata
= bl_get_data(bd
);
272 backlight_device_unregister(bd
);
275 DRM_INFO("radeon atom LVDS backlight unloaded\n");
279 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
281 void radeon_atom_backlight_init(struct radeon_encoder
*encoder
)
285 static void radeon_atom_backlight_exit(struct radeon_encoder
*encoder
)
291 /* evil but including atombios.h is much worse */
292 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
293 struct drm_display_mode
*mode
);
295 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
296 const struct drm_display_mode
*mode
,
297 struct drm_display_mode
*adjusted_mode
)
299 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
300 struct drm_device
*dev
= encoder
->dev
;
301 struct radeon_device
*rdev
= dev
->dev_private
;
303 /* set the active encoder to connector routing */
304 radeon_encoder_set_active_device(encoder
);
305 drm_mode_set_crtcinfo(adjusted_mode
, 0);
308 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
309 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
310 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
312 /* get the native mode for scaling */
313 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
)) {
314 radeon_panel_mode_fixup(encoder
, adjusted_mode
);
315 } else if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)) {
316 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
318 if (tv_dac
->tv_std
== TV_STD_NTSC
||
319 tv_dac
->tv_std
== TV_STD_NTSC_J
||
320 tv_dac
->tv_std
== TV_STD_PAL_M
)
321 radeon_atom_get_tv_timings(rdev
, 0, adjusted_mode
);
323 radeon_atom_get_tv_timings(rdev
, 1, adjusted_mode
);
325 } else if (radeon_encoder
->rmx_type
!= RMX_OFF
) {
326 radeon_panel_mode_fixup(encoder
, adjusted_mode
);
329 if (ASIC_IS_DCE3(rdev
) &&
330 ((radeon_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
331 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
))) {
332 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
333 radeon_dp_set_link_config(connector
, adjusted_mode
);
340 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
342 struct drm_device
*dev
= encoder
->dev
;
343 struct radeon_device
*rdev
= dev
->dev_private
;
344 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
345 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
347 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
349 memset(&args
, 0, sizeof(args
));
351 switch (radeon_encoder
->encoder_id
) {
352 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
354 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
356 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
358 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
362 args
.ucAction
= action
;
364 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
365 args
.ucDacStandard
= ATOM_DAC1_PS2
;
366 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
367 args
.ucDacStandard
= ATOM_DAC1_CV
;
369 switch (dac_info
->tv_std
) {
372 case TV_STD_SCART_PAL
:
375 args
.ucDacStandard
= ATOM_DAC1_PAL
;
381 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
385 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
387 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
392 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
394 struct drm_device
*dev
= encoder
->dev
;
395 struct radeon_device
*rdev
= dev
->dev_private
;
396 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
397 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
399 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
401 memset(&args
, 0, sizeof(args
));
403 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
405 args
.sTVEncoder
.ucAction
= action
;
407 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
408 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
410 switch (dac_info
->tv_std
) {
412 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
415 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
418 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
421 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
424 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
426 case TV_STD_SCART_PAL
:
427 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
430 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
433 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
436 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
441 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
443 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
447 static u8
radeon_atom_get_bpc(struct drm_encoder
*encoder
)
452 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
453 bpc
= radeon_crtc
->bpc
;
458 return PANEL_BPC_UNDEFINE
;
460 return PANEL_6BIT_PER_COLOR
;
463 return PANEL_8BIT_PER_COLOR
;
465 return PANEL_10BIT_PER_COLOR
;
467 return PANEL_12BIT_PER_COLOR
;
469 return PANEL_16BIT_PER_COLOR
;
473 union dvo_encoder_control
{
474 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
475 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
476 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
477 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4
;
481 atombios_dvo_setup(struct drm_encoder
*encoder
, int action
)
483 struct drm_device
*dev
= encoder
->dev
;
484 struct radeon_device
*rdev
= dev
->dev_private
;
485 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
486 union dvo_encoder_control args
;
487 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
490 memset(&args
, 0, sizeof(args
));
492 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
495 /* some R4xx chips have the wrong frev */
496 if (rdev
->family
<= CHIP_RV410
)
504 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
506 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
507 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
509 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
513 args
.dvo
.sDVOEncoder
.ucAction
= action
;
514 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
515 /* DFP1, CRT1, TV1 depending on the type of port */
516 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
518 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
519 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
523 args
.dvo_v3
.ucAction
= action
;
524 args
.dvo_v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
525 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
529 args
.dvo_v4
.ucAction
= action
;
530 args
.dvo_v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
531 args
.dvo_v4
.ucDVOConfig
= 0; /* XXX */
532 args
.dvo_v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
535 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
540 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
544 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
547 union lvds_encoder_control
{
548 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
549 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
553 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
555 struct drm_device
*dev
= encoder
->dev
;
556 struct radeon_device
*rdev
= dev
->dev_private
;
557 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
558 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
559 union lvds_encoder_control args
;
561 int hdmi_detected
= 0;
567 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
570 memset(&args
, 0, sizeof(args
));
572 switch (radeon_encoder
->encoder_id
) {
573 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
574 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
576 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
578 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
580 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
581 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
582 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
584 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
588 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
597 args
.v1
.ucAction
= action
;
599 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
600 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
601 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
602 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
603 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
604 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
605 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
608 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
609 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
610 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
611 /*if (pScrn->rgbBits == 8) */
612 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
618 args
.v2
.ucAction
= action
;
620 if (dig
->coherent_mode
)
621 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
624 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
625 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
626 args
.v2
.ucTruncate
= 0;
627 args
.v2
.ucSpatial
= 0;
628 args
.v2
.ucTemporal
= 0;
630 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
631 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
632 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
633 if (dig
->lcd_misc
& ATOM_PANEL_MISC_SPATIAL
) {
634 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
635 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
636 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
638 if (dig
->lcd_misc
& ATOM_PANEL_MISC_TEMPORAL
) {
639 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
640 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
641 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
642 if (((dig
->lcd_misc
>> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
) & 0x3) == 2)
643 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
647 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
648 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
649 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
653 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
658 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
662 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
666 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
668 struct drm_device
*dev
= encoder
->dev
;
669 struct radeon_device
*rdev
= dev
->dev_private
;
670 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
671 struct drm_connector
*connector
;
672 struct radeon_connector
*radeon_connector
;
673 struct radeon_connector_atom_dig
*dig_connector
;
675 /* dp bridges are always DP */
676 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
677 return ATOM_ENCODER_MODE_DP
;
679 /* DVO is always DVO */
680 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
681 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
682 return ATOM_ENCODER_MODE_DVO
;
684 connector
= radeon_get_connector_for_encoder(encoder
);
685 /* if we don't have an active device yet, just use one of
686 * the connectors tied to the encoder.
689 connector
= radeon_get_connector_for_encoder_init(encoder
);
690 radeon_connector
= to_radeon_connector(connector
);
692 switch (connector
->connector_type
) {
693 case DRM_MODE_CONNECTOR_DVII
:
694 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
695 if (radeon_audio
!= 0) {
696 if (radeon_connector
->use_digital
&&
697 (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
))
698 return ATOM_ENCODER_MODE_HDMI
;
699 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector
)) &&
700 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
701 return ATOM_ENCODER_MODE_HDMI
;
702 else if (radeon_connector
->use_digital
)
703 return ATOM_ENCODER_MODE_DVI
;
705 return ATOM_ENCODER_MODE_CRT
;
706 } else if (radeon_connector
->use_digital
) {
707 return ATOM_ENCODER_MODE_DVI
;
709 return ATOM_ENCODER_MODE_CRT
;
712 case DRM_MODE_CONNECTOR_DVID
:
713 case DRM_MODE_CONNECTOR_HDMIA
:
715 if (radeon_audio
!= 0) {
716 if (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
)
717 return ATOM_ENCODER_MODE_HDMI
;
718 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector
)) &&
719 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
720 return ATOM_ENCODER_MODE_HDMI
;
722 return ATOM_ENCODER_MODE_DVI
;
724 return ATOM_ENCODER_MODE_DVI
;
727 case DRM_MODE_CONNECTOR_LVDS
:
728 return ATOM_ENCODER_MODE_LVDS
;
730 case DRM_MODE_CONNECTOR_DisplayPort
:
731 dig_connector
= radeon_connector
->con_priv
;
732 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
733 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
734 if (radeon_audio
!= 0 &&
735 drm_detect_monitor_audio(radeon_connector_edid(connector
)) &&
736 ASIC_IS_DCE4(rdev
) && !ASIC_IS_DCE5(rdev
))
737 return ATOM_ENCODER_MODE_DP_AUDIO
;
738 return ATOM_ENCODER_MODE_DP
;
739 } else if (radeon_audio
!= 0) {
740 if (radeon_connector
->audio
== RADEON_AUDIO_ENABLE
)
741 return ATOM_ENCODER_MODE_HDMI
;
742 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector
)) &&
743 (radeon_connector
->audio
== RADEON_AUDIO_AUTO
))
744 return ATOM_ENCODER_MODE_HDMI
;
746 return ATOM_ENCODER_MODE_DVI
;
748 return ATOM_ENCODER_MODE_DVI
;
751 case DRM_MODE_CONNECTOR_eDP
:
752 if (radeon_audio
!= 0 &&
753 drm_detect_monitor_audio(radeon_connector_edid(connector
)) &&
754 ASIC_IS_DCE4(rdev
) && !ASIC_IS_DCE5(rdev
))
755 return ATOM_ENCODER_MODE_DP_AUDIO
;
756 return ATOM_ENCODER_MODE_DP
;
757 case DRM_MODE_CONNECTOR_DVIA
:
758 case DRM_MODE_CONNECTOR_VGA
:
759 return ATOM_ENCODER_MODE_CRT
;
761 case DRM_MODE_CONNECTOR_Composite
:
762 case DRM_MODE_CONNECTOR_SVIDEO
:
763 case DRM_MODE_CONNECTOR_9PinDIN
:
765 return ATOM_ENCODER_MODE_TV
;
766 /*return ATOM_ENCODER_MODE_CV;*/
772 * DIG Encoder/Transmitter Setup
775 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
776 * Supports up to 3 digital outputs
777 * - 2 DIG encoder blocks.
778 * DIG1 can drive UNIPHY link A or link B
779 * DIG2 can drive UNIPHY link B or LVTMA
782 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
783 * Supports up to 5 digital outputs
784 * - 2 DIG encoder blocks.
785 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
788 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
789 * Supports up to 6 digital outputs
790 * - 6 DIG encoder blocks.
791 * - DIG to PHY mapping is hardcoded
792 * DIG1 drives UNIPHY0 link A, A+B
793 * DIG2 drives UNIPHY0 link B
794 * DIG3 drives UNIPHY1 link A, A+B
795 * DIG4 drives UNIPHY1 link B
796 * DIG5 drives UNIPHY2 link A, A+B
797 * DIG6 drives UNIPHY2 link B
800 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
801 * Supports up to 6 digital outputs
802 * - 2 DIG encoder blocks.
804 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
806 * DIG1 drives UNIPHY0/1/2 link A
807 * DIG2 drives UNIPHY0/1/2 link B
810 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
812 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
813 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
814 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
815 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
818 union dig_encoder_control
{
819 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
820 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
821 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
822 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
826 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
, int panel_mode
)
828 struct drm_device
*dev
= encoder
->dev
;
829 struct radeon_device
*rdev
= dev
->dev_private
;
830 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
831 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
832 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
833 union dig_encoder_control args
;
837 int dp_lane_count
= 0;
838 int hpd_id
= RADEON_HPD_NONE
;
841 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
842 struct radeon_connector_atom_dig
*dig_connector
=
843 radeon_connector
->con_priv
;
845 dp_clock
= dig_connector
->dp_clock
;
846 dp_lane_count
= dig_connector
->dp_lane_count
;
847 hpd_id
= radeon_connector
->hpd
.hpd
;
850 /* no dig encoder assigned */
851 if (dig
->dig_encoder
== -1)
854 memset(&args
, 0, sizeof(args
));
856 if (ASIC_IS_DCE4(rdev
))
857 index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
859 if (dig
->dig_encoder
)
860 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
862 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
865 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
872 args
.v1
.ucAction
= action
;
873 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
874 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
875 args
.v3
.ucPanelMode
= panel_mode
;
877 args
.v1
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
879 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
880 args
.v1
.ucLaneNum
= dp_lane_count
;
881 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
882 args
.v1
.ucLaneNum
= 8;
884 args
.v1
.ucLaneNum
= 4;
886 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
887 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
888 switch (radeon_encoder
->encoder_id
) {
889 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
890 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
893 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
894 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
897 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
901 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
903 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
907 args
.v3
.ucAction
= action
;
908 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
909 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
910 args
.v3
.ucPanelMode
= panel_mode
;
912 args
.v3
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
914 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
915 args
.v3
.ucLaneNum
= dp_lane_count
;
916 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
917 args
.v3
.ucLaneNum
= 8;
919 args
.v3
.ucLaneNum
= 4;
921 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
922 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
923 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
924 args
.v3
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
927 args
.v4
.ucAction
= action
;
928 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
929 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
930 args
.v4
.ucPanelMode
= panel_mode
;
932 args
.v4
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
934 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
935 args
.v4
.ucLaneNum
= dp_lane_count
;
936 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
937 args
.v4
.ucLaneNum
= 8;
939 args
.v4
.ucLaneNum
= 4;
941 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
942 if (dp_clock
== 540000)
943 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
944 else if (dp_clock
== 324000)
945 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
;
946 else if (dp_clock
== 270000)
947 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
949 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
;
951 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
952 args
.v4
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
953 if (hpd_id
== RADEON_HPD_NONE
)
954 args
.v4
.ucHPD_ID
= 0;
956 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
959 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
964 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
968 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
972 union dig_transmitter_control
{
973 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
974 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
975 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
976 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
977 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
981 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
, uint8_t lane_num
, uint8_t lane_set
)
983 struct drm_device
*dev
= encoder
->dev
;
984 struct radeon_device
*rdev
= dev
->dev_private
;
985 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
986 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
987 struct drm_connector
*connector
;
988 union dig_transmitter_control args
;
994 int dp_lane_count
= 0;
995 int connector_object_id
= 0;
996 int igp_lane_info
= 0;
997 int dig_encoder
= dig
->dig_encoder
;
998 int hpd_id
= RADEON_HPD_NONE
;
1000 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1001 connector
= radeon_get_connector_for_encoder_init(encoder
);
1002 /* just needed to avoid bailing in the encoder check. the encoder
1003 * isn't used for init
1007 connector
= radeon_get_connector_for_encoder(encoder
);
1010 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1011 struct radeon_connector_atom_dig
*dig_connector
=
1012 radeon_connector
->con_priv
;
1014 hpd_id
= radeon_connector
->hpd
.hpd
;
1015 dp_clock
= dig_connector
->dp_clock
;
1016 dp_lane_count
= dig_connector
->dp_lane_count
;
1017 connector_object_id
=
1018 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1019 igp_lane_info
= dig_connector
->igp_lane_info
;
1022 if (encoder
->crtc
) {
1023 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1024 pll_id
= radeon_crtc
->pll_id
;
1027 /* no dig encoder assigned */
1028 if (dig_encoder
== -1)
1031 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)))
1034 memset(&args
, 0, sizeof(args
));
1036 switch (radeon_encoder
->encoder_id
) {
1037 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1038 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1043 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1044 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1046 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1047 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
1051 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1058 args
.v1
.ucAction
= action
;
1059 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1060 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
1061 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1062 args
.v1
.asMode
.ucLaneSel
= lane_num
;
1063 args
.v1
.asMode
.ucLaneSet
= lane_set
;
1066 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1067 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1068 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1070 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1073 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
1076 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
1078 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
1080 if ((rdev
->flags
& RADEON_IS_IGP
) &&
1081 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
1083 !radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
)) {
1084 if (igp_lane_info
& 0x1)
1085 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
1086 else if (igp_lane_info
& 0x2)
1087 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
1088 else if (igp_lane_info
& 0x4)
1089 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
1090 else if (igp_lane_info
& 0x8)
1091 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
1093 if (igp_lane_info
& 0x3)
1094 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
1095 else if (igp_lane_info
& 0xc)
1096 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
1101 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
1103 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
1106 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1107 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1108 if (dig
->coherent_mode
)
1109 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1110 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1111 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
1115 args
.v2
.ucAction
= action
;
1116 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1117 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
1118 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1119 args
.v2
.asMode
.ucLaneSel
= lane_num
;
1120 args
.v2
.asMode
.ucLaneSet
= lane_set
;
1123 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1124 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1125 args
.v2
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1127 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1130 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
1132 args
.v2
.acConfig
.ucLinkSel
= 1;
1134 switch (radeon_encoder
->encoder_id
) {
1135 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1136 args
.v2
.acConfig
.ucTransmitterSel
= 0;
1138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1139 args
.v2
.acConfig
.ucTransmitterSel
= 1;
1141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1142 args
.v2
.acConfig
.ucTransmitterSel
= 2;
1147 args
.v2
.acConfig
.fCoherentMode
= 1;
1148 args
.v2
.acConfig
.fDPConnector
= 1;
1149 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1150 if (dig
->coherent_mode
)
1151 args
.v2
.acConfig
.fCoherentMode
= 1;
1152 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1153 args
.v2
.acConfig
.fDualLinkConnector
= 1;
1157 args
.v3
.ucAction
= action
;
1158 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1159 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
1160 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1161 args
.v3
.asMode
.ucLaneSel
= lane_num
;
1162 args
.v3
.asMode
.ucLaneSet
= lane_set
;
1165 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1166 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1167 args
.v3
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1169 args
.v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1173 args
.v3
.ucLaneNum
= dp_lane_count
;
1174 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1175 args
.v3
.ucLaneNum
= 8;
1177 args
.v3
.ucLaneNum
= 4;
1180 args
.v3
.acConfig
.ucLinkSel
= 1;
1181 if (dig_encoder
& 1)
1182 args
.v3
.acConfig
.ucEncoderSel
= 1;
1184 /* Select the PLL for the PHY
1185 * DP PHY should be clocked from external src if there is
1188 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1189 if (is_dp
&& rdev
->clock
.dp_extclk
)
1190 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
1192 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
1194 switch (radeon_encoder
->encoder_id
) {
1195 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1196 args
.v3
.acConfig
.ucTransmitterSel
= 0;
1198 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1199 args
.v3
.acConfig
.ucTransmitterSel
= 1;
1201 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1202 args
.v3
.acConfig
.ucTransmitterSel
= 2;
1207 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1208 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1209 if (dig
->coherent_mode
)
1210 args
.v3
.acConfig
.fCoherentMode
= 1;
1211 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1212 args
.v3
.acConfig
.fDualLinkConnector
= 1;
1216 args
.v4
.ucAction
= action
;
1217 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1218 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
1219 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1220 args
.v4
.asMode
.ucLaneSel
= lane_num
;
1221 args
.v4
.asMode
.ucLaneSet
= lane_set
;
1224 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1225 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1226 args
.v4
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
1228 args
.v4
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1232 args
.v4
.ucLaneNum
= dp_lane_count
;
1233 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1234 args
.v4
.ucLaneNum
= 8;
1236 args
.v4
.ucLaneNum
= 4;
1239 args
.v4
.acConfig
.ucLinkSel
= 1;
1240 if (dig_encoder
& 1)
1241 args
.v4
.acConfig
.ucEncoderSel
= 1;
1243 /* Select the PLL for the PHY
1244 * DP PHY should be clocked from external src if there is
1247 /* On DCE5 DCPLL usually generates the DP ref clock */
1249 if (rdev
->clock
.dp_extclk
)
1250 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
1252 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
1254 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1256 switch (radeon_encoder
->encoder_id
) {
1257 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1258 args
.v4
.acConfig
.ucTransmitterSel
= 0;
1260 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1261 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1263 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1264 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1269 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1270 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1271 if (dig
->coherent_mode
)
1272 args
.v4
.acConfig
.fCoherentMode
= 1;
1273 if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1274 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1278 args
.v5
.ucAction
= action
;
1280 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1282 args
.v5
.usSymClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1284 switch (radeon_encoder
->encoder_id
) {
1285 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1287 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1289 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1293 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1295 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1299 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1301 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1304 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1308 args
.v5
.ucLaneNum
= dp_lane_count
;
1309 else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1310 args
.v5
.ucLaneNum
= 8;
1312 args
.v5
.ucLaneNum
= 4;
1313 args
.v5
.ucConnObjId
= connector_object_id
;
1314 args
.v5
.ucDigMode
= atombios_get_encoder_mode(encoder
);
1316 if (is_dp
&& rdev
->clock
.dp_extclk
)
1317 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1319 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1322 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1323 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1324 if (dig
->coherent_mode
)
1325 args
.v5
.asConfig
.ucCoherentMode
= 1;
1327 if (hpd_id
== RADEON_HPD_NONE
)
1328 args
.v5
.asConfig
.ucHPDSel
= 0;
1330 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1331 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1332 args
.v5
.ucDPLaneSet
= lane_set
;
1335 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1340 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1344 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1348 atombios_set_edp_panel_power(struct drm_connector
*connector
, int action
)
1350 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1351 struct drm_device
*dev
= radeon_connector
->base
.dev
;
1352 struct radeon_device
*rdev
= dev
->dev_private
;
1353 union dig_transmitter_control args
;
1354 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1357 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1360 if (!ASIC_IS_DCE4(rdev
))
1363 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1364 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1367 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1370 memset(&args
, 0, sizeof(args
));
1372 args
.v1
.ucAction
= action
;
1374 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1376 /* wait for the panel to power up */
1377 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1380 for (i
= 0; i
< 300; i
++) {
1381 if (radeon_hpd_sense(rdev
, radeon_connector
->hpd
.hpd
))
1391 union external_encoder_control
{
1392 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1393 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1397 atombios_external_encoder_setup(struct drm_encoder
*encoder
,
1398 struct drm_encoder
*ext_encoder
,
1401 struct drm_device
*dev
= encoder
->dev
;
1402 struct radeon_device
*rdev
= dev
->dev_private
;
1403 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1404 struct radeon_encoder
*ext_radeon_encoder
= to_radeon_encoder(ext_encoder
);
1405 union external_encoder_control args
;
1406 struct drm_connector
*connector
;
1407 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1410 int dp_lane_count
= 0;
1411 int connector_object_id
= 0;
1412 u32 ext_enum
= (ext_radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1414 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1415 connector
= radeon_get_connector_for_encoder_init(encoder
);
1417 connector
= radeon_get_connector_for_encoder(encoder
);
1420 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1421 struct radeon_connector_atom_dig
*dig_connector
=
1422 radeon_connector
->con_priv
;
1424 dp_clock
= dig_connector
->dp_clock
;
1425 dp_lane_count
= dig_connector
->dp_lane_count
;
1426 connector_object_id
=
1427 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1430 memset(&args
, 0, sizeof(args
));
1432 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1437 /* no params on frev 1 */
1443 args
.v1
.sDigEncoder
.ucAction
= action
;
1444 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1445 args
.v1
.sDigEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1447 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1448 if (dp_clock
== 270000)
1449 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1450 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1451 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1452 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1454 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1457 args
.v3
.sExtEncoder
.ucAction
= action
;
1458 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1459 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1461 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1462 args
.v3
.sExtEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1464 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1465 if (dp_clock
== 270000)
1466 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1467 else if (dp_clock
== 540000)
1468 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1469 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1470 } else if (radeon_dig_monitor_is_duallink(encoder
, radeon_encoder
->pixel_clock
))
1471 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1473 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1475 case GRAPH_OBJECT_ENUM_ID1
:
1476 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1478 case GRAPH_OBJECT_ENUM_ID2
:
1479 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1481 case GRAPH_OBJECT_ENUM_ID3
:
1482 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1485 args
.v3
.sExtEncoder
.ucBitPerColor
= radeon_atom_get_bpc(encoder
);
1488 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1493 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1496 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1500 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
1502 struct drm_device
*dev
= encoder
->dev
;
1503 struct radeon_device
*rdev
= dev
->dev_private
;
1504 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1505 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1506 ENABLE_YUV_PS_ALLOCATION args
;
1507 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
1510 memset(&args
, 0, sizeof(args
));
1512 if (rdev
->family
>= CHIP_R600
)
1513 reg
= R600_BIOS_3_SCRATCH
;
1515 reg
= RADEON_BIOS_3_SCRATCH
;
1517 /* XXX: fix up scratch reg handling */
1519 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1520 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
1521 (radeon_crtc
->crtc_id
<< 18)));
1522 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1523 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
1528 args
.ucEnable
= ATOM_ENABLE
;
1529 args
.ucCRTC
= radeon_crtc
->crtc_id
;
1531 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1537 radeon_atom_encoder_dpms_avivo(struct drm_encoder
*encoder
, int mode
)
1539 struct drm_device
*dev
= encoder
->dev
;
1540 struct radeon_device
*rdev
= dev
->dev_private
;
1541 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1542 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
1545 memset(&args
, 0, sizeof(args
));
1547 switch (radeon_encoder
->encoder_id
) {
1548 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1549 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1550 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
1552 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1553 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1554 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1555 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1557 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1558 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1560 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1561 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1562 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1564 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
1566 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1567 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1568 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1569 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1570 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1571 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1573 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
1575 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1576 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1577 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1578 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1579 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1580 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1582 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
1589 case DRM_MODE_DPMS_ON
:
1590 args
.ucAction
= ATOM_ENABLE
;
1591 /* workaround for DVOOutputControl on some RS690 systems */
1592 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DDI
) {
1593 u32 reg
= RREG32(RADEON_BIOS_3_SCRATCH
);
1594 WREG32(RADEON_BIOS_3_SCRATCH
, reg
& ~ATOM_S3_DFP2I_ACTIVE
);
1595 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1596 WREG32(RADEON_BIOS_3_SCRATCH
, reg
);
1598 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1599 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1600 args
.ucAction
= ATOM_LCD_BLON
;
1601 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1604 case DRM_MODE_DPMS_STANDBY
:
1605 case DRM_MODE_DPMS_SUSPEND
:
1606 case DRM_MODE_DPMS_OFF
:
1607 args
.ucAction
= ATOM_DISABLE
;
1608 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1609 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1610 args
.ucAction
= ATOM_LCD_BLOFF
;
1611 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1618 radeon_atom_encoder_dpms_dig(struct drm_encoder
*encoder
, int mode
)
1620 struct drm_device
*dev
= encoder
->dev
;
1621 struct radeon_device
*rdev
= dev
->dev_private
;
1622 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1623 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
1624 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1625 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1626 struct radeon_connector
*radeon_connector
= NULL
;
1627 struct radeon_connector_atom_dig
*radeon_dig_connector
= NULL
;
1628 bool travis_quirk
= false;
1632 radeon_connector
= to_radeon_connector(connector
);
1633 radeon_dig_connector
= radeon_connector
->con_priv
;
1634 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector
) ==
1635 ENCODER_OBJECT_ID_TRAVIS
) &&
1636 (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
1637 !ASIC_IS_DCE5(rdev
))
1638 travis_quirk
= true;
1642 case DRM_MODE_DPMS_ON
:
1643 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE5(rdev
)) {
1645 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1647 dig
->panel_mode
= radeon_dp_get_panel_mode(encoder
, connector
);
1649 /* setup and enable the encoder */
1650 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1651 atombios_dig_encoder_setup(encoder
,
1652 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1655 if (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
))
1656 atombios_external_encoder_setup(encoder
, ext_encoder
,
1657 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1659 } else if (ASIC_IS_DCE4(rdev
)) {
1660 /* setup and enable the encoder */
1661 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1663 /* setup and enable the encoder and transmitter */
1664 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
, 0);
1665 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
, 0, 0);
1667 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1668 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1669 atombios_set_edp_panel_power(connector
,
1670 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1671 radeon_dig_connector
->edp_on
= true;
1674 /* enable the transmitter */
1675 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1676 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1677 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1678 radeon_dp_link_train(encoder
, connector
);
1679 if (ASIC_IS_DCE4(rdev
))
1680 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1682 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1683 atombios_dig_transmitter_setup(encoder
,
1684 ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
1686 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_ENABLE
);
1688 case DRM_MODE_DPMS_STANDBY
:
1689 case DRM_MODE_DPMS_SUSPEND
:
1690 case DRM_MODE_DPMS_OFF
:
1691 if (ASIC_IS_DCE4(rdev
)) {
1692 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
)
1693 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1696 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_DISABLE
);
1697 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1698 atombios_dig_transmitter_setup(encoder
,
1699 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1701 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) &&
1702 connector
&& !travis_quirk
)
1703 radeon_dp_set_rx_power_state(connector
, DP_SET_POWER_D3
);
1704 if (ASIC_IS_DCE4(rdev
)) {
1705 /* disable the transmitter */
1706 atombios_dig_transmitter_setup(encoder
,
1707 ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1709 /* disable the encoder and transmitter */
1710 atombios_dig_transmitter_setup(encoder
,
1711 ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1712 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
, 0);
1714 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder
)) && connector
) {
1716 radeon_dp_set_rx_power_state(connector
, DP_SET_POWER_D3
);
1717 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1718 atombios_set_edp_panel_power(connector
,
1719 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1720 radeon_dig_connector
->edp_on
= false;
1726 encoder_mode
= atombios_get_encoder_mode(encoder
);
1727 if (connector
&& (radeon_audio
!= 0) &&
1728 ((encoder_mode
== ATOM_ENCODER_MODE_HDMI
) ||
1729 (ENCODER_MODE_IS_DP(encoder_mode
) &&
1730 drm_detect_monitor_audio(radeon_connector_edid(connector
)))))
1731 radeon_audio_dpms(encoder
, mode
);
1735 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1737 struct drm_device
*dev
= encoder
->dev
;
1738 struct radeon_device
*rdev
= dev
->dev_private
;
1739 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1741 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1742 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
1743 radeon_encoder
->active_device
);
1744 switch (radeon_encoder
->encoder_id
) {
1745 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1746 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1747 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1748 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1749 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1750 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1751 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1752 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1753 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1755 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1757 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1758 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1759 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1760 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1762 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1763 if (ASIC_IS_DCE5(rdev
)) {
1765 case DRM_MODE_DPMS_ON
:
1766 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
1768 case DRM_MODE_DPMS_STANDBY
:
1769 case DRM_MODE_DPMS_SUSPEND
:
1770 case DRM_MODE_DPMS_OFF
:
1771 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
1774 } else if (ASIC_IS_DCE3(rdev
))
1775 radeon_atom_encoder_dpms_dig(encoder
, mode
);
1777 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1779 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1780 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1781 if (ASIC_IS_DCE5(rdev
)) {
1783 case DRM_MODE_DPMS_ON
:
1784 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1786 case DRM_MODE_DPMS_STANDBY
:
1787 case DRM_MODE_DPMS_SUSPEND
:
1788 case DRM_MODE_DPMS_OFF
:
1789 atombios_dac_setup(encoder
, ATOM_DISABLE
);
1793 radeon_atom_encoder_dpms_avivo(encoder
, mode
);
1799 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
1803 union crtc_source_param
{
1804 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1805 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1809 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
1811 struct drm_device
*dev
= encoder
->dev
;
1812 struct radeon_device
*rdev
= dev
->dev_private
;
1813 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1814 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1815 union crtc_source_param args
;
1816 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1818 struct radeon_encoder_atom_dig
*dig
;
1820 memset(&args
, 0, sizeof(args
));
1822 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1830 if (ASIC_IS_AVIVO(rdev
))
1831 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1833 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
1834 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1836 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
1839 switch (radeon_encoder
->encoder_id
) {
1840 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1841 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1842 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1844 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1845 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1846 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1847 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1849 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1851 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1852 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1853 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1854 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1856 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1857 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1858 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1859 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1860 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1861 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1863 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1865 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1866 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1867 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1868 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1869 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1870 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1872 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1877 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1878 if (radeon_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1879 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1881 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1882 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1883 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1884 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1886 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1887 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1888 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1890 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1892 switch (radeon_encoder
->encoder_id
) {
1893 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1894 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1895 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1897 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1898 dig
= radeon_encoder
->enc_priv
;
1899 switch (dig
->dig_encoder
) {
1901 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1904 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1907 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1910 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1913 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1916 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1919 args
.v2
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1923 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1924 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1926 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1927 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1928 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1929 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1930 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1932 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1934 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1935 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1936 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1937 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1938 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1940 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1947 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1951 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1953 /* update scratch regs with new routing */
1954 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1958 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1959 struct drm_display_mode
*mode
)
1961 struct drm_device
*dev
= encoder
->dev
;
1962 struct radeon_device
*rdev
= dev
->dev_private
;
1963 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1964 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1966 /* Funky macbooks */
1967 if ((dev
->pdev
->device
== 0x71C5) &&
1968 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1969 (dev
->pdev
->subsystem_device
== 0x0080)) {
1970 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1971 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1973 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1974 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1976 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1980 /* set scaler clears this on some chips */
1981 if (ASIC_IS_AVIVO(rdev
) &&
1982 (!(radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)))) {
1983 if (ASIC_IS_DCE8(rdev
)) {
1984 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1985 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1988 WREG32(CIK_LB_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1989 } else if (ASIC_IS_DCE4(rdev
)) {
1990 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1991 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1992 EVERGREEN_INTERLEAVE_EN
);
1994 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1996 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1997 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1998 AVIVO_D1MODE_INTERLEAVE_EN
);
2000 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
2005 static int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder
)
2007 struct drm_device
*dev
= encoder
->dev
;
2008 struct radeon_device
*rdev
= dev
->dev_private
;
2009 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
2010 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2011 struct drm_encoder
*test_encoder
;
2012 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2013 uint32_t dig_enc_in_use
= 0;
2015 if (ASIC_IS_DCE6(rdev
)) {
2017 switch (radeon_encoder
->encoder_id
) {
2018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2030 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2040 } else if (ASIC_IS_DCE4(rdev
)) {
2042 if (ASIC_IS_DCE41(rdev
) && !ASIC_IS_DCE61(rdev
)) {
2043 /* ontario follows DCE4 */
2044 if (rdev
->family
== CHIP_PALM
) {
2050 /* llano follows DCE3.2 */
2051 return radeon_crtc
->crtc_id
;
2053 switch (radeon_encoder
->encoder_id
) {
2054 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2060 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2066 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2076 /* on DCE32 and encoder can driver any block so just crtc id */
2077 if (ASIC_IS_DCE32(rdev
)) {
2078 return radeon_crtc
->crtc_id
;
2081 /* on DCE3 - LVTMA can only be driven by DIGB */
2082 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2083 struct radeon_encoder
*radeon_test_encoder
;
2085 if (encoder
== test_encoder
)
2088 if (!radeon_encoder_is_digital(test_encoder
))
2091 radeon_test_encoder
= to_radeon_encoder(test_encoder
);
2092 dig
= radeon_test_encoder
->enc_priv
;
2094 if (dig
->dig_encoder
>= 0)
2095 dig_enc_in_use
|= (1 << dig
->dig_encoder
);
2098 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
) {
2099 if (dig_enc_in_use
& 0x2)
2100 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2103 if (!(dig_enc_in_use
& 1))
2108 /* This only needs to be called once at startup */
2110 radeon_atom_encoder_init(struct radeon_device
*rdev
)
2112 struct drm_device
*dev
= rdev
->ddev
;
2113 struct drm_encoder
*encoder
;
2115 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2116 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2117 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2119 switch (radeon_encoder
->encoder_id
) {
2120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2124 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2125 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
2131 if (ext_encoder
&& (ASIC_IS_DCE41(rdev
) || ASIC_IS_DCE61(rdev
)))
2132 atombios_external_encoder_setup(encoder
, ext_encoder
,
2133 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
2138 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
2139 struct drm_display_mode
*mode
,
2140 struct drm_display_mode
*adjusted_mode
)
2142 struct drm_device
*dev
= encoder
->dev
;
2143 struct radeon_device
*rdev
= dev
->dev_private
;
2144 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2145 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
2148 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
2150 /* need to call this here rather than in prepare() since we need some crtc info */
2151 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2153 if (ASIC_IS_AVIVO(rdev
) && !ASIC_IS_DCE4(rdev
)) {
2154 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
2155 atombios_yuv_setup(encoder
, true);
2157 atombios_yuv_setup(encoder
, false);
2160 switch (radeon_encoder
->encoder_id
) {
2161 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2162 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2163 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2164 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2165 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
2167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2172 /* handled in dpms */
2173 encoder_mode
= atombios_get_encoder_mode(encoder
);
2174 if (connector
&& (radeon_audio
!= 0) &&
2175 ((encoder_mode
== ATOM_ENCODER_MODE_HDMI
) ||
2176 (ENCODER_MODE_IS_DP(encoder_mode
) &&
2177 drm_detect_monitor_audio(radeon_connector_edid(connector
)))))
2178 radeon_audio_mode_set(encoder
, adjusted_mode
);
2180 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2181 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2182 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2183 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
2185 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2186 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2187 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2188 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2189 atombios_dac_setup(encoder
, ATOM_ENABLE
);
2190 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) {
2191 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2192 atombios_tv_setup(encoder
, ATOM_ENABLE
);
2194 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2199 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
2203 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2205 struct drm_device
*dev
= encoder
->dev
;
2206 struct radeon_device
*rdev
= dev
->dev_private
;
2207 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2208 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2210 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
2211 ATOM_DEVICE_CV_SUPPORT
|
2212 ATOM_DEVICE_CRT_SUPPORT
)) {
2213 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
2214 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
2217 memset(&args
, 0, sizeof(args
));
2219 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2222 args
.sDacload
.ucMisc
= 0;
2224 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
2225 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
2226 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
2228 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
2230 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
2231 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
2232 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
2233 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
2234 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2235 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
2237 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2238 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2239 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
2241 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
2244 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2251 static enum drm_connector_status
2252 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2254 struct drm_device
*dev
= encoder
->dev
;
2255 struct radeon_device
*rdev
= dev
->dev_private
;
2256 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2257 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2258 uint32_t bios_0_scratch
;
2260 if (!atombios_dac_load_detect(encoder
, connector
)) {
2261 DRM_DEBUG_KMS("detect returned false \n");
2262 return connector_status_unknown
;
2265 if (rdev
->family
>= CHIP_R600
)
2266 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2268 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2270 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2271 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2272 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2273 return connector_status_connected
;
2275 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2276 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2277 return connector_status_connected
;
2279 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2280 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2281 return connector_status_connected
;
2283 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2284 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2285 return connector_status_connected
; /* CTV */
2286 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2287 return connector_status_connected
; /* STV */
2289 return connector_status_disconnected
;
2292 static enum drm_connector_status
2293 radeon_atom_dig_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2295 struct drm_device
*dev
= encoder
->dev
;
2296 struct radeon_device
*rdev
= dev
->dev_private
;
2297 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2298 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2299 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2302 if (!ASIC_IS_DCE4(rdev
))
2303 return connector_status_unknown
;
2306 return connector_status_unknown
;
2308 if ((radeon_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
2309 return connector_status_unknown
;
2311 /* load detect on the dp bridge */
2312 atombios_external_encoder_setup(encoder
, ext_encoder
,
2313 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
2315 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2317 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
2318 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2319 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
2320 return connector_status_connected
;
2322 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2323 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
2324 return connector_status_connected
;
2326 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2327 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
2328 return connector_status_connected
;
2330 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2331 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
2332 return connector_status_connected
; /* CTV */
2333 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
2334 return connector_status_connected
; /* STV */
2336 return connector_status_disconnected
;
2340 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder
*encoder
)
2342 struct drm_encoder
*ext_encoder
= radeon_get_external_encoder(encoder
);
2345 /* ddc_setup on the dp bridge */
2346 atombios_external_encoder_setup(encoder
, ext_encoder
,
2347 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
2351 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
2353 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
2354 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2355 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
2357 if ((radeon_encoder
->active_device
&
2358 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
2359 (radeon_encoder_get_dp_bridge_encoder_id(encoder
) !=
2360 ENCODER_OBJECT_ID_NONE
)) {
2361 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
2363 dig
->dig_encoder
= radeon_atom_pick_dig_encoder(encoder
);
2364 if (radeon_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
) {
2365 if (rdev
->family
>= CHIP_R600
)
2366 dig
->afmt
= rdev
->mode_info
.afmt
[dig
->dig_encoder
];
2368 /* RS600/690/740 have only 1 afmt block */
2369 dig
->afmt
= rdev
->mode_info
.afmt
[0];
2374 radeon_atom_output_lock(encoder
, true);
2377 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
2379 /* select the clock/data port if it uses a router */
2380 if (radeon_connector
->router
.cd_valid
)
2381 radeon_router_select_cd_port(radeon_connector
);
2383 /* turn eDP panel on for mode set */
2384 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
2385 atombios_set_edp_panel_power(connector
,
2386 ATOM_TRANSMITTER_ACTION_POWER_ON
);
2389 /* this is needed for the pll/ss setup to work correctly in some cases */
2390 atombios_set_encoder_crtc_source(encoder
);
2391 /* set up the FMT blocks */
2392 if (ASIC_IS_DCE8(rdev
))
2393 dce8_program_fmt(encoder
);
2394 else if (ASIC_IS_DCE4(rdev
))
2395 dce4_program_fmt(encoder
);
2396 else if (ASIC_IS_DCE3(rdev
))
2397 dce3_program_fmt(encoder
);
2398 else if (ASIC_IS_AVIVO(rdev
))
2399 avivo_program_fmt(encoder
);
2402 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
2404 /* need to call this here as we need the crtc set up */
2405 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
2406 radeon_atom_output_lock(encoder
, false);
2409 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
2411 struct drm_device
*dev
= encoder
->dev
;
2412 struct radeon_device
*rdev
= dev
->dev_private
;
2413 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2414 struct radeon_encoder_atom_dig
*dig
;
2416 /* check for pre-DCE3 cards with shared encoders;
2417 * can't really use the links individually, so don't disable
2418 * the encoder if it's in use by another connector
2420 if (!ASIC_IS_DCE3(rdev
)) {
2421 struct drm_encoder
*other_encoder
;
2422 struct radeon_encoder
*other_radeon_encoder
;
2424 list_for_each_entry(other_encoder
, &dev
->mode_config
.encoder_list
, head
) {
2425 other_radeon_encoder
= to_radeon_encoder(other_encoder
);
2426 if ((radeon_encoder
->encoder_id
== other_radeon_encoder
->encoder_id
) &&
2427 drm_helper_encoder_in_use(other_encoder
))
2432 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
2434 switch (radeon_encoder
->encoder_id
) {
2435 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2436 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2437 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2438 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2439 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_DISABLE
);
2441 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2442 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2443 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2444 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2445 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2446 /* handled in dpms */
2448 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2449 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2450 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2451 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
2453 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2454 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2455 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2456 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2457 atombios_dac_setup(encoder
, ATOM_DISABLE
);
2458 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2459 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2464 if (radeon_encoder_is_digital(encoder
)) {
2465 dig
= radeon_encoder
->enc_priv
;
2466 dig
->dig_encoder
= -1;
2468 radeon_encoder
->active_device
= 0;
2471 /* these are handled by the primary encoders */
2472 static void radeon_atom_ext_prepare(struct drm_encoder
*encoder
)
2477 static void radeon_atom_ext_commit(struct drm_encoder
*encoder
)
2483 radeon_atom_ext_mode_set(struct drm_encoder
*encoder
,
2484 struct drm_display_mode
*mode
,
2485 struct drm_display_mode
*adjusted_mode
)
2490 static void radeon_atom_ext_disable(struct drm_encoder
*encoder
)
2496 radeon_atom_ext_dpms(struct drm_encoder
*encoder
, int mode
)
2501 static bool radeon_atom_ext_mode_fixup(struct drm_encoder
*encoder
,
2502 const struct drm_display_mode
*mode
,
2503 struct drm_display_mode
*adjusted_mode
)
2508 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs
= {
2509 .dpms
= radeon_atom_ext_dpms
,
2510 .mode_fixup
= radeon_atom_ext_mode_fixup
,
2511 .prepare
= radeon_atom_ext_prepare
,
2512 .mode_set
= radeon_atom_ext_mode_set
,
2513 .commit
= radeon_atom_ext_commit
,
2514 .disable
= radeon_atom_ext_disable
,
2515 /* no detect for TMDS/LVDS yet */
2518 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
2519 .dpms
= radeon_atom_encoder_dpms
,
2520 .mode_fixup
= radeon_atom_mode_fixup
,
2521 .prepare
= radeon_atom_encoder_prepare
,
2522 .mode_set
= radeon_atom_encoder_mode_set
,
2523 .commit
= radeon_atom_encoder_commit
,
2524 .disable
= radeon_atom_encoder_disable
,
2525 .detect
= radeon_atom_dig_detect
,
2528 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
2529 .dpms
= radeon_atom_encoder_dpms
,
2530 .mode_fixup
= radeon_atom_mode_fixup
,
2531 .prepare
= radeon_atom_encoder_prepare
,
2532 .mode_set
= radeon_atom_encoder_mode_set
,
2533 .commit
= radeon_atom_encoder_commit
,
2534 .detect
= radeon_atom_dac_detect
,
2537 void radeon_enc_destroy(struct drm_encoder
*encoder
)
2539 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2540 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2541 radeon_atom_backlight_exit(radeon_encoder
);
2542 kfree(radeon_encoder
->enc_priv
);
2543 drm_encoder_cleanup(encoder
);
2544 kfree(radeon_encoder
);
2547 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
2548 .destroy
= radeon_enc_destroy
,
2551 static struct radeon_encoder_atom_dac
*
2552 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
2554 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
2555 struct radeon_device
*rdev
= dev
->dev_private
;
2556 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
2561 dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
2565 static struct radeon_encoder_atom_dig
*
2566 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
2568 int encoder_enum
= (radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2569 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
2574 /* coherent mode by default */
2575 dig
->coherent_mode
= true;
2576 dig
->dig_encoder
= -1;
2578 if (encoder_enum
== 2)
2587 radeon_add_atom_encoder(struct drm_device
*dev
,
2588 uint32_t encoder_enum
,
2589 uint32_t supported_device
,
2592 struct radeon_device
*rdev
= dev
->dev_private
;
2593 struct drm_encoder
*encoder
;
2594 struct radeon_encoder
*radeon_encoder
;
2596 /* see if we already added it */
2597 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2598 radeon_encoder
= to_radeon_encoder(encoder
);
2599 if (radeon_encoder
->encoder_enum
== encoder_enum
) {
2600 radeon_encoder
->devices
|= supported_device
;
2607 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
2608 if (!radeon_encoder
)
2611 encoder
= &radeon_encoder
->base
;
2612 switch (rdev
->num_crtc
) {
2614 encoder
->possible_crtcs
= 0x1;
2618 encoder
->possible_crtcs
= 0x3;
2621 encoder
->possible_crtcs
= 0xf;
2624 encoder
->possible_crtcs
= 0x3f;
2628 radeon_encoder
->enc_priv
= NULL
;
2630 radeon_encoder
->encoder_enum
= encoder_enum
;
2631 radeon_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
2632 radeon_encoder
->devices
= supported_device
;
2633 radeon_encoder
->rmx_type
= RMX_OFF
;
2634 radeon_encoder
->underscan_type
= UNDERSCAN_OFF
;
2635 radeon_encoder
->is_ext_encoder
= false;
2636 radeon_encoder
->caps
= caps
;
2638 switch (radeon_encoder
->encoder_id
) {
2639 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2640 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2641 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2642 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2643 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2644 radeon_encoder
->rmx_type
= RMX_FULL
;
2645 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2646 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2648 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2649 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2651 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2653 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2654 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2655 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2656 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2658 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2660 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2661 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
2662 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2663 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2665 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2666 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2667 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2668 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2669 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2670 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2671 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2672 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2673 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2674 radeon_encoder
->rmx_type
= RMX_FULL
;
2675 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2676 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2677 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
2678 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2679 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2681 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2682 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2684 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2686 case ENCODER_OBJECT_ID_SI170B
:
2687 case ENCODER_OBJECT_ID_CH7303
:
2688 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
2689 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
2690 case ENCODER_OBJECT_ID_TITFP513
:
2691 case ENCODER_OBJECT_ID_VT1623
:
2692 case ENCODER_OBJECT_ID_HDMI_SI1930
:
2693 case ENCODER_OBJECT_ID_TRAVIS
:
2694 case ENCODER_OBJECT_ID_NUTMEG
:
2695 /* these are handled by the primary encoders */
2696 radeon_encoder
->is_ext_encoder
= true;
2697 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2698 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2699 else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
2700 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2702 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2703 drm_encoder_helper_add(encoder
, &radeon_atom_ext_helper_funcs
);