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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / atombios_encoders.c
1 /*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "radeon_audio.h"
31 #include "atom.h"
32 #include <linux/backlight.h>
33
34 extern int atom_debug;
35
36 static u8
37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
38 {
39 u8 backlight_level;
40 u32 bios_2_scratch;
41
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
44 else
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
46
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
49
50 return backlight_level;
51 }
52
53 static void
54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
55 u8 backlight_level)
56 {
57 u32 bios_2_scratch;
58
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
61 else
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
63
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
67
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
70 else
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
72 }
73
74 u8
75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
76 {
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
79
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
81 return 0;
82
83 return radeon_atom_get_backlight_level_from_reg(rdev);
84 }
85
86 void
87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
88 {
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
94 int index;
95
96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
97 return;
98
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
101 dig = radeon_encoder->enc_priv;
102 dig->backlight_level = level;
103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
104
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
112 } else {
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
117 }
118 break;
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 else {
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
128 }
129 break;
130 default:
131 break;
132 }
133 }
134 }
135
136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137
138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
139 {
140 u8 level;
141
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
144 level = 0;
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
147 else
148 level = bd->props.brightness;
149
150 return level;
151 }
152
153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154 {
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
157
158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
159
160 return 0;
161 }
162
163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164 {
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
169
170 return radeon_atom_get_backlight_level_from_reg(rdev);
171 }
172
173 static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
176 };
177
178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
180 {
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
187 char bl_name[16];
188
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, drm_connector->kdev,
217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
225 dig = radeon_encoder->enc_priv;
226 dig->bl_dev = bd;
227
228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
232 * off again.
233 */
234 if (bd->props.brightness == 0)
235 bd->props.brightness = RADEON_MAX_BL_LEVEL;
236 bd->props.power = FB_BLANK_UNBLANK;
237 backlight_update_status(bd);
238
239 DRM_INFO("radeon atom DIG backlight initialized\n");
240 rdev->mode_info.bl_encoder = radeon_encoder;
241
242 return;
243
244 error:
245 kfree(pdata);
246 return;
247 }
248
249 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
250 {
251 struct drm_device *dev = radeon_encoder->base.dev;
252 struct radeon_device *rdev = dev->dev_private;
253 struct backlight_device *bd = NULL;
254 struct radeon_encoder_atom_dig *dig;
255
256 if (!radeon_encoder->enc_priv)
257 return;
258
259 if (!rdev->is_atom_bios)
260 return;
261
262 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
263 return;
264
265 dig = radeon_encoder->enc_priv;
266 bd = dig->bl_dev;
267 dig->bl_dev = NULL;
268
269 if (bd) {
270 struct radeon_legacy_backlight_privdata *pdata;
271
272 pdata = bl_get_data(bd);
273 backlight_device_unregister(bd);
274 kfree(pdata);
275
276 DRM_INFO("radeon atom LVDS backlight unloaded\n");
277 }
278 }
279
280 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
281
282 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
283 {
284 }
285
286 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
287 {
288 }
289
290 #endif
291
292 /* evil but including atombios.h is much worse */
293 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
294 struct drm_display_mode *mode);
295
296 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
297 const struct drm_display_mode *mode,
298 struct drm_display_mode *adjusted_mode)
299 {
300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
301 struct drm_device *dev = encoder->dev;
302 struct radeon_device *rdev = dev->dev_private;
303
304 /* set the active encoder to connector routing */
305 radeon_encoder_set_active_device(encoder);
306 drm_mode_set_crtcinfo(adjusted_mode, 0);
307
308 /* hw bug */
309 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
310 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
311 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
312
313 /* get the native mode for scaling */
314 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
315 radeon_panel_mode_fixup(encoder, adjusted_mode);
316 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
317 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
318 if (tv_dac) {
319 if (tv_dac->tv_std == TV_STD_NTSC ||
320 tv_dac->tv_std == TV_STD_NTSC_J ||
321 tv_dac->tv_std == TV_STD_PAL_M)
322 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
323 else
324 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
325 }
326 } else if (radeon_encoder->rmx_type != RMX_OFF) {
327 radeon_panel_mode_fixup(encoder, adjusted_mode);
328 }
329
330 if (ASIC_IS_DCE3(rdev) &&
331 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
332 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
333 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
334 radeon_dp_set_link_config(connector, adjusted_mode);
335 }
336
337 return true;
338 }
339
340 static void
341 atombios_dac_setup(struct drm_encoder *encoder, int action)
342 {
343 struct drm_device *dev = encoder->dev;
344 struct radeon_device *rdev = dev->dev_private;
345 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
346 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
347 int index = 0;
348 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
349
350 memset(&args, 0, sizeof(args));
351
352 switch (radeon_encoder->encoder_id) {
353 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
354 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
355 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
356 break;
357 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
358 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
359 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
360 break;
361 }
362
363 args.ucAction = action;
364
365 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
366 args.ucDacStandard = ATOM_DAC1_PS2;
367 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
368 args.ucDacStandard = ATOM_DAC1_CV;
369 else {
370 switch (dac_info->tv_std) {
371 case TV_STD_PAL:
372 case TV_STD_PAL_M:
373 case TV_STD_SCART_PAL:
374 case TV_STD_SECAM:
375 case TV_STD_PAL_CN:
376 args.ucDacStandard = ATOM_DAC1_PAL;
377 break;
378 case TV_STD_NTSC:
379 case TV_STD_NTSC_J:
380 case TV_STD_PAL_60:
381 default:
382 args.ucDacStandard = ATOM_DAC1_NTSC;
383 break;
384 }
385 }
386 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
387
388 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
389
390 }
391
392 static void
393 atombios_tv_setup(struct drm_encoder *encoder, int action)
394 {
395 struct drm_device *dev = encoder->dev;
396 struct radeon_device *rdev = dev->dev_private;
397 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
398 TV_ENCODER_CONTROL_PS_ALLOCATION args;
399 int index = 0;
400 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
401
402 memset(&args, 0, sizeof(args));
403
404 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
405
406 args.sTVEncoder.ucAction = action;
407
408 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
409 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
410 else {
411 switch (dac_info->tv_std) {
412 case TV_STD_NTSC:
413 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
414 break;
415 case TV_STD_PAL:
416 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
417 break;
418 case TV_STD_PAL_M:
419 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
420 break;
421 case TV_STD_PAL_60:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
423 break;
424 case TV_STD_NTSC_J:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
426 break;
427 case TV_STD_SCART_PAL:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
429 break;
430 case TV_STD_SECAM:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
432 break;
433 case TV_STD_PAL_CN:
434 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
435 break;
436 default:
437 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
438 break;
439 }
440 }
441
442 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
443
444 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
445
446 }
447
448 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
449 {
450 int bpc = 8;
451
452 if (encoder->crtc) {
453 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
454 bpc = radeon_crtc->bpc;
455 }
456
457 switch (bpc) {
458 case 0:
459 return PANEL_BPC_UNDEFINE;
460 case 6:
461 return PANEL_6BIT_PER_COLOR;
462 case 8:
463 default:
464 return PANEL_8BIT_PER_COLOR;
465 case 10:
466 return PANEL_10BIT_PER_COLOR;
467 case 12:
468 return PANEL_12BIT_PER_COLOR;
469 case 16:
470 return PANEL_16BIT_PER_COLOR;
471 }
472 }
473
474 union dvo_encoder_control {
475 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
476 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
477 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
478 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
479 };
480
481 void
482 atombios_dvo_setup(struct drm_encoder *encoder, int action)
483 {
484 struct drm_device *dev = encoder->dev;
485 struct radeon_device *rdev = dev->dev_private;
486 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
487 union dvo_encoder_control args;
488 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
489 uint8_t frev, crev;
490
491 memset(&args, 0, sizeof(args));
492
493 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
494 return;
495
496 /* some R4xx chips have the wrong frev */
497 if (rdev->family <= CHIP_RV410)
498 frev = 1;
499
500 switch (frev) {
501 case 1:
502 switch (crev) {
503 case 1:
504 /* R4xx, R5xx */
505 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
506
507 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
508 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
509
510 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
511 break;
512 case 2:
513 /* RS600/690/740 */
514 args.dvo.sDVOEncoder.ucAction = action;
515 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
516 /* DFP1, CRT1, TV1 depending on the type of port */
517 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
518
519 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
520 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
521 break;
522 case 3:
523 /* R6xx */
524 args.dvo_v3.ucAction = action;
525 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
526 args.dvo_v3.ucDVOConfig = 0; /* XXX */
527 break;
528 case 4:
529 /* DCE8 */
530 args.dvo_v4.ucAction = action;
531 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
532 args.dvo_v4.ucDVOConfig = 0; /* XXX */
533 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
534 break;
535 default:
536 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
537 break;
538 }
539 break;
540 default:
541 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
542 break;
543 }
544
545 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
546 }
547
548 union lvds_encoder_control {
549 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
550 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
551 };
552
553 void
554 atombios_digital_setup(struct drm_encoder *encoder, int action)
555 {
556 struct drm_device *dev = encoder->dev;
557 struct radeon_device *rdev = dev->dev_private;
558 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
559 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
560 union lvds_encoder_control args;
561 int index = 0;
562 int hdmi_detected = 0;
563 uint8_t frev, crev;
564
565 if (!dig)
566 return;
567
568 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
569 hdmi_detected = 1;
570
571 memset(&args, 0, sizeof(args));
572
573 switch (radeon_encoder->encoder_id) {
574 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
575 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
576 break;
577 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
579 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
580 break;
581 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
582 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
583 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
584 else
585 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
586 break;
587 }
588
589 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
590 return;
591
592 switch (frev) {
593 case 1:
594 case 2:
595 switch (crev) {
596 case 1:
597 args.v1.ucMisc = 0;
598 args.v1.ucAction = action;
599 if (hdmi_detected)
600 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
601 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
602 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
603 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
604 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
605 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
606 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
607 } else {
608 if (dig->linkb)
609 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
610 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
611 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
612 /*if (pScrn->rgbBits == 8) */
613 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
614 }
615 break;
616 case 2:
617 case 3:
618 args.v2.ucMisc = 0;
619 args.v2.ucAction = action;
620 if (crev == 3) {
621 if (dig->coherent_mode)
622 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
623 }
624 if (hdmi_detected)
625 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
626 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
627 args.v2.ucTruncate = 0;
628 args.v2.ucSpatial = 0;
629 args.v2.ucTemporal = 0;
630 args.v2.ucFRC = 0;
631 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
632 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
633 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
634 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
635 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
636 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
637 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
638 }
639 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
640 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
641 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
642 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
643 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
644 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
645 }
646 } else {
647 if (dig->linkb)
648 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
649 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
650 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
651 }
652 break;
653 default:
654 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
655 break;
656 }
657 break;
658 default:
659 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
660 break;
661 }
662
663 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
664 }
665
666 int
667 atombios_get_encoder_mode(struct drm_encoder *encoder)
668 {
669 struct drm_device *dev = encoder->dev;
670 struct radeon_device *rdev = dev->dev_private;
671 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
672 struct drm_connector *connector;
673 struct radeon_connector *radeon_connector;
674 struct radeon_connector_atom_dig *dig_connector;
675 struct radeon_encoder_atom_dig *dig_enc;
676
677 if (radeon_encoder_is_digital(encoder)) {
678 dig_enc = radeon_encoder->enc_priv;
679 if (dig_enc->active_mst_links)
680 return ATOM_ENCODER_MODE_DP_MST;
681 }
682 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
683 return ATOM_ENCODER_MODE_DP_MST;
684 /* dp bridges are always DP */
685 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
686 return ATOM_ENCODER_MODE_DP;
687
688 /* DVO is always DVO */
689 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
690 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
691 return ATOM_ENCODER_MODE_DVO;
692
693 connector = radeon_get_connector_for_encoder(encoder);
694 /* if we don't have an active device yet, just use one of
695 * the connectors tied to the encoder.
696 */
697 if (!connector)
698 connector = radeon_get_connector_for_encoder_init(encoder);
699 radeon_connector = to_radeon_connector(connector);
700
701 switch (connector->connector_type) {
702 case DRM_MODE_CONNECTOR_DVII:
703 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
704 if (radeon_audio != 0) {
705 if (radeon_connector->use_digital &&
706 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
707 return ATOM_ENCODER_MODE_HDMI;
708 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
709 (radeon_connector->audio == RADEON_AUDIO_AUTO))
710 return ATOM_ENCODER_MODE_HDMI;
711 else if (radeon_connector->use_digital)
712 return ATOM_ENCODER_MODE_DVI;
713 else
714 return ATOM_ENCODER_MODE_CRT;
715 } else if (radeon_connector->use_digital) {
716 return ATOM_ENCODER_MODE_DVI;
717 } else {
718 return ATOM_ENCODER_MODE_CRT;
719 }
720 break;
721 case DRM_MODE_CONNECTOR_DVID:
722 case DRM_MODE_CONNECTOR_HDMIA:
723 default:
724 if (radeon_audio != 0) {
725 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
726 return ATOM_ENCODER_MODE_HDMI;
727 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
728 (radeon_connector->audio == RADEON_AUDIO_AUTO))
729 return ATOM_ENCODER_MODE_HDMI;
730 else
731 return ATOM_ENCODER_MODE_DVI;
732 } else {
733 return ATOM_ENCODER_MODE_DVI;
734 }
735 break;
736 case DRM_MODE_CONNECTOR_LVDS:
737 return ATOM_ENCODER_MODE_LVDS;
738 break;
739 case DRM_MODE_CONNECTOR_DisplayPort:
740 dig_connector = radeon_connector->con_priv;
741 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
742 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
743 if (radeon_audio != 0 &&
744 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
745 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
746 return ATOM_ENCODER_MODE_DP_AUDIO;
747 return ATOM_ENCODER_MODE_DP;
748 } else if (radeon_audio != 0) {
749 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
750 return ATOM_ENCODER_MODE_HDMI;
751 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
752 (radeon_connector->audio == RADEON_AUDIO_AUTO))
753 return ATOM_ENCODER_MODE_HDMI;
754 else
755 return ATOM_ENCODER_MODE_DVI;
756 } else {
757 return ATOM_ENCODER_MODE_DVI;
758 }
759 break;
760 case DRM_MODE_CONNECTOR_eDP:
761 if (radeon_audio != 0 &&
762 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
763 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
764 return ATOM_ENCODER_MODE_DP_AUDIO;
765 return ATOM_ENCODER_MODE_DP;
766 case DRM_MODE_CONNECTOR_DVIA:
767 case DRM_MODE_CONNECTOR_VGA:
768 return ATOM_ENCODER_MODE_CRT;
769 break;
770 case DRM_MODE_CONNECTOR_Composite:
771 case DRM_MODE_CONNECTOR_SVIDEO:
772 case DRM_MODE_CONNECTOR_9PinDIN:
773 /* fix me */
774 return ATOM_ENCODER_MODE_TV;
775 /*return ATOM_ENCODER_MODE_CV;*/
776 break;
777 }
778 }
779
780 /*
781 * DIG Encoder/Transmitter Setup
782 *
783 * DCE 3.0/3.1
784 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
785 * Supports up to 3 digital outputs
786 * - 2 DIG encoder blocks.
787 * DIG1 can drive UNIPHY link A or link B
788 * DIG2 can drive UNIPHY link B or LVTMA
789 *
790 * DCE 3.2
791 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
792 * Supports up to 5 digital outputs
793 * - 2 DIG encoder blocks.
794 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
795 *
796 * DCE 4.0/5.0/6.0
797 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
798 * Supports up to 6 digital outputs
799 * - 6 DIG encoder blocks.
800 * - DIG to PHY mapping is hardcoded
801 * DIG1 drives UNIPHY0 link A, A+B
802 * DIG2 drives UNIPHY0 link B
803 * DIG3 drives UNIPHY1 link A, A+B
804 * DIG4 drives UNIPHY1 link B
805 * DIG5 drives UNIPHY2 link A, A+B
806 * DIG6 drives UNIPHY2 link B
807 *
808 * DCE 4.1
809 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
810 * Supports up to 6 digital outputs
811 * - 2 DIG encoder blocks.
812 * llano
813 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
814 * ontario
815 * DIG1 drives UNIPHY0/1/2 link A
816 * DIG2 drives UNIPHY0/1/2 link B
817 *
818 * Routing
819 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
820 * Examples:
821 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
822 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
823 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
824 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
825 */
826
827 union dig_encoder_control {
828 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
829 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
830 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
831 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
832 };
833
834 void
835 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
836 {
837 struct drm_device *dev = encoder->dev;
838 struct radeon_device *rdev = dev->dev_private;
839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
840 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
841 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
842 union dig_encoder_control args;
843 int index = 0;
844 uint8_t frev, crev;
845 int dp_clock = 0;
846 int dp_lane_count = 0;
847 int hpd_id = RADEON_HPD_NONE;
848
849 if (connector) {
850 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
851 struct radeon_connector_atom_dig *dig_connector =
852 radeon_connector->con_priv;
853
854 dp_clock = dig_connector->dp_clock;
855 dp_lane_count = dig_connector->dp_lane_count;
856 hpd_id = radeon_connector->hpd.hpd;
857 }
858
859 /* no dig encoder assigned */
860 if (dig->dig_encoder == -1)
861 return;
862
863 memset(&args, 0, sizeof(args));
864
865 if (ASIC_IS_DCE4(rdev))
866 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
867 else {
868 if (dig->dig_encoder)
869 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
870 else
871 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
872 }
873
874 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
875 return;
876
877 switch (frev) {
878 case 1:
879 switch (crev) {
880 case 1:
881 args.v1.ucAction = action;
882 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
883 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
884 args.v3.ucPanelMode = panel_mode;
885 else
886 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
887
888 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
889 args.v1.ucLaneNum = dp_lane_count;
890 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
891 args.v1.ucLaneNum = 8;
892 else
893 args.v1.ucLaneNum = 4;
894
895 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
896 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
897 switch (radeon_encoder->encoder_id) {
898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
899 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
900 break;
901 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
902 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
903 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
904 break;
905 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
906 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
907 break;
908 }
909 if (dig->linkb)
910 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
911 else
912 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
913 break;
914 case 2:
915 case 3:
916 args.v3.ucAction = action;
917 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
918 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
919 args.v3.ucPanelMode = panel_mode;
920 else
921 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
922
923 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
924 args.v3.ucLaneNum = dp_lane_count;
925 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
926 args.v3.ucLaneNum = 8;
927 else
928 args.v3.ucLaneNum = 4;
929
930 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
931 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
932 if (enc_override != -1)
933 args.v3.acConfig.ucDigSel = enc_override;
934 else
935 args.v3.acConfig.ucDigSel = dig->dig_encoder;
936 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
937 break;
938 case 4:
939 args.v4.ucAction = action;
940 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
941 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
942 args.v4.ucPanelMode = panel_mode;
943 else
944 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
945
946 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
947 args.v4.ucLaneNum = dp_lane_count;
948 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
949 args.v4.ucLaneNum = 8;
950 else
951 args.v4.ucLaneNum = 4;
952
953 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
954 if (dp_clock == 540000)
955 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
956 else if (dp_clock == 324000)
957 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
958 else if (dp_clock == 270000)
959 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
960 else
961 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
962 }
963
964 if (enc_override != -1)
965 args.v4.acConfig.ucDigSel = enc_override;
966 else
967 args.v4.acConfig.ucDigSel = dig->dig_encoder;
968 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
969 if (hpd_id == RADEON_HPD_NONE)
970 args.v4.ucHPD_ID = 0;
971 else
972 args.v4.ucHPD_ID = hpd_id + 1;
973 break;
974 default:
975 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
976 break;
977 }
978 break;
979 default:
980 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
981 break;
982 }
983
984 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
985
986 }
987
988 void
989 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
990 {
991 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
992 }
993
994 union dig_transmitter_control {
995 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
996 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
997 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
998 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
999 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1000 };
1001
1002 void
1003 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1004 {
1005 struct drm_device *dev = encoder->dev;
1006 struct radeon_device *rdev = dev->dev_private;
1007 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1008 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1009 struct drm_connector *connector;
1010 union dig_transmitter_control args;
1011 int index = 0;
1012 uint8_t frev, crev;
1013 bool is_dp = false;
1014 int pll_id = 0;
1015 int dp_clock = 0;
1016 int dp_lane_count = 0;
1017 int connector_object_id = 0;
1018 int igp_lane_info = 0;
1019 int dig_encoder = dig->dig_encoder;
1020 int hpd_id = RADEON_HPD_NONE;
1021
1022 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1023 connector = radeon_get_connector_for_encoder_init(encoder);
1024 /* just needed to avoid bailing in the encoder check. the encoder
1025 * isn't used for init
1026 */
1027 dig_encoder = 0;
1028 } else
1029 connector = radeon_get_connector_for_encoder(encoder);
1030
1031 if (connector) {
1032 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1033 struct radeon_connector_atom_dig *dig_connector =
1034 radeon_connector->con_priv;
1035
1036 hpd_id = radeon_connector->hpd.hpd;
1037 dp_clock = dig_connector->dp_clock;
1038 dp_lane_count = dig_connector->dp_lane_count;
1039 connector_object_id =
1040 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1041 igp_lane_info = dig_connector->igp_lane_info;
1042 }
1043
1044 if (encoder->crtc) {
1045 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1046 pll_id = radeon_crtc->pll_id;
1047 }
1048
1049 /* no dig encoder assigned */
1050 if (dig_encoder == -1)
1051 return;
1052
1053 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1054 is_dp = true;
1055
1056 memset(&args, 0, sizeof(args));
1057
1058 switch (radeon_encoder->encoder_id) {
1059 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1060 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1061 break;
1062 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1065 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1066 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1067 break;
1068 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1069 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1070 break;
1071 }
1072
1073 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1074 return;
1075
1076 switch (frev) {
1077 case 1:
1078 switch (crev) {
1079 case 1:
1080 args.v1.ucAction = action;
1081 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1082 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1083 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1084 args.v1.asMode.ucLaneSel = lane_num;
1085 args.v1.asMode.ucLaneSet = lane_set;
1086 } else {
1087 if (is_dp)
1088 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1089 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1090 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1091 else
1092 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1093 }
1094
1095 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1096
1097 if (dig_encoder)
1098 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1099 else
1100 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1101
1102 if ((rdev->flags & RADEON_IS_IGP) &&
1103 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1104 if (is_dp ||
1105 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1106 if (igp_lane_info & 0x1)
1107 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1108 else if (igp_lane_info & 0x2)
1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1110 else if (igp_lane_info & 0x4)
1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1112 else if (igp_lane_info & 0x8)
1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1114 } else {
1115 if (igp_lane_info & 0x3)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1117 else if (igp_lane_info & 0xc)
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1119 }
1120 }
1121
1122 if (dig->linkb)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1124 else
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1126
1127 if (is_dp)
1128 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1129 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1130 if (dig->coherent_mode)
1131 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1132 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1133 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1134 }
1135 break;
1136 case 2:
1137 args.v2.ucAction = action;
1138 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1139 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1140 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1141 args.v2.asMode.ucLaneSel = lane_num;
1142 args.v2.asMode.ucLaneSet = lane_set;
1143 } else {
1144 if (is_dp)
1145 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1146 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1147 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1148 else
1149 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1150 }
1151
1152 args.v2.acConfig.ucEncoderSel = dig_encoder;
1153 if (dig->linkb)
1154 args.v2.acConfig.ucLinkSel = 1;
1155
1156 switch (radeon_encoder->encoder_id) {
1157 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1158 args.v2.acConfig.ucTransmitterSel = 0;
1159 break;
1160 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1161 args.v2.acConfig.ucTransmitterSel = 1;
1162 break;
1163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1164 args.v2.acConfig.ucTransmitterSel = 2;
1165 break;
1166 }
1167
1168 if (is_dp) {
1169 args.v2.acConfig.fCoherentMode = 1;
1170 args.v2.acConfig.fDPConnector = 1;
1171 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1172 if (dig->coherent_mode)
1173 args.v2.acConfig.fCoherentMode = 1;
1174 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1175 args.v2.acConfig.fDualLinkConnector = 1;
1176 }
1177 break;
1178 case 3:
1179 args.v3.ucAction = action;
1180 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1181 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1182 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1183 args.v3.asMode.ucLaneSel = lane_num;
1184 args.v3.asMode.ucLaneSet = lane_set;
1185 } else {
1186 if (is_dp)
1187 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1188 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1189 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1190 else
1191 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1192 }
1193
1194 if (is_dp)
1195 args.v3.ucLaneNum = dp_lane_count;
1196 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1197 args.v3.ucLaneNum = 8;
1198 else
1199 args.v3.ucLaneNum = 4;
1200
1201 if (dig->linkb)
1202 args.v3.acConfig.ucLinkSel = 1;
1203 if (dig_encoder & 1)
1204 args.v3.acConfig.ucEncoderSel = 1;
1205
1206 /* Select the PLL for the PHY
1207 * DP PHY should be clocked from external src if there is
1208 * one.
1209 */
1210 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1211 if (is_dp && rdev->clock.dp_extclk)
1212 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1213 else
1214 args.v3.acConfig.ucRefClkSource = pll_id;
1215
1216 switch (radeon_encoder->encoder_id) {
1217 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1218 args.v3.acConfig.ucTransmitterSel = 0;
1219 break;
1220 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1221 args.v3.acConfig.ucTransmitterSel = 1;
1222 break;
1223 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1224 args.v3.acConfig.ucTransmitterSel = 2;
1225 break;
1226 }
1227
1228 if (is_dp)
1229 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1230 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1231 if (dig->coherent_mode)
1232 args.v3.acConfig.fCoherentMode = 1;
1233 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1234 args.v3.acConfig.fDualLinkConnector = 1;
1235 }
1236 break;
1237 case 4:
1238 args.v4.ucAction = action;
1239 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1240 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1241 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1242 args.v4.asMode.ucLaneSel = lane_num;
1243 args.v4.asMode.ucLaneSet = lane_set;
1244 } else {
1245 if (is_dp)
1246 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1247 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1248 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1249 else
1250 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1251 }
1252
1253 if (is_dp)
1254 args.v4.ucLaneNum = dp_lane_count;
1255 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1256 args.v4.ucLaneNum = 8;
1257 else
1258 args.v4.ucLaneNum = 4;
1259
1260 if (dig->linkb)
1261 args.v4.acConfig.ucLinkSel = 1;
1262 if (dig_encoder & 1)
1263 args.v4.acConfig.ucEncoderSel = 1;
1264
1265 /* Select the PLL for the PHY
1266 * DP PHY should be clocked from external src if there is
1267 * one.
1268 */
1269 /* On DCE5 DCPLL usually generates the DP ref clock */
1270 if (is_dp) {
1271 if (rdev->clock.dp_extclk)
1272 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1273 else
1274 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1275 } else
1276 args.v4.acConfig.ucRefClkSource = pll_id;
1277
1278 switch (radeon_encoder->encoder_id) {
1279 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1280 args.v4.acConfig.ucTransmitterSel = 0;
1281 break;
1282 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1283 args.v4.acConfig.ucTransmitterSel = 1;
1284 break;
1285 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1286 args.v4.acConfig.ucTransmitterSel = 2;
1287 break;
1288 }
1289
1290 if (is_dp)
1291 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1292 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1293 if (dig->coherent_mode)
1294 args.v4.acConfig.fCoherentMode = 1;
1295 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1296 args.v4.acConfig.fDualLinkConnector = 1;
1297 }
1298 break;
1299 case 5:
1300 args.v5.ucAction = action;
1301 if (is_dp)
1302 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1303 else
1304 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1305
1306 switch (radeon_encoder->encoder_id) {
1307 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1308 if (dig->linkb)
1309 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1310 else
1311 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1312 break;
1313 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1314 if (dig->linkb)
1315 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1316 else
1317 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1318 break;
1319 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1320 if (dig->linkb)
1321 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1322 else
1323 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1324 break;
1325 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1326 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1327 break;
1328 }
1329 if (is_dp)
1330 args.v5.ucLaneNum = dp_lane_count;
1331 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1332 args.v5.ucLaneNum = 8;
1333 else
1334 args.v5.ucLaneNum = 4;
1335 args.v5.ucConnObjId = connector_object_id;
1336 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1337
1338 if (is_dp && rdev->clock.dp_extclk)
1339 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1340 else
1341 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1342
1343 if (is_dp)
1344 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1345 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1346 if (dig->coherent_mode)
1347 args.v5.asConfig.ucCoherentMode = 1;
1348 }
1349 if (hpd_id == RADEON_HPD_NONE)
1350 args.v5.asConfig.ucHPDSel = 0;
1351 else
1352 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1353 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1354 args.v5.ucDPLaneSet = lane_set;
1355 break;
1356 default:
1357 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1358 break;
1359 }
1360 break;
1361 default:
1362 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1363 break;
1364 }
1365
1366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1367 }
1368
1369 void
1370 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1371 {
1372 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1373 }
1374
1375 bool
1376 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1377 {
1378 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1379 struct drm_device *dev = radeon_connector->base.dev;
1380 struct radeon_device *rdev = dev->dev_private;
1381 union dig_transmitter_control args;
1382 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1383 uint8_t frev, crev;
1384
1385 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1386 goto done;
1387
1388 if (!ASIC_IS_DCE4(rdev))
1389 goto done;
1390
1391 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1392 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1393 goto done;
1394
1395 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1396 goto done;
1397
1398 memset(&args, 0, sizeof(args));
1399
1400 args.v1.ucAction = action;
1401
1402 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1403
1404 /* wait for the panel to power up */
1405 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1406 int i;
1407
1408 for (i = 0; i < 300; i++) {
1409 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1410 return true;
1411 mdelay(1);
1412 }
1413 return false;
1414 }
1415 done:
1416 return true;
1417 }
1418
1419 union external_encoder_control {
1420 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1421 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1422 };
1423
1424 static void
1425 atombios_external_encoder_setup(struct drm_encoder *encoder,
1426 struct drm_encoder *ext_encoder,
1427 int action)
1428 {
1429 struct drm_device *dev = encoder->dev;
1430 struct radeon_device *rdev = dev->dev_private;
1431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1432 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1433 union external_encoder_control args;
1434 struct drm_connector *connector;
1435 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1436 u8 frev, crev;
1437 int dp_clock = 0;
1438 int dp_lane_count = 0;
1439 int connector_object_id = 0;
1440 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1441
1442 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1443 connector = radeon_get_connector_for_encoder_init(encoder);
1444 else
1445 connector = radeon_get_connector_for_encoder(encoder);
1446
1447 if (connector) {
1448 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1449 struct radeon_connector_atom_dig *dig_connector =
1450 radeon_connector->con_priv;
1451
1452 dp_clock = dig_connector->dp_clock;
1453 dp_lane_count = dig_connector->dp_lane_count;
1454 connector_object_id =
1455 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1456 }
1457
1458 memset(&args, 0, sizeof(args));
1459
1460 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1461 return;
1462
1463 switch (frev) {
1464 case 1:
1465 /* no params on frev 1 */
1466 break;
1467 case 2:
1468 switch (crev) {
1469 case 1:
1470 case 2:
1471 args.v1.sDigEncoder.ucAction = action;
1472 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1473 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1474
1475 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1476 if (dp_clock == 270000)
1477 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1478 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1479 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1480 args.v1.sDigEncoder.ucLaneNum = 8;
1481 else
1482 args.v1.sDigEncoder.ucLaneNum = 4;
1483 break;
1484 case 3:
1485 args.v3.sExtEncoder.ucAction = action;
1486 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1487 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1488 else
1489 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1490 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1491
1492 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1493 if (dp_clock == 270000)
1494 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1495 else if (dp_clock == 540000)
1496 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1497 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1498 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1499 args.v3.sExtEncoder.ucLaneNum = 8;
1500 else
1501 args.v3.sExtEncoder.ucLaneNum = 4;
1502 switch (ext_enum) {
1503 case GRAPH_OBJECT_ENUM_ID1:
1504 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1505 break;
1506 case GRAPH_OBJECT_ENUM_ID2:
1507 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1508 break;
1509 case GRAPH_OBJECT_ENUM_ID3:
1510 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1511 break;
1512 }
1513 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1514 break;
1515 default:
1516 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1517 return;
1518 }
1519 break;
1520 default:
1521 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1522 return;
1523 }
1524 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1525 }
1526
1527 static void
1528 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1529 {
1530 struct drm_device *dev = encoder->dev;
1531 struct radeon_device *rdev = dev->dev_private;
1532 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1533 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1534 ENABLE_YUV_PS_ALLOCATION args;
1535 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1536 uint32_t temp, reg;
1537
1538 memset(&args, 0, sizeof(args));
1539
1540 if (rdev->family >= CHIP_R600)
1541 reg = R600_BIOS_3_SCRATCH;
1542 else
1543 reg = RADEON_BIOS_3_SCRATCH;
1544
1545 /* XXX: fix up scratch reg handling */
1546 temp = RREG32(reg);
1547 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1548 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1549 (radeon_crtc->crtc_id << 18)));
1550 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1551 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1552 else
1553 WREG32(reg, 0);
1554
1555 if (enable)
1556 args.ucEnable = ATOM_ENABLE;
1557 args.ucCRTC = radeon_crtc->crtc_id;
1558
1559 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1560
1561 WREG32(reg, temp);
1562 }
1563
1564 static void
1565 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1566 {
1567 struct drm_device *dev = encoder->dev;
1568 struct radeon_device *rdev = dev->dev_private;
1569 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1570 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1571 int index = 0;
1572
1573 memset(&args, 0, sizeof(args));
1574
1575 switch (radeon_encoder->encoder_id) {
1576 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1578 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1579 break;
1580 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1581 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1582 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1583 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1584 break;
1585 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1586 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1587 break;
1588 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1590 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1591 else
1592 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1593 break;
1594 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1595 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1596 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1597 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1598 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1599 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1600 else
1601 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1602 break;
1603 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1604 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1605 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1606 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1607 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1608 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1609 else
1610 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1611 break;
1612 default:
1613 return;
1614 }
1615
1616 switch (mode) {
1617 case DRM_MODE_DPMS_ON:
1618 args.ucAction = ATOM_ENABLE;
1619 /* workaround for DVOOutputControl on some RS690 systems */
1620 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1621 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1622 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1623 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1624 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1625 } else
1626 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1627 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1628 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1629
1630 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1631 }
1632 break;
1633 case DRM_MODE_DPMS_STANDBY:
1634 case DRM_MODE_DPMS_SUSPEND:
1635 case DRM_MODE_DPMS_OFF:
1636 args.ucAction = ATOM_DISABLE;
1637 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1638 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1639 args.ucAction = ATOM_LCD_BLOFF;
1640 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1641 }
1642 break;
1643 }
1644 }
1645
1646 static void
1647 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1648 {
1649 struct drm_device *dev = encoder->dev;
1650 struct radeon_device *rdev = dev->dev_private;
1651 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1652 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1653 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1654 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1655 struct radeon_connector *radeon_connector = NULL;
1656 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1657 bool travis_quirk = false;
1658
1659 if (connector) {
1660 radeon_connector = to_radeon_connector(connector);
1661 radeon_dig_connector = radeon_connector->con_priv;
1662 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1663 ENCODER_OBJECT_ID_TRAVIS) &&
1664 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1665 !ASIC_IS_DCE5(rdev))
1666 travis_quirk = true;
1667 }
1668
1669 switch (mode) {
1670 case DRM_MODE_DPMS_ON:
1671 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1672 if (!connector)
1673 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1674 else
1675 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1676
1677 /* setup and enable the encoder */
1678 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1679 atombios_dig_encoder_setup(encoder,
1680 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1681 dig->panel_mode);
1682 if (ext_encoder) {
1683 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1684 atombios_external_encoder_setup(encoder, ext_encoder,
1685 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1686 }
1687 } else if (ASIC_IS_DCE4(rdev)) {
1688 /* setup and enable the encoder */
1689 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1690 } else {
1691 /* setup and enable the encoder and transmitter */
1692 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1693 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1694 }
1695 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1696 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1697 atombios_set_edp_panel_power(connector,
1698 ATOM_TRANSMITTER_ACTION_POWER_ON);
1699 radeon_dig_connector->edp_on = true;
1700 }
1701 }
1702 /* enable the transmitter */
1703 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1704 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1705 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1706 radeon_dp_link_train(encoder, connector);
1707 if (ASIC_IS_DCE4(rdev))
1708 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1709 }
1710 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1711 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1712 if (ext_encoder)
1713 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1714 break;
1715 case DRM_MODE_DPMS_STANDBY:
1716 case DRM_MODE_DPMS_SUSPEND:
1717 case DRM_MODE_DPMS_OFF:
1718
1719 /* don't power off encoders with active MST links */
1720 if (dig->active_mst_links)
1721 return;
1722
1723 if (ASIC_IS_DCE4(rdev)) {
1724 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1725 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1726 }
1727 if (ext_encoder)
1728 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1729 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1730 atombios_dig_transmitter_setup(encoder,
1731 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1732
1733 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1734 connector && !travis_quirk)
1735 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1736 if (ASIC_IS_DCE4(rdev)) {
1737 /* disable the transmitter */
1738 atombios_dig_transmitter_setup(encoder,
1739 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1740 } else {
1741 /* disable the encoder and transmitter */
1742 atombios_dig_transmitter_setup(encoder,
1743 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1744 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1745 }
1746 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1747 if (travis_quirk)
1748 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1749 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1750 atombios_set_edp_panel_power(connector,
1751 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1752 radeon_dig_connector->edp_on = false;
1753 }
1754 }
1755 break;
1756 }
1757 }
1758
1759 static void
1760 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1761 {
1762 struct drm_device *dev = encoder->dev;
1763 struct radeon_device *rdev = dev->dev_private;
1764 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1765 int encoder_mode = atombios_get_encoder_mode(encoder);
1766
1767 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1768 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1769 radeon_encoder->active_device);
1770
1771 if ((radeon_audio != 0) &&
1772 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1773 ENCODER_MODE_IS_DP(encoder_mode)))
1774 radeon_audio_dpms(encoder, mode);
1775
1776 switch (radeon_encoder->encoder_id) {
1777 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1778 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1779 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1780 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1781 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1782 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1783 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1784 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1785 radeon_atom_encoder_dpms_avivo(encoder, mode);
1786 break;
1787 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1788 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1789 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1790 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1791 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1792 radeon_atom_encoder_dpms_dig(encoder, mode);
1793 break;
1794 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1795 if (ASIC_IS_DCE5(rdev)) {
1796 switch (mode) {
1797 case DRM_MODE_DPMS_ON:
1798 atombios_dvo_setup(encoder, ATOM_ENABLE);
1799 break;
1800 case DRM_MODE_DPMS_STANDBY:
1801 case DRM_MODE_DPMS_SUSPEND:
1802 case DRM_MODE_DPMS_OFF:
1803 atombios_dvo_setup(encoder, ATOM_DISABLE);
1804 break;
1805 }
1806 } else if (ASIC_IS_DCE3(rdev))
1807 radeon_atom_encoder_dpms_dig(encoder, mode);
1808 else
1809 radeon_atom_encoder_dpms_avivo(encoder, mode);
1810 break;
1811 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1813 if (ASIC_IS_DCE5(rdev)) {
1814 switch (mode) {
1815 case DRM_MODE_DPMS_ON:
1816 atombios_dac_setup(encoder, ATOM_ENABLE);
1817 break;
1818 case DRM_MODE_DPMS_STANDBY:
1819 case DRM_MODE_DPMS_SUSPEND:
1820 case DRM_MODE_DPMS_OFF:
1821 atombios_dac_setup(encoder, ATOM_DISABLE);
1822 break;
1823 }
1824 } else
1825 radeon_atom_encoder_dpms_avivo(encoder, mode);
1826 break;
1827 default:
1828 return;
1829 }
1830
1831 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1832
1833 }
1834
1835 union crtc_source_param {
1836 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1837 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1838 };
1839
1840 static void
1841 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1842 {
1843 struct drm_device *dev = encoder->dev;
1844 struct radeon_device *rdev = dev->dev_private;
1845 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1846 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1847 union crtc_source_param args;
1848 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1849 uint8_t frev, crev;
1850 struct radeon_encoder_atom_dig *dig;
1851
1852 memset(&args, 0, sizeof(args));
1853
1854 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1855 return;
1856
1857 switch (frev) {
1858 case 1:
1859 switch (crev) {
1860 case 1:
1861 default:
1862 if (ASIC_IS_AVIVO(rdev))
1863 args.v1.ucCRTC = radeon_crtc->crtc_id;
1864 else {
1865 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1866 args.v1.ucCRTC = radeon_crtc->crtc_id;
1867 } else {
1868 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1869 }
1870 }
1871 switch (radeon_encoder->encoder_id) {
1872 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1873 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1874 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1875 break;
1876 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1877 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1878 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1879 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1880 else
1881 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1882 break;
1883 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1884 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1885 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1886 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1887 break;
1888 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1889 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1890 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1891 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1892 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1893 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1894 else
1895 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1896 break;
1897 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1898 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1899 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1900 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1901 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1902 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1903 else
1904 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1905 break;
1906 }
1907 break;
1908 case 2:
1909 args.v2.ucCRTC = radeon_crtc->crtc_id;
1910 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1911 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1912
1913 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1914 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1915 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1916 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1917 else
1918 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1919 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1920 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1921 } else {
1922 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1923 }
1924 switch (radeon_encoder->encoder_id) {
1925 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1926 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1927 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1928 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1929 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1930 dig = radeon_encoder->enc_priv;
1931 switch (dig->dig_encoder) {
1932 case 0:
1933 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1934 break;
1935 case 1:
1936 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1937 break;
1938 case 2:
1939 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1940 break;
1941 case 3:
1942 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1943 break;
1944 case 4:
1945 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1946 break;
1947 case 5:
1948 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1949 break;
1950 case 6:
1951 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1952 break;
1953 }
1954 break;
1955 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1956 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1957 break;
1958 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1959 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1960 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1961 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1962 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1963 else
1964 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1965 break;
1966 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1967 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1968 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1969 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1970 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1971 else
1972 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1973 break;
1974 }
1975 break;
1976 }
1977 break;
1978 default:
1979 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1980 return;
1981 }
1982
1983 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1984
1985 /* update scratch regs with new routing */
1986 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1987 }
1988
1989 void
1990 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
1991 {
1992 struct drm_device *dev = encoder->dev;
1993 struct radeon_device *rdev = dev->dev_private;
1994 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1995 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1996 uint8_t frev, crev;
1997 union crtc_source_param args;
1998
1999 memset(&args, 0, sizeof(args));
2000
2001 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2002 return;
2003
2004 if (frev != 1 && crev != 2)
2005 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2006
2007 args.v2.ucCRTC = radeon_crtc->crtc_id;
2008 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2009
2010 switch (fe) {
2011 case 0:
2012 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2013 break;
2014 case 1:
2015 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2016 break;
2017 case 2:
2018 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2019 break;
2020 case 3:
2021 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2022 break;
2023 case 4:
2024 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2025 break;
2026 case 5:
2027 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2028 break;
2029 case 6:
2030 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2031 break;
2032 }
2033 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2034 }
2035
2036 static void
2037 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2038 struct drm_display_mode *mode)
2039 {
2040 struct drm_device *dev = encoder->dev;
2041 struct radeon_device *rdev = dev->dev_private;
2042 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2043 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2044
2045 /* Funky macbooks */
2046 if ((dev->pdev->device == 0x71C5) &&
2047 (dev->pdev->subsystem_vendor == 0x106b) &&
2048 (dev->pdev->subsystem_device == 0x0080)) {
2049 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2050 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2051
2052 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2053 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2054
2055 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2056 }
2057 }
2058
2059 /* set scaler clears this on some chips */
2060 if (ASIC_IS_AVIVO(rdev) &&
2061 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2062 if (ASIC_IS_DCE8(rdev)) {
2063 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2064 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2065 CIK_INTERLEAVE_EN);
2066 else
2067 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2068 } else if (ASIC_IS_DCE4(rdev)) {
2069 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2070 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2071 EVERGREEN_INTERLEAVE_EN);
2072 else
2073 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2074 } else {
2075 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2076 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2077 AVIVO_D1MODE_INTERLEAVE_EN);
2078 else
2079 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2080 }
2081 }
2082 }
2083
2084 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2085 {
2086 if (enc_idx < 0)
2087 return;
2088 rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2089 }
2090
2091 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2092 {
2093 struct drm_device *dev = encoder->dev;
2094 struct radeon_device *rdev = dev->dev_private;
2095 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2096 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2097 struct drm_encoder *test_encoder;
2098 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2099 uint32_t dig_enc_in_use = 0;
2100 int enc_idx = -1;
2101
2102 if (fe_idx >= 0) {
2103 enc_idx = fe_idx;
2104 goto assigned;
2105 }
2106 if (ASIC_IS_DCE6(rdev)) {
2107 /* DCE6 */
2108 switch (radeon_encoder->encoder_id) {
2109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2110 if (dig->linkb)
2111 enc_idx = 1;
2112 else
2113 enc_idx = 0;
2114 break;
2115 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2116 if (dig->linkb)
2117 enc_idx = 3;
2118 else
2119 enc_idx = 2;
2120 break;
2121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2122 if (dig->linkb)
2123 enc_idx = 5;
2124 else
2125 enc_idx = 4;
2126 break;
2127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2128 enc_idx = 6;
2129 break;
2130 }
2131 goto assigned;
2132 } else if (ASIC_IS_DCE4(rdev)) {
2133 /* DCE4/5 */
2134 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2135 /* ontario follows DCE4 */
2136 if (rdev->family == CHIP_PALM) {
2137 if (dig->linkb)
2138 enc_idx = 1;
2139 else
2140 enc_idx = 0;
2141 } else
2142 /* llano follows DCE3.2 */
2143 enc_idx = radeon_crtc->crtc_id;
2144 } else {
2145 switch (radeon_encoder->encoder_id) {
2146 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2147 if (dig->linkb)
2148 enc_idx = 1;
2149 else
2150 enc_idx = 0;
2151 break;
2152 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2153 if (dig->linkb)
2154 enc_idx = 3;
2155 else
2156 enc_idx = 2;
2157 break;
2158 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2159 if (dig->linkb)
2160 enc_idx = 5;
2161 else
2162 enc_idx = 4;
2163 break;
2164 }
2165 }
2166 goto assigned;
2167 }
2168
2169 /* on DCE32 and encoder can driver any block so just crtc id */
2170 if (ASIC_IS_DCE32(rdev)) {
2171 enc_idx = radeon_crtc->crtc_id;
2172 goto assigned;
2173 }
2174
2175 /* on DCE3 - LVTMA can only be driven by DIGB */
2176 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2177 struct radeon_encoder *radeon_test_encoder;
2178
2179 if (encoder == test_encoder)
2180 continue;
2181
2182 if (!radeon_encoder_is_digital(test_encoder))
2183 continue;
2184
2185 radeon_test_encoder = to_radeon_encoder(test_encoder);
2186 dig = radeon_test_encoder->enc_priv;
2187
2188 if (dig->dig_encoder >= 0)
2189 dig_enc_in_use |= (1 << dig->dig_encoder);
2190 }
2191
2192 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2193 if (dig_enc_in_use & 0x2)
2194 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2195 return 1;
2196 }
2197 if (!(dig_enc_in_use & 1))
2198 return 0;
2199 return 1;
2200
2201 assigned:
2202 if (enc_idx == -1) {
2203 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2204 return 0;
2205 }
2206 if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2207 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2208 }
2209 rdev->mode_info.active_encoders |= (1 << enc_idx);
2210 return enc_idx;
2211 }
2212
2213 /* This only needs to be called once at startup */
2214 void
2215 radeon_atom_encoder_init(struct radeon_device *rdev)
2216 {
2217 struct drm_device *dev = rdev->ddev;
2218 struct drm_encoder *encoder;
2219
2220 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2221 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2222 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2223
2224 switch (radeon_encoder->encoder_id) {
2225 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2229 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2230 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2231 break;
2232 default:
2233 break;
2234 }
2235
2236 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2237 atombios_external_encoder_setup(encoder, ext_encoder,
2238 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2239 }
2240 }
2241
2242 static void
2243 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2244 struct drm_display_mode *mode,
2245 struct drm_display_mode *adjusted_mode)
2246 {
2247 struct drm_device *dev = encoder->dev;
2248 struct radeon_device *rdev = dev->dev_private;
2249 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2250 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2251 int encoder_mode;
2252
2253 radeon_encoder->pixel_clock = adjusted_mode->clock;
2254
2255 /* need to call this here rather than in prepare() since we need some crtc info */
2256 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2257
2258 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2259 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2260 atombios_yuv_setup(encoder, true);
2261 else
2262 atombios_yuv_setup(encoder, false);
2263 }
2264
2265 switch (radeon_encoder->encoder_id) {
2266 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2267 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2268 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2269 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2270 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2271 break;
2272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2273 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2276 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2277 /* handled in dpms */
2278 break;
2279 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2280 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2281 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2282 atombios_dvo_setup(encoder, ATOM_ENABLE);
2283 break;
2284 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2285 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2286 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2287 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2288 atombios_dac_setup(encoder, ATOM_ENABLE);
2289 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2290 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2291 atombios_tv_setup(encoder, ATOM_ENABLE);
2292 else
2293 atombios_tv_setup(encoder, ATOM_DISABLE);
2294 }
2295 break;
2296 }
2297
2298 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2299
2300 encoder_mode = atombios_get_encoder_mode(encoder);
2301 if (connector && (radeon_audio != 0) &&
2302 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2303 ENCODER_MODE_IS_DP(encoder_mode)))
2304 radeon_audio_mode_set(encoder, adjusted_mode);
2305 }
2306
2307 static bool
2308 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2309 {
2310 struct drm_device *dev = encoder->dev;
2311 struct radeon_device *rdev = dev->dev_private;
2312 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2313 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2314
2315 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2316 ATOM_DEVICE_CV_SUPPORT |
2317 ATOM_DEVICE_CRT_SUPPORT)) {
2318 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2319 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2320 uint8_t frev, crev;
2321
2322 memset(&args, 0, sizeof(args));
2323
2324 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2325 return false;
2326
2327 args.sDacload.ucMisc = 0;
2328
2329 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2330 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2331 args.sDacload.ucDacType = ATOM_DAC_A;
2332 else
2333 args.sDacload.ucDacType = ATOM_DAC_B;
2334
2335 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2336 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2337 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2338 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2339 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2340 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2341 if (crev >= 3)
2342 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2343 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2344 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2345 if (crev >= 3)
2346 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2347 }
2348
2349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2350
2351 return true;
2352 } else
2353 return false;
2354 }
2355
2356 static enum drm_connector_status
2357 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2358 {
2359 struct drm_device *dev = encoder->dev;
2360 struct radeon_device *rdev = dev->dev_private;
2361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2362 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2363 uint32_t bios_0_scratch;
2364
2365 if (!atombios_dac_load_detect(encoder, connector)) {
2366 DRM_DEBUG_KMS("detect returned false \n");
2367 return connector_status_unknown;
2368 }
2369
2370 if (rdev->family >= CHIP_R600)
2371 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2372 else
2373 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2374
2375 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2376 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2377 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2378 return connector_status_connected;
2379 }
2380 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2381 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2382 return connector_status_connected;
2383 }
2384 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2385 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2386 return connector_status_connected;
2387 }
2388 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2389 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2390 return connector_status_connected; /* CTV */
2391 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2392 return connector_status_connected; /* STV */
2393 }
2394 return connector_status_disconnected;
2395 }
2396
2397 static enum drm_connector_status
2398 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2399 {
2400 struct drm_device *dev = encoder->dev;
2401 struct radeon_device *rdev = dev->dev_private;
2402 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2403 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2404 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2405 u32 bios_0_scratch;
2406
2407 if (!ASIC_IS_DCE4(rdev))
2408 return connector_status_unknown;
2409
2410 if (!ext_encoder)
2411 return connector_status_unknown;
2412
2413 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2414 return connector_status_unknown;
2415
2416 /* load detect on the dp bridge */
2417 atombios_external_encoder_setup(encoder, ext_encoder,
2418 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2419
2420 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2421
2422 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2423 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2424 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2425 return connector_status_connected;
2426 }
2427 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2428 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2429 return connector_status_connected;
2430 }
2431 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2432 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2433 return connector_status_connected;
2434 }
2435 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2436 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2437 return connector_status_connected; /* CTV */
2438 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2439 return connector_status_connected; /* STV */
2440 }
2441 return connector_status_disconnected;
2442 }
2443
2444 void
2445 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2446 {
2447 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2448
2449 if (ext_encoder)
2450 /* ddc_setup on the dp bridge */
2451 atombios_external_encoder_setup(encoder, ext_encoder,
2452 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2453
2454 }
2455
2456 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2457 {
2458 struct radeon_device *rdev = encoder->dev->dev_private;
2459 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2460 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2461
2462 if ((radeon_encoder->active_device &
2463 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2464 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2465 ENCODER_OBJECT_ID_NONE)) {
2466 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2467 if (dig) {
2468 if (dig->dig_encoder >= 0)
2469 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2470 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2471 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2472 if (rdev->family >= CHIP_R600)
2473 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2474 else
2475 /* RS600/690/740 have only 1 afmt block */
2476 dig->afmt = rdev->mode_info.afmt[0];
2477 }
2478 }
2479 }
2480
2481 radeon_atom_output_lock(encoder, true);
2482
2483 if (connector) {
2484 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2485
2486 /* select the clock/data port if it uses a router */
2487 if (radeon_connector->router.cd_valid)
2488 radeon_router_select_cd_port(radeon_connector);
2489
2490 /* turn eDP panel on for mode set */
2491 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2492 atombios_set_edp_panel_power(connector,
2493 ATOM_TRANSMITTER_ACTION_POWER_ON);
2494 }
2495
2496 /* this is needed for the pll/ss setup to work correctly in some cases */
2497 atombios_set_encoder_crtc_source(encoder);
2498 /* set up the FMT blocks */
2499 if (ASIC_IS_DCE8(rdev))
2500 dce8_program_fmt(encoder);
2501 else if (ASIC_IS_DCE4(rdev))
2502 dce4_program_fmt(encoder);
2503 else if (ASIC_IS_DCE3(rdev))
2504 dce3_program_fmt(encoder);
2505 else if (ASIC_IS_AVIVO(rdev))
2506 avivo_program_fmt(encoder);
2507 }
2508
2509 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2510 {
2511 /* need to call this here as we need the crtc set up */
2512 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2513 radeon_atom_output_lock(encoder, false);
2514 }
2515
2516 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2517 {
2518 struct drm_device *dev = encoder->dev;
2519 struct radeon_device *rdev = dev->dev_private;
2520 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2521 struct radeon_encoder_atom_dig *dig;
2522
2523 /* check for pre-DCE3 cards with shared encoders;
2524 * can't really use the links individually, so don't disable
2525 * the encoder if it's in use by another connector
2526 */
2527 if (!ASIC_IS_DCE3(rdev)) {
2528 struct drm_encoder *other_encoder;
2529 struct radeon_encoder *other_radeon_encoder;
2530
2531 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2532 other_radeon_encoder = to_radeon_encoder(other_encoder);
2533 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2534 drm_helper_encoder_in_use(other_encoder))
2535 goto disable_done;
2536 }
2537 }
2538
2539 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2540
2541 switch (radeon_encoder->encoder_id) {
2542 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2544 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2545 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2546 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2547 break;
2548 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2549 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2550 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2551 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2553 /* handled in dpms */
2554 break;
2555 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2556 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2558 atombios_dvo_setup(encoder, ATOM_DISABLE);
2559 break;
2560 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2562 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2563 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2564 atombios_dac_setup(encoder, ATOM_DISABLE);
2565 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2566 atombios_tv_setup(encoder, ATOM_DISABLE);
2567 break;
2568 }
2569
2570 disable_done:
2571 if (radeon_encoder_is_digital(encoder)) {
2572 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2573 if (rdev->asic->display.hdmi_enable)
2574 radeon_hdmi_enable(rdev, encoder, false);
2575 }
2576 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2577 dig = radeon_encoder->enc_priv;
2578 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2579 dig->dig_encoder = -1;
2580 radeon_encoder->active_device = 0;
2581 }
2582 } else
2583 radeon_encoder->active_device = 0;
2584 }
2585
2586 /* these are handled by the primary encoders */
2587 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2588 {
2589
2590 }
2591
2592 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2593 {
2594
2595 }
2596
2597 static void
2598 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2599 struct drm_display_mode *mode,
2600 struct drm_display_mode *adjusted_mode)
2601 {
2602
2603 }
2604
2605 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2606 {
2607
2608 }
2609
2610 static void
2611 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2612 {
2613
2614 }
2615
2616 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2617 const struct drm_display_mode *mode,
2618 struct drm_display_mode *adjusted_mode)
2619 {
2620 return true;
2621 }
2622
2623 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2624 .dpms = radeon_atom_ext_dpms,
2625 .mode_fixup = radeon_atom_ext_mode_fixup,
2626 .prepare = radeon_atom_ext_prepare,
2627 .mode_set = radeon_atom_ext_mode_set,
2628 .commit = radeon_atom_ext_commit,
2629 .disable = radeon_atom_ext_disable,
2630 /* no detect for TMDS/LVDS yet */
2631 };
2632
2633 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2634 .dpms = radeon_atom_encoder_dpms,
2635 .mode_fixup = radeon_atom_mode_fixup,
2636 .prepare = radeon_atom_encoder_prepare,
2637 .mode_set = radeon_atom_encoder_mode_set,
2638 .commit = radeon_atom_encoder_commit,
2639 .disable = radeon_atom_encoder_disable,
2640 .detect = radeon_atom_dig_detect,
2641 };
2642
2643 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2644 .dpms = radeon_atom_encoder_dpms,
2645 .mode_fixup = radeon_atom_mode_fixup,
2646 .prepare = radeon_atom_encoder_prepare,
2647 .mode_set = radeon_atom_encoder_mode_set,
2648 .commit = radeon_atom_encoder_commit,
2649 .detect = radeon_atom_dac_detect,
2650 };
2651
2652 void radeon_enc_destroy(struct drm_encoder *encoder)
2653 {
2654 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2655 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2656 radeon_atom_backlight_exit(radeon_encoder);
2657 kfree(radeon_encoder->enc_priv);
2658 drm_encoder_cleanup(encoder);
2659 kfree(radeon_encoder);
2660 }
2661
2662 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2663 .destroy = radeon_enc_destroy,
2664 };
2665
2666 static struct radeon_encoder_atom_dac *
2667 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2668 {
2669 struct drm_device *dev = radeon_encoder->base.dev;
2670 struct radeon_device *rdev = dev->dev_private;
2671 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2672
2673 if (!dac)
2674 return NULL;
2675
2676 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2677 return dac;
2678 }
2679
2680 static struct radeon_encoder_atom_dig *
2681 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2682 {
2683 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2684 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2685
2686 if (!dig)
2687 return NULL;
2688
2689 /* coherent mode by default */
2690 dig->coherent_mode = true;
2691 dig->dig_encoder = -1;
2692
2693 if (encoder_enum == 2)
2694 dig->linkb = true;
2695 else
2696 dig->linkb = false;
2697
2698 return dig;
2699 }
2700
2701 void
2702 radeon_add_atom_encoder(struct drm_device *dev,
2703 uint32_t encoder_enum,
2704 uint32_t supported_device,
2705 u16 caps)
2706 {
2707 struct radeon_device *rdev = dev->dev_private;
2708 struct drm_encoder *encoder;
2709 struct radeon_encoder *radeon_encoder;
2710
2711 /* see if we already added it */
2712 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2713 radeon_encoder = to_radeon_encoder(encoder);
2714 if (radeon_encoder->encoder_enum == encoder_enum) {
2715 radeon_encoder->devices |= supported_device;
2716 return;
2717 }
2718
2719 }
2720
2721 /* add a new one */
2722 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2723 if (!radeon_encoder)
2724 return;
2725
2726 encoder = &radeon_encoder->base;
2727 switch (rdev->num_crtc) {
2728 case 1:
2729 encoder->possible_crtcs = 0x1;
2730 break;
2731 case 2:
2732 default:
2733 encoder->possible_crtcs = 0x3;
2734 break;
2735 case 4:
2736 encoder->possible_crtcs = 0xf;
2737 break;
2738 case 6:
2739 encoder->possible_crtcs = 0x3f;
2740 break;
2741 }
2742
2743 radeon_encoder->enc_priv = NULL;
2744
2745 radeon_encoder->encoder_enum = encoder_enum;
2746 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2747 radeon_encoder->devices = supported_device;
2748 radeon_encoder->rmx_type = RMX_OFF;
2749 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2750 radeon_encoder->is_ext_encoder = false;
2751 radeon_encoder->caps = caps;
2752
2753 switch (radeon_encoder->encoder_id) {
2754 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2755 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2756 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2757 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2758 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2759 radeon_encoder->rmx_type = RMX_FULL;
2760 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2761 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2762 } else {
2763 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2764 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2765 }
2766 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2767 break;
2768 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2769 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2770 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2771 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2772 break;
2773 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2774 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2775 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2776 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2777 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2778 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2779 break;
2780 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2781 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2782 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2783 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2784 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2785 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2786 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2787 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2788 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2789 radeon_encoder->rmx_type = RMX_FULL;
2790 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2791 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2792 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2793 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2794 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2795 } else {
2796 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2797 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2798 }
2799 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2800 break;
2801 case ENCODER_OBJECT_ID_SI170B:
2802 case ENCODER_OBJECT_ID_CH7303:
2803 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2804 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2805 case ENCODER_OBJECT_ID_TITFP513:
2806 case ENCODER_OBJECT_ID_VT1623:
2807 case ENCODER_OBJECT_ID_HDMI_SI1930:
2808 case ENCODER_OBJECT_ID_TRAVIS:
2809 case ENCODER_OBJECT_ID_NUTMEG:
2810 /* these are handled by the primary encoders */
2811 radeon_encoder->is_ext_encoder = true;
2812 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2813 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2814 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2815 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2816 else
2817 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2818 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2819 break;
2820 }
2821 }
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