2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/hdmi.h>
26 #include "radeon_audio.h"
29 #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8
30 #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
32 u32
dce6_endpoint_rreg(struct radeon_device
*rdev
,
33 u32 block_offset
, u32 reg
)
38 spin_lock_irqsave(&rdev
->end_idx_lock
, flags
);
39 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
40 r
= RREG32(AZ_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
41 spin_unlock_irqrestore(&rdev
->end_idx_lock
, flags
);
46 void dce6_endpoint_wreg(struct radeon_device
*rdev
,
47 u32 block_offset
, u32 reg
, u32 v
)
51 spin_lock_irqsave(&rdev
->end_idx_lock
, flags
);
52 if (ASIC_IS_DCE8(rdev
))
53 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
55 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX
+ block_offset
,
56 AZ_ENDPOINT_REG_WRITE_EN
| AZ_ENDPOINT_REG_INDEX(reg
));
57 WREG32(AZ_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
58 spin_unlock_irqrestore(&rdev
->end_idx_lock
, flags
);
61 static void dce6_afmt_get_connected_pins(struct radeon_device
*rdev
)
66 for (i
= 0; i
< rdev
->audio
.num_pins
; i
++) {
67 offset
= rdev
->audio
.pin
[i
].offset
;
68 tmp
= RREG32_ENDPOINT(offset
,
69 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
70 if (((tmp
& PORT_CONNECTIVITY_MASK
) >> PORT_CONNECTIVITY_SHIFT
) == 1)
71 rdev
->audio
.pin
[i
].connected
= false;
73 rdev
->audio
.pin
[i
].connected
= true;
77 struct r600_audio_pin
*dce6_audio_get_pin(struct radeon_device
*rdev
)
81 dce6_afmt_get_connected_pins(rdev
);
83 for (i
= 0; i
< rdev
->audio
.num_pins
; i
++) {
84 if (rdev
->audio
.pin
[i
].connected
)
85 return &rdev
->audio
.pin
[i
];
87 DRM_ERROR("No connected audio pins found!\n");
91 void dce6_afmt_select_pin(struct drm_encoder
*encoder
)
93 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
94 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
95 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
98 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
101 offset
= dig
->afmt
->offset
;
103 WREG32(AFMT_AUDIO_SRC_CONTROL
+ offset
,
104 AFMT_AUDIO_SRC_SELECT(dig
->afmt
->pin
->id
));
107 void dce6_afmt_write_latency_fields(struct drm_encoder
*encoder
,
108 struct drm_connector
*connector
, struct drm_display_mode
*mode
)
110 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
111 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
112 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
115 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
118 offset
= dig
->afmt
->pin
->offset
;
120 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
121 if (connector
->latency_present
[1])
122 tmp
= VIDEO_LIPSYNC(connector
->video_latency
[1]) |
123 AUDIO_LIPSYNC(connector
->audio_latency
[1]);
125 tmp
= VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
127 if (connector
->latency_present
[0])
128 tmp
= VIDEO_LIPSYNC(connector
->video_latency
[0]) |
129 AUDIO_LIPSYNC(connector
->audio_latency
[0]);
131 tmp
= VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
133 WREG32_ENDPOINT(offset
, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
136 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder
*encoder
,
137 u8
*sadb
, int sad_count
)
139 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
140 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
141 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
144 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
147 offset
= dig
->afmt
->pin
->offset
;
149 /* program the speaker allocation */
150 tmp
= RREG32_ENDPOINT(offset
, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
151 tmp
&= ~(DP_CONNECTION
| SPEAKER_ALLOCATION_MASK
);
153 tmp
|= HDMI_CONNECTION
;
155 tmp
|= SPEAKER_ALLOCATION(sadb
[0]);
157 tmp
|= SPEAKER_ALLOCATION(5); /* stereo */
158 WREG32_ENDPOINT(offset
, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
161 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder
*encoder
,
162 u8
*sadb
, int sad_count
)
164 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
165 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
166 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
169 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
172 offset
= dig
->afmt
->pin
->offset
;
174 /* program the speaker allocation */
175 tmp
= RREG32_ENDPOINT(offset
, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
176 tmp
&= ~(HDMI_CONNECTION
| SPEAKER_ALLOCATION_MASK
);
178 tmp
|= DP_CONNECTION
;
180 tmp
|= SPEAKER_ALLOCATION(sadb
[0]);
182 tmp
|= SPEAKER_ALLOCATION(5); /* stereo */
183 WREG32_ENDPOINT(offset
, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
186 void dce6_afmt_write_sad_regs(struct drm_encoder
*encoder
,
187 struct cea_sad
*sads
, int sad_count
)
191 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
192 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
193 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
194 static const u16 eld_reg_to_type
[][2] = {
195 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
196 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
197 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
198 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
199 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
200 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
201 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
202 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
203 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
204 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
205 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
206 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
209 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
212 offset
= dig
->afmt
->pin
->offset
;
214 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
217 int max_channels
= -1;
220 for (j
= 0; j
< sad_count
; j
++) {
221 struct cea_sad
*sad
= &sads
[j
];
223 if (sad
->format
== eld_reg_to_type
[i
][1]) {
224 if (sad
->channels
> max_channels
) {
225 value
= MAX_CHANNELS(sad
->channels
) |
226 DESCRIPTOR_BYTE_2(sad
->byte2
) |
227 SUPPORTED_FREQUENCIES(sad
->freq
);
228 max_channels
= sad
->channels
;
231 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
232 stereo_freqs
|= sad
->freq
;
238 value
|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs
);
240 WREG32_ENDPOINT(offset
, eld_reg_to_type
[i
][0], value
);
244 void dce6_audio_enable(struct radeon_device
*rdev
,
245 struct r600_audio_pin
*pin
,
251 WREG32_ENDPOINT(pin
->offset
, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
252 enable_mask
? AUDIO_ENABLED
: 0);
255 void dce6_hdmi_audio_set_dto(struct radeon_device
*rdev
,
256 struct radeon_crtc
*crtc
, unsigned int clock
)
258 /* Two dtos; generally use dto0 for HDMI */
262 value
|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc
->crtc_id
);
264 WREG32(DCCG_AUDIO_DTO_SOURCE
, value
);
266 /* Express [24MHz / target pixel clock] as an exact rational
267 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
268 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
270 WREG32(DCCG_AUDIO_DTO0_PHASE
, 24000);
271 WREG32(DCCG_AUDIO_DTO0_MODULE
, clock
);
274 void dce6_dp_audio_set_dto(struct radeon_device
*rdev
,
275 struct radeon_crtc
*crtc
, unsigned int clock
)
277 /* Two dtos; generally use dto1 for DP */
279 value
|= DCCG_AUDIO_DTO_SEL
;
282 value
|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc
->crtc_id
);
284 WREG32(DCCG_AUDIO_DTO_SOURCE
, value
);
286 /* Express [24MHz / target pixel clock] as an exact rational
287 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
288 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
290 if (ASIC_IS_DCE8(rdev
)) {
291 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE
, 24000);
292 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE
, clock
);
294 WREG32(DCCG_AUDIO_DTO1_PHASE
, 24000);
295 WREG32(DCCG_AUDIO_DTO1_MODULE
, clock
);