drm/radeon/kms: add query for crtc hw id from crtc id to get info V2

[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / evergreend.h

/*
 * Copyright 2010 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Alex Deucher
 */
#ifndef EVERGREEND_H
#define EVERGREEND_H

#define EVERGREEN_MAX_SH_GPRS           256
#define EVERGREEN_MAX_TEMP_GPRS         16
#define EVERGREEN_MAX_SH_THREADS        256
#define EVERGREEN_MAX_SH_STACK_ENTRIES  4096
#define EVERGREEN_MAX_FRC_EOV_CNT       16384
#define EVERGREEN_MAX_BACKENDS          8
#define EVERGREEN_MAX_BACKENDS_MASK     0xFF
#define EVERGREEN_MAX_SIMDS             16
#define EVERGREEN_MAX_SIMDS_MASK        0xFFFF
#define EVERGREEN_MAX_PIPES             8
#define EVERGREEN_MAX_PIPES_MASK        0xFF
#define EVERGREEN_MAX_LDS_NUM           0xFFFF

/* Registers */

#define RCU_IND_INDEX                                   0x100
#define RCU_IND_DATA                                    0x104

#define GRBM_GFX_INDEX                                  0x802C
#define         INSTANCE_INDEX(x)                       ((x) << 0)
#define         SE_INDEX(x)                             ((x) << 16)
#define         INSTANCE_BROADCAST_WRITES               (1 << 30)
#define         SE_BROADCAST_WRITES                     (1 << 31)
#define RLC_GFX_INDEX                                   0x3fC4
#define CC_GC_SHADER_PIPE_CONFIG                        0x8950
#define         WRITE_DIS                               (1 << 0)
#define CC_RB_BACKEND_DISABLE                           0x98F4
#define         BACKEND_DISABLE(x)                      ((x) << 16)
#define GB_ADDR_CONFIG                                  0x98F8
#define         NUM_PIPES(x)                            ((x) << 0)
#define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
#define         BANK_INTERLEAVE_SIZE(x)                 ((x) << 8)
#define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
#define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
#define         NUM_GPUS(x)                             ((x) << 20)
#define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
#define         ROW_SIZE(x)                             ((x) << 28)
#define GB_BACKEND_MAP                                  0x98FC
#define DMIF_ADDR_CONFIG                                0xBD4
#define HDP_ADDR_CONFIG                                 0x2F48

#define CC_SYS_RB_BACKEND_DISABLE                       0x3F88
#define GC_USER_RB_BACKEND_DISABLE                      0x9B7C

#define CGTS_SYS_TCC_DISABLE                            0x3F90
#define CGTS_TCC_DISABLE                                0x9148
#define CGTS_USER_SYS_TCC_DISABLE                       0x3F94
#define CGTS_USER_TCC_DISABLE                           0x914C

#define CONFIG_MEMSIZE                                  0x5428

#define CP_ME_CNTL                                      0x86D8
#define         CP_ME_HALT                                      (1 << 28)
#define         CP_PFP_HALT                                     (1 << 26)
#define CP_ME_RAM_DATA                                  0xC160
#define CP_ME_RAM_RADDR                                 0xC158
#define CP_ME_RAM_WADDR                                 0xC15C
#define CP_MEQ_THRESHOLDS                               0x8764
#define         STQ_SPLIT(x)                                    ((x) << 0)
#define CP_PERFMON_CNTL                                 0x87FC
#define CP_PFP_UCODE_ADDR                               0xC150
#define CP_PFP_UCODE_DATA                               0xC154
#define CP_QUEUE_THRESHOLDS                             0x8760
#define         ROQ_IB1_START(x)                                ((x) << 0)
#define         ROQ_IB2_START(x)                                ((x) << 8)
#define CP_RB_BASE                                      0xC100
#define CP_RB_CNTL                                      0xC104
#define         RB_BUFSZ(x)                                     ((x) << 0)
#define         RB_BLKSZ(x)                                     ((x) << 8)
#define         RB_NO_UPDATE                                    (1 << 27)
#define         RB_RPTR_WR_ENA                                  (1 << 31)
#define         BUF_SWAP_32BIT                                  (2 << 16)
#define CP_RB_RPTR                                      0x8700
#define CP_RB_RPTR_ADDR                                 0xC10C
#define CP_RB_RPTR_ADDR_HI                              0xC110
#define CP_RB_RPTR_WR                                   0xC108
#define CP_RB_WPTR                                      0xC114
#define CP_RB_WPTR_ADDR                                 0xC118
#define CP_RB_WPTR_ADDR_HI                              0xC11C
#define CP_RB_WPTR_DELAY                                0x8704
#define CP_SEM_WAIT_TIMER                               0x85BC
#define CP_DEBUG                                        0xC1FC


#define GC_USER_SHADER_PIPE_CONFIG                      0x8954
#define         INACTIVE_QD_PIPES(x)                            ((x) << 8)
#define         INACTIVE_QD_PIPES_MASK                          0x0000FF00
#define         INACTIVE_SIMDS(x)                               ((x) << 16)
#define         INACTIVE_SIMDS_MASK                             0x00FF0000

#define GRBM_CNTL                                       0x8000
#define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
#define GRBM_SOFT_RESET                                 0x8020
#define         SOFT_RESET_CP                                   (1 << 0)
#define         SOFT_RESET_CB                                   (1 << 1)
#define         SOFT_RESET_DB                                   (1 << 3)
#define         SOFT_RESET_PA                                   (1 << 5)
#define         SOFT_RESET_SC                                   (1 << 6)
#define         SOFT_RESET_SPI                                  (1 << 8)
#define         SOFT_RESET_SH                                   (1 << 9)
#define         SOFT_RESET_SX                                   (1 << 10)
#define         SOFT_RESET_TC                                   (1 << 11)
#define         SOFT_RESET_TA                                   (1 << 12)
#define         SOFT_RESET_VC                                   (1 << 13)
#define         SOFT_RESET_VGT                                  (1 << 14)

#define GRBM_STATUS                                     0x8010
#define         CMDFIFO_AVAIL_MASK                              0x0000000F
#define         SRBM_RQ_PENDING                                 (1 << 5)
#define         CF_RQ_PENDING                                   (1 << 7)
#define         PF_RQ_PENDING                                   (1 << 8)
#define         GRBM_EE_BUSY                                    (1 << 10)
#define         SX_CLEAN                                        (1 << 11)
#define         DB_CLEAN                                        (1 << 12)
#define         CB_CLEAN                                        (1 << 13)
#define         TA_BUSY                                         (1 << 14)
#define         VGT_BUSY_NO_DMA                                 (1 << 16)
#define         VGT_BUSY                                        (1 << 17)
#define         SX_BUSY                                         (1 << 20)
#define         SH_BUSY                                         (1 << 21)
#define         SPI_BUSY                                        (1 << 22)
#define         SC_BUSY                                         (1 << 24)
#define         PA_BUSY                                         (1 << 25)
#define         DB_BUSY                                         (1 << 26)
#define         CP_COHERENCY_BUSY                               (1 << 28)
#define         CP_BUSY                                         (1 << 29)
#define         CB_BUSY                                         (1 << 30)
#define         GUI_ACTIVE                                      (1 << 31)
#define GRBM_STATUS_SE0                                 0x8014
#define GRBM_STATUS_SE1                                 0x8018
#define         SE_SX_CLEAN                                     (1 << 0)
#define         SE_DB_CLEAN                                     (1 << 1)
#define         SE_CB_CLEAN                                     (1 << 2)
#define         SE_TA_BUSY                                      (1 << 25)
#define         SE_SX_BUSY                                      (1 << 26)
#define         SE_SPI_BUSY                                     (1 << 27)
#define         SE_SH_BUSY                                      (1 << 28)
#define         SE_SC_BUSY                                      (1 << 29)
#define         SE_DB_BUSY                                      (1 << 30)
#define         SE_CB_BUSY                                      (1 << 31)

#define HDP_HOST_PATH_CNTL                              0x2C00
#define HDP_NONSURFACE_BASE                             0x2C04
#define HDP_NONSURFACE_INFO                             0x2C08
#define HDP_NONSURFACE_SIZE                             0x2C0C
#define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
#define HDP_TILING_CONFIG                               0x2F3C

#define MC_SHARED_CHMAP                                         0x2004
#define         NOOFCHAN_SHIFT                                  12
#define         NOOFCHAN_MASK                                   0x00003000

#define MC_ARB_RAMCFG                                   0x2760
#define         NOOFBANK_SHIFT                                  0
#define         NOOFBANK_MASK                                   0x00000003
#define         NOOFRANK_SHIFT                                  2
#define         NOOFRANK_MASK                                   0x00000004
#define         NOOFROWS_SHIFT                                  3
#define         NOOFROWS_MASK                                   0x00000038
#define         NOOFCOLS_SHIFT                                  6
#define         NOOFCOLS_MASK                                   0x000000C0
#define         CHANSIZE_SHIFT                                  8
#define         CHANSIZE_MASK                                   0x00000100
#define         BURSTLENGTH_SHIFT                               9
#define         BURSTLENGTH_MASK                                0x00000200
#define         CHANSIZE_OVERRIDE                               (1 << 11)
#define MC_VM_AGP_TOP                                   0x2028
#define MC_VM_AGP_BOT                                   0x202C
#define MC_VM_AGP_BASE                                  0x2030
#define MC_VM_FB_LOCATION                               0x2024
#define MC_VM_MB_L1_TLB0_CNTL                           0x2234
#define MC_VM_MB_L1_TLB1_CNTL                           0x2238
#define MC_VM_MB_L1_TLB2_CNTL                           0x223C
#define MC_VM_MB_L1_TLB3_CNTL                           0x2240
#define         ENABLE_L1_TLB                                   (1 << 0)
#define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
#define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
#define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
#define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
#define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
#define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
#define         EFFECTIVE_L1_TLB_SIZE(x)                        ((x)<<15)
#define         EFFECTIVE_L1_QUEUE_SIZE(x)                      ((x)<<18)
#define MC_VM_MD_L1_TLB0_CNTL                           0x2654
#define MC_VM_MD_L1_TLB1_CNTL                           0x2658
#define MC_VM_MD_L1_TLB2_CNTL                           0x265C
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
#define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034

#define PA_CL_ENHANCE                                   0x8A14
#define         CLIP_VTX_REORDER_ENA                            (1 << 0)
#define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
#define PA_SC_AA_CONFIG                                 0x28C04
#define PA_SC_CLIPRECT_RULE                             0x2820C
#define PA_SC_EDGERULE                                  0x28230
#define PA_SC_FIFO_SIZE                                 0x8BCC
#define         SC_PRIM_FIFO_SIZE(x)                            ((x) << 0)
#define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 12)
#define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 20)
#define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
#define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
#define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
#define PA_SC_LINE_STIPPLE                              0x28A0C
#define PA_SC_LINE_STIPPLE_STATE                        0x8B10

#define SCRATCH_REG0                                    0x8500
#define SCRATCH_REG1                                    0x8504
#define SCRATCH_REG2                                    0x8508
#define SCRATCH_REG3                                    0x850C
#define SCRATCH_REG4                                    0x8510
#define SCRATCH_REG5                                    0x8514
#define SCRATCH_REG6                                    0x8518
#define SCRATCH_REG7                                    0x851C
#define SCRATCH_UMSK                                    0x8540
#define SCRATCH_ADDR                                    0x8544

#define SMX_DC_CTL0                                     0xA020
#define         USE_HASH_FUNCTION                               (1 << 0)
#define         NUMBER_OF_SETS(x)                               ((x) << 1)
#define         FLUSH_ALL_ON_EVENT                              (1 << 10)
#define         STALL_ON_EVENT                                  (1 << 11)
#define SMX_EVENT_CTL                                   0xA02C
#define         ES_FLUSH_CTL(x)                                 ((x) << 0)
#define         GS_FLUSH_CTL(x)                                 ((x) << 3)
#define         ACK_FLUSH_CTL(x)                                ((x) << 6)
#define         SYNC_FLUSH_CTL                                  (1 << 8)

#define SPI_CONFIG_CNTL                                 0x9100
#define         GPR_WRITE_PRIORITY(x)                           ((x) << 0)
#define SPI_CONFIG_CNTL_1                               0x913C
#define         VTX_DONE_DELAY(x)                               ((x) << 0)
#define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
#define SPI_INPUT_Z                                     0x286D8
#define SPI_PS_IN_CONTROL_0                             0x286CC
#define         NUM_INTERP(x)                                   ((x)<<0)
#define         POSITION_ENA                                    (1<<8)
#define         POSITION_CENTROID                               (1<<9)
#define         POSITION_ADDR(x)                                ((x)<<10)
#define         PARAM_GEN(x)                                    ((x)<<15)
#define         PARAM_GEN_ADDR(x)                               ((x)<<19)
#define         BARYC_SAMPLE_CNTL(x)                            ((x)<<26)
#define         PERSP_GRADIENT_ENA                              (1<<28)
#define         LINEAR_GRADIENT_ENA                             (1<<29)
#define         POSITION_SAMPLE                                 (1<<30)
#define         BARYC_AT_SAMPLE_ENA                             (1<<31)

#define SQ_CONFIG                                       0x8C00
#define         VC_ENABLE                                       (1 << 0)
#define         EXPORT_SRC_C                                    (1 << 1)
#define         CS_PRIO(x)                                      ((x) << 18)
#define         LS_PRIO(x)                                      ((x) << 20)
#define         HS_PRIO(x)                                      ((x) << 22)
#define         PS_PRIO(x)                                      ((x) << 24)
#define         VS_PRIO(x)                                      ((x) << 26)
#define         GS_PRIO(x)                                      ((x) << 28)
#define         ES_PRIO(x)                                      ((x) << 30)
#define SQ_GPR_RESOURCE_MGMT_1                          0x8C04
#define         NUM_PS_GPRS(x)                                  ((x) << 0)
#define         NUM_VS_GPRS(x)                                  ((x) << 16)
#define         NUM_CLAUSE_TEMP_GPRS(x)                         ((x) << 28)
#define SQ_GPR_RESOURCE_MGMT_2                          0x8C08
#define         NUM_GS_GPRS(x)                                  ((x) << 0)
#define         NUM_ES_GPRS(x)                                  ((x) << 16)
#define SQ_GPR_RESOURCE_MGMT_3                          0x8C0C
#define         NUM_HS_GPRS(x)                                  ((x) << 0)
#define         NUM_LS_GPRS(x)                                  ((x) << 16)
#define SQ_THREAD_RESOURCE_MGMT                         0x8C18
#define         NUM_PS_THREADS(x)                               ((x) << 0)
#define         NUM_VS_THREADS(x)                               ((x) << 8)
#define         NUM_GS_THREADS(x)                               ((x) << 16)
#define         NUM_ES_THREADS(x)                               ((x) << 24)
#define SQ_THREAD_RESOURCE_MGMT_2                       0x8C1C
#define         NUM_HS_THREADS(x)                               ((x) << 0)
#define         NUM_LS_THREADS(x)                               ((x) << 8)
#define SQ_STACK_RESOURCE_MGMT_1                        0x8C20
#define         NUM_PS_STACK_ENTRIES(x)                         ((x) << 0)
#define         NUM_VS_STACK_ENTRIES(x)                         ((x) << 16)
#define SQ_STACK_RESOURCE_MGMT_2                        0x8C24
#define         NUM_GS_STACK_ENTRIES(x)                         ((x) << 0)
#define         NUM_ES_STACK_ENTRIES(x)                         ((x) << 16)
#define SQ_STACK_RESOURCE_MGMT_3                        0x8C28
#define         NUM_HS_STACK_ENTRIES(x)                         ((x) << 0)
#define         NUM_LS_STACK_ENTRIES(x)                         ((x) << 16)
#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                    0x8D8C
#define SQ_LDS_RESOURCE_MGMT                            0x8E2C

#define SQ_MS_FIFO_SIZES                                0x8CF0
#define         CACHE_FIFO_SIZE(x)                              ((x) << 0)
#define         FETCH_FIFO_HIWATER(x)                           ((x) << 8)
#define         DONE_FIFO_HIWATER(x)                            ((x) << 16)
#define         ALU_UPDATE_FIFO_HIWATER(x)                      ((x) << 24)

#define SX_DEBUG_1                                      0x9058
#define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
#define SX_EXPORT_BUFFER_SIZES                          0x900C
#define         COLOR_BUFFER_SIZE(x)                            ((x) << 0)
#define         POSITION_BUFFER_SIZE(x)                         ((x) << 8)
#define         SMX_BUFFER_SIZE(x)                              ((x) << 16)
#define SX_MISC                                         0x28350

#define CB_PERF_CTR0_SEL_0                              0x9A20
#define CB_PERF_CTR0_SEL_1                              0x9A24
#define CB_PERF_CTR1_SEL_0                              0x9A28
#define CB_PERF_CTR1_SEL_1                              0x9A2C
#define CB_PERF_CTR2_SEL_0                              0x9A30
#define CB_PERF_CTR2_SEL_1                              0x9A34
#define CB_PERF_CTR3_SEL_0                              0x9A38
#define CB_PERF_CTR3_SEL_1                              0x9A3C

#define TA_CNTL_AUX                                     0x9508
#define         DISABLE_CUBE_WRAP                               (1 << 0)
#define         DISABLE_CUBE_ANISO                              (1 << 1)
#define         SYNC_GRADIENT                                   (1 << 24)
#define         SYNC_WALKER                                     (1 << 25)
#define         SYNC_ALIGNER                                    (1 << 26)

#define VGT_CACHE_INVALIDATION                          0x88C4
#define         CACHE_INVALIDATION(x)                           ((x) << 0)
#define                 VC_ONLY                                         0
#define                 TC_ONLY                                         1
#define                 VC_AND_TC                                       2
#define         AUTO_INVLD_EN(x)                                ((x) << 6)
#define                 NO_AUTO                                         0
#define                 ES_AUTO                                         1
#define                 GS_AUTO                                         2
#define                 ES_AND_GS_AUTO                                  3
#define VGT_GS_VERTEX_REUSE                             0x88D4
#define VGT_NUM_INSTANCES                               0x8974
#define VGT_OUT_DEALLOC_CNTL                            0x28C5C
#define         DEALLOC_DIST_MASK                               0x0000007F
#define VGT_VERTEX_REUSE_BLOCK_CNTL                     0x28C58
#define         VTX_REUSE_DEPTH_MASK                            0x000000FF

#define VM_CONTEXT0_CNTL                                0x1410
#define         ENABLE_CONTEXT                                  (1 << 0)
#define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
#define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
#define VM_CONTEXT1_CNTL                                0x1414
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153C
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155C
#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
#define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
#define         REQUEST_TYPE(x)                                 (((x) & 0xf) << 0)
#define         RESPONSE_TYPE_MASK                              0x000000F0
#define         RESPONSE_TYPE_SHIFT                             4
#define VM_L2_CNTL                                      0x1400
#define         ENABLE_L2_CACHE                                 (1 << 0)
#define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
#define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
#define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 14)
#define VM_L2_CNTL2                                     0x1404
#define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
#define         INVALIDATE_L2_CACHE                             (1 << 1)
#define VM_L2_CNTL3                                     0x1408
#define         BANK_SELECT(x)                                  ((x) << 0)
#define         CACHE_UPDATE_MODE(x)                            ((x) << 6)
#define VM_L2_STATUS                                    0x140C
#define         L2_BUSY                                         (1 << 0)

#define WAIT_UNTIL                                      0x8040

#define SRBM_STATUS                                     0x0E50
#define SRBM_SOFT_RESET                                 0x0E60
#define         SRBM_SOFT_RESET_ALL_MASK                0x00FEEFA6
#define         SOFT_RESET_BIF                          (1 << 1)
#define         SOFT_RESET_CG                           (1 << 2)
#define         SOFT_RESET_DC                           (1 << 5)
#define         SOFT_RESET_GRBM                         (1 << 8)
#define         SOFT_RESET_HDP                          (1 << 9)
#define         SOFT_RESET_IH                           (1 << 10)
#define         SOFT_RESET_MC                           (1 << 11)
#define         SOFT_RESET_RLC                          (1 << 13)
#define         SOFT_RESET_ROM                          (1 << 14)
#define         SOFT_RESET_SEM                          (1 << 15)
#define         SOFT_RESET_VMC                          (1 << 17)
#define         SOFT_RESET_TST                          (1 << 21)
#define         SOFT_RESET_REGBB                        (1 << 22)
#define         SOFT_RESET_ORB                          (1 << 23)

#define IH_RB_CNTL                                        0x3e00
#       define IH_RB_ENABLE                               (1 << 0)
#       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
#       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
#define IH_RB_BASE                                        0x3e04
#define IH_RB_RPTR                                        0x3e08
#define IH_RB_WPTR                                        0x3e0c
#       define RB_OVERFLOW                                (1 << 0)
#       define WPTR_OFFSET_MASK                           0x3fffc
#define IH_RB_WPTR_ADDR_HI                                0x3e10
#define IH_RB_WPTR_ADDR_LO                                0x3e14
#define IH_CNTL                                           0x3e18
#       define ENABLE_INTR                                (1 << 0)
#       define IH_MC_SWAP(x)                              ((x) << 2)
#       define IH_MC_SWAP_NONE                            0
#       define IH_MC_SWAP_16BIT                           1
#       define IH_MC_SWAP_32BIT                           2
#       define IH_MC_SWAP_64BIT                           3
#       define RPTR_REARM                                 (1 << 4)
#       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
#       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)

#define CP_INT_CNTL                                     0xc124
#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
#       define SCRATCH_INT_ENABLE                       (1 << 25)
#       define TIME_STAMP_INT_ENABLE                    (1 << 26)
#       define IB2_INT_ENABLE                           (1 << 29)
#       define IB1_INT_ENABLE                           (1 << 30)
#       define RB_INT_ENABLE                            (1 << 31)
#define CP_INT_STATUS                                   0xc128
#       define SCRATCH_INT_STAT                         (1 << 25)
#       define TIME_STAMP_INT_STAT                      (1 << 26)
#       define IB2_INT_STAT                             (1 << 29)
#       define IB1_INT_STAT                             (1 << 30)
#       define RB_INT_STAT                              (1 << 31)

#define GRBM_INT_CNTL                                   0x8060
#       define RDERR_INT_ENABLE                         (1 << 0)
#       define GUI_IDLE_INT_ENABLE                      (1 << 19)

/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
#define CRTC_STATUS_FRAME_COUNT                         0x6e98

/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
#define VLINE_STATUS                                    0x6bb8
#       define VLINE_OCCURRED                           (1 << 0)
#       define VLINE_ACK                                (1 << 4)
#       define VLINE_STAT                               (1 << 12)
#       define VLINE_INTERRUPT                          (1 << 16)
#       define VLINE_INTERRUPT_TYPE                     (1 << 17)
/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
#define VBLANK_STATUS                                   0x6bbc
#       define VBLANK_OCCURRED                          (1 << 0)
#       define VBLANK_ACK                               (1 << 4)
#       define VBLANK_STAT                              (1 << 12)
#       define VBLANK_INTERRUPT                         (1 << 16)
#       define VBLANK_INTERRUPT_TYPE                    (1 << 17)

/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
#define INT_MASK                                        0x6b40
#       define VBLANK_INT_MASK                          (1 << 0)
#       define VLINE_INT_MASK                           (1 << 4)

#define DISP_INTERRUPT_STATUS                           0x60f4
#       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
#       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
#       define DC_HPD1_INTERRUPT                        (1 << 17)
#       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
#       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
#       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
#       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
#       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
#define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
#       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
#       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
#       define DC_HPD2_INTERRUPT                        (1 << 17)
#       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
#       define DISP_TIMER_INTERRUPT                     (1 << 24)
#define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
#       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
#       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
#       define DC_HPD3_INTERRUPT                        (1 << 17)
#       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
#define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
#       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
#       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
#       define DC_HPD4_INTERRUPT                        (1 << 17)
#       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
#define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
#       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
#       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
#       define DC_HPD5_INTERRUPT                        (1 << 17)
#       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6050
#       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
#       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
#       define DC_HPD6_INTERRUPT                        (1 << 17)
#       define DC_HPD6_RX_INTERRUPT                     (1 << 18)

/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
#define GRPH_INT_STATUS                                 0x6858
#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
#define GRPH_INT_CONTROL                                0x685c
#       define GRPH_PFLIP_INT_MASK                      (1 << 0)
#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)

#define DACA_AUTODETECT_INT_CONTROL                     0x66c8
#define DACB_AUTODETECT_INT_CONTROL                     0x67c8

#define DC_HPD1_INT_STATUS                              0x601c
#define DC_HPD2_INT_STATUS                              0x6028
#define DC_HPD3_INT_STATUS                              0x6034
#define DC_HPD4_INT_STATUS                              0x6040
#define DC_HPD5_INT_STATUS                              0x604c
#define DC_HPD6_INT_STATUS                              0x6058
#       define DC_HPDx_INT_STATUS                       (1 << 0)
#       define DC_HPDx_SENSE                            (1 << 1)
#       define DC_HPDx_RX_INT_STATUS                    (1 << 8)

#define DC_HPD1_INT_CONTROL                             0x6020
#define DC_HPD2_INT_CONTROL                             0x602c
#define DC_HPD3_INT_CONTROL                             0x6038
#define DC_HPD4_INT_CONTROL                             0x6044
#define DC_HPD5_INT_CONTROL                             0x6050
#define DC_HPD6_INT_CONTROL                             0x605c
#       define DC_HPDx_INT_ACK                          (1 << 0)
#       define DC_HPDx_INT_POLARITY                     (1 << 8)
#       define DC_HPDx_INT_EN                           (1 << 16)
#       define DC_HPDx_RX_INT_ACK                       (1 << 20)
#       define DC_HPDx_RX_INT_EN                        (1 << 24)

#define DC_HPD1_CONTROL                                   0x6024
#define DC_HPD2_CONTROL                                   0x6030
#define DC_HPD3_CONTROL                                   0x603c
#define DC_HPD4_CONTROL                                   0x6048
#define DC_HPD5_CONTROL                                   0x6054
#define DC_HPD6_CONTROL                                   0x6060
#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
#       define DC_HPDx_EN                                 (1 << 28)

#endif