2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include "radeon_audio.h"
31 #include <drm/radeon_drm.h>
35 #include "cayman_blit_shaders.h"
36 #include "radeon_ucode.h"
37 #include "clearstate_cayman.h"
39 static const u32 tn_rlc_save_restore_register_list
[] =
165 extern bool evergreen_is_display_hung(struct radeon_device
*rdev
);
166 extern void evergreen_print_gpu_status_regs(struct radeon_device
*rdev
);
167 extern void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
);
168 extern void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
);
169 extern int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
);
170 extern void evergreen_mc_program(struct radeon_device
*rdev
);
171 extern void evergreen_irq_suspend(struct radeon_device
*rdev
);
172 extern int evergreen_mc_init(struct radeon_device
*rdev
);
173 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device
*rdev
);
174 extern void evergreen_pcie_gen2_enable(struct radeon_device
*rdev
);
175 extern void evergreen_program_aspm(struct radeon_device
*rdev
);
176 extern void sumo_rlc_fini(struct radeon_device
*rdev
);
177 extern int sumo_rlc_init(struct radeon_device
*rdev
);
178 extern void evergreen_gpu_pci_config_reset(struct radeon_device
*rdev
);
181 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
182 MODULE_FIRMWARE("radeon/BARTS_me.bin");
183 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
184 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
185 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
186 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
187 MODULE_FIRMWARE("radeon/TURKS_me.bin");
188 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
189 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
190 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
191 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
192 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
193 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
194 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
195 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
196 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
197 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
198 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
199 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
200 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
201 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
204 static const u32 cayman_golden_registers2
[] =
206 0x3e5c, 0xffffffff, 0x00000000,
207 0x3e48, 0xffffffff, 0x00000000,
208 0x3e4c, 0xffffffff, 0x00000000,
209 0x3e64, 0xffffffff, 0x00000000,
210 0x3e50, 0xffffffff, 0x00000000,
211 0x3e60, 0xffffffff, 0x00000000
214 static const u32 cayman_golden_registers
[] =
216 0x5eb4, 0xffffffff, 0x00000002,
217 0x5e78, 0x8f311ff1, 0x001000f0,
218 0x3f90, 0xffff0000, 0xff000000,
219 0x9148, 0xffff0000, 0xff000000,
220 0x3f94, 0xffff0000, 0xff000000,
221 0x914c, 0xffff0000, 0xff000000,
222 0xc78, 0x00000080, 0x00000080,
223 0xbd4, 0x70073777, 0x00011003,
224 0xd02c, 0xbfffff1f, 0x08421000,
225 0xd0b8, 0x73773777, 0x02011003,
226 0x5bc0, 0x00200000, 0x50100000,
227 0x98f8, 0x33773777, 0x02011003,
228 0x98fc, 0xffffffff, 0x76541032,
229 0x7030, 0x31000311, 0x00000011,
230 0x2f48, 0x33773777, 0x42010001,
231 0x6b28, 0x00000010, 0x00000012,
232 0x7728, 0x00000010, 0x00000012,
233 0x10328, 0x00000010, 0x00000012,
234 0x10f28, 0x00000010, 0x00000012,
235 0x11b28, 0x00000010, 0x00000012,
236 0x12728, 0x00000010, 0x00000012,
237 0x240c, 0x000007ff, 0x00000000,
238 0x8a14, 0xf000001f, 0x00000007,
239 0x8b24, 0x3fff3fff, 0x00ff0fff,
240 0x8b10, 0x0000ff0f, 0x00000000,
241 0x28a4c, 0x07ffffff, 0x06000000,
242 0x10c, 0x00000001, 0x00010003,
243 0xa02c, 0xffffffff, 0x0000009b,
244 0x913c, 0x0000010f, 0x01000100,
245 0x8c04, 0xf8ff00ff, 0x40600060,
246 0x28350, 0x00000f01, 0x00000000,
247 0x9508, 0x3700001f, 0x00000002,
248 0x960c, 0xffffffff, 0x54763210,
249 0x88c4, 0x001f3ae3, 0x00000082,
250 0x88d0, 0xffffffff, 0x0f40df40,
251 0x88d4, 0x0000001f, 0x00000010,
252 0x8974, 0xffffffff, 0x00000000
255 static const u32 dvst_golden_registers2
[] =
257 0x8f8, 0xffffffff, 0,
258 0x8fc, 0x00380000, 0,
259 0x8f8, 0xffffffff, 1,
263 static const u32 dvst_golden_registers
[] =
265 0x690, 0x3fff3fff, 0x20c00033,
266 0x918c, 0x0fff0fff, 0x00010006,
267 0x91a8, 0x0fff0fff, 0x00010006,
268 0x9150, 0xffffdfff, 0x6e944040,
269 0x917c, 0x0fff0fff, 0x00030002,
270 0x9198, 0x0fff0fff, 0x00030002,
271 0x915c, 0x0fff0fff, 0x00010000,
272 0x3f90, 0xffff0001, 0xff000000,
273 0x9178, 0x0fff0fff, 0x00070000,
274 0x9194, 0x0fff0fff, 0x00070000,
275 0x9148, 0xffff0001, 0xff000000,
276 0x9190, 0x0fff0fff, 0x00090008,
277 0x91ac, 0x0fff0fff, 0x00090008,
278 0x3f94, 0xffff0000, 0xff000000,
279 0x914c, 0xffff0000, 0xff000000,
280 0x929c, 0x00000fff, 0x00000001,
281 0x55e4, 0xff607fff, 0xfc000100,
282 0x8a18, 0xff000fff, 0x00000100,
283 0x8b28, 0xff000fff, 0x00000100,
284 0x9144, 0xfffc0fff, 0x00000100,
285 0x6ed8, 0x00010101, 0x00010000,
286 0x9830, 0xffffffff, 0x00000000,
287 0x9834, 0xf00fffff, 0x00000400,
288 0x9838, 0xfffffffe, 0x00000000,
289 0xd0c0, 0xff000fff, 0x00000100,
290 0xd02c, 0xbfffff1f, 0x08421000,
291 0xd0b8, 0x73773777, 0x12010001,
292 0x5bb0, 0x000000f0, 0x00000070,
293 0x98f8, 0x73773777, 0x12010001,
294 0x98fc, 0xffffffff, 0x00000010,
295 0x9b7c, 0x00ff0000, 0x00fc0000,
296 0x8030, 0x00001f0f, 0x0000100a,
297 0x2f48, 0x73773777, 0x12010001,
298 0x2408, 0x00030000, 0x000c007f,
299 0x8a14, 0xf000003f, 0x00000007,
300 0x8b24, 0x3fff3fff, 0x00ff0fff,
301 0x8b10, 0x0000ff0f, 0x00000000,
302 0x28a4c, 0x07ffffff, 0x06000000,
303 0x4d8, 0x00000fff, 0x00000100,
304 0xa008, 0xffffffff, 0x00010000,
305 0x913c, 0xffff03ff, 0x01000100,
306 0x8c00, 0x000000ff, 0x00000003,
307 0x8c04, 0xf8ff00ff, 0x40600060,
308 0x8cf0, 0x1fff1fff, 0x08e00410,
309 0x28350, 0x00000f01, 0x00000000,
310 0x9508, 0xf700071f, 0x00000002,
311 0x960c, 0xffffffff, 0x54763210,
312 0x20ef8, 0x01ff01ff, 0x00000002,
313 0x20e98, 0xfffffbff, 0x00200000,
314 0x2015c, 0xffffffff, 0x00000f40,
315 0x88c4, 0x001f3ae3, 0x00000082,
316 0x8978, 0x3fffffff, 0x04050140,
317 0x88d4, 0x0000001f, 0x00000010,
318 0x8974, 0xffffffff, 0x00000000
321 static const u32 scrapper_golden_registers
[] =
323 0x690, 0x3fff3fff, 0x20c00033,
324 0x918c, 0x0fff0fff, 0x00010006,
325 0x918c, 0x0fff0fff, 0x00010006,
326 0x91a8, 0x0fff0fff, 0x00010006,
327 0x91a8, 0x0fff0fff, 0x00010006,
328 0x9150, 0xffffdfff, 0x6e944040,
329 0x9150, 0xffffdfff, 0x6e944040,
330 0x917c, 0x0fff0fff, 0x00030002,
331 0x917c, 0x0fff0fff, 0x00030002,
332 0x9198, 0x0fff0fff, 0x00030002,
333 0x9198, 0x0fff0fff, 0x00030002,
334 0x915c, 0x0fff0fff, 0x00010000,
335 0x915c, 0x0fff0fff, 0x00010000,
336 0x3f90, 0xffff0001, 0xff000000,
337 0x3f90, 0xffff0001, 0xff000000,
338 0x9178, 0x0fff0fff, 0x00070000,
339 0x9178, 0x0fff0fff, 0x00070000,
340 0x9194, 0x0fff0fff, 0x00070000,
341 0x9194, 0x0fff0fff, 0x00070000,
342 0x9148, 0xffff0001, 0xff000000,
343 0x9148, 0xffff0001, 0xff000000,
344 0x9190, 0x0fff0fff, 0x00090008,
345 0x9190, 0x0fff0fff, 0x00090008,
346 0x91ac, 0x0fff0fff, 0x00090008,
347 0x91ac, 0x0fff0fff, 0x00090008,
348 0x3f94, 0xffff0000, 0xff000000,
349 0x3f94, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x914c, 0xffff0000, 0xff000000,
352 0x929c, 0x00000fff, 0x00000001,
353 0x929c, 0x00000fff, 0x00000001,
354 0x55e4, 0xff607fff, 0xfc000100,
355 0x8a18, 0xff000fff, 0x00000100,
356 0x8a18, 0xff000fff, 0x00000100,
357 0x8b28, 0xff000fff, 0x00000100,
358 0x8b28, 0xff000fff, 0x00000100,
359 0x9144, 0xfffc0fff, 0x00000100,
360 0x9144, 0xfffc0fff, 0x00000100,
361 0x6ed8, 0x00010101, 0x00010000,
362 0x9830, 0xffffffff, 0x00000000,
363 0x9830, 0xffffffff, 0x00000000,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9834, 0xf00fffff, 0x00000400,
366 0x9838, 0xfffffffe, 0x00000000,
367 0x9838, 0xfffffffe, 0x00000000,
368 0xd0c0, 0xff000fff, 0x00000100,
369 0xd02c, 0xbfffff1f, 0x08421000,
370 0xd02c, 0xbfffff1f, 0x08421000,
371 0xd0b8, 0x73773777, 0x12010001,
372 0xd0b8, 0x73773777, 0x12010001,
373 0x5bb0, 0x000000f0, 0x00000070,
374 0x98f8, 0x73773777, 0x12010001,
375 0x98f8, 0x73773777, 0x12010001,
376 0x98fc, 0xffffffff, 0x00000010,
377 0x98fc, 0xffffffff, 0x00000010,
378 0x9b7c, 0x00ff0000, 0x00fc0000,
379 0x9b7c, 0x00ff0000, 0x00fc0000,
380 0x8030, 0x00001f0f, 0x0000100a,
381 0x8030, 0x00001f0f, 0x0000100a,
382 0x2f48, 0x73773777, 0x12010001,
383 0x2f48, 0x73773777, 0x12010001,
384 0x2408, 0x00030000, 0x000c007f,
385 0x8a14, 0xf000003f, 0x00000007,
386 0x8a14, 0xf000003f, 0x00000007,
387 0x8b24, 0x3fff3fff, 0x00ff0fff,
388 0x8b24, 0x3fff3fff, 0x00ff0fff,
389 0x8b10, 0x0000ff0f, 0x00000000,
390 0x8b10, 0x0000ff0f, 0x00000000,
391 0x28a4c, 0x07ffffff, 0x06000000,
392 0x28a4c, 0x07ffffff, 0x06000000,
393 0x4d8, 0x00000fff, 0x00000100,
394 0x4d8, 0x00000fff, 0x00000100,
395 0xa008, 0xffffffff, 0x00010000,
396 0xa008, 0xffffffff, 0x00010000,
397 0x913c, 0xffff03ff, 0x01000100,
398 0x913c, 0xffff03ff, 0x01000100,
399 0x90e8, 0x001fffff, 0x010400c0,
400 0x8c00, 0x000000ff, 0x00000003,
401 0x8c00, 0x000000ff, 0x00000003,
402 0x8c04, 0xf8ff00ff, 0x40600060,
403 0x8c04, 0xf8ff00ff, 0x40600060,
404 0x8c30, 0x0000000f, 0x00040005,
405 0x8cf0, 0x1fff1fff, 0x08e00410,
406 0x8cf0, 0x1fff1fff, 0x08e00410,
407 0x900c, 0x00ffffff, 0x0017071f,
408 0x28350, 0x00000f01, 0x00000000,
409 0x28350, 0x00000f01, 0x00000000,
410 0x9508, 0xf700071f, 0x00000002,
411 0x9508, 0xf700071f, 0x00000002,
412 0x9688, 0x00300000, 0x0017000f,
413 0x960c, 0xffffffff, 0x54763210,
414 0x960c, 0xffffffff, 0x54763210,
415 0x20ef8, 0x01ff01ff, 0x00000002,
416 0x20e98, 0xfffffbff, 0x00200000,
417 0x2015c, 0xffffffff, 0x00000f40,
418 0x88c4, 0x001f3ae3, 0x00000082,
419 0x88c4, 0x001f3ae3, 0x00000082,
420 0x8978, 0x3fffffff, 0x04050140,
421 0x8978, 0x3fffffff, 0x04050140,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x88d4, 0x0000001f, 0x00000010,
424 0x8974, 0xffffffff, 0x00000000,
425 0x8974, 0xffffffff, 0x00000000
428 static void ni_init_golden_registers(struct radeon_device
*rdev
)
430 switch (rdev
->family
) {
432 radeon_program_register_sequence(rdev
,
433 cayman_golden_registers
,
434 (const u32
)ARRAY_SIZE(cayman_golden_registers
));
435 radeon_program_register_sequence(rdev
,
436 cayman_golden_registers2
,
437 (const u32
)ARRAY_SIZE(cayman_golden_registers2
));
440 if ((rdev
->pdev
->device
== 0x9900) ||
441 (rdev
->pdev
->device
== 0x9901) ||
442 (rdev
->pdev
->device
== 0x9903) ||
443 (rdev
->pdev
->device
== 0x9904) ||
444 (rdev
->pdev
->device
== 0x9905) ||
445 (rdev
->pdev
->device
== 0x9906) ||
446 (rdev
->pdev
->device
== 0x9907) ||
447 (rdev
->pdev
->device
== 0x9908) ||
448 (rdev
->pdev
->device
== 0x9909) ||
449 (rdev
->pdev
->device
== 0x990A) ||
450 (rdev
->pdev
->device
== 0x990B) ||
451 (rdev
->pdev
->device
== 0x990C) ||
452 (rdev
->pdev
->device
== 0x990D) ||
453 (rdev
->pdev
->device
== 0x990E) ||
454 (rdev
->pdev
->device
== 0x990F) ||
455 (rdev
->pdev
->device
== 0x9910) ||
456 (rdev
->pdev
->device
== 0x9913) ||
457 (rdev
->pdev
->device
== 0x9917) ||
458 (rdev
->pdev
->device
== 0x9918)) {
459 radeon_program_register_sequence(rdev
,
460 dvst_golden_registers
,
461 (const u32
)ARRAY_SIZE(dvst_golden_registers
));
462 radeon_program_register_sequence(rdev
,
463 dvst_golden_registers2
,
464 (const u32
)ARRAY_SIZE(dvst_golden_registers2
));
466 radeon_program_register_sequence(rdev
,
467 scrapper_golden_registers
,
468 (const u32
)ARRAY_SIZE(scrapper_golden_registers
));
469 radeon_program_register_sequence(rdev
,
470 dvst_golden_registers2
,
471 (const u32
)ARRAY_SIZE(dvst_golden_registers2
));
479 #define BTC_IO_MC_REGS_SIZE 29
481 static const u32 barts_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
482 {0x00000077, 0xff010100},
483 {0x00000078, 0x00000000},
484 {0x00000079, 0x00001434},
485 {0x0000007a, 0xcc08ec08},
486 {0x0000007b, 0x00040000},
487 {0x0000007c, 0x000080c0},
488 {0x0000007d, 0x09000000},
489 {0x0000007e, 0x00210404},
490 {0x00000081, 0x08a8e800},
491 {0x00000082, 0x00030444},
492 {0x00000083, 0x00000000},
493 {0x00000085, 0x00000001},
494 {0x00000086, 0x00000002},
495 {0x00000087, 0x48490000},
496 {0x00000088, 0x20244647},
497 {0x00000089, 0x00000005},
498 {0x0000008b, 0x66030000},
499 {0x0000008c, 0x00006603},
500 {0x0000008d, 0x00000100},
501 {0x0000008f, 0x00001c0a},
502 {0x00000090, 0xff000001},
503 {0x00000094, 0x00101101},
504 {0x00000095, 0x00000fff},
505 {0x00000096, 0x00116fff},
506 {0x00000097, 0x60010000},
507 {0x00000098, 0x10010000},
508 {0x00000099, 0x00006000},
509 {0x0000009a, 0x00001000},
510 {0x0000009f, 0x00946a00}
513 static const u32 turks_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
514 {0x00000077, 0xff010100},
515 {0x00000078, 0x00000000},
516 {0x00000079, 0x00001434},
517 {0x0000007a, 0xcc08ec08},
518 {0x0000007b, 0x00040000},
519 {0x0000007c, 0x000080c0},
520 {0x0000007d, 0x09000000},
521 {0x0000007e, 0x00210404},
522 {0x00000081, 0x08a8e800},
523 {0x00000082, 0x00030444},
524 {0x00000083, 0x00000000},
525 {0x00000085, 0x00000001},
526 {0x00000086, 0x00000002},
527 {0x00000087, 0x48490000},
528 {0x00000088, 0x20244647},
529 {0x00000089, 0x00000005},
530 {0x0000008b, 0x66030000},
531 {0x0000008c, 0x00006603},
532 {0x0000008d, 0x00000100},
533 {0x0000008f, 0x00001c0a},
534 {0x00000090, 0xff000001},
535 {0x00000094, 0x00101101},
536 {0x00000095, 0x00000fff},
537 {0x00000096, 0x00116fff},
538 {0x00000097, 0x60010000},
539 {0x00000098, 0x10010000},
540 {0x00000099, 0x00006000},
541 {0x0000009a, 0x00001000},
542 {0x0000009f, 0x00936a00}
545 static const u32 caicos_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
546 {0x00000077, 0xff010100},
547 {0x00000078, 0x00000000},
548 {0x00000079, 0x00001434},
549 {0x0000007a, 0xcc08ec08},
550 {0x0000007b, 0x00040000},
551 {0x0000007c, 0x000080c0},
552 {0x0000007d, 0x09000000},
553 {0x0000007e, 0x00210404},
554 {0x00000081, 0x08a8e800},
555 {0x00000082, 0x00030444},
556 {0x00000083, 0x00000000},
557 {0x00000085, 0x00000001},
558 {0x00000086, 0x00000002},
559 {0x00000087, 0x48490000},
560 {0x00000088, 0x20244647},
561 {0x00000089, 0x00000005},
562 {0x0000008b, 0x66030000},
563 {0x0000008c, 0x00006603},
564 {0x0000008d, 0x00000100},
565 {0x0000008f, 0x00001c0a},
566 {0x00000090, 0xff000001},
567 {0x00000094, 0x00101101},
568 {0x00000095, 0x00000fff},
569 {0x00000096, 0x00116fff},
570 {0x00000097, 0x60010000},
571 {0x00000098, 0x10010000},
572 {0x00000099, 0x00006000},
573 {0x0000009a, 0x00001000},
574 {0x0000009f, 0x00916a00}
577 static const u32 cayman_io_mc_regs
[BTC_IO_MC_REGS_SIZE
][2] = {
578 {0x00000077, 0xff010100},
579 {0x00000078, 0x00000000},
580 {0x00000079, 0x00001434},
581 {0x0000007a, 0xcc08ec08},
582 {0x0000007b, 0x00040000},
583 {0x0000007c, 0x000080c0},
584 {0x0000007d, 0x09000000},
585 {0x0000007e, 0x00210404},
586 {0x00000081, 0x08a8e800},
587 {0x00000082, 0x00030444},
588 {0x00000083, 0x00000000},
589 {0x00000085, 0x00000001},
590 {0x00000086, 0x00000002},
591 {0x00000087, 0x48490000},
592 {0x00000088, 0x20244647},
593 {0x00000089, 0x00000005},
594 {0x0000008b, 0x66030000},
595 {0x0000008c, 0x00006603},
596 {0x0000008d, 0x00000100},
597 {0x0000008f, 0x00001c0a},
598 {0x00000090, 0xff000001},
599 {0x00000094, 0x00101101},
600 {0x00000095, 0x00000fff},
601 {0x00000096, 0x00116fff},
602 {0x00000097, 0x60010000},
603 {0x00000098, 0x10010000},
604 {0x00000099, 0x00006000},
605 {0x0000009a, 0x00001000},
606 {0x0000009f, 0x00976b00}
609 int ni_mc_load_microcode(struct radeon_device
*rdev
)
611 const __be32
*fw_data
;
612 u32 mem_type
, running
, blackout
= 0;
614 int i
, ucode_size
, regs_size
;
619 switch (rdev
->family
) {
621 io_mc_regs
= (u32
*)&barts_io_mc_regs
;
622 ucode_size
= BTC_MC_UCODE_SIZE
;
623 regs_size
= BTC_IO_MC_REGS_SIZE
;
626 io_mc_regs
= (u32
*)&turks_io_mc_regs
;
627 ucode_size
= BTC_MC_UCODE_SIZE
;
628 regs_size
= BTC_IO_MC_REGS_SIZE
;
632 io_mc_regs
= (u32
*)&caicos_io_mc_regs
;
633 ucode_size
= BTC_MC_UCODE_SIZE
;
634 regs_size
= BTC_IO_MC_REGS_SIZE
;
637 io_mc_regs
= (u32
*)&cayman_io_mc_regs
;
638 ucode_size
= CAYMAN_MC_UCODE_SIZE
;
639 regs_size
= BTC_IO_MC_REGS_SIZE
;
643 mem_type
= (RREG32(MC_SEQ_MISC0
) & MC_SEQ_MISC0_GDDR5_MASK
) >> MC_SEQ_MISC0_GDDR5_SHIFT
;
644 running
= RREG32(MC_SEQ_SUP_CNTL
) & RUN_MASK
;
646 if ((mem_type
== MC_SEQ_MISC0_GDDR5_VALUE
) && (running
== 0)) {
648 blackout
= RREG32(MC_SHARED_BLACKOUT_CNTL
);
649 WREG32(MC_SHARED_BLACKOUT_CNTL
, 1);
652 /* reset the engine and set to writable */
653 WREG32(MC_SEQ_SUP_CNTL
, 0x00000008);
654 WREG32(MC_SEQ_SUP_CNTL
, 0x00000010);
656 /* load mc io regs */
657 for (i
= 0; i
< regs_size
; i
++) {
658 WREG32(MC_SEQ_IO_DEBUG_INDEX
, io_mc_regs
[(i
<< 1)]);
659 WREG32(MC_SEQ_IO_DEBUG_DATA
, io_mc_regs
[(i
<< 1) + 1]);
661 /* load the MC ucode */
662 fw_data
= (const __be32
*)rdev
->mc_fw
->data
;
663 for (i
= 0; i
< ucode_size
; i
++)
664 WREG32(MC_SEQ_SUP_PGM
, be32_to_cpup(fw_data
++));
666 /* put the engine back into the active state */
667 WREG32(MC_SEQ_SUP_CNTL
, 0x00000008);
668 WREG32(MC_SEQ_SUP_CNTL
, 0x00000004);
669 WREG32(MC_SEQ_SUP_CNTL
, 0x00000001);
671 /* wait for training to complete */
672 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
673 if (RREG32(MC_IO_PAD_CNTL_D0
) & MEM_FALL_OUT_CMD
)
679 WREG32(MC_SHARED_BLACKOUT_CNTL
, blackout
);
685 int ni_init_microcode(struct radeon_device
*rdev
)
687 const char *chip_name
;
688 const char *rlc_chip_name
;
689 size_t pfp_req_size
, me_req_size
, rlc_req_size
, mc_req_size
;
690 size_t smc_req_size
= 0;
696 switch (rdev
->family
) {
699 rlc_chip_name
= "BTC";
700 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
701 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
702 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
703 mc_req_size
= BTC_MC_UCODE_SIZE
* 4;
704 smc_req_size
= ALIGN(BARTS_SMC_UCODE_SIZE
, 4);
708 rlc_chip_name
= "BTC";
709 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
710 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
711 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
712 mc_req_size
= BTC_MC_UCODE_SIZE
* 4;
713 smc_req_size
= ALIGN(TURKS_SMC_UCODE_SIZE
, 4);
716 chip_name
= "CAICOS";
717 rlc_chip_name
= "BTC";
718 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
719 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
720 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
721 mc_req_size
= BTC_MC_UCODE_SIZE
* 4;
722 smc_req_size
= ALIGN(CAICOS_SMC_UCODE_SIZE
, 4);
725 chip_name
= "CAYMAN";
726 rlc_chip_name
= "CAYMAN";
727 pfp_req_size
= CAYMAN_PFP_UCODE_SIZE
* 4;
728 me_req_size
= CAYMAN_PM4_UCODE_SIZE
* 4;
729 rlc_req_size
= CAYMAN_RLC_UCODE_SIZE
* 4;
730 mc_req_size
= CAYMAN_MC_UCODE_SIZE
* 4;
731 smc_req_size
= ALIGN(CAYMAN_SMC_UCODE_SIZE
, 4);
735 rlc_chip_name
= "ARUBA";
736 /* pfp/me same size as CAYMAN */
737 pfp_req_size
= CAYMAN_PFP_UCODE_SIZE
* 4;
738 me_req_size
= CAYMAN_PM4_UCODE_SIZE
* 4;
739 rlc_req_size
= ARUBA_RLC_UCODE_SIZE
* 4;
745 DRM_INFO("Loading %s Microcode\n", chip_name
);
747 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
748 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, rdev
->dev
);
751 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
753 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
754 rdev
->pfp_fw
->size
, fw_name
);
759 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
760 err
= request_firmware(&rdev
->me_fw
, fw_name
, rdev
->dev
);
763 if (rdev
->me_fw
->size
!= me_req_size
) {
765 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
766 rdev
->me_fw
->size
, fw_name
);
770 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
771 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, rdev
->dev
);
774 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
776 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
777 rdev
->rlc_fw
->size
, fw_name
);
781 /* no MC ucode on TN */
782 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
783 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_mc.bin", chip_name
);
784 err
= request_firmware(&rdev
->mc_fw
, fw_name
, rdev
->dev
);
787 if (rdev
->mc_fw
->size
!= mc_req_size
) {
789 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
790 rdev
->mc_fw
->size
, fw_name
);
795 if ((rdev
->family
>= CHIP_BARTS
) && (rdev
->family
<= CHIP_CAYMAN
)) {
796 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_smc.bin", chip_name
);
797 err
= request_firmware(&rdev
->smc_fw
, fw_name
, rdev
->dev
);
800 "smc: error loading firmware \"%s\"\n",
802 release_firmware(rdev
->smc_fw
);
805 } else if (rdev
->smc_fw
->size
!= smc_req_size
) {
807 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
808 rdev
->mc_fw
->size
, fw_name
);
817 "ni_cp: Failed to load firmware \"%s\"\n",
819 release_firmware(rdev
->pfp_fw
);
821 release_firmware(rdev
->me_fw
);
823 release_firmware(rdev
->rlc_fw
);
825 release_firmware(rdev
->mc_fw
);
831 int tn_get_temp(struct radeon_device
*rdev
)
833 u32 temp
= RREG32_SMC(TN_CURRENT_GNB_TEMP
) & 0x7ff;
834 int actual_temp
= (temp
/ 8) - 49;
836 return actual_temp
* 1000;
842 static void cayman_gpu_init(struct radeon_device
*rdev
)
844 u32 gb_addr_config
= 0;
845 u32 mc_shared_chmap
, mc_arb_ramcfg
;
846 u32 cgts_tcc_disable
;
849 u32 cgts_sm_ctrl_reg
;
850 u32 hdp_host_path_cntl
;
852 u32 disabled_rb_mask
;
855 switch (rdev
->family
) {
857 rdev
->config
.cayman
.max_shader_engines
= 2;
858 rdev
->config
.cayman
.max_pipes_per_simd
= 4;
859 rdev
->config
.cayman
.max_tile_pipes
= 8;
860 rdev
->config
.cayman
.max_simds_per_se
= 12;
861 rdev
->config
.cayman
.max_backends_per_se
= 4;
862 rdev
->config
.cayman
.max_texture_channel_caches
= 8;
863 rdev
->config
.cayman
.max_gprs
= 256;
864 rdev
->config
.cayman
.max_threads
= 256;
865 rdev
->config
.cayman
.max_gs_threads
= 32;
866 rdev
->config
.cayman
.max_stack_entries
= 512;
867 rdev
->config
.cayman
.sx_num_of_sets
= 8;
868 rdev
->config
.cayman
.sx_max_export_size
= 256;
869 rdev
->config
.cayman
.sx_max_export_pos_size
= 64;
870 rdev
->config
.cayman
.sx_max_export_smx_size
= 192;
871 rdev
->config
.cayman
.max_hw_contexts
= 8;
872 rdev
->config
.cayman
.sq_num_cf_insts
= 2;
874 rdev
->config
.cayman
.sc_prim_fifo_size
= 0x100;
875 rdev
->config
.cayman
.sc_hiz_tile_fifo_size
= 0x30;
876 rdev
->config
.cayman
.sc_earlyz_tile_fifo_size
= 0x130;
877 gb_addr_config
= CAYMAN_GB_ADDR_CONFIG_GOLDEN
;
881 rdev
->config
.cayman
.max_shader_engines
= 1;
882 rdev
->config
.cayman
.max_pipes_per_simd
= 4;
883 rdev
->config
.cayman
.max_tile_pipes
= 2;
884 if ((rdev
->pdev
->device
== 0x9900) ||
885 (rdev
->pdev
->device
== 0x9901) ||
886 (rdev
->pdev
->device
== 0x9905) ||
887 (rdev
->pdev
->device
== 0x9906) ||
888 (rdev
->pdev
->device
== 0x9907) ||
889 (rdev
->pdev
->device
== 0x9908) ||
890 (rdev
->pdev
->device
== 0x9909) ||
891 (rdev
->pdev
->device
== 0x990B) ||
892 (rdev
->pdev
->device
== 0x990C) ||
893 (rdev
->pdev
->device
== 0x990F) ||
894 (rdev
->pdev
->device
== 0x9910) ||
895 (rdev
->pdev
->device
== 0x9917) ||
896 (rdev
->pdev
->device
== 0x9999) ||
897 (rdev
->pdev
->device
== 0x999C)) {
898 rdev
->config
.cayman
.max_simds_per_se
= 6;
899 rdev
->config
.cayman
.max_backends_per_se
= 2;
900 rdev
->config
.cayman
.max_hw_contexts
= 8;
901 rdev
->config
.cayman
.sx_max_export_size
= 256;
902 rdev
->config
.cayman
.sx_max_export_pos_size
= 64;
903 rdev
->config
.cayman
.sx_max_export_smx_size
= 192;
904 } else if ((rdev
->pdev
->device
== 0x9903) ||
905 (rdev
->pdev
->device
== 0x9904) ||
906 (rdev
->pdev
->device
== 0x990A) ||
907 (rdev
->pdev
->device
== 0x990D) ||
908 (rdev
->pdev
->device
== 0x990E) ||
909 (rdev
->pdev
->device
== 0x9913) ||
910 (rdev
->pdev
->device
== 0x9918) ||
911 (rdev
->pdev
->device
== 0x999D)) {
912 rdev
->config
.cayman
.max_simds_per_se
= 4;
913 rdev
->config
.cayman
.max_backends_per_se
= 2;
914 rdev
->config
.cayman
.max_hw_contexts
= 8;
915 rdev
->config
.cayman
.sx_max_export_size
= 256;
916 rdev
->config
.cayman
.sx_max_export_pos_size
= 64;
917 rdev
->config
.cayman
.sx_max_export_smx_size
= 192;
918 } else if ((rdev
->pdev
->device
== 0x9919) ||
919 (rdev
->pdev
->device
== 0x9990) ||
920 (rdev
->pdev
->device
== 0x9991) ||
921 (rdev
->pdev
->device
== 0x9994) ||
922 (rdev
->pdev
->device
== 0x9995) ||
923 (rdev
->pdev
->device
== 0x9996) ||
924 (rdev
->pdev
->device
== 0x999A) ||
925 (rdev
->pdev
->device
== 0x99A0)) {
926 rdev
->config
.cayman
.max_simds_per_se
= 3;
927 rdev
->config
.cayman
.max_backends_per_se
= 1;
928 rdev
->config
.cayman
.max_hw_contexts
= 4;
929 rdev
->config
.cayman
.sx_max_export_size
= 128;
930 rdev
->config
.cayman
.sx_max_export_pos_size
= 32;
931 rdev
->config
.cayman
.sx_max_export_smx_size
= 96;
933 rdev
->config
.cayman
.max_simds_per_se
= 2;
934 rdev
->config
.cayman
.max_backends_per_se
= 1;
935 rdev
->config
.cayman
.max_hw_contexts
= 4;
936 rdev
->config
.cayman
.sx_max_export_size
= 128;
937 rdev
->config
.cayman
.sx_max_export_pos_size
= 32;
938 rdev
->config
.cayman
.sx_max_export_smx_size
= 96;
940 rdev
->config
.cayman
.max_texture_channel_caches
= 2;
941 rdev
->config
.cayman
.max_gprs
= 256;
942 rdev
->config
.cayman
.max_threads
= 256;
943 rdev
->config
.cayman
.max_gs_threads
= 32;
944 rdev
->config
.cayman
.max_stack_entries
= 512;
945 rdev
->config
.cayman
.sx_num_of_sets
= 8;
946 rdev
->config
.cayman
.sq_num_cf_insts
= 2;
948 rdev
->config
.cayman
.sc_prim_fifo_size
= 0x40;
949 rdev
->config
.cayman
.sc_hiz_tile_fifo_size
= 0x30;
950 rdev
->config
.cayman
.sc_earlyz_tile_fifo_size
= 0x130;
951 gb_addr_config
= ARUBA_GB_ADDR_CONFIG_GOLDEN
;
956 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
957 WREG32((0x2c14 + j
), 0x00000000);
958 WREG32((0x2c18 + j
), 0x00000000);
959 WREG32((0x2c1c + j
), 0x00000000);
960 WREG32((0x2c20 + j
), 0x00000000);
961 WREG32((0x2c24 + j
), 0x00000000);
964 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
966 evergreen_fix_pci_max_read_req_size(rdev
);
968 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
969 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
971 tmp
= (mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
;
972 rdev
->config
.cayman
.mem_row_size_in_kb
= (4 * (1 << (8 + tmp
))) / 1024;
973 if (rdev
->config
.cayman
.mem_row_size_in_kb
> 4)
974 rdev
->config
.cayman
.mem_row_size_in_kb
= 4;
975 /* XXX use MC settings? */
976 rdev
->config
.cayman
.shader_engine_tile_size
= 32;
977 rdev
->config
.cayman
.num_gpus
= 1;
978 rdev
->config
.cayman
.multi_gpu_tile_size
= 64;
980 tmp
= (gb_addr_config
& NUM_PIPES_MASK
) >> NUM_PIPES_SHIFT
;
981 rdev
->config
.cayman
.num_tile_pipes
= (1 << tmp
);
982 tmp
= (gb_addr_config
& PIPE_INTERLEAVE_SIZE_MASK
) >> PIPE_INTERLEAVE_SIZE_SHIFT
;
983 rdev
->config
.cayman
.mem_max_burst_length_bytes
= (tmp
+ 1) * 256;
984 tmp
= (gb_addr_config
& NUM_SHADER_ENGINES_MASK
) >> NUM_SHADER_ENGINES_SHIFT
;
985 rdev
->config
.cayman
.num_shader_engines
= tmp
+ 1;
986 tmp
= (gb_addr_config
& NUM_GPUS_MASK
) >> NUM_GPUS_SHIFT
;
987 rdev
->config
.cayman
.num_gpus
= tmp
+ 1;
988 tmp
= (gb_addr_config
& MULTI_GPU_TILE_SIZE_MASK
) >> MULTI_GPU_TILE_SIZE_SHIFT
;
989 rdev
->config
.cayman
.multi_gpu_tile_size
= 1 << tmp
;
990 tmp
= (gb_addr_config
& ROW_SIZE_MASK
) >> ROW_SIZE_SHIFT
;
991 rdev
->config
.cayman
.mem_row_size_in_kb
= 1 << tmp
;
994 /* setup tiling info dword. gb_addr_config is not adequate since it does
995 * not have bank info, so create a custom tiling dword.
998 * bits 11:8 group_size
999 * bits 15:12 row_size
1001 rdev
->config
.cayman
.tile_config
= 0;
1002 switch (rdev
->config
.cayman
.num_tile_pipes
) {
1005 rdev
->config
.cayman
.tile_config
|= (0 << 0);
1008 rdev
->config
.cayman
.tile_config
|= (1 << 0);
1011 rdev
->config
.cayman
.tile_config
|= (2 << 0);
1014 rdev
->config
.cayman
.tile_config
|= (3 << 0);
1018 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1019 if (rdev
->flags
& RADEON_IS_IGP
)
1020 rdev
->config
.cayman
.tile_config
|= 1 << 4;
1022 switch ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
) {
1023 case 0: /* four banks */
1024 rdev
->config
.cayman
.tile_config
|= 0 << 4;
1026 case 1: /* eight banks */
1027 rdev
->config
.cayman
.tile_config
|= 1 << 4;
1029 case 2: /* sixteen banks */
1031 rdev
->config
.cayman
.tile_config
|= 2 << 4;
1035 rdev
->config
.cayman
.tile_config
|=
1036 ((gb_addr_config
& PIPE_INTERLEAVE_SIZE_MASK
) >> PIPE_INTERLEAVE_SIZE_SHIFT
) << 8;
1037 rdev
->config
.cayman
.tile_config
|=
1038 ((gb_addr_config
& ROW_SIZE_MASK
) >> ROW_SIZE_SHIFT
) << 12;
1041 for (i
= (rdev
->config
.cayman
.max_shader_engines
- 1); i
>= 0; i
--) {
1042 u32 rb_disable_bitmap
;
1044 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1045 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1046 rb_disable_bitmap
= (RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000) >> 16;
1048 tmp
|= rb_disable_bitmap
;
1050 /* enabled rb are just the one not disabled :) */
1051 disabled_rb_mask
= tmp
;
1053 for (i
= 0; i
< (rdev
->config
.cayman
.max_backends_per_se
* rdev
->config
.cayman
.max_shader_engines
); i
++)
1055 /* if all the backends are disabled, fix it up here */
1056 if ((disabled_rb_mask
& tmp
) == tmp
) {
1057 for (i
= 0; i
< (rdev
->config
.cayman
.max_backends_per_se
* rdev
->config
.cayman
.max_shader_engines
); i
++)
1058 disabled_rb_mask
&= ~(1 << i
);
1061 for (i
= 0; i
< rdev
->config
.cayman
.max_shader_engines
; i
++) {
1062 u32 simd_disable_bitmap
;
1064 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1065 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_INDEX(i
));
1066 simd_disable_bitmap
= (RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0xffff0000) >> 16;
1067 simd_disable_bitmap
|= 0xffffffff << rdev
->config
.cayman
.max_simds_per_se
;
1069 tmp
|= simd_disable_bitmap
;
1071 rdev
->config
.cayman
.active_simds
= hweight32(~tmp
);
1073 WREG32(GRBM_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1074 WREG32(RLC_GFX_INDEX
, INSTANCE_BROADCAST_WRITES
| SE_BROADCAST_WRITES
);
1076 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
1077 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
1078 if (ASIC_IS_DCE6(rdev
))
1079 WREG32(DMIF_ADDR_CALC
, gb_addr_config
);
1080 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
1081 WREG32(DMA_TILING_CONFIG
+ DMA0_REGISTER_OFFSET
, gb_addr_config
);
1082 WREG32(DMA_TILING_CONFIG
+ DMA1_REGISTER_OFFSET
, gb_addr_config
);
1083 WREG32(UVD_UDEC_ADDR_CONFIG
, gb_addr_config
);
1084 WREG32(UVD_UDEC_DB_ADDR_CONFIG
, gb_addr_config
);
1085 WREG32(UVD_UDEC_DBW_ADDR_CONFIG
, gb_addr_config
);
1087 if ((rdev
->config
.cayman
.max_backends_per_se
== 1) &&
1088 (rdev
->flags
& RADEON_IS_IGP
)) {
1089 if ((disabled_rb_mask
& 3) == 1) {
1090 /* RB0 disabled, RB1 enabled */
1093 /* RB1 disabled, RB0 enabled */
1097 tmp
= gb_addr_config
& NUM_PIPES_MASK
;
1098 tmp
= r6xx_remap_render_backend(rdev
, tmp
,
1099 rdev
->config
.cayman
.max_backends_per_se
*
1100 rdev
->config
.cayman
.max_shader_engines
,
1101 CAYMAN_MAX_BACKENDS
, disabled_rb_mask
);
1103 WREG32(GB_BACKEND_MAP
, tmp
);
1105 cgts_tcc_disable
= 0xffff0000;
1106 for (i
= 0; i
< rdev
->config
.cayman
.max_texture_channel_caches
; i
++)
1107 cgts_tcc_disable
&= ~(1 << (16 + i
));
1108 WREG32(CGTS_TCC_DISABLE
, cgts_tcc_disable
);
1109 WREG32(CGTS_SYS_TCC_DISABLE
, cgts_tcc_disable
);
1110 WREG32(CGTS_USER_SYS_TCC_DISABLE
, cgts_tcc_disable
);
1111 WREG32(CGTS_USER_TCC_DISABLE
, cgts_tcc_disable
);
1113 /* reprogram the shader complex */
1114 cgts_sm_ctrl_reg
= RREG32(CGTS_SM_CTRL_REG
);
1115 for (i
= 0; i
< 16; i
++)
1116 WREG32(CGTS_SM_CTRL_REG
, OVERRIDE
);
1117 WREG32(CGTS_SM_CTRL_REG
, cgts_sm_ctrl_reg
);
1119 /* set HW defaults for 3D engine */
1120 WREG32(CP_MEQ_THRESHOLDS
, MEQ1_START(0x30) | MEQ2_START(0x60));
1122 sx_debug_1
= RREG32(SX_DEBUG_1
);
1123 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
1124 WREG32(SX_DEBUG_1
, sx_debug_1
);
1126 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
1127 smx_dc_ctl0
&= ~NUMBER_OF_SETS(0x1ff);
1128 smx_dc_ctl0
|= NUMBER_OF_SETS(rdev
->config
.cayman
.sx_num_of_sets
);
1129 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
1131 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE
);
1133 /* need to be explicitly zero-ed */
1134 WREG32(VGT_OFFCHIP_LDS_BASE
, 0);
1135 WREG32(SQ_LSTMP_RING_BASE
, 0);
1136 WREG32(SQ_HSTMP_RING_BASE
, 0);
1137 WREG32(SQ_ESTMP_RING_BASE
, 0);
1138 WREG32(SQ_GSTMP_RING_BASE
, 0);
1139 WREG32(SQ_VSTMP_RING_BASE
, 0);
1140 WREG32(SQ_PSTMP_RING_BASE
, 0);
1142 WREG32(TA_CNTL_AUX
, DISABLE_CUBE_ANISO
);
1144 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.cayman
.sx_max_export_size
/ 4) - 1) |
1145 POSITION_BUFFER_SIZE((rdev
->config
.cayman
.sx_max_export_pos_size
/ 4) - 1) |
1146 SMX_BUFFER_SIZE((rdev
->config
.cayman
.sx_max_export_smx_size
/ 4) - 1)));
1148 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.cayman
.sc_prim_fifo_size
) |
1149 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.cayman
.sc_hiz_tile_fifo_size
) |
1150 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.cayman
.sc_earlyz_tile_fifo_size
)));
1153 WREG32(VGT_NUM_INSTANCES
, 1);
1155 WREG32(CP_PERFMON_CNTL
, 0);
1157 WREG32(SQ_MS_FIFO_SIZES
, (CACHE_FIFO_SIZE(16 * rdev
->config
.cayman
.sq_num_cf_insts
) |
1158 FETCH_FIFO_HIWATER(0x4) |
1159 DONE_FIFO_HIWATER(0xe0) |
1160 ALU_UPDATE_FIFO_HIWATER(0x8)));
1162 WREG32(SQ_GPR_RESOURCE_MGMT_1
, NUM_CLAUSE_TEMP_GPRS(4));
1163 WREG32(SQ_CONFIG
, (VC_ENABLE
|
1168 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, DYN_GPR_ENABLE
);
1170 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
1171 FORCE_EOV_MAX_REZ_CNT(255)));
1173 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
) |
1174 AUTO_INVLD_EN(ES_AND_GS_AUTO
));
1176 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1177 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1179 WREG32(CB_PERF_CTR0_SEL_0
, 0);
1180 WREG32(CB_PERF_CTR0_SEL_1
, 0);
1181 WREG32(CB_PERF_CTR1_SEL_0
, 0);
1182 WREG32(CB_PERF_CTR1_SEL_1
, 0);
1183 WREG32(CB_PERF_CTR2_SEL_0
, 0);
1184 WREG32(CB_PERF_CTR2_SEL_1
, 0);
1185 WREG32(CB_PERF_CTR3_SEL_0
, 0);
1186 WREG32(CB_PERF_CTR3_SEL_1
, 0);
1188 tmp
= RREG32(HDP_MISC_CNTL
);
1189 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
1190 WREG32(HDP_MISC_CNTL
, tmp
);
1192 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
1193 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1195 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
1199 /* set clockgating golden values on TN */
1200 if (rdev
->family
== CHIP_ARUBA
) {
1201 tmp
= RREG32_CG(CG_CGTT_LOCAL_0
);
1203 WREG32_CG(CG_CGTT_LOCAL_0
, tmp
);
1204 tmp
= RREG32_CG(CG_CGTT_LOCAL_1
);
1206 WREG32_CG(CG_CGTT_LOCAL_1
, tmp
);
1213 void cayman_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
1215 /* flush hdp cache */
1216 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
1218 /* bits 0-7 are the VM contexts0-7 */
1219 WREG32(VM_INVALIDATE_REQUEST
, 1);
1222 static int cayman_pcie_gart_enable(struct radeon_device
*rdev
)
1226 if (rdev
->gart
.robj
== NULL
) {
1227 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
1230 r
= radeon_gart_table_vram_pin(rdev
);
1233 /* Setup TLB control */
1234 WREG32(MC_VM_MX_L1_TLB_CNTL
,
1237 ENABLE_L1_FRAGMENT_PROCESSING
|
1238 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1239 ENABLE_ADVANCED_DRIVER_MODEL
|
1240 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
);
1241 /* Setup L2 cache */
1242 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
|
1243 ENABLE_L2_FRAGMENT_PROCESSING
|
1244 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1245 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
|
1246 EFFECTIVE_L2_QUEUE_SIZE(7) |
1247 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1248 WREG32(VM_L2_CNTL2
, INVALIDATE_ALL_L1_TLBS
| INVALIDATE_L2_CACHE
);
1249 WREG32(VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
|
1251 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1252 /* setup context0 */
1253 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
1254 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
1255 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
1256 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
1257 (u32
)(rdev
->dummy_page
.addr
>> 12));
1258 WREG32(VM_CONTEXT0_CNTL2
, 0);
1259 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
1260 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1266 /* empty context1-7 */
1267 /* Assign the pt base to something valid for now; the pts used for
1268 * the VMs are determined by the application and setup and assigned
1269 * on the fly in the vm part of radeon_gart.c
1271 for (i
= 1; i
< 8; i
++) {
1272 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
+ (i
<< 2), 0);
1273 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
+ (i
<< 2), rdev
->vm_manager
.max_pfn
);
1274 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (i
<< 2),
1275 rdev
->vm_manager
.saved_table_addr
[i
]);
1278 /* enable context1-7 */
1279 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
,
1280 (u32
)(rdev
->dummy_page
.addr
>> 12));
1281 WREG32(VM_CONTEXT1_CNTL2
, 4);
1282 WREG32(VM_CONTEXT1_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(1) |
1283 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size
- 9) |
1284 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1285 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
|
1286 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1287 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
|
1288 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1289 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
|
1290 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1291 VALID_PROTECTION_FAULT_ENABLE_DEFAULT
|
1292 READ_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1293 READ_PROTECTION_FAULT_ENABLE_DEFAULT
|
1294 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
1295 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
);
1297 cayman_pcie_gart_tlb_flush(rdev
);
1298 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1299 (unsigned)(rdev
->mc
.gtt_size
>> 20),
1300 (unsigned long long)rdev
->gart
.table_addr
);
1301 rdev
->gart
.ready
= true;
1305 static void cayman_pcie_gart_disable(struct radeon_device
*rdev
)
1309 for (i
= 1; i
< 8; ++i
) {
1310 rdev
->vm_manager
.saved_table_addr
[i
] = RREG32(
1311 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (i
<< 2));
1314 /* Disable all tables */
1315 WREG32(VM_CONTEXT0_CNTL
, 0);
1316 WREG32(VM_CONTEXT1_CNTL
, 0);
1317 /* Setup TLB control */
1318 WREG32(MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
|
1319 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1320 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
);
1321 /* Setup L2 cache */
1322 WREG32(VM_L2_CNTL
, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1323 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
|
1324 EFFECTIVE_L2_QUEUE_SIZE(7) |
1325 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1326 WREG32(VM_L2_CNTL2
, 0);
1327 WREG32(VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
|
1328 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1329 radeon_gart_table_vram_unpin(rdev
);
1332 static void cayman_pcie_gart_fini(struct radeon_device
*rdev
)
1334 cayman_pcie_gart_disable(rdev
);
1335 radeon_gart_table_vram_free(rdev
);
1336 radeon_gart_fini(rdev
);
1339 void cayman_cp_int_cntl_setup(struct radeon_device
*rdev
,
1340 int ring
, u32 cp_int_cntl
)
1342 u32 srbm_gfx_cntl
= RREG32(SRBM_GFX_CNTL
) & ~3;
1344 WREG32(SRBM_GFX_CNTL
, srbm_gfx_cntl
| (ring
& 3));
1345 WREG32(CP_INT_CNTL
, cp_int_cntl
);
1351 void cayman_fence_ring_emit(struct radeon_device
*rdev
,
1352 struct radeon_fence
*fence
)
1354 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
1355 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
1356 u32 cp_coher_cntl
= PACKET3_FULL_CACHE_ENA
| PACKET3_TC_ACTION_ENA
|
1357 PACKET3_SH_ACTION_ENA
;
1359 /* flush read cache over gart for this vmid */
1360 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
1361 radeon_ring_write(ring
, PACKET3_ENGINE_ME
| cp_coher_cntl
);
1362 radeon_ring_write(ring
, 0xFFFFFFFF);
1363 radeon_ring_write(ring
, 0);
1364 radeon_ring_write(ring
, 10); /* poll interval */
1365 /* EVENT_WRITE_EOP - flush caches, send int */
1366 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
1367 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS
) | EVENT_INDEX(5));
1368 radeon_ring_write(ring
, lower_32_bits(addr
));
1369 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1370 radeon_ring_write(ring
, fence
->seq
);
1371 radeon_ring_write(ring
, 0);
1374 void cayman_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1376 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
1377 unsigned vm_id
= ib
->vm
? ib
->vm
->ids
[ib
->ring
].id
: 0;
1378 u32 cp_coher_cntl
= PACKET3_FULL_CACHE_ENA
| PACKET3_TC_ACTION_ENA
|
1379 PACKET3_SH_ACTION_ENA
;
1381 /* set to DX10/11 mode */
1382 radeon_ring_write(ring
, PACKET3(PACKET3_MODE_CONTROL
, 0));
1383 radeon_ring_write(ring
, 1);
1385 if (ring
->rptr_save_reg
) {
1386 uint32_t next_rptr
= ring
->wptr
+ 3 + 4 + 8;
1387 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1388 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
1389 PACKET3_SET_CONFIG_REG_START
) >> 2));
1390 radeon_ring_write(ring
, next_rptr
);
1393 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
1394 radeon_ring_write(ring
,
1398 (ib
->gpu_addr
& 0xFFFFFFFC));
1399 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
1400 radeon_ring_write(ring
, ib
->length_dw
| (vm_id
<< 24));
1402 /* flush read cache over gart for this vmid */
1403 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
1404 radeon_ring_write(ring
, PACKET3_ENGINE_ME
| cp_coher_cntl
);
1405 radeon_ring_write(ring
, 0xFFFFFFFF);
1406 radeon_ring_write(ring
, 0);
1407 radeon_ring_write(ring
, (vm_id
<< 24) | 10); /* poll interval */
1410 static void cayman_cp_enable(struct radeon_device
*rdev
, bool enable
)
1413 WREG32(CP_ME_CNTL
, 0);
1415 if (rdev
->asic
->copy
.copy_ring_index
== RADEON_RING_TYPE_GFX_INDEX
)
1416 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
1417 WREG32(CP_ME_CNTL
, (CP_ME_HALT
| CP_PFP_HALT
));
1418 WREG32(SCRATCH_UMSK
, 0);
1419 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
1423 u32
cayman_gfx_get_rptr(struct radeon_device
*rdev
,
1424 struct radeon_ring
*ring
)
1428 if (rdev
->wb
.enabled
)
1429 rptr
= rdev
->wb
.wb
[ring
->rptr_offs
/4];
1431 if (ring
->idx
== RADEON_RING_TYPE_GFX_INDEX
)
1432 rptr
= RREG32(CP_RB0_RPTR
);
1433 else if (ring
->idx
== CAYMAN_RING_TYPE_CP1_INDEX
)
1434 rptr
= RREG32(CP_RB1_RPTR
);
1436 rptr
= RREG32(CP_RB2_RPTR
);
1442 u32
cayman_gfx_get_wptr(struct radeon_device
*rdev
,
1443 struct radeon_ring
*ring
)
1447 if (ring
->idx
== RADEON_RING_TYPE_GFX_INDEX
)
1448 wptr
= RREG32(CP_RB0_WPTR
);
1449 else if (ring
->idx
== CAYMAN_RING_TYPE_CP1_INDEX
)
1450 wptr
= RREG32(CP_RB1_WPTR
);
1452 wptr
= RREG32(CP_RB2_WPTR
);
1457 void cayman_gfx_set_wptr(struct radeon_device
*rdev
,
1458 struct radeon_ring
*ring
)
1460 if (ring
->idx
== RADEON_RING_TYPE_GFX_INDEX
) {
1461 WREG32(CP_RB0_WPTR
, ring
->wptr
);
1462 (void)RREG32(CP_RB0_WPTR
);
1463 } else if (ring
->idx
== CAYMAN_RING_TYPE_CP1_INDEX
) {
1464 WREG32(CP_RB1_WPTR
, ring
->wptr
);
1465 (void)RREG32(CP_RB1_WPTR
);
1467 WREG32(CP_RB2_WPTR
, ring
->wptr
);
1468 (void)RREG32(CP_RB2_WPTR
);
1472 static int cayman_cp_load_microcode(struct radeon_device
*rdev
)
1474 const __be32
*fw_data
;
1477 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1480 cayman_cp_enable(rdev
, false);
1482 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1483 WREG32(CP_PFP_UCODE_ADDR
, 0);
1484 for (i
= 0; i
< CAYMAN_PFP_UCODE_SIZE
; i
++)
1485 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1486 WREG32(CP_PFP_UCODE_ADDR
, 0);
1488 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1489 WREG32(CP_ME_RAM_WADDR
, 0);
1490 for (i
= 0; i
< CAYMAN_PM4_UCODE_SIZE
; i
++)
1491 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1493 WREG32(CP_PFP_UCODE_ADDR
, 0);
1494 WREG32(CP_ME_RAM_WADDR
, 0);
1495 WREG32(CP_ME_RAM_RADDR
, 0);
1499 static int cayman_cp_start(struct radeon_device
*rdev
)
1501 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1504 r
= radeon_ring_lock(rdev
, ring
, 7);
1506 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1509 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1510 radeon_ring_write(ring
, 0x1);
1511 radeon_ring_write(ring
, 0x0);
1512 radeon_ring_write(ring
, rdev
->config
.cayman
.max_hw_contexts
- 1);
1513 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1514 radeon_ring_write(ring
, 0);
1515 radeon_ring_write(ring
, 0);
1516 radeon_ring_unlock_commit(rdev
, ring
, false);
1518 cayman_cp_enable(rdev
, true);
1520 r
= radeon_ring_lock(rdev
, ring
, cayman_default_size
+ 19);
1522 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1526 /* setup clear context state */
1527 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1528 radeon_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1530 for (i
= 0; i
< cayman_default_size
; i
++)
1531 radeon_ring_write(ring
, cayman_default_state
[i
]);
1533 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1534 radeon_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1536 /* set clear context state */
1537 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1538 radeon_ring_write(ring
, 0);
1540 /* SQ_VTX_BASE_VTX_LOC */
1541 radeon_ring_write(ring
, 0xc0026f00);
1542 radeon_ring_write(ring
, 0x00000000);
1543 radeon_ring_write(ring
, 0x00000000);
1544 radeon_ring_write(ring
, 0x00000000);
1547 radeon_ring_write(ring
, 0xc0036f00);
1548 radeon_ring_write(ring
, 0x00000bc4);
1549 radeon_ring_write(ring
, 0xffffffff);
1550 radeon_ring_write(ring
, 0xffffffff);
1551 radeon_ring_write(ring
, 0xffffffff);
1553 radeon_ring_write(ring
, 0xc0026900);
1554 radeon_ring_write(ring
, 0x00000316);
1555 radeon_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1556 radeon_ring_write(ring
, 0x00000010); /* */
1558 radeon_ring_unlock_commit(rdev
, ring
, false);
1560 /* XXX init other rings */
1565 static void cayman_cp_fini(struct radeon_device
*rdev
)
1567 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1568 cayman_cp_enable(rdev
, false);
1569 radeon_ring_fini(rdev
, ring
);
1570 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
1573 static int cayman_cp_resume(struct radeon_device
*rdev
)
1575 static const int ridx
[] = {
1576 RADEON_RING_TYPE_GFX_INDEX
,
1577 CAYMAN_RING_TYPE_CP1_INDEX
,
1578 CAYMAN_RING_TYPE_CP2_INDEX
1580 static const unsigned cp_rb_cntl
[] = {
1585 static const unsigned cp_rb_rptr_addr
[] = {
1590 static const unsigned cp_rb_rptr_addr_hi
[] = {
1591 CP_RB0_RPTR_ADDR_HI
,
1592 CP_RB1_RPTR_ADDR_HI
,
1595 static const unsigned cp_rb_base
[] = {
1600 static const unsigned cp_rb_rptr
[] = {
1605 static const unsigned cp_rb_wptr
[] = {
1610 struct radeon_ring
*ring
;
1613 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1614 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1620 RREG32(GRBM_SOFT_RESET
);
1622 WREG32(GRBM_SOFT_RESET
, 0);
1623 RREG32(GRBM_SOFT_RESET
);
1625 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
1626 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
1628 /* Set the write pointer delay */
1629 WREG32(CP_RB_WPTR_DELAY
, 0);
1631 WREG32(CP_DEBUG
, (1 << 27));
1633 /* set the wb address whether it's enabled or not */
1634 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
1635 WREG32(SCRATCH_UMSK
, 0xff);
1637 for (i
= 0; i
< 3; ++i
) {
1641 /* Set ring buffer size */
1642 ring
= &rdev
->ring
[ridx
[i
]];
1643 rb_cntl
= order_base_2(ring
->ring_size
/ 8);
1644 rb_cntl
|= order_base_2(RADEON_GPU_PAGE_SIZE
/8) << 8;
1646 rb_cntl
|= BUF_SWAP_32BIT
;
1648 WREG32(cp_rb_cntl
[i
], rb_cntl
);
1650 /* set the wb address whether it's enabled or not */
1651 addr
= rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
;
1652 WREG32(cp_rb_rptr_addr
[i
], addr
& 0xFFFFFFFC);
1653 WREG32(cp_rb_rptr_addr_hi
[i
], upper_32_bits(addr
) & 0xFF);
1656 /* set the rb base addr, this causes an internal reset of ALL rings */
1657 for (i
= 0; i
< 3; ++i
) {
1658 ring
= &rdev
->ring
[ridx
[i
]];
1659 WREG32(cp_rb_base
[i
], ring
->gpu_addr
>> 8);
1662 for (i
= 0; i
< 3; ++i
) {
1663 /* Initialize the ring buffer's read and write pointers */
1664 ring
= &rdev
->ring
[ridx
[i
]];
1665 WREG32_P(cp_rb_cntl
[i
], RB_RPTR_WR_ENA
, ~RB_RPTR_WR_ENA
);
1668 WREG32(cp_rb_rptr
[i
], 0);
1669 WREG32(cp_rb_wptr
[i
], ring
->wptr
);
1672 WREG32_P(cp_rb_cntl
[i
], 0, ~RB_RPTR_WR_ENA
);
1675 /* start the rings */
1676 cayman_cp_start(rdev
);
1677 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= true;
1678 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= false;
1679 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= false;
1680 /* this only test cp0 */
1681 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
]);
1683 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
1684 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= false;
1685 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= false;
1689 if (rdev
->asic
->copy
.copy_ring_index
== RADEON_RING_TYPE_GFX_INDEX
)
1690 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.real_vram_size
);
1695 u32
cayman_gpu_check_soft_reset(struct radeon_device
*rdev
)
1701 tmp
= RREG32(GRBM_STATUS
);
1702 if (tmp
& (PA_BUSY
| SC_BUSY
|
1704 TA_BUSY
| VGT_BUSY
|
1706 GDS_BUSY
| SPI_BUSY
|
1707 IA_BUSY
| IA_BUSY_NO_DMA
))
1708 reset_mask
|= RADEON_RESET_GFX
;
1710 if (tmp
& (CF_RQ_PENDING
| PF_RQ_PENDING
|
1711 CP_BUSY
| CP_COHERENCY_BUSY
))
1712 reset_mask
|= RADEON_RESET_CP
;
1714 if (tmp
& GRBM_EE_BUSY
)
1715 reset_mask
|= RADEON_RESET_GRBM
| RADEON_RESET_GFX
| RADEON_RESET_CP
;
1717 /* DMA_STATUS_REG 0 */
1718 tmp
= RREG32(DMA_STATUS_REG
+ DMA0_REGISTER_OFFSET
);
1719 if (!(tmp
& DMA_IDLE
))
1720 reset_mask
|= RADEON_RESET_DMA
;
1722 /* DMA_STATUS_REG 1 */
1723 tmp
= RREG32(DMA_STATUS_REG
+ DMA1_REGISTER_OFFSET
);
1724 if (!(tmp
& DMA_IDLE
))
1725 reset_mask
|= RADEON_RESET_DMA1
;
1728 tmp
= RREG32(SRBM_STATUS2
);
1730 reset_mask
|= RADEON_RESET_DMA
;
1732 if (tmp
& DMA1_BUSY
)
1733 reset_mask
|= RADEON_RESET_DMA1
;
1736 tmp
= RREG32(SRBM_STATUS
);
1737 if (tmp
& (RLC_RQ_PENDING
| RLC_BUSY
))
1738 reset_mask
|= RADEON_RESET_RLC
;
1741 reset_mask
|= RADEON_RESET_IH
;
1744 reset_mask
|= RADEON_RESET_SEM
;
1746 if (tmp
& GRBM_RQ_PENDING
)
1747 reset_mask
|= RADEON_RESET_GRBM
;
1750 reset_mask
|= RADEON_RESET_VMC
;
1752 if (tmp
& (MCB_BUSY
| MCB_NON_DISPLAY_BUSY
|
1753 MCC_BUSY
| MCD_BUSY
))
1754 reset_mask
|= RADEON_RESET_MC
;
1756 if (evergreen_is_display_hung(rdev
))
1757 reset_mask
|= RADEON_RESET_DISPLAY
;
1760 tmp
= RREG32(VM_L2_STATUS
);
1762 reset_mask
|= RADEON_RESET_VMC
;
1764 /* Skip MC reset as it's mostly likely not hung, just busy */
1765 if (reset_mask
& RADEON_RESET_MC
) {
1766 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask
);
1767 reset_mask
&= ~RADEON_RESET_MC
;
1773 static void cayman_gpu_soft_reset(struct radeon_device
*rdev
, u32 reset_mask
)
1775 struct evergreen_mc_save save
;
1776 u32 grbm_soft_reset
= 0, srbm_soft_reset
= 0;
1779 if (reset_mask
== 0)
1782 dev_info(rdev
->dev
, "GPU softreset: 0x%08X\n", reset_mask
);
1784 evergreen_print_gpu_status_regs(rdev
);
1785 dev_info(rdev
->dev
, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1787 dev_info(rdev
->dev
, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1789 dev_info(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1791 dev_info(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1794 /* Disable CP parsing/prefetching */
1795 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
);
1797 if (reset_mask
& RADEON_RESET_DMA
) {
1799 tmp
= RREG32(DMA_RB_CNTL
+ DMA0_REGISTER_OFFSET
);
1800 tmp
&= ~DMA_RB_ENABLE
;
1801 WREG32(DMA_RB_CNTL
+ DMA0_REGISTER_OFFSET
, tmp
);
1804 if (reset_mask
& RADEON_RESET_DMA1
) {
1806 tmp
= RREG32(DMA_RB_CNTL
+ DMA1_REGISTER_OFFSET
);
1807 tmp
&= ~DMA_RB_ENABLE
;
1808 WREG32(DMA_RB_CNTL
+ DMA1_REGISTER_OFFSET
, tmp
);
1813 evergreen_mc_stop(rdev
, &save
);
1814 if (evergreen_mc_wait_for_idle(rdev
)) {
1815 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1818 if (reset_mask
& (RADEON_RESET_GFX
| RADEON_RESET_COMPUTE
)) {
1819 grbm_soft_reset
= SOFT_RESET_CB
|
1833 if (reset_mask
& RADEON_RESET_CP
) {
1834 grbm_soft_reset
|= SOFT_RESET_CP
| SOFT_RESET_VGT
;
1836 srbm_soft_reset
|= SOFT_RESET_GRBM
;
1839 if (reset_mask
& RADEON_RESET_DMA
)
1840 srbm_soft_reset
|= SOFT_RESET_DMA
;
1842 if (reset_mask
& RADEON_RESET_DMA1
)
1843 srbm_soft_reset
|= SOFT_RESET_DMA1
;
1845 if (reset_mask
& RADEON_RESET_DISPLAY
)
1846 srbm_soft_reset
|= SOFT_RESET_DC
;
1848 if (reset_mask
& RADEON_RESET_RLC
)
1849 srbm_soft_reset
|= SOFT_RESET_RLC
;
1851 if (reset_mask
& RADEON_RESET_SEM
)
1852 srbm_soft_reset
|= SOFT_RESET_SEM
;
1854 if (reset_mask
& RADEON_RESET_IH
)
1855 srbm_soft_reset
|= SOFT_RESET_IH
;
1857 if (reset_mask
& RADEON_RESET_GRBM
)
1858 srbm_soft_reset
|= SOFT_RESET_GRBM
;
1860 if (reset_mask
& RADEON_RESET_VMC
)
1861 srbm_soft_reset
|= SOFT_RESET_VMC
;
1863 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
1864 if (reset_mask
& RADEON_RESET_MC
)
1865 srbm_soft_reset
|= SOFT_RESET_MC
;
1868 if (grbm_soft_reset
) {
1869 tmp
= RREG32(GRBM_SOFT_RESET
);
1870 tmp
|= grbm_soft_reset
;
1871 dev_info(rdev
->dev
, "GRBM_SOFT_RESET=0x%08X\n", tmp
);
1872 WREG32(GRBM_SOFT_RESET
, tmp
);
1873 tmp
= RREG32(GRBM_SOFT_RESET
);
1877 tmp
&= ~grbm_soft_reset
;
1878 WREG32(GRBM_SOFT_RESET
, tmp
);
1879 tmp
= RREG32(GRBM_SOFT_RESET
);
1882 if (srbm_soft_reset
) {
1883 tmp
= RREG32(SRBM_SOFT_RESET
);
1884 tmp
|= srbm_soft_reset
;
1885 dev_info(rdev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1886 WREG32(SRBM_SOFT_RESET
, tmp
);
1887 tmp
= RREG32(SRBM_SOFT_RESET
);
1891 tmp
&= ~srbm_soft_reset
;
1892 WREG32(SRBM_SOFT_RESET
, tmp
);
1893 tmp
= RREG32(SRBM_SOFT_RESET
);
1896 /* Wait a little for things to settle down */
1899 evergreen_mc_resume(rdev
, &save
);
1902 evergreen_print_gpu_status_regs(rdev
);
1905 int cayman_asic_reset(struct radeon_device
*rdev
)
1909 reset_mask
= cayman_gpu_check_soft_reset(rdev
);
1912 r600_set_bios_scratch_engine_hung(rdev
, true);
1914 cayman_gpu_soft_reset(rdev
, reset_mask
);
1916 reset_mask
= cayman_gpu_check_soft_reset(rdev
);
1919 evergreen_gpu_pci_config_reset(rdev
);
1921 r600_set_bios_scratch_engine_hung(rdev
, false);
1927 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1929 * @rdev: radeon_device pointer
1930 * @ring: radeon_ring structure holding ring information
1932 * Check if the GFX engine is locked up.
1933 * Returns true if the engine appears to be locked up, false if not.
1935 bool cayman_gfx_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
1937 u32 reset_mask
= cayman_gpu_check_soft_reset(rdev
);
1939 if (!(reset_mask
& (RADEON_RESET_GFX
|
1940 RADEON_RESET_COMPUTE
|
1941 RADEON_RESET_CP
))) {
1942 radeon_ring_lockup_update(rdev
, ring
);
1945 return radeon_ring_test_lockup(rdev
, ring
);
1948 static int cayman_startup(struct radeon_device
*rdev
)
1950 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1953 /* enable pcie gen2 link */
1954 evergreen_pcie_gen2_enable(rdev
);
1956 evergreen_program_aspm(rdev
);
1958 /* scratch needs to be initialized before MC */
1959 r
= r600_vram_scratch_init(rdev
);
1963 evergreen_mc_program(rdev
);
1965 if (!(rdev
->flags
& RADEON_IS_IGP
) && !rdev
->pm
.dpm_enabled
) {
1966 r
= ni_mc_load_microcode(rdev
);
1968 DRM_ERROR("Failed to load MC firmware!\n");
1973 r
= cayman_pcie_gart_enable(rdev
);
1976 cayman_gpu_init(rdev
);
1978 /* allocate rlc buffers */
1979 if (rdev
->flags
& RADEON_IS_IGP
) {
1980 rdev
->rlc
.reg_list
= tn_rlc_save_restore_register_list
;
1981 rdev
->rlc
.reg_list_size
=
1982 (u32
)ARRAY_SIZE(tn_rlc_save_restore_register_list
);
1983 rdev
->rlc
.cs_data
= cayman_cs_data
;
1984 r
= sumo_rlc_init(rdev
);
1986 DRM_ERROR("Failed to init rlc BOs!\n");
1991 /* allocate wb buffer */
1992 r
= radeon_wb_init(rdev
);
1996 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
1998 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
2002 r
= uvd_v2_2_resume(rdev
);
2004 r
= radeon_fence_driver_start_ring(rdev
,
2005 R600_RING_TYPE_UVD_INDEX
);
2007 dev_err(rdev
->dev
, "UVD fences init error (%d).\n", r
);
2010 rdev
->ring
[R600_RING_TYPE_UVD_INDEX
].ring_size
= 0;
2012 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
2014 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
2018 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
2020 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
2024 r
= radeon_fence_driver_start_ring(rdev
, R600_RING_TYPE_DMA_INDEX
);
2026 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
2030 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_DMA1_INDEX
);
2032 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
2037 if (!rdev
->irq
.installed
) {
2038 r
= radeon_irq_kms_init(rdev
);
2043 r
= r600_irq_init(rdev
);
2045 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
2046 radeon_irq_kms_fini(rdev
);
2049 evergreen_irq_set(rdev
);
2051 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
2056 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
2057 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, R600_WB_DMA_RPTR_OFFSET
,
2058 DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
2062 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_DMA1_INDEX
];
2063 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, CAYMAN_WB_DMA1_RPTR_OFFSET
,
2064 DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0));
2068 r
= cayman_cp_load_microcode(rdev
);
2071 r
= cayman_cp_resume(rdev
);
2075 r
= cayman_dma_resume(rdev
);
2079 ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
2080 if (ring
->ring_size
) {
2081 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, 0,
2084 r
= uvd_v1_0_init(rdev
);
2086 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r
);
2089 r
= radeon_ib_pool_init(rdev
);
2091 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
2095 r
= radeon_vm_manager_init(rdev
);
2097 dev_err(rdev
->dev
, "vm manager initialization failed (%d).\n", r
);
2101 r
= radeon_audio_init(rdev
);
2108 int cayman_resume(struct radeon_device
*rdev
)
2112 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2113 * posting will perform necessary task to bring back GPU into good
2117 atom_asic_init(rdev
->mode_info
.atom_context
);
2119 /* init golden registers */
2120 ni_init_golden_registers(rdev
);
2122 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
2123 radeon_pm_resume(rdev
);
2125 rdev
->accel_working
= true;
2126 r
= cayman_startup(rdev
);
2128 DRM_ERROR("cayman startup failed on resume\n");
2129 rdev
->accel_working
= false;
2135 int cayman_suspend(struct radeon_device
*rdev
)
2137 radeon_pm_suspend(rdev
);
2138 radeon_audio_fini(rdev
);
2139 radeon_vm_manager_fini(rdev
);
2140 cayman_cp_enable(rdev
, false);
2141 cayman_dma_stop(rdev
);
2142 uvd_v1_0_fini(rdev
);
2143 radeon_uvd_suspend(rdev
);
2144 evergreen_irq_suspend(rdev
);
2145 radeon_wb_disable(rdev
);
2146 cayman_pcie_gart_disable(rdev
);
2150 /* Plan is to move initialization in that function and use
2151 * helper function so that radeon_device_init pretty much
2152 * do nothing more than calling asic specific function. This
2153 * should also allow to remove a bunch of callback function
2156 int cayman_init(struct radeon_device
*rdev
)
2158 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2162 if (!radeon_get_bios(rdev
)) {
2163 if (ASIC_IS_AVIVO(rdev
))
2166 /* Must be an ATOMBIOS */
2167 if (!rdev
->is_atom_bios
) {
2168 dev_err(rdev
->dev
, "Expecting atombios for cayman GPU\n");
2171 r
= radeon_atombios_init(rdev
);
2175 /* Post card if necessary */
2176 if (!radeon_card_posted(rdev
)) {
2178 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2181 DRM_INFO("GPU not posted. posting now...\n");
2182 atom_asic_init(rdev
->mode_info
.atom_context
);
2184 /* init golden registers */
2185 ni_init_golden_registers(rdev
);
2186 /* Initialize scratch registers */
2187 r600_scratch_init(rdev
);
2188 /* Initialize surface registers */
2189 radeon_surface_init(rdev
);
2190 /* Initialize clocks */
2191 radeon_get_clock_info(rdev
->ddev
);
2193 r
= radeon_fence_driver_init(rdev
);
2196 /* initialize memory controller */
2197 r
= evergreen_mc_init(rdev
);
2200 /* Memory manager */
2201 r
= radeon_bo_init(rdev
);
2205 if (rdev
->flags
& RADEON_IS_IGP
) {
2206 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
2207 r
= ni_init_microcode(rdev
);
2209 DRM_ERROR("Failed to load firmware!\n");
2214 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
2215 r
= ni_init_microcode(rdev
);
2217 DRM_ERROR("Failed to load firmware!\n");
2223 /* Initialize power management */
2224 radeon_pm_init(rdev
);
2226 ring
->ring_obj
= NULL
;
2227 r600_ring_init(rdev
, ring
, 1024 * 1024);
2229 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
2230 ring
->ring_obj
= NULL
;
2231 r600_ring_init(rdev
, ring
, 64 * 1024);
2233 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_DMA1_INDEX
];
2234 ring
->ring_obj
= NULL
;
2235 r600_ring_init(rdev
, ring
, 64 * 1024);
2237 r
= radeon_uvd_init(rdev
);
2239 ring
= &rdev
->ring
[R600_RING_TYPE_UVD_INDEX
];
2240 ring
->ring_obj
= NULL
;
2241 r600_ring_init(rdev
, ring
, 4096);
2244 rdev
->ih
.ring_obj
= NULL
;
2245 r600_ih_ring_init(rdev
, 64 * 1024);
2247 r
= r600_pcie_gart_init(rdev
);
2251 rdev
->accel_working
= true;
2252 r
= cayman_startup(rdev
);
2254 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
2255 cayman_cp_fini(rdev
);
2256 cayman_dma_fini(rdev
);
2257 r600_irq_fini(rdev
);
2258 if (rdev
->flags
& RADEON_IS_IGP
)
2259 sumo_rlc_fini(rdev
);
2260 radeon_wb_fini(rdev
);
2261 radeon_ib_pool_fini(rdev
);
2262 radeon_vm_manager_fini(rdev
);
2263 radeon_irq_kms_fini(rdev
);
2264 cayman_pcie_gart_fini(rdev
);
2265 rdev
->accel_working
= false;
2268 /* Don't start up if the MC ucode is missing.
2269 * The default clocks and voltages before the MC ucode
2270 * is loaded are not suffient for advanced operations.
2272 * We can skip this check for TN, because there is no MC
2275 if (!rdev
->mc_fw
&& !(rdev
->flags
& RADEON_IS_IGP
)) {
2276 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2283 void cayman_fini(struct radeon_device
*rdev
)
2285 radeon_pm_fini(rdev
);
2286 cayman_cp_fini(rdev
);
2287 cayman_dma_fini(rdev
);
2288 r600_irq_fini(rdev
);
2289 if (rdev
->flags
& RADEON_IS_IGP
)
2290 sumo_rlc_fini(rdev
);
2291 radeon_wb_fini(rdev
);
2292 radeon_vm_manager_fini(rdev
);
2293 radeon_ib_pool_fini(rdev
);
2294 radeon_irq_kms_fini(rdev
);
2295 uvd_v1_0_fini(rdev
);
2296 radeon_uvd_fini(rdev
);
2297 cayman_pcie_gart_fini(rdev
);
2298 r600_vram_scratch_fini(rdev
);
2299 radeon_gem_fini(rdev
);
2300 radeon_fence_driver_fini(rdev
);
2301 radeon_bo_fini(rdev
);
2302 radeon_atombios_fini(rdev
);
2310 int cayman_vm_init(struct radeon_device
*rdev
)
2313 rdev
->vm_manager
.nvm
= 8;
2314 /* base offset of vram pages */
2315 if (rdev
->flags
& RADEON_IS_IGP
) {
2316 u64 tmp
= RREG32(FUS_MC_VM_FB_OFFSET
);
2318 rdev
->vm_manager
.vram_base_offset
= tmp
;
2320 rdev
->vm_manager
.vram_base_offset
= 0;
2324 void cayman_vm_fini(struct radeon_device
*rdev
)
2329 * cayman_vm_decode_fault - print human readable fault info
2331 * @rdev: radeon_device pointer
2332 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2333 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2335 * Print human readable fault information (cayman/TN).
2337 void cayman_vm_decode_fault(struct radeon_device
*rdev
,
2338 u32 status
, u32 addr
)
2340 u32 mc_id
= (status
& MEMORY_CLIENT_ID_MASK
) >> MEMORY_CLIENT_ID_SHIFT
;
2341 u32 vmid
= (status
& FAULT_VMID_MASK
) >> FAULT_VMID_SHIFT
;
2342 u32 protections
= (status
& PROTECTIONS_MASK
) >> PROTECTIONS_SHIFT
;
2434 block
= "TC_TFETCH";
2444 block
= "TC_VFETCH";
2483 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2484 protections
, vmid
, addr
,
2485 (status
& MEMORY_CLIENT_RW_MASK
) ? "write" : "read",
2490 * cayman_vm_flush - vm flush using the CP
2492 * @rdev: radeon_device pointer
2494 * Update the page table base and flush the VM TLB
2495 * using the CP (cayman-si).
2497 void cayman_vm_flush(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
2498 unsigned vm_id
, uint64_t pd_addr
)
2500 radeon_ring_write(ring
, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (vm_id
<< 2), 0));
2501 radeon_ring_write(ring
, pd_addr
>> 12);
2503 /* flush hdp cache */
2504 radeon_ring_write(ring
, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0));
2505 radeon_ring_write(ring
, 0x1);
2507 /* bits 0-7 are the VM contexts0-7 */
2508 radeon_ring_write(ring
, PACKET0(VM_INVALIDATE_REQUEST
, 0));
2509 radeon_ring_write(ring
, 1 << vm_id
);
2511 /* wait for the invalidate to complete */
2512 radeon_ring_write(ring
, PACKET3(PACKET3_WAIT_REG_MEM
, 5));
2513 radeon_ring_write(ring
, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2514 WAIT_REG_MEM_ENGINE(0))); /* me */
2515 radeon_ring_write(ring
, VM_INVALIDATE_REQUEST
>> 2);
2516 radeon_ring_write(ring
, 0);
2517 radeon_ring_write(ring
, 0); /* ref */
2518 radeon_ring_write(ring
, 0); /* mask */
2519 radeon_ring_write(ring
, 0x20); /* poll interval */
2521 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2522 radeon_ring_write(ring
, PACKET3(PACKET3_PFP_SYNC_ME
, 0));
2523 radeon_ring_write(ring
, 0x0);