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Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixes
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "r100d.h"
35 #include "rs100d.h"
36 #include "rv200d.h"
37 #include "rv250d.h"
38
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
41
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
44
45 /* Firmware Names */
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54 MODULE_FIRMWARE(FIRMWARE_R100);
55 MODULE_FIRMWARE(FIRMWARE_R200);
56 MODULE_FIRMWARE(FIRMWARE_R300);
57 MODULE_FIRMWARE(FIRMWARE_R420);
58 MODULE_FIRMWARE(FIRMWARE_RS690);
59 MODULE_FIRMWARE(FIRMWARE_RS600);
60 MODULE_FIRMWARE(FIRMWARE_R520);
61
62 #include "r100_track.h"
63
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
66 */
67
68 /* hpd for digital panel detect/disconnect */
69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
70 {
71 bool connected = false;
72
73 switch (hpd) {
74 case RADEON_HPD_1:
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
76 connected = true;
77 break;
78 case RADEON_HPD_2:
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86 }
87
88 void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90 {
91 u32 tmp;
92 bool connected = r100_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
97 if (connected)
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
99 else
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
105 if (connected)
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
107 else
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
110 break;
111 default:
112 break;
113 }
114 }
115
116 void r100_hpd_init(struct radeon_device *rdev)
117 {
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 rdev->irq.hpd[0] = true;
126 break;
127 case RADEON_HPD_2:
128 rdev->irq.hpd[1] = true;
129 break;
130 default:
131 break;
132 }
133 }
134 if (rdev->irq.installed)
135 r100_irq_set(rdev);
136 }
137
138 void r100_hpd_fini(struct radeon_device *rdev)
139 {
140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
142
143 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
144 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
145 switch (radeon_connector->hpd.hpd) {
146 case RADEON_HPD_1:
147 rdev->irq.hpd[0] = false;
148 break;
149 case RADEON_HPD_2:
150 rdev->irq.hpd[1] = false;
151 break;
152 default:
153 break;
154 }
155 }
156 }
157
158 /*
159 * PCI GART
160 */
161 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
162 {
163 /* TODO: can we do somethings here ? */
164 /* It seems hw only cache one entry so we should discard this
165 * entry otherwise if first GPU GART read hit this entry it
166 * could end up in wrong address. */
167 }
168
169 int r100_pci_gart_init(struct radeon_device *rdev)
170 {
171 int r;
172
173 if (rdev->gart.table.ram.ptr) {
174 WARN(1, "R100 PCI GART already initialized.\n");
175 return 0;
176 }
177 /* Initialize common gart structure */
178 r = radeon_gart_init(rdev);
179 if (r)
180 return r;
181 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
182 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
183 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
184 return radeon_gart_table_ram_alloc(rdev);
185 }
186
187 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
188 void r100_enable_bm(struct radeon_device *rdev)
189 {
190 uint32_t tmp;
191 /* Enable bus mastering */
192 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
193 WREG32(RADEON_BUS_CNTL, tmp);
194 }
195
196 int r100_pci_gart_enable(struct radeon_device *rdev)
197 {
198 uint32_t tmp;
199
200 /* discard memory request outside of configured range */
201 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
202 WREG32(RADEON_AIC_CNTL, tmp);
203 /* set address range for PCI address translate */
204 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
205 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
206 WREG32(RADEON_AIC_HI_ADDR, tmp);
207 /* set PCI GART page-table base address */
208 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
209 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
210 WREG32(RADEON_AIC_CNTL, tmp);
211 r100_pci_gart_tlb_flush(rdev);
212 rdev->gart.ready = true;
213 return 0;
214 }
215
216 void r100_pci_gart_disable(struct radeon_device *rdev)
217 {
218 uint32_t tmp;
219
220 /* discard memory request outside of configured range */
221 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
222 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
223 WREG32(RADEON_AIC_LO_ADDR, 0);
224 WREG32(RADEON_AIC_HI_ADDR, 0);
225 }
226
227 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
228 {
229 if (i < 0 || i > rdev->gart.num_gpu_pages) {
230 return -EINVAL;
231 }
232 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
233 return 0;
234 }
235
236 void r100_pci_gart_fini(struct radeon_device *rdev)
237 {
238 r100_pci_gart_disable(rdev);
239 radeon_gart_table_ram_free(rdev);
240 radeon_gart_fini(rdev);
241 }
242
243 int r100_irq_set(struct radeon_device *rdev)
244 {
245 uint32_t tmp = 0;
246
247 if (!rdev->irq.installed) {
248 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
249 WREG32(R_000040_GEN_INT_CNTL, 0);
250 return -EINVAL;
251 }
252 if (rdev->irq.sw_int) {
253 tmp |= RADEON_SW_INT_ENABLE;
254 }
255 if (rdev->irq.crtc_vblank_int[0]) {
256 tmp |= RADEON_CRTC_VBLANK_MASK;
257 }
258 if (rdev->irq.crtc_vblank_int[1]) {
259 tmp |= RADEON_CRTC2_VBLANK_MASK;
260 }
261 if (rdev->irq.hpd[0]) {
262 tmp |= RADEON_FP_DETECT_MASK;
263 }
264 if (rdev->irq.hpd[1]) {
265 tmp |= RADEON_FP2_DETECT_MASK;
266 }
267 WREG32(RADEON_GEN_INT_CNTL, tmp);
268 return 0;
269 }
270
271 void r100_irq_disable(struct radeon_device *rdev)
272 {
273 u32 tmp;
274
275 WREG32(R_000040_GEN_INT_CNTL, 0);
276 /* Wait and acknowledge irq */
277 mdelay(1);
278 tmp = RREG32(R_000044_GEN_INT_STATUS);
279 WREG32(R_000044_GEN_INT_STATUS, tmp);
280 }
281
282 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
283 {
284 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
285 uint32_t irq_mask = RADEON_SW_INT_TEST |
286 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
287 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
288
289 if (irqs) {
290 WREG32(RADEON_GEN_INT_STATUS, irqs);
291 }
292 return irqs & irq_mask;
293 }
294
295 int r100_irq_process(struct radeon_device *rdev)
296 {
297 uint32_t status, msi_rearm;
298 bool queue_hotplug = false;
299
300 status = r100_irq_ack(rdev);
301 if (!status) {
302 return IRQ_NONE;
303 }
304 if (rdev->shutdown) {
305 return IRQ_NONE;
306 }
307 while (status) {
308 /* SW interrupt */
309 if (status & RADEON_SW_INT_TEST) {
310 radeon_fence_process(rdev);
311 }
312 /* Vertical blank interrupts */
313 if (status & RADEON_CRTC_VBLANK_STAT) {
314 drm_handle_vblank(rdev->ddev, 0);
315 }
316 if (status & RADEON_CRTC2_VBLANK_STAT) {
317 drm_handle_vblank(rdev->ddev, 1);
318 }
319 if (status & RADEON_FP_DETECT_STAT) {
320 queue_hotplug = true;
321 DRM_DEBUG("HPD1\n");
322 }
323 if (status & RADEON_FP2_DETECT_STAT) {
324 queue_hotplug = true;
325 DRM_DEBUG("HPD2\n");
326 }
327 status = r100_irq_ack(rdev);
328 }
329 if (queue_hotplug)
330 queue_work(rdev->wq, &rdev->hotplug_work);
331 if (rdev->msi_enabled) {
332 switch (rdev->family) {
333 case CHIP_RS400:
334 case CHIP_RS480:
335 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
336 WREG32(RADEON_AIC_CNTL, msi_rearm);
337 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
338 break;
339 default:
340 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
341 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
342 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
343 break;
344 }
345 }
346 return IRQ_HANDLED;
347 }
348
349 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
350 {
351 if (crtc == 0)
352 return RREG32(RADEON_CRTC_CRNT_FRAME);
353 else
354 return RREG32(RADEON_CRTC2_CRNT_FRAME);
355 }
356
357 void r100_fence_ring_emit(struct radeon_device *rdev,
358 struct radeon_fence *fence)
359 {
360 /* Who ever call radeon_fence_emit should call ring_lock and ask
361 * for enough space (today caller are ib schedule and buffer move) */
362 /* Wait until IDLE & CLEAN */
363 radeon_ring_write(rdev, PACKET0(0x1720, 0));
364 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
365 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
366 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
367 RADEON_HDP_READ_BUFFER_INVALIDATE);
368 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
369 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
370 /* Emit fence sequence & fire IRQ */
371 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
372 radeon_ring_write(rdev, fence->seq);
373 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
374 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
375 }
376
377 int r100_wb_init(struct radeon_device *rdev)
378 {
379 int r;
380
381 if (rdev->wb.wb_obj == NULL) {
382 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
383 RADEON_GEM_DOMAIN_GTT,
384 &rdev->wb.wb_obj);
385 if (r) {
386 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
387 return r;
388 }
389 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
390 if (unlikely(r != 0))
391 return r;
392 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
393 &rdev->wb.gpu_addr);
394 if (r) {
395 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
396 radeon_bo_unreserve(rdev->wb.wb_obj);
397 return r;
398 }
399 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
400 radeon_bo_unreserve(rdev->wb.wb_obj);
401 if (r) {
402 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
403 return r;
404 }
405 }
406 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
407 WREG32(R_00070C_CP_RB_RPTR_ADDR,
408 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
409 WREG32(R_000770_SCRATCH_UMSK, 0xff);
410 return 0;
411 }
412
413 void r100_wb_disable(struct radeon_device *rdev)
414 {
415 WREG32(R_000770_SCRATCH_UMSK, 0);
416 }
417
418 void r100_wb_fini(struct radeon_device *rdev)
419 {
420 int r;
421
422 r100_wb_disable(rdev);
423 if (rdev->wb.wb_obj) {
424 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
425 if (unlikely(r != 0)) {
426 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
427 return;
428 }
429 radeon_bo_kunmap(rdev->wb.wb_obj);
430 radeon_bo_unpin(rdev->wb.wb_obj);
431 radeon_bo_unreserve(rdev->wb.wb_obj);
432 radeon_bo_unref(&rdev->wb.wb_obj);
433 rdev->wb.wb = NULL;
434 rdev->wb.wb_obj = NULL;
435 }
436 }
437
438 int r100_copy_blit(struct radeon_device *rdev,
439 uint64_t src_offset,
440 uint64_t dst_offset,
441 unsigned num_pages,
442 struct radeon_fence *fence)
443 {
444 uint32_t cur_pages;
445 uint32_t stride_bytes = PAGE_SIZE;
446 uint32_t pitch;
447 uint32_t stride_pixels;
448 unsigned ndw;
449 int num_loops;
450 int r = 0;
451
452 /* radeon limited to 16k stride */
453 stride_bytes &= 0x3fff;
454 /* radeon pitch is /64 */
455 pitch = stride_bytes / 64;
456 stride_pixels = stride_bytes / 4;
457 num_loops = DIV_ROUND_UP(num_pages, 8191);
458
459 /* Ask for enough room for blit + flush + fence */
460 ndw = 64 + (10 * num_loops);
461 r = radeon_ring_lock(rdev, ndw);
462 if (r) {
463 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
464 return -EINVAL;
465 }
466 while (num_pages > 0) {
467 cur_pages = num_pages;
468 if (cur_pages > 8191) {
469 cur_pages = 8191;
470 }
471 num_pages -= cur_pages;
472
473 /* pages are in Y direction - height
474 page width in X direction - width */
475 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
476 radeon_ring_write(rdev,
477 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
478 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
479 RADEON_GMC_SRC_CLIPPING |
480 RADEON_GMC_DST_CLIPPING |
481 RADEON_GMC_BRUSH_NONE |
482 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
483 RADEON_GMC_SRC_DATATYPE_COLOR |
484 RADEON_ROP3_S |
485 RADEON_DP_SRC_SOURCE_MEMORY |
486 RADEON_GMC_CLR_CMP_CNTL_DIS |
487 RADEON_GMC_WR_MSK_DIS);
488 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
489 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
490 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
491 radeon_ring_write(rdev, 0);
492 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
493 radeon_ring_write(rdev, num_pages);
494 radeon_ring_write(rdev, num_pages);
495 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
496 }
497 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
498 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
499 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
500 radeon_ring_write(rdev,
501 RADEON_WAIT_2D_IDLECLEAN |
502 RADEON_WAIT_HOST_IDLECLEAN |
503 RADEON_WAIT_DMA_GUI_IDLE);
504 if (fence) {
505 r = radeon_fence_emit(rdev, fence);
506 }
507 radeon_ring_unlock_commit(rdev);
508 return r;
509 }
510
511 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
512 {
513 unsigned i;
514 u32 tmp;
515
516 for (i = 0; i < rdev->usec_timeout; i++) {
517 tmp = RREG32(R_000E40_RBBM_STATUS);
518 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
519 return 0;
520 }
521 udelay(1);
522 }
523 return -1;
524 }
525
526 void r100_ring_start(struct radeon_device *rdev)
527 {
528 int r;
529
530 r = radeon_ring_lock(rdev, 2);
531 if (r) {
532 return;
533 }
534 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
535 radeon_ring_write(rdev,
536 RADEON_ISYNC_ANY2D_IDLE3D |
537 RADEON_ISYNC_ANY3D_IDLE2D |
538 RADEON_ISYNC_WAIT_IDLEGUI |
539 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
540 radeon_ring_unlock_commit(rdev);
541 }
542
543
544 /* Load the microcode for the CP */
545 static int r100_cp_init_microcode(struct radeon_device *rdev)
546 {
547 struct platform_device *pdev;
548 const char *fw_name = NULL;
549 int err;
550
551 DRM_DEBUG("\n");
552
553 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
554 err = IS_ERR(pdev);
555 if (err) {
556 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
557 return -EINVAL;
558 }
559 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
560 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
561 (rdev->family == CHIP_RS200)) {
562 DRM_INFO("Loading R100 Microcode\n");
563 fw_name = FIRMWARE_R100;
564 } else if ((rdev->family == CHIP_R200) ||
565 (rdev->family == CHIP_RV250) ||
566 (rdev->family == CHIP_RV280) ||
567 (rdev->family == CHIP_RS300)) {
568 DRM_INFO("Loading R200 Microcode\n");
569 fw_name = FIRMWARE_R200;
570 } else if ((rdev->family == CHIP_R300) ||
571 (rdev->family == CHIP_R350) ||
572 (rdev->family == CHIP_RV350) ||
573 (rdev->family == CHIP_RV380) ||
574 (rdev->family == CHIP_RS400) ||
575 (rdev->family == CHIP_RS480)) {
576 DRM_INFO("Loading R300 Microcode\n");
577 fw_name = FIRMWARE_R300;
578 } else if ((rdev->family == CHIP_R420) ||
579 (rdev->family == CHIP_R423) ||
580 (rdev->family == CHIP_RV410)) {
581 DRM_INFO("Loading R400 Microcode\n");
582 fw_name = FIRMWARE_R420;
583 } else if ((rdev->family == CHIP_RS690) ||
584 (rdev->family == CHIP_RS740)) {
585 DRM_INFO("Loading RS690/RS740 Microcode\n");
586 fw_name = FIRMWARE_RS690;
587 } else if (rdev->family == CHIP_RS600) {
588 DRM_INFO("Loading RS600 Microcode\n");
589 fw_name = FIRMWARE_RS600;
590 } else if ((rdev->family == CHIP_RV515) ||
591 (rdev->family == CHIP_R520) ||
592 (rdev->family == CHIP_RV530) ||
593 (rdev->family == CHIP_R580) ||
594 (rdev->family == CHIP_RV560) ||
595 (rdev->family == CHIP_RV570)) {
596 DRM_INFO("Loading R500 Microcode\n");
597 fw_name = FIRMWARE_R520;
598 }
599
600 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
601 platform_device_unregister(pdev);
602 if (err) {
603 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
604 fw_name);
605 } else if (rdev->me_fw->size % 8) {
606 printk(KERN_ERR
607 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
608 rdev->me_fw->size, fw_name);
609 err = -EINVAL;
610 release_firmware(rdev->me_fw);
611 rdev->me_fw = NULL;
612 }
613 return err;
614 }
615
616 static void r100_cp_load_microcode(struct radeon_device *rdev)
617 {
618 const __be32 *fw_data;
619 int i, size;
620
621 if (r100_gui_wait_for_idle(rdev)) {
622 printk(KERN_WARNING "Failed to wait GUI idle while "
623 "programming pipes. Bad things might happen.\n");
624 }
625
626 if (rdev->me_fw) {
627 size = rdev->me_fw->size / 4;
628 fw_data = (const __be32 *)&rdev->me_fw->data[0];
629 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
630 for (i = 0; i < size; i += 2) {
631 WREG32(RADEON_CP_ME_RAM_DATAH,
632 be32_to_cpup(&fw_data[i]));
633 WREG32(RADEON_CP_ME_RAM_DATAL,
634 be32_to_cpup(&fw_data[i + 1]));
635 }
636 }
637 }
638
639 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
640 {
641 unsigned rb_bufsz;
642 unsigned rb_blksz;
643 unsigned max_fetch;
644 unsigned pre_write_timer;
645 unsigned pre_write_limit;
646 unsigned indirect2_start;
647 unsigned indirect1_start;
648 uint32_t tmp;
649 int r;
650
651 if (r100_debugfs_cp_init(rdev)) {
652 DRM_ERROR("Failed to register debugfs file for CP !\n");
653 }
654 /* Reset CP */
655 tmp = RREG32(RADEON_CP_CSQ_STAT);
656 if ((tmp & (1 << 31))) {
657 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
658 WREG32(RADEON_CP_CSQ_MODE, 0);
659 WREG32(RADEON_CP_CSQ_CNTL, 0);
660 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
661 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
662 mdelay(2);
663 WREG32(RADEON_RBBM_SOFT_RESET, 0);
664 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
665 mdelay(2);
666 tmp = RREG32(RADEON_CP_CSQ_STAT);
667 if ((tmp & (1 << 31))) {
668 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
669 }
670 } else {
671 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
672 }
673
674 if (!rdev->me_fw) {
675 r = r100_cp_init_microcode(rdev);
676 if (r) {
677 DRM_ERROR("Failed to load firmware!\n");
678 return r;
679 }
680 }
681
682 /* Align ring size */
683 rb_bufsz = drm_order(ring_size / 8);
684 ring_size = (1 << (rb_bufsz + 1)) * 4;
685 r100_cp_load_microcode(rdev);
686 r = radeon_ring_init(rdev, ring_size);
687 if (r) {
688 return r;
689 }
690 /* Each time the cp read 1024 bytes (16 dword/quadword) update
691 * the rptr copy in system ram */
692 rb_blksz = 9;
693 /* cp will read 128bytes at a time (4 dwords) */
694 max_fetch = 1;
695 rdev->cp.align_mask = 16 - 1;
696 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
697 pre_write_timer = 64;
698 /* Force CP_RB_WPTR write if written more than one time before the
699 * delay expire
700 */
701 pre_write_limit = 0;
702 /* Setup the cp cache like this (cache size is 96 dwords) :
703 * RING 0 to 15
704 * INDIRECT1 16 to 79
705 * INDIRECT2 80 to 95
706 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
707 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
708 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
709 * Idea being that most of the gpu cmd will be through indirect1 buffer
710 * so it gets the bigger cache.
711 */
712 indirect2_start = 80;
713 indirect1_start = 16;
714 /* cp setup */
715 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
716 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
717 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
718 REG_SET(RADEON_MAX_FETCH, max_fetch) |
719 RADEON_RB_NO_UPDATE);
720 #ifdef __BIG_ENDIAN
721 tmp |= RADEON_BUF_SWAP_32BIT;
722 #endif
723 WREG32(RADEON_CP_RB_CNTL, tmp);
724
725 /* Set ring address */
726 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
727 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
728 /* Force read & write ptr to 0 */
729 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
730 WREG32(RADEON_CP_RB_RPTR_WR, 0);
731 WREG32(RADEON_CP_RB_WPTR, 0);
732 WREG32(RADEON_CP_RB_CNTL, tmp);
733 udelay(10);
734 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
735 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
736 /* Set cp mode to bus mastering & enable cp*/
737 WREG32(RADEON_CP_CSQ_MODE,
738 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
739 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
740 WREG32(0x718, 0);
741 WREG32(0x744, 0x00004D4D);
742 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
743 radeon_ring_start(rdev);
744 r = radeon_ring_test(rdev);
745 if (r) {
746 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
747 return r;
748 }
749 rdev->cp.ready = true;
750 return 0;
751 }
752
753 void r100_cp_fini(struct radeon_device *rdev)
754 {
755 if (r100_cp_wait_for_idle(rdev)) {
756 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
757 }
758 /* Disable ring */
759 r100_cp_disable(rdev);
760 radeon_ring_fini(rdev);
761 DRM_INFO("radeon: cp finalized\n");
762 }
763
764 void r100_cp_disable(struct radeon_device *rdev)
765 {
766 /* Disable ring */
767 rdev->cp.ready = false;
768 WREG32(RADEON_CP_CSQ_MODE, 0);
769 WREG32(RADEON_CP_CSQ_CNTL, 0);
770 if (r100_gui_wait_for_idle(rdev)) {
771 printk(KERN_WARNING "Failed to wait GUI idle while "
772 "programming pipes. Bad things might happen.\n");
773 }
774 }
775
776 int r100_cp_reset(struct radeon_device *rdev)
777 {
778 uint32_t tmp;
779 bool reinit_cp;
780 int i;
781
782 reinit_cp = rdev->cp.ready;
783 rdev->cp.ready = false;
784 WREG32(RADEON_CP_CSQ_MODE, 0);
785 WREG32(RADEON_CP_CSQ_CNTL, 0);
786 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
787 (void)RREG32(RADEON_RBBM_SOFT_RESET);
788 udelay(200);
789 WREG32(RADEON_RBBM_SOFT_RESET, 0);
790 /* Wait to prevent race in RBBM_STATUS */
791 mdelay(1);
792 for (i = 0; i < rdev->usec_timeout; i++) {
793 tmp = RREG32(RADEON_RBBM_STATUS);
794 if (!(tmp & (1 << 16))) {
795 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
796 tmp);
797 if (reinit_cp) {
798 return r100_cp_init(rdev, rdev->cp.ring_size);
799 }
800 return 0;
801 }
802 DRM_UDELAY(1);
803 }
804 tmp = RREG32(RADEON_RBBM_STATUS);
805 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
806 return -1;
807 }
808
809 void r100_cp_commit(struct radeon_device *rdev)
810 {
811 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
812 (void)RREG32(RADEON_CP_RB_WPTR);
813 }
814
815
816 /*
817 * CS functions
818 */
819 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
820 struct radeon_cs_packet *pkt,
821 const unsigned *auth, unsigned n,
822 radeon_packet0_check_t check)
823 {
824 unsigned reg;
825 unsigned i, j, m;
826 unsigned idx;
827 int r;
828
829 idx = pkt->idx + 1;
830 reg = pkt->reg;
831 /* Check that register fall into register range
832 * determined by the number of entry (n) in the
833 * safe register bitmap.
834 */
835 if (pkt->one_reg_wr) {
836 if ((reg >> 7) > n) {
837 return -EINVAL;
838 }
839 } else {
840 if (((reg + (pkt->count << 2)) >> 7) > n) {
841 return -EINVAL;
842 }
843 }
844 for (i = 0; i <= pkt->count; i++, idx++) {
845 j = (reg >> 7);
846 m = 1 << ((reg >> 2) & 31);
847 if (auth[j] & m) {
848 r = check(p, pkt, idx, reg);
849 if (r) {
850 return r;
851 }
852 }
853 if (pkt->one_reg_wr) {
854 if (!(auth[j] & m)) {
855 break;
856 }
857 } else {
858 reg += 4;
859 }
860 }
861 return 0;
862 }
863
864 void r100_cs_dump_packet(struct radeon_cs_parser *p,
865 struct radeon_cs_packet *pkt)
866 {
867 volatile uint32_t *ib;
868 unsigned i;
869 unsigned idx;
870
871 ib = p->ib->ptr;
872 idx = pkt->idx;
873 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
874 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
875 }
876 }
877
878 /**
879 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
880 * @parser: parser structure holding parsing context.
881 * @pkt: where to store packet informations
882 *
883 * Assume that chunk_ib_index is properly set. Will return -EINVAL
884 * if packet is bigger than remaining ib size. or if packets is unknown.
885 **/
886 int r100_cs_packet_parse(struct radeon_cs_parser *p,
887 struct radeon_cs_packet *pkt,
888 unsigned idx)
889 {
890 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
891 uint32_t header;
892
893 if (idx >= ib_chunk->length_dw) {
894 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
895 idx, ib_chunk->length_dw);
896 return -EINVAL;
897 }
898 header = radeon_get_ib_value(p, idx);
899 pkt->idx = idx;
900 pkt->type = CP_PACKET_GET_TYPE(header);
901 pkt->count = CP_PACKET_GET_COUNT(header);
902 switch (pkt->type) {
903 case PACKET_TYPE0:
904 pkt->reg = CP_PACKET0_GET_REG(header);
905 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
906 break;
907 case PACKET_TYPE3:
908 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
909 break;
910 case PACKET_TYPE2:
911 pkt->count = -1;
912 break;
913 default:
914 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
915 return -EINVAL;
916 }
917 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
918 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
919 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
920 return -EINVAL;
921 }
922 return 0;
923 }
924
925 /**
926 * r100_cs_packet_next_vline() - parse userspace VLINE packet
927 * @parser: parser structure holding parsing context.
928 *
929 * Userspace sends a special sequence for VLINE waits.
930 * PACKET0 - VLINE_START_END + value
931 * PACKET0 - WAIT_UNTIL +_value
932 * RELOC (P3) - crtc_id in reloc.
933 *
934 * This function parses this and relocates the VLINE START END
935 * and WAIT UNTIL packets to the correct crtc.
936 * It also detects a switched off crtc and nulls out the
937 * wait in that case.
938 */
939 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
940 {
941 struct drm_mode_object *obj;
942 struct drm_crtc *crtc;
943 struct radeon_crtc *radeon_crtc;
944 struct radeon_cs_packet p3reloc, waitreloc;
945 int crtc_id;
946 int r;
947 uint32_t header, h_idx, reg;
948 volatile uint32_t *ib;
949
950 ib = p->ib->ptr;
951
952 /* parse the wait until */
953 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
954 if (r)
955 return r;
956
957 /* check its a wait until and only 1 count */
958 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
959 waitreloc.count != 0) {
960 DRM_ERROR("vline wait had illegal wait until segment\n");
961 r = -EINVAL;
962 return r;
963 }
964
965 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
966 DRM_ERROR("vline wait had illegal wait until\n");
967 r = -EINVAL;
968 return r;
969 }
970
971 /* jump over the NOP */
972 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
973 if (r)
974 return r;
975
976 h_idx = p->idx - 2;
977 p->idx += waitreloc.count + 2;
978 p->idx += p3reloc.count + 2;
979
980 header = radeon_get_ib_value(p, h_idx);
981 crtc_id = radeon_get_ib_value(p, h_idx + 5);
982 reg = CP_PACKET0_GET_REG(header);
983 mutex_lock(&p->rdev->ddev->mode_config.mutex);
984 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
985 if (!obj) {
986 DRM_ERROR("cannot find crtc %d\n", crtc_id);
987 r = -EINVAL;
988 goto out;
989 }
990 crtc = obj_to_crtc(obj);
991 radeon_crtc = to_radeon_crtc(crtc);
992 crtc_id = radeon_crtc->crtc_id;
993
994 if (!crtc->enabled) {
995 /* if the CRTC isn't enabled - we need to nop out the wait until */
996 ib[h_idx + 2] = PACKET2(0);
997 ib[h_idx + 3] = PACKET2(0);
998 } else if (crtc_id == 1) {
999 switch (reg) {
1000 case AVIVO_D1MODE_VLINE_START_END:
1001 header &= ~R300_CP_PACKET0_REG_MASK;
1002 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1003 break;
1004 case RADEON_CRTC_GUI_TRIG_VLINE:
1005 header &= ~R300_CP_PACKET0_REG_MASK;
1006 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1007 break;
1008 default:
1009 DRM_ERROR("unknown crtc reloc\n");
1010 r = -EINVAL;
1011 goto out;
1012 }
1013 ib[h_idx] = header;
1014 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1015 }
1016 out:
1017 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1018 return r;
1019 }
1020
1021 /**
1022 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1023 * @parser: parser structure holding parsing context.
1024 * @data: pointer to relocation data
1025 * @offset_start: starting offset
1026 * @offset_mask: offset mask (to align start offset on)
1027 * @reloc: reloc informations
1028 *
1029 * Check next packet is relocation packet3, do bo validation and compute
1030 * GPU offset using the provided start.
1031 **/
1032 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1033 struct radeon_cs_reloc **cs_reloc)
1034 {
1035 struct radeon_cs_chunk *relocs_chunk;
1036 struct radeon_cs_packet p3reloc;
1037 unsigned idx;
1038 int r;
1039
1040 if (p->chunk_relocs_idx == -1) {
1041 DRM_ERROR("No relocation chunk !\n");
1042 return -EINVAL;
1043 }
1044 *cs_reloc = NULL;
1045 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1046 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1047 if (r) {
1048 return r;
1049 }
1050 p->idx += p3reloc.count + 2;
1051 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1052 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1053 p3reloc.idx);
1054 r100_cs_dump_packet(p, &p3reloc);
1055 return -EINVAL;
1056 }
1057 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1058 if (idx >= relocs_chunk->length_dw) {
1059 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1060 idx, relocs_chunk->length_dw);
1061 r100_cs_dump_packet(p, &p3reloc);
1062 return -EINVAL;
1063 }
1064 /* FIXME: we assume reloc size is 4 dwords */
1065 *cs_reloc = p->relocs_ptr[(idx / 4)];
1066 return 0;
1067 }
1068
1069 static int r100_get_vtx_size(uint32_t vtx_fmt)
1070 {
1071 int vtx_size;
1072 vtx_size = 2;
1073 /* ordered according to bits in spec */
1074 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1075 vtx_size++;
1076 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1077 vtx_size += 3;
1078 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1079 vtx_size++;
1080 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1081 vtx_size++;
1082 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1083 vtx_size += 3;
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1085 vtx_size++;
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1087 vtx_size++;
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1089 vtx_size += 2;
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1091 vtx_size += 2;
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1093 vtx_size++;
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1095 vtx_size += 2;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1097 vtx_size++;
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1099 vtx_size += 2;
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1101 vtx_size++;
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1103 vtx_size++;
1104 /* blend weight */
1105 if (vtx_fmt & (0x7 << 15))
1106 vtx_size += (vtx_fmt >> 15) & 0x7;
1107 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1108 vtx_size += 3;
1109 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1110 vtx_size += 2;
1111 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1112 vtx_size++;
1113 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1114 vtx_size++;
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1116 vtx_size++;
1117 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1118 vtx_size++;
1119 return vtx_size;
1120 }
1121
1122 static int r100_packet0_check(struct radeon_cs_parser *p,
1123 struct radeon_cs_packet *pkt,
1124 unsigned idx, unsigned reg)
1125 {
1126 struct radeon_cs_reloc *reloc;
1127 struct r100_cs_track *track;
1128 volatile uint32_t *ib;
1129 uint32_t tmp;
1130 int r;
1131 int i, face;
1132 u32 tile_flags = 0;
1133 u32 idx_value;
1134
1135 ib = p->ib->ptr;
1136 track = (struct r100_cs_track *)p->track;
1137
1138 idx_value = radeon_get_ib_value(p, idx);
1139
1140 switch (reg) {
1141 case RADEON_CRTC_GUI_TRIG_VLINE:
1142 r = r100_cs_packet_parse_vline(p);
1143 if (r) {
1144 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1145 idx, reg);
1146 r100_cs_dump_packet(p, pkt);
1147 return r;
1148 }
1149 break;
1150 /* FIXME: only allow PACKET3 blit? easier to check for out of
1151 * range access */
1152 case RADEON_DST_PITCH_OFFSET:
1153 case RADEON_SRC_PITCH_OFFSET:
1154 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1155 if (r)
1156 return r;
1157 break;
1158 case RADEON_RB3D_DEPTHOFFSET:
1159 r = r100_cs_packet_next_reloc(p, &reloc);
1160 if (r) {
1161 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1162 idx, reg);
1163 r100_cs_dump_packet(p, pkt);
1164 return r;
1165 }
1166 track->zb.robj = reloc->robj;
1167 track->zb.offset = idx_value;
1168 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1169 break;
1170 case RADEON_RB3D_COLOROFFSET:
1171 r = r100_cs_packet_next_reloc(p, &reloc);
1172 if (r) {
1173 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1174 idx, reg);
1175 r100_cs_dump_packet(p, pkt);
1176 return r;
1177 }
1178 track->cb[0].robj = reloc->robj;
1179 track->cb[0].offset = idx_value;
1180 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1181 break;
1182 case RADEON_PP_TXOFFSET_0:
1183 case RADEON_PP_TXOFFSET_1:
1184 case RADEON_PP_TXOFFSET_2:
1185 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1186 r = r100_cs_packet_next_reloc(p, &reloc);
1187 if (r) {
1188 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1189 idx, reg);
1190 r100_cs_dump_packet(p, pkt);
1191 return r;
1192 }
1193 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1194 track->textures[i].robj = reloc->robj;
1195 break;
1196 case RADEON_PP_CUBIC_OFFSET_T0_0:
1197 case RADEON_PP_CUBIC_OFFSET_T0_1:
1198 case RADEON_PP_CUBIC_OFFSET_T0_2:
1199 case RADEON_PP_CUBIC_OFFSET_T0_3:
1200 case RADEON_PP_CUBIC_OFFSET_T0_4:
1201 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1202 r = r100_cs_packet_next_reloc(p, &reloc);
1203 if (r) {
1204 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1205 idx, reg);
1206 r100_cs_dump_packet(p, pkt);
1207 return r;
1208 }
1209 track->textures[0].cube_info[i].offset = idx_value;
1210 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1211 track->textures[0].cube_info[i].robj = reloc->robj;
1212 break;
1213 case RADEON_PP_CUBIC_OFFSET_T1_0:
1214 case RADEON_PP_CUBIC_OFFSET_T1_1:
1215 case RADEON_PP_CUBIC_OFFSET_T1_2:
1216 case RADEON_PP_CUBIC_OFFSET_T1_3:
1217 case RADEON_PP_CUBIC_OFFSET_T1_4:
1218 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1219 r = r100_cs_packet_next_reloc(p, &reloc);
1220 if (r) {
1221 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1222 idx, reg);
1223 r100_cs_dump_packet(p, pkt);
1224 return r;
1225 }
1226 track->textures[1].cube_info[i].offset = idx_value;
1227 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1228 track->textures[1].cube_info[i].robj = reloc->robj;
1229 break;
1230 case RADEON_PP_CUBIC_OFFSET_T2_0:
1231 case RADEON_PP_CUBIC_OFFSET_T2_1:
1232 case RADEON_PP_CUBIC_OFFSET_T2_2:
1233 case RADEON_PP_CUBIC_OFFSET_T2_3:
1234 case RADEON_PP_CUBIC_OFFSET_T2_4:
1235 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1236 r = r100_cs_packet_next_reloc(p, &reloc);
1237 if (r) {
1238 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1239 idx, reg);
1240 r100_cs_dump_packet(p, pkt);
1241 return r;
1242 }
1243 track->textures[2].cube_info[i].offset = idx_value;
1244 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1245 track->textures[2].cube_info[i].robj = reloc->robj;
1246 break;
1247 case RADEON_RE_WIDTH_HEIGHT:
1248 track->maxy = ((idx_value >> 16) & 0x7FF);
1249 break;
1250 case RADEON_RB3D_COLORPITCH:
1251 r = r100_cs_packet_next_reloc(p, &reloc);
1252 if (r) {
1253 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1254 idx, reg);
1255 r100_cs_dump_packet(p, pkt);
1256 return r;
1257 }
1258
1259 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1260 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1261 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1262 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1263
1264 tmp = idx_value & ~(0x7 << 16);
1265 tmp |= tile_flags;
1266 ib[idx] = tmp;
1267
1268 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1269 break;
1270 case RADEON_RB3D_DEPTHPITCH:
1271 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1272 break;
1273 case RADEON_RB3D_CNTL:
1274 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1275 case 7:
1276 case 8:
1277 case 9:
1278 case 11:
1279 case 12:
1280 track->cb[0].cpp = 1;
1281 break;
1282 case 3:
1283 case 4:
1284 case 15:
1285 track->cb[0].cpp = 2;
1286 break;
1287 case 6:
1288 track->cb[0].cpp = 4;
1289 break;
1290 default:
1291 DRM_ERROR("Invalid color buffer format (%d) !\n",
1292 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1293 return -EINVAL;
1294 }
1295 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1296 break;
1297 case RADEON_RB3D_ZSTENCILCNTL:
1298 switch (idx_value & 0xf) {
1299 case 0:
1300 track->zb.cpp = 2;
1301 break;
1302 case 2:
1303 case 3:
1304 case 4:
1305 case 5:
1306 case 9:
1307 case 11:
1308 track->zb.cpp = 4;
1309 break;
1310 default:
1311 break;
1312 }
1313 break;
1314 case RADEON_RB3D_ZPASS_ADDR:
1315 r = r100_cs_packet_next_reloc(p, &reloc);
1316 if (r) {
1317 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1318 idx, reg);
1319 r100_cs_dump_packet(p, pkt);
1320 return r;
1321 }
1322 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1323 break;
1324 case RADEON_PP_CNTL:
1325 {
1326 uint32_t temp = idx_value >> 4;
1327 for (i = 0; i < track->num_texture; i++)
1328 track->textures[i].enabled = !!(temp & (1 << i));
1329 }
1330 break;
1331 case RADEON_SE_VF_CNTL:
1332 track->vap_vf_cntl = idx_value;
1333 break;
1334 case RADEON_SE_VTX_FMT:
1335 track->vtx_size = r100_get_vtx_size(idx_value);
1336 break;
1337 case RADEON_PP_TEX_SIZE_0:
1338 case RADEON_PP_TEX_SIZE_1:
1339 case RADEON_PP_TEX_SIZE_2:
1340 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1341 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1342 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1343 break;
1344 case RADEON_PP_TEX_PITCH_0:
1345 case RADEON_PP_TEX_PITCH_1:
1346 case RADEON_PP_TEX_PITCH_2:
1347 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1348 track->textures[i].pitch = idx_value + 32;
1349 break;
1350 case RADEON_PP_TXFILTER_0:
1351 case RADEON_PP_TXFILTER_1:
1352 case RADEON_PP_TXFILTER_2:
1353 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1354 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1355 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1356 tmp = (idx_value >> 23) & 0x7;
1357 if (tmp == 2 || tmp == 6)
1358 track->textures[i].roundup_w = false;
1359 tmp = (idx_value >> 27) & 0x7;
1360 if (tmp == 2 || tmp == 6)
1361 track->textures[i].roundup_h = false;
1362 break;
1363 case RADEON_PP_TXFORMAT_0:
1364 case RADEON_PP_TXFORMAT_1:
1365 case RADEON_PP_TXFORMAT_2:
1366 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1367 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1368 track->textures[i].use_pitch = 1;
1369 } else {
1370 track->textures[i].use_pitch = 0;
1371 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1372 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1373 }
1374 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1375 track->textures[i].tex_coord_type = 2;
1376 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1377 case RADEON_TXFORMAT_I8:
1378 case RADEON_TXFORMAT_RGB332:
1379 case RADEON_TXFORMAT_Y8:
1380 track->textures[i].cpp = 1;
1381 break;
1382 case RADEON_TXFORMAT_AI88:
1383 case RADEON_TXFORMAT_ARGB1555:
1384 case RADEON_TXFORMAT_RGB565:
1385 case RADEON_TXFORMAT_ARGB4444:
1386 case RADEON_TXFORMAT_VYUY422:
1387 case RADEON_TXFORMAT_YVYU422:
1388 case RADEON_TXFORMAT_SHADOW16:
1389 case RADEON_TXFORMAT_LDUDV655:
1390 case RADEON_TXFORMAT_DUDV88:
1391 track->textures[i].cpp = 2;
1392 break;
1393 case RADEON_TXFORMAT_ARGB8888:
1394 case RADEON_TXFORMAT_RGBA8888:
1395 case RADEON_TXFORMAT_SHADOW32:
1396 case RADEON_TXFORMAT_LDUDUV8888:
1397 track->textures[i].cpp = 4;
1398 break;
1399 case RADEON_TXFORMAT_DXT1:
1400 track->textures[i].cpp = 1;
1401 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1402 break;
1403 case RADEON_TXFORMAT_DXT23:
1404 case RADEON_TXFORMAT_DXT45:
1405 track->textures[i].cpp = 1;
1406 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1407 break;
1408 }
1409 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1410 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1411 break;
1412 case RADEON_PP_CUBIC_FACES_0:
1413 case RADEON_PP_CUBIC_FACES_1:
1414 case RADEON_PP_CUBIC_FACES_2:
1415 tmp = idx_value;
1416 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1417 for (face = 0; face < 4; face++) {
1418 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1419 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1420 }
1421 break;
1422 default:
1423 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1424 reg, idx);
1425 return -EINVAL;
1426 }
1427 return 0;
1428 }
1429
1430 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1431 struct radeon_cs_packet *pkt,
1432 struct radeon_bo *robj)
1433 {
1434 unsigned idx;
1435 u32 value;
1436 idx = pkt->idx + 1;
1437 value = radeon_get_ib_value(p, idx + 2);
1438 if ((value + 1) > radeon_bo_size(robj)) {
1439 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1440 "(need %u have %lu) !\n",
1441 value + 1,
1442 radeon_bo_size(robj));
1443 return -EINVAL;
1444 }
1445 return 0;
1446 }
1447
1448 static int r100_packet3_check(struct radeon_cs_parser *p,
1449 struct radeon_cs_packet *pkt)
1450 {
1451 struct radeon_cs_reloc *reloc;
1452 struct r100_cs_track *track;
1453 unsigned idx;
1454 volatile uint32_t *ib;
1455 int r;
1456
1457 ib = p->ib->ptr;
1458 idx = pkt->idx + 1;
1459 track = (struct r100_cs_track *)p->track;
1460 switch (pkt->opcode) {
1461 case PACKET3_3D_LOAD_VBPNTR:
1462 r = r100_packet3_load_vbpntr(p, pkt, idx);
1463 if (r)
1464 return r;
1465 break;
1466 case PACKET3_INDX_BUFFER:
1467 r = r100_cs_packet_next_reloc(p, &reloc);
1468 if (r) {
1469 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1470 r100_cs_dump_packet(p, pkt);
1471 return r;
1472 }
1473 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1474 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1475 if (r) {
1476 return r;
1477 }
1478 break;
1479 case 0x23:
1480 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1481 r = r100_cs_packet_next_reloc(p, &reloc);
1482 if (r) {
1483 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1484 r100_cs_dump_packet(p, pkt);
1485 return r;
1486 }
1487 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1488 track->num_arrays = 1;
1489 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1490
1491 track->arrays[0].robj = reloc->robj;
1492 track->arrays[0].esize = track->vtx_size;
1493
1494 track->max_indx = radeon_get_ib_value(p, idx+1);
1495
1496 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1497 track->immd_dwords = pkt->count - 1;
1498 r = r100_cs_track_check(p->rdev, track);
1499 if (r)
1500 return r;
1501 break;
1502 case PACKET3_3D_DRAW_IMMD:
1503 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1504 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1505 return -EINVAL;
1506 }
1507 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1508 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1509 track->immd_dwords = pkt->count - 1;
1510 r = r100_cs_track_check(p->rdev, track);
1511 if (r)
1512 return r;
1513 break;
1514 /* triggers drawing using in-packet vertex data */
1515 case PACKET3_3D_DRAW_IMMD_2:
1516 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1517 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1518 return -EINVAL;
1519 }
1520 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1521 track->immd_dwords = pkt->count;
1522 r = r100_cs_track_check(p->rdev, track);
1523 if (r)
1524 return r;
1525 break;
1526 /* triggers drawing using in-packet vertex data */
1527 case PACKET3_3D_DRAW_VBUF_2:
1528 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1529 r = r100_cs_track_check(p->rdev, track);
1530 if (r)
1531 return r;
1532 break;
1533 /* triggers drawing of vertex buffers setup elsewhere */
1534 case PACKET3_3D_DRAW_INDX_2:
1535 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1536 r = r100_cs_track_check(p->rdev, track);
1537 if (r)
1538 return r;
1539 break;
1540 /* triggers drawing using indices to vertex buffer */
1541 case PACKET3_3D_DRAW_VBUF:
1542 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1543 r = r100_cs_track_check(p->rdev, track);
1544 if (r)
1545 return r;
1546 break;
1547 /* triggers drawing of vertex buffers setup elsewhere */
1548 case PACKET3_3D_DRAW_INDX:
1549 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1550 r = r100_cs_track_check(p->rdev, track);
1551 if (r)
1552 return r;
1553 break;
1554 /* triggers drawing using indices to vertex buffer */
1555 case PACKET3_NOP:
1556 break;
1557 default:
1558 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1559 return -EINVAL;
1560 }
1561 return 0;
1562 }
1563
1564 int r100_cs_parse(struct radeon_cs_parser *p)
1565 {
1566 struct radeon_cs_packet pkt;
1567 struct r100_cs_track *track;
1568 int r;
1569
1570 track = kzalloc(sizeof(*track), GFP_KERNEL);
1571 r100_cs_track_clear(p->rdev, track);
1572 p->track = track;
1573 do {
1574 r = r100_cs_packet_parse(p, &pkt, p->idx);
1575 if (r) {
1576 return r;
1577 }
1578 p->idx += pkt.count + 2;
1579 switch (pkt.type) {
1580 case PACKET_TYPE0:
1581 if (p->rdev->family >= CHIP_R200)
1582 r = r100_cs_parse_packet0(p, &pkt,
1583 p->rdev->config.r100.reg_safe_bm,
1584 p->rdev->config.r100.reg_safe_bm_size,
1585 &r200_packet0_check);
1586 else
1587 r = r100_cs_parse_packet0(p, &pkt,
1588 p->rdev->config.r100.reg_safe_bm,
1589 p->rdev->config.r100.reg_safe_bm_size,
1590 &r100_packet0_check);
1591 break;
1592 case PACKET_TYPE2:
1593 break;
1594 case PACKET_TYPE3:
1595 r = r100_packet3_check(p, &pkt);
1596 break;
1597 default:
1598 DRM_ERROR("Unknown packet type %d !\n",
1599 pkt.type);
1600 return -EINVAL;
1601 }
1602 if (r) {
1603 return r;
1604 }
1605 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1606 return 0;
1607 }
1608
1609
1610 /*
1611 * Global GPU functions
1612 */
1613 void r100_errata(struct radeon_device *rdev)
1614 {
1615 rdev->pll_errata = 0;
1616
1617 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1618 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1619 }
1620
1621 if (rdev->family == CHIP_RV100 ||
1622 rdev->family == CHIP_RS100 ||
1623 rdev->family == CHIP_RS200) {
1624 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1625 }
1626 }
1627
1628 /* Wait for vertical sync on primary CRTC */
1629 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1630 {
1631 uint32_t crtc_gen_cntl, tmp;
1632 int i;
1633
1634 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1635 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1636 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1637 return;
1638 }
1639 /* Clear the CRTC_VBLANK_SAVE bit */
1640 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1641 for (i = 0; i < rdev->usec_timeout; i++) {
1642 tmp = RREG32(RADEON_CRTC_STATUS);
1643 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1644 return;
1645 }
1646 DRM_UDELAY(1);
1647 }
1648 }
1649
1650 /* Wait for vertical sync on secondary CRTC */
1651 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1652 {
1653 uint32_t crtc2_gen_cntl, tmp;
1654 int i;
1655
1656 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1657 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1658 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1659 return;
1660
1661 /* Clear the CRTC_VBLANK_SAVE bit */
1662 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1663 for (i = 0; i < rdev->usec_timeout; i++) {
1664 tmp = RREG32(RADEON_CRTC2_STATUS);
1665 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1666 return;
1667 }
1668 DRM_UDELAY(1);
1669 }
1670 }
1671
1672 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1673 {
1674 unsigned i;
1675 uint32_t tmp;
1676
1677 for (i = 0; i < rdev->usec_timeout; i++) {
1678 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1679 if (tmp >= n) {
1680 return 0;
1681 }
1682 DRM_UDELAY(1);
1683 }
1684 return -1;
1685 }
1686
1687 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1688 {
1689 unsigned i;
1690 uint32_t tmp;
1691
1692 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1693 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1694 " Bad things might happen.\n");
1695 }
1696 for (i = 0; i < rdev->usec_timeout; i++) {
1697 tmp = RREG32(RADEON_RBBM_STATUS);
1698 if (!(tmp & (1 << 31))) {
1699 return 0;
1700 }
1701 DRM_UDELAY(1);
1702 }
1703 return -1;
1704 }
1705
1706 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1707 {
1708 unsigned i;
1709 uint32_t tmp;
1710
1711 for (i = 0; i < rdev->usec_timeout; i++) {
1712 /* read MC_STATUS */
1713 tmp = RREG32(0x0150);
1714 if (tmp & (1 << 2)) {
1715 return 0;
1716 }
1717 DRM_UDELAY(1);
1718 }
1719 return -1;
1720 }
1721
1722 void r100_gpu_init(struct radeon_device *rdev)
1723 {
1724 /* TODO: anythings to do here ? pipes ? */
1725 r100_hdp_reset(rdev);
1726 }
1727
1728 void r100_hdp_reset(struct radeon_device *rdev)
1729 {
1730 uint32_t tmp;
1731
1732 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1733 tmp |= (7 << 28);
1734 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1735 (void)RREG32(RADEON_HOST_PATH_CNTL);
1736 udelay(200);
1737 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1738 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1739 (void)RREG32(RADEON_HOST_PATH_CNTL);
1740 }
1741
1742 int r100_rb2d_reset(struct radeon_device *rdev)
1743 {
1744 uint32_t tmp;
1745 int i;
1746
1747 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1748 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1749 udelay(200);
1750 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1751 /* Wait to prevent race in RBBM_STATUS */
1752 mdelay(1);
1753 for (i = 0; i < rdev->usec_timeout; i++) {
1754 tmp = RREG32(RADEON_RBBM_STATUS);
1755 if (!(tmp & (1 << 26))) {
1756 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1757 tmp);
1758 return 0;
1759 }
1760 DRM_UDELAY(1);
1761 }
1762 tmp = RREG32(RADEON_RBBM_STATUS);
1763 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1764 return -1;
1765 }
1766
1767 int r100_gpu_reset(struct radeon_device *rdev)
1768 {
1769 uint32_t status;
1770
1771 /* reset order likely matter */
1772 status = RREG32(RADEON_RBBM_STATUS);
1773 /* reset HDP */
1774 r100_hdp_reset(rdev);
1775 /* reset rb2d */
1776 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1777 r100_rb2d_reset(rdev);
1778 }
1779 /* TODO: reset 3D engine */
1780 /* reset CP */
1781 status = RREG32(RADEON_RBBM_STATUS);
1782 if (status & (1 << 16)) {
1783 r100_cp_reset(rdev);
1784 }
1785 /* Check if GPU is idle */
1786 status = RREG32(RADEON_RBBM_STATUS);
1787 if (status & (1 << 31)) {
1788 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1789 return -1;
1790 }
1791 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1792 return 0;
1793 }
1794
1795 void r100_set_common_regs(struct radeon_device *rdev)
1796 {
1797 /* set these so they don't interfere with anything */
1798 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1799 WREG32(RADEON_SUBPIC_CNTL, 0);
1800 WREG32(RADEON_VIPH_CONTROL, 0);
1801 WREG32(RADEON_I2C_CNTL_1, 0);
1802 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1803 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1804 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1805 }
1806
1807 /*
1808 * VRAM info
1809 */
1810 static void r100_vram_get_type(struct radeon_device *rdev)
1811 {
1812 uint32_t tmp;
1813
1814 rdev->mc.vram_is_ddr = false;
1815 if (rdev->flags & RADEON_IS_IGP)
1816 rdev->mc.vram_is_ddr = true;
1817 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1818 rdev->mc.vram_is_ddr = true;
1819 if ((rdev->family == CHIP_RV100) ||
1820 (rdev->family == CHIP_RS100) ||
1821 (rdev->family == CHIP_RS200)) {
1822 tmp = RREG32(RADEON_MEM_CNTL);
1823 if (tmp & RV100_HALF_MODE) {
1824 rdev->mc.vram_width = 32;
1825 } else {
1826 rdev->mc.vram_width = 64;
1827 }
1828 if (rdev->flags & RADEON_SINGLE_CRTC) {
1829 rdev->mc.vram_width /= 4;
1830 rdev->mc.vram_is_ddr = true;
1831 }
1832 } else if (rdev->family <= CHIP_RV280) {
1833 tmp = RREG32(RADEON_MEM_CNTL);
1834 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1835 rdev->mc.vram_width = 128;
1836 } else {
1837 rdev->mc.vram_width = 64;
1838 }
1839 } else {
1840 /* newer IGPs */
1841 rdev->mc.vram_width = 128;
1842 }
1843 }
1844
1845 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1846 {
1847 u32 aper_size;
1848 u8 byte;
1849
1850 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1851
1852 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1853 * that is has the 2nd generation multifunction PCI interface
1854 */
1855 if (rdev->family == CHIP_RV280 ||
1856 rdev->family >= CHIP_RV350) {
1857 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1858 ~RADEON_HDP_APER_CNTL);
1859 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1860 return aper_size * 2;
1861 }
1862
1863 /* Older cards have all sorts of funny issues to deal with. First
1864 * check if it's a multifunction card by reading the PCI config
1865 * header type... Limit those to one aperture size
1866 */
1867 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1868 if (byte & 0x80) {
1869 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1870 DRM_INFO("Limiting VRAM to one aperture\n");
1871 return aper_size;
1872 }
1873
1874 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1875 * have set it up. We don't write this as it's broken on some ASICs but
1876 * we expect the BIOS to have done the right thing (might be too optimistic...)
1877 */
1878 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1879 return aper_size * 2;
1880 return aper_size;
1881 }
1882
1883 void r100_vram_init_sizes(struct radeon_device *rdev)
1884 {
1885 u64 config_aper_size;
1886 u32 accessible;
1887
1888 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1889
1890 if (rdev->flags & RADEON_IS_IGP) {
1891 uint32_t tom;
1892 /* read NB_TOM to get the amount of ram stolen for the GPU */
1893 tom = RREG32(RADEON_NB_TOM);
1894 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1895 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1896 rdev->mc.vram_location = (tom & 0xffff) << 16;
1897 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1898 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1899 } else {
1900 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1901 /* Some production boards of m6 will report 0
1902 * if it's 8 MB
1903 */
1904 if (rdev->mc.real_vram_size == 0) {
1905 rdev->mc.real_vram_size = 8192 * 1024;
1906 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1907 }
1908 /* let driver place VRAM */
1909 rdev->mc.vram_location = 0xFFFFFFFFUL;
1910 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1911 * Novell bug 204882 + along with lots of ubuntu ones */
1912 if (config_aper_size > rdev->mc.real_vram_size)
1913 rdev->mc.mc_vram_size = config_aper_size;
1914 else
1915 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1916 }
1917
1918 /* work out accessible VRAM */
1919 accessible = r100_get_accessible_vram(rdev);
1920
1921 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1922 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1923
1924 if (accessible > rdev->mc.aper_size)
1925 accessible = rdev->mc.aper_size;
1926
1927 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1928 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1929
1930 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1931 rdev->mc.real_vram_size = rdev->mc.aper_size;
1932 }
1933
1934 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1935 {
1936 uint32_t temp;
1937
1938 temp = RREG32(RADEON_CONFIG_CNTL);
1939 if (state == false) {
1940 temp &= ~(1<<8);
1941 temp |= (1<<9);
1942 } else {
1943 temp &= ~(1<<9);
1944 }
1945 WREG32(RADEON_CONFIG_CNTL, temp);
1946 }
1947
1948 void r100_vram_info(struct radeon_device *rdev)
1949 {
1950 r100_vram_get_type(rdev);
1951
1952 r100_vram_init_sizes(rdev);
1953 }
1954
1955
1956 /*
1957 * Indirect registers accessor
1958 */
1959 void r100_pll_errata_after_index(struct radeon_device *rdev)
1960 {
1961 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1962 return;
1963 }
1964 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1965 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1966 }
1967
1968 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1969 {
1970 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1971 * or the chip could hang on a subsequent access
1972 */
1973 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1974 udelay(5000);
1975 }
1976
1977 /* This function is required to workaround a hardware bug in some (all?)
1978 * revisions of the R300. This workaround should be called after every
1979 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1980 * may not be correct.
1981 */
1982 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1983 uint32_t save, tmp;
1984
1985 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1986 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1987 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1988 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1989 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1990 }
1991 }
1992
1993 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1994 {
1995 uint32_t data;
1996
1997 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1998 r100_pll_errata_after_index(rdev);
1999 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2000 r100_pll_errata_after_data(rdev);
2001 return data;
2002 }
2003
2004 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2005 {
2006 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2007 r100_pll_errata_after_index(rdev);
2008 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2009 r100_pll_errata_after_data(rdev);
2010 }
2011
2012 void r100_set_safe_registers(struct radeon_device *rdev)
2013 {
2014 if (ASIC_IS_RN50(rdev)) {
2015 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2016 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2017 } else if (rdev->family < CHIP_R200) {
2018 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2019 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2020 } else {
2021 r200_set_safe_registers(rdev);
2022 }
2023 }
2024
2025 /*
2026 * Debugfs info
2027 */
2028 #if defined(CONFIG_DEBUG_FS)
2029 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2030 {
2031 struct drm_info_node *node = (struct drm_info_node *) m->private;
2032 struct drm_device *dev = node->minor->dev;
2033 struct radeon_device *rdev = dev->dev_private;
2034 uint32_t reg, value;
2035 unsigned i;
2036
2037 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2038 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2039 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2040 for (i = 0; i < 64; i++) {
2041 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2042 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2043 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2044 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2045 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2046 }
2047 return 0;
2048 }
2049
2050 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2051 {
2052 struct drm_info_node *node = (struct drm_info_node *) m->private;
2053 struct drm_device *dev = node->minor->dev;
2054 struct radeon_device *rdev = dev->dev_private;
2055 uint32_t rdp, wdp;
2056 unsigned count, i, j;
2057
2058 radeon_ring_free_size(rdev);
2059 rdp = RREG32(RADEON_CP_RB_RPTR);
2060 wdp = RREG32(RADEON_CP_RB_WPTR);
2061 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2062 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2063 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2064 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2065 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2066 seq_printf(m, "%u dwords in ring\n", count);
2067 for (j = 0; j <= count; j++) {
2068 i = (rdp + j) & rdev->cp.ptr_mask;
2069 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2070 }
2071 return 0;
2072 }
2073
2074
2075 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2076 {
2077 struct drm_info_node *node = (struct drm_info_node *) m->private;
2078 struct drm_device *dev = node->minor->dev;
2079 struct radeon_device *rdev = dev->dev_private;
2080 uint32_t csq_stat, csq2_stat, tmp;
2081 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2082 unsigned i;
2083
2084 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2085 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2086 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2087 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2088 r_rptr = (csq_stat >> 0) & 0x3ff;
2089 r_wptr = (csq_stat >> 10) & 0x3ff;
2090 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2091 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2092 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2093 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2094 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2095 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2096 seq_printf(m, "Ring rptr %u\n", r_rptr);
2097 seq_printf(m, "Ring wptr %u\n", r_wptr);
2098 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2099 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2100 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2101 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2102 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2103 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2104 seq_printf(m, "Ring fifo:\n");
2105 for (i = 0; i < 256; i++) {
2106 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2107 tmp = RREG32(RADEON_CP_CSQ_DATA);
2108 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2109 }
2110 seq_printf(m, "Indirect1 fifo:\n");
2111 for (i = 256; i <= 512; i++) {
2112 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2113 tmp = RREG32(RADEON_CP_CSQ_DATA);
2114 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2115 }
2116 seq_printf(m, "Indirect2 fifo:\n");
2117 for (i = 640; i < ib1_wptr; i++) {
2118 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2119 tmp = RREG32(RADEON_CP_CSQ_DATA);
2120 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2121 }
2122 return 0;
2123 }
2124
2125 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2126 {
2127 struct drm_info_node *node = (struct drm_info_node *) m->private;
2128 struct drm_device *dev = node->minor->dev;
2129 struct radeon_device *rdev = dev->dev_private;
2130 uint32_t tmp;
2131
2132 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2133 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2134 tmp = RREG32(RADEON_MC_FB_LOCATION);
2135 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2136 tmp = RREG32(RADEON_BUS_CNTL);
2137 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2138 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2139 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2140 tmp = RREG32(RADEON_AGP_BASE);
2141 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2142 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2143 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2144 tmp = RREG32(0x01D0);
2145 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2146 tmp = RREG32(RADEON_AIC_LO_ADDR);
2147 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2148 tmp = RREG32(RADEON_AIC_HI_ADDR);
2149 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2150 tmp = RREG32(0x01E4);
2151 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2152 return 0;
2153 }
2154
2155 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2156 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2157 };
2158
2159 static struct drm_info_list r100_debugfs_cp_list[] = {
2160 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2161 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2162 };
2163
2164 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2165 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2166 };
2167 #endif
2168
2169 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2170 {
2171 #if defined(CONFIG_DEBUG_FS)
2172 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2173 #else
2174 return 0;
2175 #endif
2176 }
2177
2178 int r100_debugfs_cp_init(struct radeon_device *rdev)
2179 {
2180 #if defined(CONFIG_DEBUG_FS)
2181 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2182 #else
2183 return 0;
2184 #endif
2185 }
2186
2187 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2188 {
2189 #if defined(CONFIG_DEBUG_FS)
2190 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2191 #else
2192 return 0;
2193 #endif
2194 }
2195
2196 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2197 uint32_t tiling_flags, uint32_t pitch,
2198 uint32_t offset, uint32_t obj_size)
2199 {
2200 int surf_index = reg * 16;
2201 int flags = 0;
2202
2203 /* r100/r200 divide by 16 */
2204 if (rdev->family < CHIP_R300)
2205 flags = pitch / 16;
2206 else
2207 flags = pitch / 8;
2208
2209 if (rdev->family <= CHIP_RS200) {
2210 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2211 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2212 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2213 if (tiling_flags & RADEON_TILING_MACRO)
2214 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2215 } else if (rdev->family <= CHIP_RV280) {
2216 if (tiling_flags & (RADEON_TILING_MACRO))
2217 flags |= R200_SURF_TILE_COLOR_MACRO;
2218 if (tiling_flags & RADEON_TILING_MICRO)
2219 flags |= R200_SURF_TILE_COLOR_MICRO;
2220 } else {
2221 if (tiling_flags & RADEON_TILING_MACRO)
2222 flags |= R300_SURF_TILE_MACRO;
2223 if (tiling_flags & RADEON_TILING_MICRO)
2224 flags |= R300_SURF_TILE_MICRO;
2225 }
2226
2227 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2228 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2229 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2230 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2231
2232 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2233 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2234 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2235 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2236 return 0;
2237 }
2238
2239 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2240 {
2241 int surf_index = reg * 16;
2242 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2243 }
2244
2245 void r100_bandwidth_update(struct radeon_device *rdev)
2246 {
2247 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2248 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2249 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2250 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2251 fixed20_12 memtcas_ff[8] = {
2252 fixed_init(1),
2253 fixed_init(2),
2254 fixed_init(3),
2255 fixed_init(0),
2256 fixed_init_half(1),
2257 fixed_init_half(2),
2258 fixed_init(0),
2259 };
2260 fixed20_12 memtcas_rs480_ff[8] = {
2261 fixed_init(0),
2262 fixed_init(1),
2263 fixed_init(2),
2264 fixed_init(3),
2265 fixed_init(0),
2266 fixed_init_half(1),
2267 fixed_init_half(2),
2268 fixed_init_half(3),
2269 };
2270 fixed20_12 memtcas2_ff[8] = {
2271 fixed_init(0),
2272 fixed_init(1),
2273 fixed_init(2),
2274 fixed_init(3),
2275 fixed_init(4),
2276 fixed_init(5),
2277 fixed_init(6),
2278 fixed_init(7),
2279 };
2280 fixed20_12 memtrbs[8] = {
2281 fixed_init(1),
2282 fixed_init_half(1),
2283 fixed_init(2),
2284 fixed_init_half(2),
2285 fixed_init(3),
2286 fixed_init_half(3),
2287 fixed_init(4),
2288 fixed_init_half(4)
2289 };
2290 fixed20_12 memtrbs_r4xx[8] = {
2291 fixed_init(4),
2292 fixed_init(5),
2293 fixed_init(6),
2294 fixed_init(7),
2295 fixed_init(8),
2296 fixed_init(9),
2297 fixed_init(10),
2298 fixed_init(11)
2299 };
2300 fixed20_12 min_mem_eff;
2301 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2302 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2303 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2304 disp_drain_rate2, read_return_rate;
2305 fixed20_12 time_disp1_drop_priority;
2306 int c;
2307 int cur_size = 16; /* in octawords */
2308 int critical_point = 0, critical_point2;
2309 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2310 int stop_req, max_stop_req;
2311 struct drm_display_mode *mode1 = NULL;
2312 struct drm_display_mode *mode2 = NULL;
2313 uint32_t pixel_bytes1 = 0;
2314 uint32_t pixel_bytes2 = 0;
2315
2316 if (rdev->mode_info.crtcs[0]->base.enabled) {
2317 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2318 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2319 }
2320 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2321 if (rdev->mode_info.crtcs[1]->base.enabled) {
2322 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2323 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2324 }
2325 }
2326
2327 min_mem_eff.full = rfixed_const_8(0);
2328 /* get modes */
2329 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2330 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2331 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2332 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2333 /* check crtc enables */
2334 if (mode2)
2335 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2336 if (mode1)
2337 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2338 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2339 }
2340
2341 /*
2342 * determine is there is enough bw for current mode
2343 */
2344 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2345 temp_ff.full = rfixed_const(100);
2346 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2347 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2348 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2349
2350 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2351 temp_ff.full = rfixed_const(temp);
2352 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2353
2354 pix_clk.full = 0;
2355 pix_clk2.full = 0;
2356 peak_disp_bw.full = 0;
2357 if (mode1) {
2358 temp_ff.full = rfixed_const(1000);
2359 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2360 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2361 temp_ff.full = rfixed_const(pixel_bytes1);
2362 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2363 }
2364 if (mode2) {
2365 temp_ff.full = rfixed_const(1000);
2366 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2367 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2368 temp_ff.full = rfixed_const(pixel_bytes2);
2369 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2370 }
2371
2372 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2373 if (peak_disp_bw.full >= mem_bw.full) {
2374 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2375 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2376 }
2377
2378 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2379 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2380 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2381 mem_trcd = ((temp >> 2) & 0x3) + 1;
2382 mem_trp = ((temp & 0x3)) + 1;
2383 mem_tras = ((temp & 0x70) >> 4) + 1;
2384 } else if (rdev->family == CHIP_R300 ||
2385 rdev->family == CHIP_R350) { /* r300, r350 */
2386 mem_trcd = (temp & 0x7) + 1;
2387 mem_trp = ((temp >> 8) & 0x7) + 1;
2388 mem_tras = ((temp >> 11) & 0xf) + 4;
2389 } else if (rdev->family == CHIP_RV350 ||
2390 rdev->family <= CHIP_RV380) {
2391 /* rv3x0 */
2392 mem_trcd = (temp & 0x7) + 3;
2393 mem_trp = ((temp >> 8) & 0x7) + 3;
2394 mem_tras = ((temp >> 11) & 0xf) + 6;
2395 } else if (rdev->family == CHIP_R420 ||
2396 rdev->family == CHIP_R423 ||
2397 rdev->family == CHIP_RV410) {
2398 /* r4xx */
2399 mem_trcd = (temp & 0xf) + 3;
2400 if (mem_trcd > 15)
2401 mem_trcd = 15;
2402 mem_trp = ((temp >> 8) & 0xf) + 3;
2403 if (mem_trp > 15)
2404 mem_trp = 15;
2405 mem_tras = ((temp >> 12) & 0x1f) + 6;
2406 if (mem_tras > 31)
2407 mem_tras = 31;
2408 } else { /* RV200, R200 */
2409 mem_trcd = (temp & 0x7) + 1;
2410 mem_trp = ((temp >> 8) & 0x7) + 1;
2411 mem_tras = ((temp >> 12) & 0xf) + 4;
2412 }
2413 /* convert to FF */
2414 trcd_ff.full = rfixed_const(mem_trcd);
2415 trp_ff.full = rfixed_const(mem_trp);
2416 tras_ff.full = rfixed_const(mem_tras);
2417
2418 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2419 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2420 data = (temp & (7 << 20)) >> 20;
2421 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2422 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2423 tcas_ff = memtcas_rs480_ff[data];
2424 else
2425 tcas_ff = memtcas_ff[data];
2426 } else
2427 tcas_ff = memtcas2_ff[data];
2428
2429 if (rdev->family == CHIP_RS400 ||
2430 rdev->family == CHIP_RS480) {
2431 /* extra cas latency stored in bits 23-25 0-4 clocks */
2432 data = (temp >> 23) & 0x7;
2433 if (data < 5)
2434 tcas_ff.full += rfixed_const(data);
2435 }
2436
2437 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2438 /* on the R300, Tcas is included in Trbs.
2439 */
2440 temp = RREG32(RADEON_MEM_CNTL);
2441 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2442 if (data == 1) {
2443 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2444 temp = RREG32(R300_MC_IND_INDEX);
2445 temp &= ~R300_MC_IND_ADDR_MASK;
2446 temp |= R300_MC_READ_CNTL_CD_mcind;
2447 WREG32(R300_MC_IND_INDEX, temp);
2448 temp = RREG32(R300_MC_IND_DATA);
2449 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2450 } else {
2451 temp = RREG32(R300_MC_READ_CNTL_AB);
2452 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2453 }
2454 } else {
2455 temp = RREG32(R300_MC_READ_CNTL_AB);
2456 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2457 }
2458 if (rdev->family == CHIP_RV410 ||
2459 rdev->family == CHIP_R420 ||
2460 rdev->family == CHIP_R423)
2461 trbs_ff = memtrbs_r4xx[data];
2462 else
2463 trbs_ff = memtrbs[data];
2464 tcas_ff.full += trbs_ff.full;
2465 }
2466
2467 sclk_eff_ff.full = sclk_ff.full;
2468
2469 if (rdev->flags & RADEON_IS_AGP) {
2470 fixed20_12 agpmode_ff;
2471 agpmode_ff.full = rfixed_const(radeon_agpmode);
2472 temp_ff.full = rfixed_const_666(16);
2473 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2474 }
2475 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2476
2477 if (ASIC_IS_R300(rdev)) {
2478 sclk_delay_ff.full = rfixed_const(250);
2479 } else {
2480 if ((rdev->family == CHIP_RV100) ||
2481 rdev->flags & RADEON_IS_IGP) {
2482 if (rdev->mc.vram_is_ddr)
2483 sclk_delay_ff.full = rfixed_const(41);
2484 else
2485 sclk_delay_ff.full = rfixed_const(33);
2486 } else {
2487 if (rdev->mc.vram_width == 128)
2488 sclk_delay_ff.full = rfixed_const(57);
2489 else
2490 sclk_delay_ff.full = rfixed_const(41);
2491 }
2492 }
2493
2494 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2495
2496 if (rdev->mc.vram_is_ddr) {
2497 if (rdev->mc.vram_width == 32) {
2498 k1.full = rfixed_const(40);
2499 c = 3;
2500 } else {
2501 k1.full = rfixed_const(20);
2502 c = 1;
2503 }
2504 } else {
2505 k1.full = rfixed_const(40);
2506 c = 3;
2507 }
2508
2509 temp_ff.full = rfixed_const(2);
2510 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2511 temp_ff.full = rfixed_const(c);
2512 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2513 temp_ff.full = rfixed_const(4);
2514 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2515 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2516 mc_latency_mclk.full += k1.full;
2517
2518 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2519 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2520
2521 /*
2522 HW cursor time assuming worst case of full size colour cursor.
2523 */
2524 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2525 temp_ff.full += trcd_ff.full;
2526 if (temp_ff.full < tras_ff.full)
2527 temp_ff.full = tras_ff.full;
2528 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2529
2530 temp_ff.full = rfixed_const(cur_size);
2531 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2532 /*
2533 Find the total latency for the display data.
2534 */
2535 disp_latency_overhead.full = rfixed_const(8);
2536 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2537 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2538 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2539
2540 if (mc_latency_mclk.full > mc_latency_sclk.full)
2541 disp_latency.full = mc_latency_mclk.full;
2542 else
2543 disp_latency.full = mc_latency_sclk.full;
2544
2545 /* setup Max GRPH_STOP_REQ default value */
2546 if (ASIC_IS_RV100(rdev))
2547 max_stop_req = 0x5c;
2548 else
2549 max_stop_req = 0x7c;
2550
2551 if (mode1) {
2552 /* CRTC1
2553 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2554 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2555 */
2556 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2557
2558 if (stop_req > max_stop_req)
2559 stop_req = max_stop_req;
2560
2561 /*
2562 Find the drain rate of the display buffer.
2563 */
2564 temp_ff.full = rfixed_const((16/pixel_bytes1));
2565 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2566
2567 /*
2568 Find the critical point of the display buffer.
2569 */
2570 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2571 crit_point_ff.full += rfixed_const_half(0);
2572
2573 critical_point = rfixed_trunc(crit_point_ff);
2574
2575 if (rdev->disp_priority == 2) {
2576 critical_point = 0;
2577 }
2578
2579 /*
2580 The critical point should never be above max_stop_req-4. Setting
2581 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2582 */
2583 if (max_stop_req - critical_point < 4)
2584 critical_point = 0;
2585
2586 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2587 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2588 critical_point = 0x10;
2589 }
2590
2591 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2592 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2593 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2594 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2595 if ((rdev->family == CHIP_R350) &&
2596 (stop_req > 0x15)) {
2597 stop_req -= 0x10;
2598 }
2599 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2600 temp |= RADEON_GRPH_BUFFER_SIZE;
2601 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2602 RADEON_GRPH_CRITICAL_AT_SOF |
2603 RADEON_GRPH_STOP_CNTL);
2604 /*
2605 Write the result into the register.
2606 */
2607 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2608 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2609
2610 #if 0
2611 if ((rdev->family == CHIP_RS400) ||
2612 (rdev->family == CHIP_RS480)) {
2613 /* attempt to program RS400 disp regs correctly ??? */
2614 temp = RREG32(RS400_DISP1_REG_CNTL);
2615 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2616 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2617 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2618 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2619 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2620 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2621 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2622 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2623 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2624 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2625 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2626 }
2627 #endif
2628
2629 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2630 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2631 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2632 }
2633
2634 if (mode2) {
2635 u32 grph2_cntl;
2636 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2637
2638 if (stop_req > max_stop_req)
2639 stop_req = max_stop_req;
2640
2641 /*
2642 Find the drain rate of the display buffer.
2643 */
2644 temp_ff.full = rfixed_const((16/pixel_bytes2));
2645 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2646
2647 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2648 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2649 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2650 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2651 if ((rdev->family == CHIP_R350) &&
2652 (stop_req > 0x15)) {
2653 stop_req -= 0x10;
2654 }
2655 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2656 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2657 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2658 RADEON_GRPH_CRITICAL_AT_SOF |
2659 RADEON_GRPH_STOP_CNTL);
2660
2661 if ((rdev->family == CHIP_RS100) ||
2662 (rdev->family == CHIP_RS200))
2663 critical_point2 = 0;
2664 else {
2665 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2666 temp_ff.full = rfixed_const(temp);
2667 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2668 if (sclk_ff.full < temp_ff.full)
2669 temp_ff.full = sclk_ff.full;
2670
2671 read_return_rate.full = temp_ff.full;
2672
2673 if (mode1) {
2674 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2675 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2676 } else {
2677 time_disp1_drop_priority.full = 0;
2678 }
2679 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2680 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2681 crit_point_ff.full += rfixed_const_half(0);
2682
2683 critical_point2 = rfixed_trunc(crit_point_ff);
2684
2685 if (rdev->disp_priority == 2) {
2686 critical_point2 = 0;
2687 }
2688
2689 if (max_stop_req - critical_point2 < 4)
2690 critical_point2 = 0;
2691
2692 }
2693
2694 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2695 /* some R300 cards have problem with this set to 0 */
2696 critical_point2 = 0x10;
2697 }
2698
2699 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2700 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2701
2702 if ((rdev->family == CHIP_RS400) ||
2703 (rdev->family == CHIP_RS480)) {
2704 #if 0
2705 /* attempt to program RS400 disp2 regs correctly ??? */
2706 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2707 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2708 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2709 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2710 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2711 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2712 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2713 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2714 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2715 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2716 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2717 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2718 #endif
2719 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2720 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2721 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2722 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2723 }
2724
2725 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2726 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2727 }
2728 }
2729
2730 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2731 {
2732 DRM_ERROR("pitch %d\n", t->pitch);
2733 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2734 DRM_ERROR("width %d\n", t->width);
2735 DRM_ERROR("width_11 %d\n", t->width_11);
2736 DRM_ERROR("height %d\n", t->height);
2737 DRM_ERROR("height_11 %d\n", t->height_11);
2738 DRM_ERROR("num levels %d\n", t->num_levels);
2739 DRM_ERROR("depth %d\n", t->txdepth);
2740 DRM_ERROR("bpp %d\n", t->cpp);
2741 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2742 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2743 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2744 DRM_ERROR("compress format %d\n", t->compress_format);
2745 }
2746
2747 static int r100_cs_track_cube(struct radeon_device *rdev,
2748 struct r100_cs_track *track, unsigned idx)
2749 {
2750 unsigned face, w, h;
2751 struct radeon_bo *cube_robj;
2752 unsigned long size;
2753
2754 for (face = 0; face < 5; face++) {
2755 cube_robj = track->textures[idx].cube_info[face].robj;
2756 w = track->textures[idx].cube_info[face].width;
2757 h = track->textures[idx].cube_info[face].height;
2758
2759 size = w * h;
2760 size *= track->textures[idx].cpp;
2761
2762 size += track->textures[idx].cube_info[face].offset;
2763
2764 if (size > radeon_bo_size(cube_robj)) {
2765 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2766 size, radeon_bo_size(cube_robj));
2767 r100_cs_track_texture_print(&track->textures[idx]);
2768 return -1;
2769 }
2770 }
2771 return 0;
2772 }
2773
2774 static int r100_track_compress_size(int compress_format, int w, int h)
2775 {
2776 int block_width, block_height, block_bytes;
2777 int wblocks, hblocks;
2778 int min_wblocks;
2779 int sz;
2780
2781 block_width = 4;
2782 block_height = 4;
2783
2784 switch (compress_format) {
2785 case R100_TRACK_COMP_DXT1:
2786 block_bytes = 8;
2787 min_wblocks = 4;
2788 break;
2789 default:
2790 case R100_TRACK_COMP_DXT35:
2791 block_bytes = 16;
2792 min_wblocks = 2;
2793 break;
2794 }
2795
2796 hblocks = (h + block_height - 1) / block_height;
2797 wblocks = (w + block_width - 1) / block_width;
2798 if (wblocks < min_wblocks)
2799 wblocks = min_wblocks;
2800 sz = wblocks * hblocks * block_bytes;
2801 return sz;
2802 }
2803
2804 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2805 struct r100_cs_track *track)
2806 {
2807 struct radeon_bo *robj;
2808 unsigned long size;
2809 unsigned u, i, w, h;
2810 int ret;
2811
2812 for (u = 0; u < track->num_texture; u++) {
2813 if (!track->textures[u].enabled)
2814 continue;
2815 robj = track->textures[u].robj;
2816 if (robj == NULL) {
2817 DRM_ERROR("No texture bound to unit %u\n", u);
2818 return -EINVAL;
2819 }
2820 size = 0;
2821 for (i = 0; i <= track->textures[u].num_levels; i++) {
2822 if (track->textures[u].use_pitch) {
2823 if (rdev->family < CHIP_R300)
2824 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2825 else
2826 w = track->textures[u].pitch / (1 << i);
2827 } else {
2828 w = track->textures[u].width;
2829 if (rdev->family >= CHIP_RV515)
2830 w |= track->textures[u].width_11;
2831 w = w / (1 << i);
2832 if (track->textures[u].roundup_w)
2833 w = roundup_pow_of_two(w);
2834 }
2835 h = track->textures[u].height;
2836 if (rdev->family >= CHIP_RV515)
2837 h |= track->textures[u].height_11;
2838 h = h / (1 << i);
2839 if (track->textures[u].roundup_h)
2840 h = roundup_pow_of_two(h);
2841 if (track->textures[u].compress_format) {
2842
2843 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2844 /* compressed textures are block based */
2845 } else
2846 size += w * h;
2847 }
2848 size *= track->textures[u].cpp;
2849
2850 switch (track->textures[u].tex_coord_type) {
2851 case 0:
2852 break;
2853 case 1:
2854 size *= (1 << track->textures[u].txdepth);
2855 break;
2856 case 2:
2857 if (track->separate_cube) {
2858 ret = r100_cs_track_cube(rdev, track, u);
2859 if (ret)
2860 return ret;
2861 } else
2862 size *= 6;
2863 break;
2864 default:
2865 DRM_ERROR("Invalid texture coordinate type %u for unit "
2866 "%u\n", track->textures[u].tex_coord_type, u);
2867 return -EINVAL;
2868 }
2869 if (size > radeon_bo_size(robj)) {
2870 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2871 "%lu\n", u, size, radeon_bo_size(robj));
2872 r100_cs_track_texture_print(&track->textures[u]);
2873 return -EINVAL;
2874 }
2875 }
2876 return 0;
2877 }
2878
2879 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2880 {
2881 unsigned i;
2882 unsigned long size;
2883 unsigned prim_walk;
2884 unsigned nverts;
2885
2886 for (i = 0; i < track->num_cb; i++) {
2887 if (track->cb[i].robj == NULL) {
2888 if (!(track->fastfill || track->color_channel_mask ||
2889 track->blend_read_enable)) {
2890 continue;
2891 }
2892 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2893 return -EINVAL;
2894 }
2895 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2896 size += track->cb[i].offset;
2897 if (size > radeon_bo_size(track->cb[i].robj)) {
2898 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2899 "(need %lu have %lu) !\n", i, size,
2900 radeon_bo_size(track->cb[i].robj));
2901 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2902 i, track->cb[i].pitch, track->cb[i].cpp,
2903 track->cb[i].offset, track->maxy);
2904 return -EINVAL;
2905 }
2906 }
2907 if (track->z_enabled) {
2908 if (track->zb.robj == NULL) {
2909 DRM_ERROR("[drm] No buffer for z buffer !\n");
2910 return -EINVAL;
2911 }
2912 size = track->zb.pitch * track->zb.cpp * track->maxy;
2913 size += track->zb.offset;
2914 if (size > radeon_bo_size(track->zb.robj)) {
2915 DRM_ERROR("[drm] Buffer too small for z buffer "
2916 "(need %lu have %lu) !\n", size,
2917 radeon_bo_size(track->zb.robj));
2918 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2919 track->zb.pitch, track->zb.cpp,
2920 track->zb.offset, track->maxy);
2921 return -EINVAL;
2922 }
2923 }
2924 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2925 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2926 switch (prim_walk) {
2927 case 1:
2928 for (i = 0; i < track->num_arrays; i++) {
2929 size = track->arrays[i].esize * track->max_indx * 4;
2930 if (track->arrays[i].robj == NULL) {
2931 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2932 "bound\n", prim_walk, i);
2933 return -EINVAL;
2934 }
2935 if (size > radeon_bo_size(track->arrays[i].robj)) {
2936 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2937 "need %lu dwords have %lu dwords\n",
2938 prim_walk, i, size >> 2,
2939 radeon_bo_size(track->arrays[i].robj)
2940 >> 2);
2941 DRM_ERROR("Max indices %u\n", track->max_indx);
2942 return -EINVAL;
2943 }
2944 }
2945 break;
2946 case 2:
2947 for (i = 0; i < track->num_arrays; i++) {
2948 size = track->arrays[i].esize * (nverts - 1) * 4;
2949 if (track->arrays[i].robj == NULL) {
2950 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2951 "bound\n", prim_walk, i);
2952 return -EINVAL;
2953 }
2954 if (size > radeon_bo_size(track->arrays[i].robj)) {
2955 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2956 "need %lu dwords have %lu dwords\n",
2957 prim_walk, i, size >> 2,
2958 radeon_bo_size(track->arrays[i].robj)
2959 >> 2);
2960 return -EINVAL;
2961 }
2962 }
2963 break;
2964 case 3:
2965 size = track->vtx_size * nverts;
2966 if (size != track->immd_dwords) {
2967 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2968 track->immd_dwords, size);
2969 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2970 nverts, track->vtx_size);
2971 return -EINVAL;
2972 }
2973 break;
2974 default:
2975 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2976 prim_walk);
2977 return -EINVAL;
2978 }
2979 return r100_cs_track_texture_check(rdev, track);
2980 }
2981
2982 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2983 {
2984 unsigned i, face;
2985
2986 if (rdev->family < CHIP_R300) {
2987 track->num_cb = 1;
2988 if (rdev->family <= CHIP_RS200)
2989 track->num_texture = 3;
2990 else
2991 track->num_texture = 6;
2992 track->maxy = 2048;
2993 track->separate_cube = 1;
2994 } else {
2995 track->num_cb = 4;
2996 track->num_texture = 16;
2997 track->maxy = 4096;
2998 track->separate_cube = 0;
2999 }
3000
3001 for (i = 0; i < track->num_cb; i++) {
3002 track->cb[i].robj = NULL;
3003 track->cb[i].pitch = 8192;
3004 track->cb[i].cpp = 16;
3005 track->cb[i].offset = 0;
3006 }
3007 track->z_enabled = true;
3008 track->zb.robj = NULL;
3009 track->zb.pitch = 8192;
3010 track->zb.cpp = 4;
3011 track->zb.offset = 0;
3012 track->vtx_size = 0x7F;
3013 track->immd_dwords = 0xFFFFFFFFUL;
3014 track->num_arrays = 11;
3015 track->max_indx = 0x00FFFFFFUL;
3016 for (i = 0; i < track->num_arrays; i++) {
3017 track->arrays[i].robj = NULL;
3018 track->arrays[i].esize = 0x7F;
3019 }
3020 for (i = 0; i < track->num_texture; i++) {
3021 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3022 track->textures[i].pitch = 16536;
3023 track->textures[i].width = 16536;
3024 track->textures[i].height = 16536;
3025 track->textures[i].width_11 = 1 << 11;
3026 track->textures[i].height_11 = 1 << 11;
3027 track->textures[i].num_levels = 12;
3028 if (rdev->family <= CHIP_RS200) {
3029 track->textures[i].tex_coord_type = 0;
3030 track->textures[i].txdepth = 0;
3031 } else {
3032 track->textures[i].txdepth = 16;
3033 track->textures[i].tex_coord_type = 1;
3034 }
3035 track->textures[i].cpp = 64;
3036 track->textures[i].robj = NULL;
3037 /* CS IB emission code makes sure texture unit are disabled */
3038 track->textures[i].enabled = false;
3039 track->textures[i].roundup_w = true;
3040 track->textures[i].roundup_h = true;
3041 if (track->separate_cube)
3042 for (face = 0; face < 5; face++) {
3043 track->textures[i].cube_info[face].robj = NULL;
3044 track->textures[i].cube_info[face].width = 16536;
3045 track->textures[i].cube_info[face].height = 16536;
3046 track->textures[i].cube_info[face].offset = 0;
3047 }
3048 }
3049 }
3050
3051 int r100_ring_test(struct radeon_device *rdev)
3052 {
3053 uint32_t scratch;
3054 uint32_t tmp = 0;
3055 unsigned i;
3056 int r;
3057
3058 r = radeon_scratch_get(rdev, &scratch);
3059 if (r) {
3060 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3061 return r;
3062 }
3063 WREG32(scratch, 0xCAFEDEAD);
3064 r = radeon_ring_lock(rdev, 2);
3065 if (r) {
3066 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3067 radeon_scratch_free(rdev, scratch);
3068 return r;
3069 }
3070 radeon_ring_write(rdev, PACKET0(scratch, 0));
3071 radeon_ring_write(rdev, 0xDEADBEEF);
3072 radeon_ring_unlock_commit(rdev);
3073 for (i = 0; i < rdev->usec_timeout; i++) {
3074 tmp = RREG32(scratch);
3075 if (tmp == 0xDEADBEEF) {
3076 break;
3077 }
3078 DRM_UDELAY(1);
3079 }
3080 if (i < rdev->usec_timeout) {
3081 DRM_INFO("ring test succeeded in %d usecs\n", i);
3082 } else {
3083 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3084 scratch, tmp);
3085 r = -EINVAL;
3086 }
3087 radeon_scratch_free(rdev, scratch);
3088 return r;
3089 }
3090
3091 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3092 {
3093 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3094 radeon_ring_write(rdev, ib->gpu_addr);
3095 radeon_ring_write(rdev, ib->length_dw);
3096 }
3097
3098 int r100_ib_test(struct radeon_device *rdev)
3099 {
3100 struct radeon_ib *ib;
3101 uint32_t scratch;
3102 uint32_t tmp = 0;
3103 unsigned i;
3104 int r;
3105
3106 r = radeon_scratch_get(rdev, &scratch);
3107 if (r) {
3108 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3109 return r;
3110 }
3111 WREG32(scratch, 0xCAFEDEAD);
3112 r = radeon_ib_get(rdev, &ib);
3113 if (r) {
3114 return r;
3115 }
3116 ib->ptr[0] = PACKET0(scratch, 0);
3117 ib->ptr[1] = 0xDEADBEEF;
3118 ib->ptr[2] = PACKET2(0);
3119 ib->ptr[3] = PACKET2(0);
3120 ib->ptr[4] = PACKET2(0);
3121 ib->ptr[5] = PACKET2(0);
3122 ib->ptr[6] = PACKET2(0);
3123 ib->ptr[7] = PACKET2(0);
3124 ib->length_dw = 8;
3125 r = radeon_ib_schedule(rdev, ib);
3126 if (r) {
3127 radeon_scratch_free(rdev, scratch);
3128 radeon_ib_free(rdev, &ib);
3129 return r;
3130 }
3131 r = radeon_fence_wait(ib->fence, false);
3132 if (r) {
3133 return r;
3134 }
3135 for (i = 0; i < rdev->usec_timeout; i++) {
3136 tmp = RREG32(scratch);
3137 if (tmp == 0xDEADBEEF) {
3138 break;
3139 }
3140 DRM_UDELAY(1);
3141 }
3142 if (i < rdev->usec_timeout) {
3143 DRM_INFO("ib test succeeded in %u usecs\n", i);
3144 } else {
3145 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3146 scratch, tmp);
3147 r = -EINVAL;
3148 }
3149 radeon_scratch_free(rdev, scratch);
3150 radeon_ib_free(rdev, &ib);
3151 return r;
3152 }
3153
3154 void r100_ib_fini(struct radeon_device *rdev)
3155 {
3156 radeon_ib_pool_fini(rdev);
3157 }
3158
3159 int r100_ib_init(struct radeon_device *rdev)
3160 {
3161 int r;
3162
3163 r = radeon_ib_pool_init(rdev);
3164 if (r) {
3165 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3166 r100_ib_fini(rdev);
3167 return r;
3168 }
3169 r = r100_ib_test(rdev);
3170 if (r) {
3171 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3172 r100_ib_fini(rdev);
3173 return r;
3174 }
3175 return 0;
3176 }
3177
3178 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3179 {
3180 /* Shutdown CP we shouldn't need to do that but better be safe than
3181 * sorry
3182 */
3183 rdev->cp.ready = false;
3184 WREG32(R_000740_CP_CSQ_CNTL, 0);
3185
3186 /* Save few CRTC registers */
3187 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3188 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3189 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3190 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3191 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3192 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3193 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3194 }
3195
3196 /* Disable VGA aperture access */
3197 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3198 /* Disable cursor, overlay, crtc */
3199 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3200 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3201 S_000054_CRTC_DISPLAY_DIS(1));
3202 WREG32(R_000050_CRTC_GEN_CNTL,
3203 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3204 S_000050_CRTC_DISP_REQ_EN_B(1));
3205 WREG32(R_000420_OV0_SCALE_CNTL,
3206 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3207 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3208 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3209 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3210 S_000360_CUR2_LOCK(1));
3211 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3212 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3213 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3214 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3215 WREG32(R_000360_CUR2_OFFSET,
3216 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3217 }
3218 }
3219
3220 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3221 {
3222 /* Update base address for crtc */
3223 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3224 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3225 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3226 rdev->mc.vram_location);
3227 }
3228 /* Restore CRTC registers */
3229 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3230 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3231 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3232 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3233 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3234 }
3235 }
3236
3237 void r100_vga_render_disable(struct radeon_device *rdev)
3238 {
3239 u32 tmp;
3240
3241 tmp = RREG8(R_0003C2_GENMO_WT);
3242 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3243 }
3244
3245 static void r100_debugfs(struct radeon_device *rdev)
3246 {
3247 int r;
3248
3249 r = r100_debugfs_mc_info_init(rdev);
3250 if (r)
3251 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3252 }
3253
3254 static void r100_mc_program(struct radeon_device *rdev)
3255 {
3256 struct r100_mc_save save;
3257
3258 /* Stops all mc clients */
3259 r100_mc_stop(rdev, &save);
3260 if (rdev->flags & RADEON_IS_AGP) {
3261 WREG32(R_00014C_MC_AGP_LOCATION,
3262 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3263 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3264 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3265 if (rdev->family > CHIP_RV200)
3266 WREG32(R_00015C_AGP_BASE_2,
3267 upper_32_bits(rdev->mc.agp_base) & 0xff);
3268 } else {
3269 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3270 WREG32(R_000170_AGP_BASE, 0);
3271 if (rdev->family > CHIP_RV200)
3272 WREG32(R_00015C_AGP_BASE_2, 0);
3273 }
3274 /* Wait for mc idle */
3275 if (r100_mc_wait_for_idle(rdev))
3276 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3277 /* Program MC, should be a 32bits limited address space */
3278 WREG32(R_000148_MC_FB_LOCATION,
3279 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3280 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3281 r100_mc_resume(rdev, &save);
3282 }
3283
3284 void r100_clock_startup(struct radeon_device *rdev)
3285 {
3286 u32 tmp;
3287
3288 if (radeon_dynclks != -1 && radeon_dynclks)
3289 radeon_legacy_set_clock_gating(rdev, 1);
3290 /* We need to force on some of the block */
3291 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3292 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3293 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3294 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3295 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3296 }
3297
3298 static int r100_startup(struct radeon_device *rdev)
3299 {
3300 int r;
3301
3302 /* set common regs */
3303 r100_set_common_regs(rdev);
3304 /* program mc */
3305 r100_mc_program(rdev);
3306 /* Resume clock */
3307 r100_clock_startup(rdev);
3308 /* Initialize GPU configuration (# pipes, ...) */
3309 r100_gpu_init(rdev);
3310 /* Initialize GART (initialize after TTM so we can allocate
3311 * memory through TTM but finalize after TTM) */
3312 r100_enable_bm(rdev);
3313 if (rdev->flags & RADEON_IS_PCI) {
3314 r = r100_pci_gart_enable(rdev);
3315 if (r)
3316 return r;
3317 }
3318 /* Enable IRQ */
3319 r100_irq_set(rdev);
3320 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3321 /* 1M ring buffer */
3322 r = r100_cp_init(rdev, 1024 * 1024);
3323 if (r) {
3324 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3325 return r;
3326 }
3327 r = r100_wb_init(rdev);
3328 if (r)
3329 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3330 r = r100_ib_init(rdev);
3331 if (r) {
3332 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3333 return r;
3334 }
3335 return 0;
3336 }
3337
3338 int r100_resume(struct radeon_device *rdev)
3339 {
3340 /* Make sur GART are not working */
3341 if (rdev->flags & RADEON_IS_PCI)
3342 r100_pci_gart_disable(rdev);
3343 /* Resume clock before doing reset */
3344 r100_clock_startup(rdev);
3345 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3346 if (radeon_gpu_reset(rdev)) {
3347 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3348 RREG32(R_000E40_RBBM_STATUS),
3349 RREG32(R_0007C0_CP_STAT));
3350 }
3351 /* post */
3352 radeon_combios_asic_init(rdev->ddev);
3353 /* Resume clock after posting */
3354 r100_clock_startup(rdev);
3355 /* Initialize surface registers */
3356 radeon_surface_init(rdev);
3357 return r100_startup(rdev);
3358 }
3359
3360 int r100_suspend(struct radeon_device *rdev)
3361 {
3362 r100_cp_disable(rdev);
3363 r100_wb_disable(rdev);
3364 r100_irq_disable(rdev);
3365 if (rdev->flags & RADEON_IS_PCI)
3366 r100_pci_gart_disable(rdev);
3367 return 0;
3368 }
3369
3370 void r100_fini(struct radeon_device *rdev)
3371 {
3372 r100_suspend(rdev);
3373 r100_cp_fini(rdev);
3374 r100_wb_fini(rdev);
3375 r100_ib_fini(rdev);
3376 radeon_gem_fini(rdev);
3377 if (rdev->flags & RADEON_IS_PCI)
3378 r100_pci_gart_fini(rdev);
3379 radeon_agp_fini(rdev);
3380 radeon_irq_kms_fini(rdev);
3381 radeon_fence_driver_fini(rdev);
3382 radeon_bo_fini(rdev);
3383 radeon_atombios_fini(rdev);
3384 kfree(rdev->bios);
3385 rdev->bios = NULL;
3386 }
3387
3388 int r100_mc_init(struct radeon_device *rdev)
3389 {
3390 int r;
3391 u32 tmp;
3392
3393 /* Setup GPU memory space */
3394 rdev->mc.vram_location = 0xFFFFFFFFUL;
3395 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3396 if (rdev->flags & RADEON_IS_IGP) {
3397 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3398 rdev->mc.vram_location = tmp << 16;
3399 }
3400 if (rdev->flags & RADEON_IS_AGP) {
3401 r = radeon_agp_init(rdev);
3402 if (r) {
3403 radeon_agp_disable(rdev);
3404 } else {
3405 rdev->mc.gtt_location = rdev->mc.agp_base;
3406 }
3407 }
3408 r = radeon_mc_setup(rdev);
3409 if (r)
3410 return r;
3411 return 0;
3412 }
3413
3414 int r100_init(struct radeon_device *rdev)
3415 {
3416 int r;
3417
3418 /* Register debugfs file specific to this group of asics */
3419 r100_debugfs(rdev);
3420 /* Disable VGA */
3421 r100_vga_render_disable(rdev);
3422 /* Initialize scratch registers */
3423 radeon_scratch_init(rdev);
3424 /* Initialize surface registers */
3425 radeon_surface_init(rdev);
3426 /* TODO: disable VGA need to use VGA request */
3427 /* BIOS*/
3428 if (!radeon_get_bios(rdev)) {
3429 if (ASIC_IS_AVIVO(rdev))
3430 return -EINVAL;
3431 }
3432 if (rdev->is_atom_bios) {
3433 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3434 return -EINVAL;
3435 } else {
3436 r = radeon_combios_init(rdev);
3437 if (r)
3438 return r;
3439 }
3440 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3441 if (radeon_gpu_reset(rdev)) {
3442 dev_warn(rdev->dev,
3443 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3444 RREG32(R_000E40_RBBM_STATUS),
3445 RREG32(R_0007C0_CP_STAT));
3446 }
3447 /* check if cards are posted or not */
3448 if (radeon_boot_test_post_card(rdev) == false)
3449 return -EINVAL;
3450 /* Set asic errata */
3451 r100_errata(rdev);
3452 /* Initialize clocks */
3453 radeon_get_clock_info(rdev->ddev);
3454 /* Initialize power management */
3455 radeon_pm_init(rdev);
3456 /* Get vram informations */
3457 r100_vram_info(rdev);
3458 /* Initialize memory controller (also test AGP) */
3459 r = r100_mc_init(rdev);
3460 if (r)
3461 return r;
3462 /* Fence driver */
3463 r = radeon_fence_driver_init(rdev);
3464 if (r)
3465 return r;
3466 r = radeon_irq_kms_init(rdev);
3467 if (r)
3468 return r;
3469 /* Memory manager */
3470 r = radeon_bo_init(rdev);
3471 if (r)
3472 return r;
3473 if (rdev->flags & RADEON_IS_PCI) {
3474 r = r100_pci_gart_init(rdev);
3475 if (r)
3476 return r;
3477 }
3478 r100_set_safe_registers(rdev);
3479 rdev->accel_working = true;
3480 r = r100_startup(rdev);
3481 if (r) {
3482 /* Somethings want wront with the accel init stop accel */
3483 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3484 r100_suspend(rdev);
3485 r100_cp_fini(rdev);
3486 r100_wb_fini(rdev);
3487 r100_ib_fini(rdev);
3488 if (rdev->flags & RADEON_IS_PCI)
3489 r100_pci_gart_fini(rdev);
3490 radeon_irq_kms_fini(rdev);
3491 rdev->accel_working = false;
3492 }
3493 return 0;
3494 }
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