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drm/radeon/kms: add support for semaphores v3
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
45
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
48
49 /* Firmware Names */
50 #define FIRMWARE_R100 "radeon/R100_cp.bin"
51 #define FIRMWARE_R200 "radeon/R200_cp.bin"
52 #define FIRMWARE_R300 "radeon/R300_cp.bin"
53 #define FIRMWARE_R420 "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
65
66 #include "r100_track.h"
67
68 /* This files gather functions specifics to:
69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70 */
71
72 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
73 struct radeon_cs_packet *pkt,
74 unsigned idx,
75 unsigned reg)
76 {
77 int r;
78 u32 tile_flags = 0;
79 u32 tmp;
80 struct radeon_cs_reloc *reloc;
81 u32 value;
82
83 r = r100_cs_packet_next_reloc(p, &reloc);
84 if (r) {
85 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
86 idx, reg);
87 r100_cs_dump_packet(p, pkt);
88 return r;
89 }
90 value = radeon_get_ib_value(p, idx);
91 tmp = value & 0x003fffff;
92 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
93
94 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
95 tile_flags |= RADEON_DST_TILE_MACRO;
96 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
97 if (reg == RADEON_SRC_PITCH_OFFSET) {
98 DRM_ERROR("Cannot src blit from microtiled surface\n");
99 r100_cs_dump_packet(p, pkt);
100 return -EINVAL;
101 }
102 tile_flags |= RADEON_DST_TILE_MICRO;
103 }
104
105 tmp |= tile_flags;
106 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
107 return 0;
108 }
109
110 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
111 struct radeon_cs_packet *pkt,
112 int idx)
113 {
114 unsigned c, i;
115 struct radeon_cs_reloc *reloc;
116 struct r100_cs_track *track;
117 int r = 0;
118 volatile uint32_t *ib;
119 u32 idx_value;
120
121 ib = p->ib->ptr;
122 track = (struct r100_cs_track *)p->track;
123 c = radeon_get_ib_value(p, idx++) & 0x1F;
124 if (c > 16) {
125 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
126 pkt->opcode);
127 r100_cs_dump_packet(p, pkt);
128 return -EINVAL;
129 }
130 track->num_arrays = c;
131 for (i = 0; i < (c - 1); i+=2, idx+=3) {
132 r = r100_cs_packet_next_reloc(p, &reloc);
133 if (r) {
134 DRM_ERROR("No reloc for packet3 %d\n",
135 pkt->opcode);
136 r100_cs_dump_packet(p, pkt);
137 return r;
138 }
139 idx_value = radeon_get_ib_value(p, idx);
140 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
141
142 track->arrays[i + 0].esize = idx_value >> 8;
143 track->arrays[i + 0].robj = reloc->robj;
144 track->arrays[i + 0].esize &= 0x7F;
145 r = r100_cs_packet_next_reloc(p, &reloc);
146 if (r) {
147 DRM_ERROR("No reloc for packet3 %d\n",
148 pkt->opcode);
149 r100_cs_dump_packet(p, pkt);
150 return r;
151 }
152 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
153 track->arrays[i + 1].robj = reloc->robj;
154 track->arrays[i + 1].esize = idx_value >> 24;
155 track->arrays[i + 1].esize &= 0x7F;
156 }
157 if (c & 1) {
158 r = r100_cs_packet_next_reloc(p, &reloc);
159 if (r) {
160 DRM_ERROR("No reloc for packet3 %d\n",
161 pkt->opcode);
162 r100_cs_dump_packet(p, pkt);
163 return r;
164 }
165 idx_value = radeon_get_ib_value(p, idx);
166 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
167 track->arrays[i + 0].robj = reloc->robj;
168 track->arrays[i + 0].esize = idx_value >> 8;
169 track->arrays[i + 0].esize &= 0x7F;
170 }
171 return r;
172 }
173
174 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
175 {
176 /* enable the pflip int */
177 radeon_irq_kms_pflip_irq_get(rdev, crtc);
178 }
179
180 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
181 {
182 /* disable the pflip int */
183 radeon_irq_kms_pflip_irq_put(rdev, crtc);
184 }
185
186 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
187 {
188 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
189 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
190 int i;
191
192 /* Lock the graphics update lock */
193 /* update the scanout addresses */
194 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
195
196 /* Wait for update_pending to go high. */
197 for (i = 0; i < rdev->usec_timeout; i++) {
198 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
199 break;
200 udelay(1);
201 }
202 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
203
204 /* Unlock the lock, so double-buffering can take place inside vblank */
205 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
206 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
207
208 /* Return current update_pending status: */
209 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
210 }
211
212 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
213 {
214 int i;
215 rdev->pm.dynpm_can_upclock = true;
216 rdev->pm.dynpm_can_downclock = true;
217
218 switch (rdev->pm.dynpm_planned_action) {
219 case DYNPM_ACTION_MINIMUM:
220 rdev->pm.requested_power_state_index = 0;
221 rdev->pm.dynpm_can_downclock = false;
222 break;
223 case DYNPM_ACTION_DOWNCLOCK:
224 if (rdev->pm.current_power_state_index == 0) {
225 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
226 rdev->pm.dynpm_can_downclock = false;
227 } else {
228 if (rdev->pm.active_crtc_count > 1) {
229 for (i = 0; i < rdev->pm.num_power_states; i++) {
230 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
231 continue;
232 else if (i >= rdev->pm.current_power_state_index) {
233 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
234 break;
235 } else {
236 rdev->pm.requested_power_state_index = i;
237 break;
238 }
239 }
240 } else
241 rdev->pm.requested_power_state_index =
242 rdev->pm.current_power_state_index - 1;
243 }
244 /* don't use the power state if crtcs are active and no display flag is set */
245 if ((rdev->pm.active_crtc_count > 0) &&
246 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
247 RADEON_PM_MODE_NO_DISPLAY)) {
248 rdev->pm.requested_power_state_index++;
249 }
250 break;
251 case DYNPM_ACTION_UPCLOCK:
252 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
253 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
254 rdev->pm.dynpm_can_upclock = false;
255 } else {
256 if (rdev->pm.active_crtc_count > 1) {
257 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
258 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
259 continue;
260 else if (i <= rdev->pm.current_power_state_index) {
261 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
262 break;
263 } else {
264 rdev->pm.requested_power_state_index = i;
265 break;
266 }
267 }
268 } else
269 rdev->pm.requested_power_state_index =
270 rdev->pm.current_power_state_index + 1;
271 }
272 break;
273 case DYNPM_ACTION_DEFAULT:
274 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
275 rdev->pm.dynpm_can_upclock = false;
276 break;
277 case DYNPM_ACTION_NONE:
278 default:
279 DRM_ERROR("Requested mode for not defined action\n");
280 return;
281 }
282 /* only one clock mode per power state */
283 rdev->pm.requested_clock_mode_index = 0;
284
285 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].sclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
289 clock_info[rdev->pm.requested_clock_mode_index].mclk,
290 rdev->pm.power_state[rdev->pm.requested_power_state_index].
291 pcie_lanes);
292 }
293
294 void r100_pm_init_profile(struct radeon_device *rdev)
295 {
296 /* default */
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
301 /* low sh */
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
306 /* mid sh */
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
311 /* high sh */
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
316 /* low mh */
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
321 /* mid mh */
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
326 /* high mh */
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
331 }
332
333 void r100_pm_misc(struct radeon_device *rdev)
334 {
335 int requested_index = rdev->pm.requested_power_state_index;
336 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
337 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
338 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
339
340 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
341 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
342 tmp = RREG32(voltage->gpio.reg);
343 if (voltage->active_high)
344 tmp |= voltage->gpio.mask;
345 else
346 tmp &= ~(voltage->gpio.mask);
347 WREG32(voltage->gpio.reg, tmp);
348 if (voltage->delay)
349 udelay(voltage->delay);
350 } else {
351 tmp = RREG32(voltage->gpio.reg);
352 if (voltage->active_high)
353 tmp &= ~voltage->gpio.mask;
354 else
355 tmp |= voltage->gpio.mask;
356 WREG32(voltage->gpio.reg, tmp);
357 if (voltage->delay)
358 udelay(voltage->delay);
359 }
360 }
361
362 sclk_cntl = RREG32_PLL(SCLK_CNTL);
363 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
364 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
365 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
366 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
367 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
368 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
369 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
370 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
371 else
372 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
373 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
374 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
375 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
376 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
377 } else
378 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
379
380 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
381 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
382 if (voltage->delay) {
383 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
384 switch (voltage->delay) {
385 case 33:
386 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
387 break;
388 case 66:
389 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
390 break;
391 case 99:
392 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
393 break;
394 case 132:
395 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
396 break;
397 }
398 } else
399 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
400 } else
401 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
402
403 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
404 sclk_cntl &= ~FORCE_HDP;
405 else
406 sclk_cntl |= FORCE_HDP;
407
408 WREG32_PLL(SCLK_CNTL, sclk_cntl);
409 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
410 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
411
412 /* set pcie lanes */
413 if ((rdev->flags & RADEON_IS_PCIE) &&
414 !(rdev->flags & RADEON_IS_IGP) &&
415 rdev->asic->set_pcie_lanes &&
416 (ps->pcie_lanes !=
417 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
418 radeon_set_pcie_lanes(rdev,
419 ps->pcie_lanes);
420 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
421 }
422 }
423
424 void r100_pm_prepare(struct radeon_device *rdev)
425 {
426 struct drm_device *ddev = rdev->ddev;
427 struct drm_crtc *crtc;
428 struct radeon_crtc *radeon_crtc;
429 u32 tmp;
430
431 /* disable any active CRTCs */
432 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
433 radeon_crtc = to_radeon_crtc(crtc);
434 if (radeon_crtc->enabled) {
435 if (radeon_crtc->crtc_id) {
436 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
437 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
438 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
439 } else {
440 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
441 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
442 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
443 }
444 }
445 }
446 }
447
448 void r100_pm_finish(struct radeon_device *rdev)
449 {
450 struct drm_device *ddev = rdev->ddev;
451 struct drm_crtc *crtc;
452 struct radeon_crtc *radeon_crtc;
453 u32 tmp;
454
455 /* enable any active CRTCs */
456 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
457 radeon_crtc = to_radeon_crtc(crtc);
458 if (radeon_crtc->enabled) {
459 if (radeon_crtc->crtc_id) {
460 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
461 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
462 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
463 } else {
464 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
465 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
466 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
467 }
468 }
469 }
470 }
471
472 bool r100_gui_idle(struct radeon_device *rdev)
473 {
474 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
475 return false;
476 else
477 return true;
478 }
479
480 /* hpd for digital panel detect/disconnect */
481 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
482 {
483 bool connected = false;
484
485 switch (hpd) {
486 case RADEON_HPD_1:
487 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
488 connected = true;
489 break;
490 case RADEON_HPD_2:
491 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
492 connected = true;
493 break;
494 default:
495 break;
496 }
497 return connected;
498 }
499
500 void r100_hpd_set_polarity(struct radeon_device *rdev,
501 enum radeon_hpd_id hpd)
502 {
503 u32 tmp;
504 bool connected = r100_hpd_sense(rdev, hpd);
505
506 switch (hpd) {
507 case RADEON_HPD_1:
508 tmp = RREG32(RADEON_FP_GEN_CNTL);
509 if (connected)
510 tmp &= ~RADEON_FP_DETECT_INT_POL;
511 else
512 tmp |= RADEON_FP_DETECT_INT_POL;
513 WREG32(RADEON_FP_GEN_CNTL, tmp);
514 break;
515 case RADEON_HPD_2:
516 tmp = RREG32(RADEON_FP2_GEN_CNTL);
517 if (connected)
518 tmp &= ~RADEON_FP2_DETECT_INT_POL;
519 else
520 tmp |= RADEON_FP2_DETECT_INT_POL;
521 WREG32(RADEON_FP2_GEN_CNTL, tmp);
522 break;
523 default:
524 break;
525 }
526 }
527
528 void r100_hpd_init(struct radeon_device *rdev)
529 {
530 struct drm_device *dev = rdev->ddev;
531 struct drm_connector *connector;
532
533 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
534 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
535 switch (radeon_connector->hpd.hpd) {
536 case RADEON_HPD_1:
537 rdev->irq.hpd[0] = true;
538 break;
539 case RADEON_HPD_2:
540 rdev->irq.hpd[1] = true;
541 break;
542 default:
543 break;
544 }
545 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
546 }
547 if (rdev->irq.installed)
548 r100_irq_set(rdev);
549 }
550
551 void r100_hpd_fini(struct radeon_device *rdev)
552 {
553 struct drm_device *dev = rdev->ddev;
554 struct drm_connector *connector;
555
556 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
557 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
558 switch (radeon_connector->hpd.hpd) {
559 case RADEON_HPD_1:
560 rdev->irq.hpd[0] = false;
561 break;
562 case RADEON_HPD_2:
563 rdev->irq.hpd[1] = false;
564 break;
565 default:
566 break;
567 }
568 }
569 }
570
571 /*
572 * PCI GART
573 */
574 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
575 {
576 /* TODO: can we do somethings here ? */
577 /* It seems hw only cache one entry so we should discard this
578 * entry otherwise if first GPU GART read hit this entry it
579 * could end up in wrong address. */
580 }
581
582 int r100_pci_gart_init(struct radeon_device *rdev)
583 {
584 int r;
585
586 if (rdev->gart.ptr) {
587 WARN(1, "R100 PCI GART already initialized\n");
588 return 0;
589 }
590 /* Initialize common gart structure */
591 r = radeon_gart_init(rdev);
592 if (r)
593 return r;
594 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
595 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
596 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
597 return radeon_gart_table_ram_alloc(rdev);
598 }
599
600 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
601 void r100_enable_bm(struct radeon_device *rdev)
602 {
603 uint32_t tmp;
604 /* Enable bus mastering */
605 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
606 WREG32(RADEON_BUS_CNTL, tmp);
607 }
608
609 int r100_pci_gart_enable(struct radeon_device *rdev)
610 {
611 uint32_t tmp;
612
613 radeon_gart_restore(rdev);
614 /* discard memory request outside of configured range */
615 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
616 WREG32(RADEON_AIC_CNTL, tmp);
617 /* set address range for PCI address translate */
618 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
619 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
620 /* set PCI GART page-table base address */
621 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
622 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
623 WREG32(RADEON_AIC_CNTL, tmp);
624 r100_pci_gart_tlb_flush(rdev);
625 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
626 (unsigned)(rdev->mc.gtt_size >> 20),
627 (unsigned long long)rdev->gart.table_addr);
628 rdev->gart.ready = true;
629 return 0;
630 }
631
632 void r100_pci_gart_disable(struct radeon_device *rdev)
633 {
634 uint32_t tmp;
635
636 /* discard memory request outside of configured range */
637 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
638 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
639 WREG32(RADEON_AIC_LO_ADDR, 0);
640 WREG32(RADEON_AIC_HI_ADDR, 0);
641 }
642
643 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
644 {
645 u32 *gtt = rdev->gart.ptr;
646
647 if (i < 0 || i > rdev->gart.num_gpu_pages) {
648 return -EINVAL;
649 }
650 gtt[i] = cpu_to_le32(lower_32_bits(addr));
651 return 0;
652 }
653
654 void r100_pci_gart_fini(struct radeon_device *rdev)
655 {
656 radeon_gart_fini(rdev);
657 r100_pci_gart_disable(rdev);
658 radeon_gart_table_ram_free(rdev);
659 }
660
661 int r100_irq_set(struct radeon_device *rdev)
662 {
663 uint32_t tmp = 0;
664
665 if (!rdev->irq.installed) {
666 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
667 WREG32(R_000040_GEN_INT_CNTL, 0);
668 return -EINVAL;
669 }
670 if (rdev->irq.sw_int) {
671 tmp |= RADEON_SW_INT_ENABLE;
672 }
673 if (rdev->irq.gui_idle) {
674 tmp |= RADEON_GUI_IDLE_MASK;
675 }
676 if (rdev->irq.crtc_vblank_int[0] ||
677 rdev->irq.pflip[0]) {
678 tmp |= RADEON_CRTC_VBLANK_MASK;
679 }
680 if (rdev->irq.crtc_vblank_int[1] ||
681 rdev->irq.pflip[1]) {
682 tmp |= RADEON_CRTC2_VBLANK_MASK;
683 }
684 if (rdev->irq.hpd[0]) {
685 tmp |= RADEON_FP_DETECT_MASK;
686 }
687 if (rdev->irq.hpd[1]) {
688 tmp |= RADEON_FP2_DETECT_MASK;
689 }
690 WREG32(RADEON_GEN_INT_CNTL, tmp);
691 return 0;
692 }
693
694 void r100_irq_disable(struct radeon_device *rdev)
695 {
696 u32 tmp;
697
698 WREG32(R_000040_GEN_INT_CNTL, 0);
699 /* Wait and acknowledge irq */
700 mdelay(1);
701 tmp = RREG32(R_000044_GEN_INT_STATUS);
702 WREG32(R_000044_GEN_INT_STATUS, tmp);
703 }
704
705 static uint32_t r100_irq_ack(struct radeon_device *rdev)
706 {
707 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
708 uint32_t irq_mask = RADEON_SW_INT_TEST |
709 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
710 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
711
712 /* the interrupt works, but the status bit is permanently asserted */
713 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
714 if (!rdev->irq.gui_idle_acked)
715 irq_mask |= RADEON_GUI_IDLE_STAT;
716 }
717
718 if (irqs) {
719 WREG32(RADEON_GEN_INT_STATUS, irqs);
720 }
721 return irqs & irq_mask;
722 }
723
724 int r100_irq_process(struct radeon_device *rdev)
725 {
726 uint32_t status, msi_rearm;
727 bool queue_hotplug = false;
728
729 /* reset gui idle ack. the status bit is broken */
730 rdev->irq.gui_idle_acked = false;
731
732 status = r100_irq_ack(rdev);
733 if (!status) {
734 return IRQ_NONE;
735 }
736 if (rdev->shutdown) {
737 return IRQ_NONE;
738 }
739 while (status) {
740 /* SW interrupt */
741 if (status & RADEON_SW_INT_TEST) {
742 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
743 }
744 /* gui idle interrupt */
745 if (status & RADEON_GUI_IDLE_STAT) {
746 rdev->irq.gui_idle_acked = true;
747 rdev->pm.gui_idle = true;
748 wake_up(&rdev->irq.idle_queue);
749 }
750 /* Vertical blank interrupts */
751 if (status & RADEON_CRTC_VBLANK_STAT) {
752 if (rdev->irq.crtc_vblank_int[0]) {
753 drm_handle_vblank(rdev->ddev, 0);
754 rdev->pm.vblank_sync = true;
755 wake_up(&rdev->irq.vblank_queue);
756 }
757 if (rdev->irq.pflip[0])
758 radeon_crtc_handle_flip(rdev, 0);
759 }
760 if (status & RADEON_CRTC2_VBLANK_STAT) {
761 if (rdev->irq.crtc_vblank_int[1]) {
762 drm_handle_vblank(rdev->ddev, 1);
763 rdev->pm.vblank_sync = true;
764 wake_up(&rdev->irq.vblank_queue);
765 }
766 if (rdev->irq.pflip[1])
767 radeon_crtc_handle_flip(rdev, 1);
768 }
769 if (status & RADEON_FP_DETECT_STAT) {
770 queue_hotplug = true;
771 DRM_DEBUG("HPD1\n");
772 }
773 if (status & RADEON_FP2_DETECT_STAT) {
774 queue_hotplug = true;
775 DRM_DEBUG("HPD2\n");
776 }
777 status = r100_irq_ack(rdev);
778 }
779 /* reset gui idle ack. the status bit is broken */
780 rdev->irq.gui_idle_acked = false;
781 if (queue_hotplug)
782 schedule_work(&rdev->hotplug_work);
783 if (rdev->msi_enabled) {
784 switch (rdev->family) {
785 case CHIP_RS400:
786 case CHIP_RS480:
787 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
788 WREG32(RADEON_AIC_CNTL, msi_rearm);
789 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
790 break;
791 default:
792 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
793 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
794 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
795 break;
796 }
797 }
798 return IRQ_HANDLED;
799 }
800
801 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
802 {
803 if (crtc == 0)
804 return RREG32(RADEON_CRTC_CRNT_FRAME);
805 else
806 return RREG32(RADEON_CRTC2_CRNT_FRAME);
807 }
808
809 /* Who ever call radeon_fence_emit should call ring_lock and ask
810 * for enough space (today caller are ib schedule and buffer move) */
811 void r100_fence_ring_emit(struct radeon_device *rdev,
812 struct radeon_fence *fence)
813 {
814 /* We have to make sure that caches are flushed before
815 * CPU might read something from VRAM. */
816 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
817 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
818 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
819 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
820 /* Wait until IDLE & CLEAN */
821 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
822 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
823 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
824 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
825 RADEON_HDP_READ_BUFFER_INVALIDATE);
826 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
827 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
828 /* Emit fence sequence & fire IRQ */
829 radeon_ring_write(rdev, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
830 radeon_ring_write(rdev, fence->seq);
831 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
832 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
833 }
834
835 void r100_semaphore_ring_emit(struct radeon_device *rdev,
836 struct radeon_semaphore *semaphore,
837 unsigned ring, bool emit_wait)
838 {
839 /* Unused on older asics, since we don't have semaphores or multiple rings */
840 BUG();
841 }
842
843 int r100_copy_blit(struct radeon_device *rdev,
844 uint64_t src_offset,
845 uint64_t dst_offset,
846 unsigned num_gpu_pages,
847 struct radeon_fence *fence)
848 {
849 uint32_t cur_pages;
850 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
851 uint32_t pitch;
852 uint32_t stride_pixels;
853 unsigned ndw;
854 int num_loops;
855 int r = 0;
856
857 /* radeon limited to 16k stride */
858 stride_bytes &= 0x3fff;
859 /* radeon pitch is /64 */
860 pitch = stride_bytes / 64;
861 stride_pixels = stride_bytes / 4;
862 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
863
864 /* Ask for enough room for blit + flush + fence */
865 ndw = 64 + (10 * num_loops);
866 r = radeon_ring_lock(rdev, ndw);
867 if (r) {
868 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
869 return -EINVAL;
870 }
871 while (num_gpu_pages > 0) {
872 cur_pages = num_gpu_pages;
873 if (cur_pages > 8191) {
874 cur_pages = 8191;
875 }
876 num_gpu_pages -= cur_pages;
877
878 /* pages are in Y direction - height
879 page width in X direction - width */
880 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
881 radeon_ring_write(rdev,
882 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
883 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
884 RADEON_GMC_SRC_CLIPPING |
885 RADEON_GMC_DST_CLIPPING |
886 RADEON_GMC_BRUSH_NONE |
887 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
888 RADEON_GMC_SRC_DATATYPE_COLOR |
889 RADEON_ROP3_S |
890 RADEON_DP_SRC_SOURCE_MEMORY |
891 RADEON_GMC_CLR_CMP_CNTL_DIS |
892 RADEON_GMC_WR_MSK_DIS);
893 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
894 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
895 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
896 radeon_ring_write(rdev, 0);
897 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
898 radeon_ring_write(rdev, num_gpu_pages);
899 radeon_ring_write(rdev, num_gpu_pages);
900 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
901 }
902 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
903 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
904 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
905 radeon_ring_write(rdev,
906 RADEON_WAIT_2D_IDLECLEAN |
907 RADEON_WAIT_HOST_IDLECLEAN |
908 RADEON_WAIT_DMA_GUI_IDLE);
909 if (fence) {
910 r = radeon_fence_emit(rdev, fence);
911 }
912 radeon_ring_unlock_commit(rdev);
913 return r;
914 }
915
916 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
917 {
918 unsigned i;
919 u32 tmp;
920
921 for (i = 0; i < rdev->usec_timeout; i++) {
922 tmp = RREG32(R_000E40_RBBM_STATUS);
923 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
924 return 0;
925 }
926 udelay(1);
927 }
928 return -1;
929 }
930
931 void r100_ring_start(struct radeon_device *rdev)
932 {
933 int r;
934
935 r = radeon_ring_lock(rdev, 2);
936 if (r) {
937 return;
938 }
939 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
940 radeon_ring_write(rdev,
941 RADEON_ISYNC_ANY2D_IDLE3D |
942 RADEON_ISYNC_ANY3D_IDLE2D |
943 RADEON_ISYNC_WAIT_IDLEGUI |
944 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
945 radeon_ring_unlock_commit(rdev);
946 }
947
948
949 /* Load the microcode for the CP */
950 static int r100_cp_init_microcode(struct radeon_device *rdev)
951 {
952 struct platform_device *pdev;
953 const char *fw_name = NULL;
954 int err;
955
956 DRM_DEBUG_KMS("\n");
957
958 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
959 err = IS_ERR(pdev);
960 if (err) {
961 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
962 return -EINVAL;
963 }
964 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
965 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
966 (rdev->family == CHIP_RS200)) {
967 DRM_INFO("Loading R100 Microcode\n");
968 fw_name = FIRMWARE_R100;
969 } else if ((rdev->family == CHIP_R200) ||
970 (rdev->family == CHIP_RV250) ||
971 (rdev->family == CHIP_RV280) ||
972 (rdev->family == CHIP_RS300)) {
973 DRM_INFO("Loading R200 Microcode\n");
974 fw_name = FIRMWARE_R200;
975 } else if ((rdev->family == CHIP_R300) ||
976 (rdev->family == CHIP_R350) ||
977 (rdev->family == CHIP_RV350) ||
978 (rdev->family == CHIP_RV380) ||
979 (rdev->family == CHIP_RS400) ||
980 (rdev->family == CHIP_RS480)) {
981 DRM_INFO("Loading R300 Microcode\n");
982 fw_name = FIRMWARE_R300;
983 } else if ((rdev->family == CHIP_R420) ||
984 (rdev->family == CHIP_R423) ||
985 (rdev->family == CHIP_RV410)) {
986 DRM_INFO("Loading R400 Microcode\n");
987 fw_name = FIRMWARE_R420;
988 } else if ((rdev->family == CHIP_RS690) ||
989 (rdev->family == CHIP_RS740)) {
990 DRM_INFO("Loading RS690/RS740 Microcode\n");
991 fw_name = FIRMWARE_RS690;
992 } else if (rdev->family == CHIP_RS600) {
993 DRM_INFO("Loading RS600 Microcode\n");
994 fw_name = FIRMWARE_RS600;
995 } else if ((rdev->family == CHIP_RV515) ||
996 (rdev->family == CHIP_R520) ||
997 (rdev->family == CHIP_RV530) ||
998 (rdev->family == CHIP_R580) ||
999 (rdev->family == CHIP_RV560) ||
1000 (rdev->family == CHIP_RV570)) {
1001 DRM_INFO("Loading R500 Microcode\n");
1002 fw_name = FIRMWARE_R520;
1003 }
1004
1005 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1006 platform_device_unregister(pdev);
1007 if (err) {
1008 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1009 fw_name);
1010 } else if (rdev->me_fw->size % 8) {
1011 printk(KERN_ERR
1012 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1013 rdev->me_fw->size, fw_name);
1014 err = -EINVAL;
1015 release_firmware(rdev->me_fw);
1016 rdev->me_fw = NULL;
1017 }
1018 return err;
1019 }
1020
1021 static void r100_cp_load_microcode(struct radeon_device *rdev)
1022 {
1023 const __be32 *fw_data;
1024 int i, size;
1025
1026 if (r100_gui_wait_for_idle(rdev)) {
1027 printk(KERN_WARNING "Failed to wait GUI idle while "
1028 "programming pipes. Bad things might happen.\n");
1029 }
1030
1031 if (rdev->me_fw) {
1032 size = rdev->me_fw->size / 4;
1033 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1034 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1035 for (i = 0; i < size; i += 2) {
1036 WREG32(RADEON_CP_ME_RAM_DATAH,
1037 be32_to_cpup(&fw_data[i]));
1038 WREG32(RADEON_CP_ME_RAM_DATAL,
1039 be32_to_cpup(&fw_data[i + 1]));
1040 }
1041 }
1042 }
1043
1044 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1045 {
1046 unsigned rb_bufsz;
1047 unsigned rb_blksz;
1048 unsigned max_fetch;
1049 unsigned pre_write_timer;
1050 unsigned pre_write_limit;
1051 unsigned indirect2_start;
1052 unsigned indirect1_start;
1053 uint32_t tmp;
1054 int r;
1055
1056 if (r100_debugfs_cp_init(rdev)) {
1057 DRM_ERROR("Failed to register debugfs file for CP !\n");
1058 }
1059 if (!rdev->me_fw) {
1060 r = r100_cp_init_microcode(rdev);
1061 if (r) {
1062 DRM_ERROR("Failed to load firmware!\n");
1063 return r;
1064 }
1065 }
1066
1067 /* Align ring size */
1068 rb_bufsz = drm_order(ring_size / 8);
1069 ring_size = (1 << (rb_bufsz + 1)) * 4;
1070 r100_cp_load_microcode(rdev);
1071 r = radeon_ring_init(rdev, ring_size);
1072 if (r) {
1073 return r;
1074 }
1075 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1076 * the rptr copy in system ram */
1077 rb_blksz = 9;
1078 /* cp will read 128bytes at a time (4 dwords) */
1079 max_fetch = 1;
1080 rdev->cp.align_mask = 16 - 1;
1081 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1082 pre_write_timer = 64;
1083 /* Force CP_RB_WPTR write if written more than one time before the
1084 * delay expire
1085 */
1086 pre_write_limit = 0;
1087 /* Setup the cp cache like this (cache size is 96 dwords) :
1088 * RING 0 to 15
1089 * INDIRECT1 16 to 79
1090 * INDIRECT2 80 to 95
1091 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1092 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1093 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1094 * Idea being that most of the gpu cmd will be through indirect1 buffer
1095 * so it gets the bigger cache.
1096 */
1097 indirect2_start = 80;
1098 indirect1_start = 16;
1099 /* cp setup */
1100 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1101 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1102 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1103 REG_SET(RADEON_MAX_FETCH, max_fetch));
1104 #ifdef __BIG_ENDIAN
1105 tmp |= RADEON_BUF_SWAP_32BIT;
1106 #endif
1107 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1108
1109 /* Set ring address */
1110 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1111 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1112 /* Force read & write ptr to 0 */
1113 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1114 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1115 rdev->cp.wptr = 0;
1116 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1117
1118 /* set the wb address whether it's enabled or not */
1119 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1120 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1121 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1122
1123 if (rdev->wb.enabled)
1124 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1125 else {
1126 tmp |= RADEON_RB_NO_UPDATE;
1127 WREG32(R_000770_SCRATCH_UMSK, 0);
1128 }
1129
1130 WREG32(RADEON_CP_RB_CNTL, tmp);
1131 udelay(10);
1132 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1133 /* Set cp mode to bus mastering & enable cp*/
1134 WREG32(RADEON_CP_CSQ_MODE,
1135 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1136 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1137 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1138 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1139 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1140 radeon_ring_start(rdev);
1141 r = radeon_ring_test(rdev);
1142 if (r) {
1143 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1144 return r;
1145 }
1146 rdev->cp.ready = true;
1147 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1148 return 0;
1149 }
1150
1151 void r100_cp_fini(struct radeon_device *rdev)
1152 {
1153 if (r100_cp_wait_for_idle(rdev)) {
1154 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1155 }
1156 /* Disable ring */
1157 r100_cp_disable(rdev);
1158 radeon_ring_fini(rdev);
1159 DRM_INFO("radeon: cp finalized\n");
1160 }
1161
1162 void r100_cp_disable(struct radeon_device *rdev)
1163 {
1164 /* Disable ring */
1165 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1166 rdev->cp.ready = false;
1167 WREG32(RADEON_CP_CSQ_MODE, 0);
1168 WREG32(RADEON_CP_CSQ_CNTL, 0);
1169 WREG32(R_000770_SCRATCH_UMSK, 0);
1170 if (r100_gui_wait_for_idle(rdev)) {
1171 printk(KERN_WARNING "Failed to wait GUI idle while "
1172 "programming pipes. Bad things might happen.\n");
1173 }
1174 }
1175
1176 void r100_cp_commit(struct radeon_device *rdev)
1177 {
1178 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1179 (void)RREG32(RADEON_CP_RB_WPTR);
1180 }
1181
1182
1183 /*
1184 * CS functions
1185 */
1186 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1187 struct radeon_cs_packet *pkt,
1188 const unsigned *auth, unsigned n,
1189 radeon_packet0_check_t check)
1190 {
1191 unsigned reg;
1192 unsigned i, j, m;
1193 unsigned idx;
1194 int r;
1195
1196 idx = pkt->idx + 1;
1197 reg = pkt->reg;
1198 /* Check that register fall into register range
1199 * determined by the number of entry (n) in the
1200 * safe register bitmap.
1201 */
1202 if (pkt->one_reg_wr) {
1203 if ((reg >> 7) > n) {
1204 return -EINVAL;
1205 }
1206 } else {
1207 if (((reg + (pkt->count << 2)) >> 7) > n) {
1208 return -EINVAL;
1209 }
1210 }
1211 for (i = 0; i <= pkt->count; i++, idx++) {
1212 j = (reg >> 7);
1213 m = 1 << ((reg >> 2) & 31);
1214 if (auth[j] & m) {
1215 r = check(p, pkt, idx, reg);
1216 if (r) {
1217 return r;
1218 }
1219 }
1220 if (pkt->one_reg_wr) {
1221 if (!(auth[j] & m)) {
1222 break;
1223 }
1224 } else {
1225 reg += 4;
1226 }
1227 }
1228 return 0;
1229 }
1230
1231 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1232 struct radeon_cs_packet *pkt)
1233 {
1234 volatile uint32_t *ib;
1235 unsigned i;
1236 unsigned idx;
1237
1238 ib = p->ib->ptr;
1239 idx = pkt->idx;
1240 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1241 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1242 }
1243 }
1244
1245 /**
1246 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1247 * @parser: parser structure holding parsing context.
1248 * @pkt: where to store packet informations
1249 *
1250 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1251 * if packet is bigger than remaining ib size. or if packets is unknown.
1252 **/
1253 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1254 struct radeon_cs_packet *pkt,
1255 unsigned idx)
1256 {
1257 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1258 uint32_t header;
1259
1260 if (idx >= ib_chunk->length_dw) {
1261 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1262 idx, ib_chunk->length_dw);
1263 return -EINVAL;
1264 }
1265 header = radeon_get_ib_value(p, idx);
1266 pkt->idx = idx;
1267 pkt->type = CP_PACKET_GET_TYPE(header);
1268 pkt->count = CP_PACKET_GET_COUNT(header);
1269 switch (pkt->type) {
1270 case PACKET_TYPE0:
1271 pkt->reg = CP_PACKET0_GET_REG(header);
1272 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1273 break;
1274 case PACKET_TYPE3:
1275 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1276 break;
1277 case PACKET_TYPE2:
1278 pkt->count = -1;
1279 break;
1280 default:
1281 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1282 return -EINVAL;
1283 }
1284 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1285 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1286 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1287 return -EINVAL;
1288 }
1289 return 0;
1290 }
1291
1292 /**
1293 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1294 * @parser: parser structure holding parsing context.
1295 *
1296 * Userspace sends a special sequence for VLINE waits.
1297 * PACKET0 - VLINE_START_END + value
1298 * PACKET0 - WAIT_UNTIL +_value
1299 * RELOC (P3) - crtc_id in reloc.
1300 *
1301 * This function parses this and relocates the VLINE START END
1302 * and WAIT UNTIL packets to the correct crtc.
1303 * It also detects a switched off crtc and nulls out the
1304 * wait in that case.
1305 */
1306 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1307 {
1308 struct drm_mode_object *obj;
1309 struct drm_crtc *crtc;
1310 struct radeon_crtc *radeon_crtc;
1311 struct radeon_cs_packet p3reloc, waitreloc;
1312 int crtc_id;
1313 int r;
1314 uint32_t header, h_idx, reg;
1315 volatile uint32_t *ib;
1316
1317 ib = p->ib->ptr;
1318
1319 /* parse the wait until */
1320 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1321 if (r)
1322 return r;
1323
1324 /* check its a wait until and only 1 count */
1325 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1326 waitreloc.count != 0) {
1327 DRM_ERROR("vline wait had illegal wait until segment\n");
1328 return -EINVAL;
1329 }
1330
1331 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1332 DRM_ERROR("vline wait had illegal wait until\n");
1333 return -EINVAL;
1334 }
1335
1336 /* jump over the NOP */
1337 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1338 if (r)
1339 return r;
1340
1341 h_idx = p->idx - 2;
1342 p->idx += waitreloc.count + 2;
1343 p->idx += p3reloc.count + 2;
1344
1345 header = radeon_get_ib_value(p, h_idx);
1346 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1347 reg = CP_PACKET0_GET_REG(header);
1348 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1349 if (!obj) {
1350 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1351 return -EINVAL;
1352 }
1353 crtc = obj_to_crtc(obj);
1354 radeon_crtc = to_radeon_crtc(crtc);
1355 crtc_id = radeon_crtc->crtc_id;
1356
1357 if (!crtc->enabled) {
1358 /* if the CRTC isn't enabled - we need to nop out the wait until */
1359 ib[h_idx + 2] = PACKET2(0);
1360 ib[h_idx + 3] = PACKET2(0);
1361 } else if (crtc_id == 1) {
1362 switch (reg) {
1363 case AVIVO_D1MODE_VLINE_START_END:
1364 header &= ~R300_CP_PACKET0_REG_MASK;
1365 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1366 break;
1367 case RADEON_CRTC_GUI_TRIG_VLINE:
1368 header &= ~R300_CP_PACKET0_REG_MASK;
1369 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1370 break;
1371 default:
1372 DRM_ERROR("unknown crtc reloc\n");
1373 return -EINVAL;
1374 }
1375 ib[h_idx] = header;
1376 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1377 }
1378
1379 return 0;
1380 }
1381
1382 /**
1383 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1384 * @parser: parser structure holding parsing context.
1385 * @data: pointer to relocation data
1386 * @offset_start: starting offset
1387 * @offset_mask: offset mask (to align start offset on)
1388 * @reloc: reloc informations
1389 *
1390 * Check next packet is relocation packet3, do bo validation and compute
1391 * GPU offset using the provided start.
1392 **/
1393 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1394 struct radeon_cs_reloc **cs_reloc)
1395 {
1396 struct radeon_cs_chunk *relocs_chunk;
1397 struct radeon_cs_packet p3reloc;
1398 unsigned idx;
1399 int r;
1400
1401 if (p->chunk_relocs_idx == -1) {
1402 DRM_ERROR("No relocation chunk !\n");
1403 return -EINVAL;
1404 }
1405 *cs_reloc = NULL;
1406 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1407 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1408 if (r) {
1409 return r;
1410 }
1411 p->idx += p3reloc.count + 2;
1412 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1413 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1414 p3reloc.idx);
1415 r100_cs_dump_packet(p, &p3reloc);
1416 return -EINVAL;
1417 }
1418 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1419 if (idx >= relocs_chunk->length_dw) {
1420 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1421 idx, relocs_chunk->length_dw);
1422 r100_cs_dump_packet(p, &p3reloc);
1423 return -EINVAL;
1424 }
1425 /* FIXME: we assume reloc size is 4 dwords */
1426 *cs_reloc = p->relocs_ptr[(idx / 4)];
1427 return 0;
1428 }
1429
1430 static int r100_get_vtx_size(uint32_t vtx_fmt)
1431 {
1432 int vtx_size;
1433 vtx_size = 2;
1434 /* ordered according to bits in spec */
1435 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1436 vtx_size++;
1437 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1438 vtx_size += 3;
1439 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1440 vtx_size++;
1441 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1442 vtx_size++;
1443 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1444 vtx_size += 3;
1445 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1446 vtx_size++;
1447 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1448 vtx_size++;
1449 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1450 vtx_size += 2;
1451 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1452 vtx_size += 2;
1453 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1454 vtx_size++;
1455 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1456 vtx_size += 2;
1457 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1458 vtx_size++;
1459 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1460 vtx_size += 2;
1461 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1462 vtx_size++;
1463 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1464 vtx_size++;
1465 /* blend weight */
1466 if (vtx_fmt & (0x7 << 15))
1467 vtx_size += (vtx_fmt >> 15) & 0x7;
1468 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1469 vtx_size += 3;
1470 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1471 vtx_size += 2;
1472 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1473 vtx_size++;
1474 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1475 vtx_size++;
1476 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1477 vtx_size++;
1478 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1479 vtx_size++;
1480 return vtx_size;
1481 }
1482
1483 static int r100_packet0_check(struct radeon_cs_parser *p,
1484 struct radeon_cs_packet *pkt,
1485 unsigned idx, unsigned reg)
1486 {
1487 struct radeon_cs_reloc *reloc;
1488 struct r100_cs_track *track;
1489 volatile uint32_t *ib;
1490 uint32_t tmp;
1491 int r;
1492 int i, face;
1493 u32 tile_flags = 0;
1494 u32 idx_value;
1495
1496 ib = p->ib->ptr;
1497 track = (struct r100_cs_track *)p->track;
1498
1499 idx_value = radeon_get_ib_value(p, idx);
1500
1501 switch (reg) {
1502 case RADEON_CRTC_GUI_TRIG_VLINE:
1503 r = r100_cs_packet_parse_vline(p);
1504 if (r) {
1505 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1506 idx, reg);
1507 r100_cs_dump_packet(p, pkt);
1508 return r;
1509 }
1510 break;
1511 /* FIXME: only allow PACKET3 blit? easier to check for out of
1512 * range access */
1513 case RADEON_DST_PITCH_OFFSET:
1514 case RADEON_SRC_PITCH_OFFSET:
1515 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1516 if (r)
1517 return r;
1518 break;
1519 case RADEON_RB3D_DEPTHOFFSET:
1520 r = r100_cs_packet_next_reloc(p, &reloc);
1521 if (r) {
1522 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1523 idx, reg);
1524 r100_cs_dump_packet(p, pkt);
1525 return r;
1526 }
1527 track->zb.robj = reloc->robj;
1528 track->zb.offset = idx_value;
1529 track->zb_dirty = true;
1530 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1531 break;
1532 case RADEON_RB3D_COLOROFFSET:
1533 r = r100_cs_packet_next_reloc(p, &reloc);
1534 if (r) {
1535 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1536 idx, reg);
1537 r100_cs_dump_packet(p, pkt);
1538 return r;
1539 }
1540 track->cb[0].robj = reloc->robj;
1541 track->cb[0].offset = idx_value;
1542 track->cb_dirty = true;
1543 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1544 break;
1545 case RADEON_PP_TXOFFSET_0:
1546 case RADEON_PP_TXOFFSET_1:
1547 case RADEON_PP_TXOFFSET_2:
1548 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1549 r = r100_cs_packet_next_reloc(p, &reloc);
1550 if (r) {
1551 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1552 idx, reg);
1553 r100_cs_dump_packet(p, pkt);
1554 return r;
1555 }
1556 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1557 track->textures[i].robj = reloc->robj;
1558 track->tex_dirty = true;
1559 break;
1560 case RADEON_PP_CUBIC_OFFSET_T0_0:
1561 case RADEON_PP_CUBIC_OFFSET_T0_1:
1562 case RADEON_PP_CUBIC_OFFSET_T0_2:
1563 case RADEON_PP_CUBIC_OFFSET_T0_3:
1564 case RADEON_PP_CUBIC_OFFSET_T0_4:
1565 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1566 r = r100_cs_packet_next_reloc(p, &reloc);
1567 if (r) {
1568 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1569 idx, reg);
1570 r100_cs_dump_packet(p, pkt);
1571 return r;
1572 }
1573 track->textures[0].cube_info[i].offset = idx_value;
1574 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1575 track->textures[0].cube_info[i].robj = reloc->robj;
1576 track->tex_dirty = true;
1577 break;
1578 case RADEON_PP_CUBIC_OFFSET_T1_0:
1579 case RADEON_PP_CUBIC_OFFSET_T1_1:
1580 case RADEON_PP_CUBIC_OFFSET_T1_2:
1581 case RADEON_PP_CUBIC_OFFSET_T1_3:
1582 case RADEON_PP_CUBIC_OFFSET_T1_4:
1583 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1584 r = r100_cs_packet_next_reloc(p, &reloc);
1585 if (r) {
1586 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1587 idx, reg);
1588 r100_cs_dump_packet(p, pkt);
1589 return r;
1590 }
1591 track->textures[1].cube_info[i].offset = idx_value;
1592 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1593 track->textures[1].cube_info[i].robj = reloc->robj;
1594 track->tex_dirty = true;
1595 break;
1596 case RADEON_PP_CUBIC_OFFSET_T2_0:
1597 case RADEON_PP_CUBIC_OFFSET_T2_1:
1598 case RADEON_PP_CUBIC_OFFSET_T2_2:
1599 case RADEON_PP_CUBIC_OFFSET_T2_3:
1600 case RADEON_PP_CUBIC_OFFSET_T2_4:
1601 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1602 r = r100_cs_packet_next_reloc(p, &reloc);
1603 if (r) {
1604 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1605 idx, reg);
1606 r100_cs_dump_packet(p, pkt);
1607 return r;
1608 }
1609 track->textures[2].cube_info[i].offset = idx_value;
1610 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1611 track->textures[2].cube_info[i].robj = reloc->robj;
1612 track->tex_dirty = true;
1613 break;
1614 case RADEON_RE_WIDTH_HEIGHT:
1615 track->maxy = ((idx_value >> 16) & 0x7FF);
1616 track->cb_dirty = true;
1617 track->zb_dirty = true;
1618 break;
1619 case RADEON_RB3D_COLORPITCH:
1620 r = r100_cs_packet_next_reloc(p, &reloc);
1621 if (r) {
1622 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1623 idx, reg);
1624 r100_cs_dump_packet(p, pkt);
1625 return r;
1626 }
1627
1628 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1629 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1630 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1631 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1632
1633 tmp = idx_value & ~(0x7 << 16);
1634 tmp |= tile_flags;
1635 ib[idx] = tmp;
1636
1637 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1638 track->cb_dirty = true;
1639 break;
1640 case RADEON_RB3D_DEPTHPITCH:
1641 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1642 track->zb_dirty = true;
1643 break;
1644 case RADEON_RB3D_CNTL:
1645 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1646 case 7:
1647 case 8:
1648 case 9:
1649 case 11:
1650 case 12:
1651 track->cb[0].cpp = 1;
1652 break;
1653 case 3:
1654 case 4:
1655 case 15:
1656 track->cb[0].cpp = 2;
1657 break;
1658 case 6:
1659 track->cb[0].cpp = 4;
1660 break;
1661 default:
1662 DRM_ERROR("Invalid color buffer format (%d) !\n",
1663 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1664 return -EINVAL;
1665 }
1666 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1667 track->cb_dirty = true;
1668 track->zb_dirty = true;
1669 break;
1670 case RADEON_RB3D_ZSTENCILCNTL:
1671 switch (idx_value & 0xf) {
1672 case 0:
1673 track->zb.cpp = 2;
1674 break;
1675 case 2:
1676 case 3:
1677 case 4:
1678 case 5:
1679 case 9:
1680 case 11:
1681 track->zb.cpp = 4;
1682 break;
1683 default:
1684 break;
1685 }
1686 track->zb_dirty = true;
1687 break;
1688 case RADEON_RB3D_ZPASS_ADDR:
1689 r = r100_cs_packet_next_reloc(p, &reloc);
1690 if (r) {
1691 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1692 idx, reg);
1693 r100_cs_dump_packet(p, pkt);
1694 return r;
1695 }
1696 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1697 break;
1698 case RADEON_PP_CNTL:
1699 {
1700 uint32_t temp = idx_value >> 4;
1701 for (i = 0; i < track->num_texture; i++)
1702 track->textures[i].enabled = !!(temp & (1 << i));
1703 track->tex_dirty = true;
1704 }
1705 break;
1706 case RADEON_SE_VF_CNTL:
1707 track->vap_vf_cntl = idx_value;
1708 break;
1709 case RADEON_SE_VTX_FMT:
1710 track->vtx_size = r100_get_vtx_size(idx_value);
1711 break;
1712 case RADEON_PP_TEX_SIZE_0:
1713 case RADEON_PP_TEX_SIZE_1:
1714 case RADEON_PP_TEX_SIZE_2:
1715 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1716 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1717 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1718 track->tex_dirty = true;
1719 break;
1720 case RADEON_PP_TEX_PITCH_0:
1721 case RADEON_PP_TEX_PITCH_1:
1722 case RADEON_PP_TEX_PITCH_2:
1723 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1724 track->textures[i].pitch = idx_value + 32;
1725 track->tex_dirty = true;
1726 break;
1727 case RADEON_PP_TXFILTER_0:
1728 case RADEON_PP_TXFILTER_1:
1729 case RADEON_PP_TXFILTER_2:
1730 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1731 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1732 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1733 tmp = (idx_value >> 23) & 0x7;
1734 if (tmp == 2 || tmp == 6)
1735 track->textures[i].roundup_w = false;
1736 tmp = (idx_value >> 27) & 0x7;
1737 if (tmp == 2 || tmp == 6)
1738 track->textures[i].roundup_h = false;
1739 track->tex_dirty = true;
1740 break;
1741 case RADEON_PP_TXFORMAT_0:
1742 case RADEON_PP_TXFORMAT_1:
1743 case RADEON_PP_TXFORMAT_2:
1744 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1745 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1746 track->textures[i].use_pitch = 1;
1747 } else {
1748 track->textures[i].use_pitch = 0;
1749 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1750 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1751 }
1752 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1753 track->textures[i].tex_coord_type = 2;
1754 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1755 case RADEON_TXFORMAT_I8:
1756 case RADEON_TXFORMAT_RGB332:
1757 case RADEON_TXFORMAT_Y8:
1758 track->textures[i].cpp = 1;
1759 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1760 break;
1761 case RADEON_TXFORMAT_AI88:
1762 case RADEON_TXFORMAT_ARGB1555:
1763 case RADEON_TXFORMAT_RGB565:
1764 case RADEON_TXFORMAT_ARGB4444:
1765 case RADEON_TXFORMAT_VYUY422:
1766 case RADEON_TXFORMAT_YVYU422:
1767 case RADEON_TXFORMAT_SHADOW16:
1768 case RADEON_TXFORMAT_LDUDV655:
1769 case RADEON_TXFORMAT_DUDV88:
1770 track->textures[i].cpp = 2;
1771 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1772 break;
1773 case RADEON_TXFORMAT_ARGB8888:
1774 case RADEON_TXFORMAT_RGBA8888:
1775 case RADEON_TXFORMAT_SHADOW32:
1776 case RADEON_TXFORMAT_LDUDUV8888:
1777 track->textures[i].cpp = 4;
1778 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1779 break;
1780 case RADEON_TXFORMAT_DXT1:
1781 track->textures[i].cpp = 1;
1782 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1783 break;
1784 case RADEON_TXFORMAT_DXT23:
1785 case RADEON_TXFORMAT_DXT45:
1786 track->textures[i].cpp = 1;
1787 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1788 break;
1789 }
1790 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1791 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1792 track->tex_dirty = true;
1793 break;
1794 case RADEON_PP_CUBIC_FACES_0:
1795 case RADEON_PP_CUBIC_FACES_1:
1796 case RADEON_PP_CUBIC_FACES_2:
1797 tmp = idx_value;
1798 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1799 for (face = 0; face < 4; face++) {
1800 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1801 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1802 }
1803 track->tex_dirty = true;
1804 break;
1805 default:
1806 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1807 reg, idx);
1808 return -EINVAL;
1809 }
1810 return 0;
1811 }
1812
1813 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1814 struct radeon_cs_packet *pkt,
1815 struct radeon_bo *robj)
1816 {
1817 unsigned idx;
1818 u32 value;
1819 idx = pkt->idx + 1;
1820 value = radeon_get_ib_value(p, idx + 2);
1821 if ((value + 1) > radeon_bo_size(robj)) {
1822 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1823 "(need %u have %lu) !\n",
1824 value + 1,
1825 radeon_bo_size(robj));
1826 return -EINVAL;
1827 }
1828 return 0;
1829 }
1830
1831 static int r100_packet3_check(struct radeon_cs_parser *p,
1832 struct radeon_cs_packet *pkt)
1833 {
1834 struct radeon_cs_reloc *reloc;
1835 struct r100_cs_track *track;
1836 unsigned idx;
1837 volatile uint32_t *ib;
1838 int r;
1839
1840 ib = p->ib->ptr;
1841 idx = pkt->idx + 1;
1842 track = (struct r100_cs_track *)p->track;
1843 switch (pkt->opcode) {
1844 case PACKET3_3D_LOAD_VBPNTR:
1845 r = r100_packet3_load_vbpntr(p, pkt, idx);
1846 if (r)
1847 return r;
1848 break;
1849 case PACKET3_INDX_BUFFER:
1850 r = r100_cs_packet_next_reloc(p, &reloc);
1851 if (r) {
1852 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1853 r100_cs_dump_packet(p, pkt);
1854 return r;
1855 }
1856 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1857 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1858 if (r) {
1859 return r;
1860 }
1861 break;
1862 case 0x23:
1863 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1864 r = r100_cs_packet_next_reloc(p, &reloc);
1865 if (r) {
1866 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1867 r100_cs_dump_packet(p, pkt);
1868 return r;
1869 }
1870 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1871 track->num_arrays = 1;
1872 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1873
1874 track->arrays[0].robj = reloc->robj;
1875 track->arrays[0].esize = track->vtx_size;
1876
1877 track->max_indx = radeon_get_ib_value(p, idx+1);
1878
1879 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1880 track->immd_dwords = pkt->count - 1;
1881 r = r100_cs_track_check(p->rdev, track);
1882 if (r)
1883 return r;
1884 break;
1885 case PACKET3_3D_DRAW_IMMD:
1886 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1887 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1888 return -EINVAL;
1889 }
1890 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1891 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1892 track->immd_dwords = pkt->count - 1;
1893 r = r100_cs_track_check(p->rdev, track);
1894 if (r)
1895 return r;
1896 break;
1897 /* triggers drawing using in-packet vertex data */
1898 case PACKET3_3D_DRAW_IMMD_2:
1899 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1900 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1901 return -EINVAL;
1902 }
1903 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1904 track->immd_dwords = pkt->count;
1905 r = r100_cs_track_check(p->rdev, track);
1906 if (r)
1907 return r;
1908 break;
1909 /* triggers drawing using in-packet vertex data */
1910 case PACKET3_3D_DRAW_VBUF_2:
1911 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1912 r = r100_cs_track_check(p->rdev, track);
1913 if (r)
1914 return r;
1915 break;
1916 /* triggers drawing of vertex buffers setup elsewhere */
1917 case PACKET3_3D_DRAW_INDX_2:
1918 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1919 r = r100_cs_track_check(p->rdev, track);
1920 if (r)
1921 return r;
1922 break;
1923 /* triggers drawing using indices to vertex buffer */
1924 case PACKET3_3D_DRAW_VBUF:
1925 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1926 r = r100_cs_track_check(p->rdev, track);
1927 if (r)
1928 return r;
1929 break;
1930 /* triggers drawing of vertex buffers setup elsewhere */
1931 case PACKET3_3D_DRAW_INDX:
1932 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1933 r = r100_cs_track_check(p->rdev, track);
1934 if (r)
1935 return r;
1936 break;
1937 /* triggers drawing using indices to vertex buffer */
1938 case PACKET3_3D_CLEAR_HIZ:
1939 case PACKET3_3D_CLEAR_ZMASK:
1940 if (p->rdev->hyperz_filp != p->filp)
1941 return -EINVAL;
1942 break;
1943 case PACKET3_NOP:
1944 break;
1945 default:
1946 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1947 return -EINVAL;
1948 }
1949 return 0;
1950 }
1951
1952 int r100_cs_parse(struct radeon_cs_parser *p)
1953 {
1954 struct radeon_cs_packet pkt;
1955 struct r100_cs_track *track;
1956 int r;
1957
1958 track = kzalloc(sizeof(*track), GFP_KERNEL);
1959 r100_cs_track_clear(p->rdev, track);
1960 p->track = track;
1961 do {
1962 r = r100_cs_packet_parse(p, &pkt, p->idx);
1963 if (r) {
1964 return r;
1965 }
1966 p->idx += pkt.count + 2;
1967 switch (pkt.type) {
1968 case PACKET_TYPE0:
1969 if (p->rdev->family >= CHIP_R200)
1970 r = r100_cs_parse_packet0(p, &pkt,
1971 p->rdev->config.r100.reg_safe_bm,
1972 p->rdev->config.r100.reg_safe_bm_size,
1973 &r200_packet0_check);
1974 else
1975 r = r100_cs_parse_packet0(p, &pkt,
1976 p->rdev->config.r100.reg_safe_bm,
1977 p->rdev->config.r100.reg_safe_bm_size,
1978 &r100_packet0_check);
1979 break;
1980 case PACKET_TYPE2:
1981 break;
1982 case PACKET_TYPE3:
1983 r = r100_packet3_check(p, &pkt);
1984 break;
1985 default:
1986 DRM_ERROR("Unknown packet type %d !\n",
1987 pkt.type);
1988 return -EINVAL;
1989 }
1990 if (r) {
1991 return r;
1992 }
1993 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1994 return 0;
1995 }
1996
1997
1998 /*
1999 * Global GPU functions
2000 */
2001 void r100_errata(struct radeon_device *rdev)
2002 {
2003 rdev->pll_errata = 0;
2004
2005 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2006 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2007 }
2008
2009 if (rdev->family == CHIP_RV100 ||
2010 rdev->family == CHIP_RS100 ||
2011 rdev->family == CHIP_RS200) {
2012 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2013 }
2014 }
2015
2016 /* Wait for vertical sync on primary CRTC */
2017 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2018 {
2019 uint32_t crtc_gen_cntl, tmp;
2020 int i;
2021
2022 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2023 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2024 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2025 return;
2026 }
2027 /* Clear the CRTC_VBLANK_SAVE bit */
2028 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2029 for (i = 0; i < rdev->usec_timeout; i++) {
2030 tmp = RREG32(RADEON_CRTC_STATUS);
2031 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2032 return;
2033 }
2034 DRM_UDELAY(1);
2035 }
2036 }
2037
2038 /* Wait for vertical sync on secondary CRTC */
2039 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2040 {
2041 uint32_t crtc2_gen_cntl, tmp;
2042 int i;
2043
2044 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2045 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2046 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2047 return;
2048
2049 /* Clear the CRTC_VBLANK_SAVE bit */
2050 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2051 for (i = 0; i < rdev->usec_timeout; i++) {
2052 tmp = RREG32(RADEON_CRTC2_STATUS);
2053 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2054 return;
2055 }
2056 DRM_UDELAY(1);
2057 }
2058 }
2059
2060 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2061 {
2062 unsigned i;
2063 uint32_t tmp;
2064
2065 for (i = 0; i < rdev->usec_timeout; i++) {
2066 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2067 if (tmp >= n) {
2068 return 0;
2069 }
2070 DRM_UDELAY(1);
2071 }
2072 return -1;
2073 }
2074
2075 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2076 {
2077 unsigned i;
2078 uint32_t tmp;
2079
2080 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2081 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2082 " Bad things might happen.\n");
2083 }
2084 for (i = 0; i < rdev->usec_timeout; i++) {
2085 tmp = RREG32(RADEON_RBBM_STATUS);
2086 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2087 return 0;
2088 }
2089 DRM_UDELAY(1);
2090 }
2091 return -1;
2092 }
2093
2094 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2095 {
2096 unsigned i;
2097 uint32_t tmp;
2098
2099 for (i = 0; i < rdev->usec_timeout; i++) {
2100 /* read MC_STATUS */
2101 tmp = RREG32(RADEON_MC_STATUS);
2102 if (tmp & RADEON_MC_IDLE) {
2103 return 0;
2104 }
2105 DRM_UDELAY(1);
2106 }
2107 return -1;
2108 }
2109
2110 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2111 {
2112 lockup->last_cp_rptr = cp->rptr;
2113 lockup->last_jiffies = jiffies;
2114 }
2115
2116 /**
2117 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2118 * @rdev: radeon device structure
2119 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2120 * @cp: radeon_cp structure holding CP information
2121 *
2122 * We don't need to initialize the lockup tracking information as we will either
2123 * have CP rptr to a different value of jiffies wrap around which will force
2124 * initialization of the lockup tracking informations.
2125 *
2126 * A possible false positivie is if we get call after while and last_cp_rptr ==
2127 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2128 * if the elapsed time since last call is bigger than 2 second than we return
2129 * false and update the tracking information. Due to this the caller must call
2130 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2131 * the fencing code should be cautious about that.
2132 *
2133 * Caller should write to the ring to force CP to do something so we don't get
2134 * false positive when CP is just gived nothing to do.
2135 *
2136 **/
2137 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2138 {
2139 unsigned long cjiffies, elapsed;
2140
2141 cjiffies = jiffies;
2142 if (!time_after(cjiffies, lockup->last_jiffies)) {
2143 /* likely a wrap around */
2144 lockup->last_cp_rptr = cp->rptr;
2145 lockup->last_jiffies = jiffies;
2146 return false;
2147 }
2148 if (cp->rptr != lockup->last_cp_rptr) {
2149 /* CP is still working no lockup */
2150 lockup->last_cp_rptr = cp->rptr;
2151 lockup->last_jiffies = jiffies;
2152 return false;
2153 }
2154 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2155 if (elapsed >= 10000) {
2156 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2157 return true;
2158 }
2159 /* give a chance to the GPU ... */
2160 return false;
2161 }
2162
2163 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2164 {
2165 u32 rbbm_status;
2166 int r;
2167
2168 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2169 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2170 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2171 return false;
2172 }
2173 /* force CP activities */
2174 r = radeon_ring_lock(rdev, 2);
2175 if (!r) {
2176 /* PACKET2 NOP */
2177 radeon_ring_write(rdev, 0x80000000);
2178 radeon_ring_write(rdev, 0x80000000);
2179 radeon_ring_unlock_commit(rdev);
2180 }
2181 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2182 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2183 }
2184
2185 void r100_bm_disable(struct radeon_device *rdev)
2186 {
2187 u32 tmp;
2188
2189 /* disable bus mastering */
2190 tmp = RREG32(R_000030_BUS_CNTL);
2191 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2192 mdelay(1);
2193 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2194 mdelay(1);
2195 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2196 tmp = RREG32(RADEON_BUS_CNTL);
2197 mdelay(1);
2198 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2199 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2200 mdelay(1);
2201 }
2202
2203 int r100_asic_reset(struct radeon_device *rdev)
2204 {
2205 struct r100_mc_save save;
2206 u32 status, tmp;
2207 int ret = 0;
2208
2209 status = RREG32(R_000E40_RBBM_STATUS);
2210 if (!G_000E40_GUI_ACTIVE(status)) {
2211 return 0;
2212 }
2213 r100_mc_stop(rdev, &save);
2214 status = RREG32(R_000E40_RBBM_STATUS);
2215 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2216 /* stop CP */
2217 WREG32(RADEON_CP_CSQ_CNTL, 0);
2218 tmp = RREG32(RADEON_CP_RB_CNTL);
2219 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2220 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2221 WREG32(RADEON_CP_RB_WPTR, 0);
2222 WREG32(RADEON_CP_RB_CNTL, tmp);
2223 /* save PCI state */
2224 pci_save_state(rdev->pdev);
2225 /* disable bus mastering */
2226 r100_bm_disable(rdev);
2227 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2228 S_0000F0_SOFT_RESET_RE(1) |
2229 S_0000F0_SOFT_RESET_PP(1) |
2230 S_0000F0_SOFT_RESET_RB(1));
2231 RREG32(R_0000F0_RBBM_SOFT_RESET);
2232 mdelay(500);
2233 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2234 mdelay(1);
2235 status = RREG32(R_000E40_RBBM_STATUS);
2236 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2237 /* reset CP */
2238 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2239 RREG32(R_0000F0_RBBM_SOFT_RESET);
2240 mdelay(500);
2241 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2242 mdelay(1);
2243 status = RREG32(R_000E40_RBBM_STATUS);
2244 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2245 /* restore PCI & busmastering */
2246 pci_restore_state(rdev->pdev);
2247 r100_enable_bm(rdev);
2248 /* Check if GPU is idle */
2249 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2250 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2251 dev_err(rdev->dev, "failed to reset GPU\n");
2252 rdev->gpu_lockup = true;
2253 ret = -1;
2254 } else
2255 dev_info(rdev->dev, "GPU reset succeed\n");
2256 r100_mc_resume(rdev, &save);
2257 return ret;
2258 }
2259
2260 void r100_set_common_regs(struct radeon_device *rdev)
2261 {
2262 struct drm_device *dev = rdev->ddev;
2263 bool force_dac2 = false;
2264 u32 tmp;
2265
2266 /* set these so they don't interfere with anything */
2267 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2268 WREG32(RADEON_SUBPIC_CNTL, 0);
2269 WREG32(RADEON_VIPH_CONTROL, 0);
2270 WREG32(RADEON_I2C_CNTL_1, 0);
2271 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2272 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2273 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2274
2275 /* always set up dac2 on rn50 and some rv100 as lots
2276 * of servers seem to wire it up to a VGA port but
2277 * don't report it in the bios connector
2278 * table.
2279 */
2280 switch (dev->pdev->device) {
2281 /* RN50 */
2282 case 0x515e:
2283 case 0x5969:
2284 force_dac2 = true;
2285 break;
2286 /* RV100*/
2287 case 0x5159:
2288 case 0x515a:
2289 /* DELL triple head servers */
2290 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2291 ((dev->pdev->subsystem_device == 0x016c) ||
2292 (dev->pdev->subsystem_device == 0x016d) ||
2293 (dev->pdev->subsystem_device == 0x016e) ||
2294 (dev->pdev->subsystem_device == 0x016f) ||
2295 (dev->pdev->subsystem_device == 0x0170) ||
2296 (dev->pdev->subsystem_device == 0x017d) ||
2297 (dev->pdev->subsystem_device == 0x017e) ||
2298 (dev->pdev->subsystem_device == 0x0183) ||
2299 (dev->pdev->subsystem_device == 0x018a) ||
2300 (dev->pdev->subsystem_device == 0x019a)))
2301 force_dac2 = true;
2302 break;
2303 }
2304
2305 if (force_dac2) {
2306 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2307 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2308 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2309
2310 /* For CRT on DAC2, don't turn it on if BIOS didn't
2311 enable it, even it's detected.
2312 */
2313
2314 /* force it to crtc0 */
2315 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2316 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2317 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2318
2319 /* set up the TV DAC */
2320 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2321 RADEON_TV_DAC_STD_MASK |
2322 RADEON_TV_DAC_RDACPD |
2323 RADEON_TV_DAC_GDACPD |
2324 RADEON_TV_DAC_BDACPD |
2325 RADEON_TV_DAC_BGADJ_MASK |
2326 RADEON_TV_DAC_DACADJ_MASK);
2327 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2328 RADEON_TV_DAC_NHOLD |
2329 RADEON_TV_DAC_STD_PS2 |
2330 (0x58 << 16));
2331
2332 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2333 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2334 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2335 }
2336
2337 /* switch PM block to ACPI mode */
2338 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2339 tmp &= ~RADEON_PM_MODE_SEL;
2340 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2341
2342 }
2343
2344 /*
2345 * VRAM info
2346 */
2347 static void r100_vram_get_type(struct radeon_device *rdev)
2348 {
2349 uint32_t tmp;
2350
2351 rdev->mc.vram_is_ddr = false;
2352 if (rdev->flags & RADEON_IS_IGP)
2353 rdev->mc.vram_is_ddr = true;
2354 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2355 rdev->mc.vram_is_ddr = true;
2356 if ((rdev->family == CHIP_RV100) ||
2357 (rdev->family == CHIP_RS100) ||
2358 (rdev->family == CHIP_RS200)) {
2359 tmp = RREG32(RADEON_MEM_CNTL);
2360 if (tmp & RV100_HALF_MODE) {
2361 rdev->mc.vram_width = 32;
2362 } else {
2363 rdev->mc.vram_width = 64;
2364 }
2365 if (rdev->flags & RADEON_SINGLE_CRTC) {
2366 rdev->mc.vram_width /= 4;
2367 rdev->mc.vram_is_ddr = true;
2368 }
2369 } else if (rdev->family <= CHIP_RV280) {
2370 tmp = RREG32(RADEON_MEM_CNTL);
2371 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2372 rdev->mc.vram_width = 128;
2373 } else {
2374 rdev->mc.vram_width = 64;
2375 }
2376 } else {
2377 /* newer IGPs */
2378 rdev->mc.vram_width = 128;
2379 }
2380 }
2381
2382 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2383 {
2384 u32 aper_size;
2385 u8 byte;
2386
2387 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2388
2389 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2390 * that is has the 2nd generation multifunction PCI interface
2391 */
2392 if (rdev->family == CHIP_RV280 ||
2393 rdev->family >= CHIP_RV350) {
2394 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2395 ~RADEON_HDP_APER_CNTL);
2396 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2397 return aper_size * 2;
2398 }
2399
2400 /* Older cards have all sorts of funny issues to deal with. First
2401 * check if it's a multifunction card by reading the PCI config
2402 * header type... Limit those to one aperture size
2403 */
2404 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2405 if (byte & 0x80) {
2406 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2407 DRM_INFO("Limiting VRAM to one aperture\n");
2408 return aper_size;
2409 }
2410
2411 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2412 * have set it up. We don't write this as it's broken on some ASICs but
2413 * we expect the BIOS to have done the right thing (might be too optimistic...)
2414 */
2415 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2416 return aper_size * 2;
2417 return aper_size;
2418 }
2419
2420 void r100_vram_init_sizes(struct radeon_device *rdev)
2421 {
2422 u64 config_aper_size;
2423
2424 /* work out accessible VRAM */
2425 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2426 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2427 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2428 /* FIXME we don't use the second aperture yet when we could use it */
2429 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2430 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2431 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2432 if (rdev->flags & RADEON_IS_IGP) {
2433 uint32_t tom;
2434 /* read NB_TOM to get the amount of ram stolen for the GPU */
2435 tom = RREG32(RADEON_NB_TOM);
2436 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2437 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2438 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2439 } else {
2440 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2441 /* Some production boards of m6 will report 0
2442 * if it's 8 MB
2443 */
2444 if (rdev->mc.real_vram_size == 0) {
2445 rdev->mc.real_vram_size = 8192 * 1024;
2446 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2447 }
2448 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2449 * Novell bug 204882 + along with lots of ubuntu ones
2450 */
2451 if (rdev->mc.aper_size > config_aper_size)
2452 config_aper_size = rdev->mc.aper_size;
2453
2454 if (config_aper_size > rdev->mc.real_vram_size)
2455 rdev->mc.mc_vram_size = config_aper_size;
2456 else
2457 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2458 }
2459 }
2460
2461 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2462 {
2463 uint32_t temp;
2464
2465 temp = RREG32(RADEON_CONFIG_CNTL);
2466 if (state == false) {
2467 temp &= ~RADEON_CFG_VGA_RAM_EN;
2468 temp |= RADEON_CFG_VGA_IO_DIS;
2469 } else {
2470 temp &= ~RADEON_CFG_VGA_IO_DIS;
2471 }
2472 WREG32(RADEON_CONFIG_CNTL, temp);
2473 }
2474
2475 void r100_mc_init(struct radeon_device *rdev)
2476 {
2477 u64 base;
2478
2479 r100_vram_get_type(rdev);
2480 r100_vram_init_sizes(rdev);
2481 base = rdev->mc.aper_base;
2482 if (rdev->flags & RADEON_IS_IGP)
2483 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2484 radeon_vram_location(rdev, &rdev->mc, base);
2485 rdev->mc.gtt_base_align = 0;
2486 if (!(rdev->flags & RADEON_IS_AGP))
2487 radeon_gtt_location(rdev, &rdev->mc);
2488 radeon_update_bandwidth_info(rdev);
2489 }
2490
2491
2492 /*
2493 * Indirect registers accessor
2494 */
2495 void r100_pll_errata_after_index(struct radeon_device *rdev)
2496 {
2497 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2498 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2499 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2500 }
2501 }
2502
2503 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2504 {
2505 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2506 * or the chip could hang on a subsequent access
2507 */
2508 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2509 udelay(5000);
2510 }
2511
2512 /* This function is required to workaround a hardware bug in some (all?)
2513 * revisions of the R300. This workaround should be called after every
2514 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2515 * may not be correct.
2516 */
2517 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2518 uint32_t save, tmp;
2519
2520 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2521 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2522 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2523 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2524 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2525 }
2526 }
2527
2528 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2529 {
2530 uint32_t data;
2531
2532 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2533 r100_pll_errata_after_index(rdev);
2534 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2535 r100_pll_errata_after_data(rdev);
2536 return data;
2537 }
2538
2539 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2540 {
2541 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2542 r100_pll_errata_after_index(rdev);
2543 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2544 r100_pll_errata_after_data(rdev);
2545 }
2546
2547 void r100_set_safe_registers(struct radeon_device *rdev)
2548 {
2549 if (ASIC_IS_RN50(rdev)) {
2550 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2551 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2552 } else if (rdev->family < CHIP_R200) {
2553 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2554 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2555 } else {
2556 r200_set_safe_registers(rdev);
2557 }
2558 }
2559
2560 /*
2561 * Debugfs info
2562 */
2563 #if defined(CONFIG_DEBUG_FS)
2564 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2565 {
2566 struct drm_info_node *node = (struct drm_info_node *) m->private;
2567 struct drm_device *dev = node->minor->dev;
2568 struct radeon_device *rdev = dev->dev_private;
2569 uint32_t reg, value;
2570 unsigned i;
2571
2572 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2573 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2574 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2575 for (i = 0; i < 64; i++) {
2576 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2577 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2578 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2579 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2580 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2581 }
2582 return 0;
2583 }
2584
2585 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2586 {
2587 struct drm_info_node *node = (struct drm_info_node *) m->private;
2588 struct drm_device *dev = node->minor->dev;
2589 struct radeon_device *rdev = dev->dev_private;
2590 uint32_t rdp, wdp;
2591 unsigned count, i, j;
2592
2593 radeon_ring_free_size(rdev);
2594 rdp = RREG32(RADEON_CP_RB_RPTR);
2595 wdp = RREG32(RADEON_CP_RB_WPTR);
2596 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2597 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2598 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2599 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2600 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2601 seq_printf(m, "%u dwords in ring\n", count);
2602 for (j = 0; j <= count; j++) {
2603 i = (rdp + j) & rdev->cp.ptr_mask;
2604 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2605 }
2606 return 0;
2607 }
2608
2609
2610 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2611 {
2612 struct drm_info_node *node = (struct drm_info_node *) m->private;
2613 struct drm_device *dev = node->minor->dev;
2614 struct radeon_device *rdev = dev->dev_private;
2615 uint32_t csq_stat, csq2_stat, tmp;
2616 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2617 unsigned i;
2618
2619 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2620 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2621 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2622 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2623 r_rptr = (csq_stat >> 0) & 0x3ff;
2624 r_wptr = (csq_stat >> 10) & 0x3ff;
2625 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2626 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2627 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2628 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2629 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2630 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2631 seq_printf(m, "Ring rptr %u\n", r_rptr);
2632 seq_printf(m, "Ring wptr %u\n", r_wptr);
2633 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2634 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2635 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2636 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2637 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2638 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2639 seq_printf(m, "Ring fifo:\n");
2640 for (i = 0; i < 256; i++) {
2641 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2642 tmp = RREG32(RADEON_CP_CSQ_DATA);
2643 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2644 }
2645 seq_printf(m, "Indirect1 fifo:\n");
2646 for (i = 256; i <= 512; i++) {
2647 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2648 tmp = RREG32(RADEON_CP_CSQ_DATA);
2649 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2650 }
2651 seq_printf(m, "Indirect2 fifo:\n");
2652 for (i = 640; i < ib1_wptr; i++) {
2653 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2654 tmp = RREG32(RADEON_CP_CSQ_DATA);
2655 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2656 }
2657 return 0;
2658 }
2659
2660 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2661 {
2662 struct drm_info_node *node = (struct drm_info_node *) m->private;
2663 struct drm_device *dev = node->minor->dev;
2664 struct radeon_device *rdev = dev->dev_private;
2665 uint32_t tmp;
2666
2667 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2668 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2669 tmp = RREG32(RADEON_MC_FB_LOCATION);
2670 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2671 tmp = RREG32(RADEON_BUS_CNTL);
2672 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2673 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2674 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2675 tmp = RREG32(RADEON_AGP_BASE);
2676 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2677 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2678 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2679 tmp = RREG32(0x01D0);
2680 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2681 tmp = RREG32(RADEON_AIC_LO_ADDR);
2682 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2683 tmp = RREG32(RADEON_AIC_HI_ADDR);
2684 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2685 tmp = RREG32(0x01E4);
2686 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2687 return 0;
2688 }
2689
2690 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2691 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2692 };
2693
2694 static struct drm_info_list r100_debugfs_cp_list[] = {
2695 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2696 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2697 };
2698
2699 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2700 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2701 };
2702 #endif
2703
2704 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2705 {
2706 #if defined(CONFIG_DEBUG_FS)
2707 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2708 #else
2709 return 0;
2710 #endif
2711 }
2712
2713 int r100_debugfs_cp_init(struct radeon_device *rdev)
2714 {
2715 #if defined(CONFIG_DEBUG_FS)
2716 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2717 #else
2718 return 0;
2719 #endif
2720 }
2721
2722 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2723 {
2724 #if defined(CONFIG_DEBUG_FS)
2725 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2726 #else
2727 return 0;
2728 #endif
2729 }
2730
2731 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2732 uint32_t tiling_flags, uint32_t pitch,
2733 uint32_t offset, uint32_t obj_size)
2734 {
2735 int surf_index = reg * 16;
2736 int flags = 0;
2737
2738 if (rdev->family <= CHIP_RS200) {
2739 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2740 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2741 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2742 if (tiling_flags & RADEON_TILING_MACRO)
2743 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2744 } else if (rdev->family <= CHIP_RV280) {
2745 if (tiling_flags & (RADEON_TILING_MACRO))
2746 flags |= R200_SURF_TILE_COLOR_MACRO;
2747 if (tiling_flags & RADEON_TILING_MICRO)
2748 flags |= R200_SURF_TILE_COLOR_MICRO;
2749 } else {
2750 if (tiling_flags & RADEON_TILING_MACRO)
2751 flags |= R300_SURF_TILE_MACRO;
2752 if (tiling_flags & RADEON_TILING_MICRO)
2753 flags |= R300_SURF_TILE_MICRO;
2754 }
2755
2756 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2757 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2758 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2759 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2760
2761 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2762 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2763 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2764 if (ASIC_IS_RN50(rdev))
2765 pitch /= 16;
2766 }
2767
2768 /* r100/r200 divide by 16 */
2769 if (rdev->family < CHIP_R300)
2770 flags |= pitch / 16;
2771 else
2772 flags |= pitch / 8;
2773
2774
2775 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2776 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2777 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2778 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2779 return 0;
2780 }
2781
2782 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2783 {
2784 int surf_index = reg * 16;
2785 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2786 }
2787
2788 void r100_bandwidth_update(struct radeon_device *rdev)
2789 {
2790 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2791 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2792 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2793 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2794 fixed20_12 memtcas_ff[8] = {
2795 dfixed_init(1),
2796 dfixed_init(2),
2797 dfixed_init(3),
2798 dfixed_init(0),
2799 dfixed_init_half(1),
2800 dfixed_init_half(2),
2801 dfixed_init(0),
2802 };
2803 fixed20_12 memtcas_rs480_ff[8] = {
2804 dfixed_init(0),
2805 dfixed_init(1),
2806 dfixed_init(2),
2807 dfixed_init(3),
2808 dfixed_init(0),
2809 dfixed_init_half(1),
2810 dfixed_init_half(2),
2811 dfixed_init_half(3),
2812 };
2813 fixed20_12 memtcas2_ff[8] = {
2814 dfixed_init(0),
2815 dfixed_init(1),
2816 dfixed_init(2),
2817 dfixed_init(3),
2818 dfixed_init(4),
2819 dfixed_init(5),
2820 dfixed_init(6),
2821 dfixed_init(7),
2822 };
2823 fixed20_12 memtrbs[8] = {
2824 dfixed_init(1),
2825 dfixed_init_half(1),
2826 dfixed_init(2),
2827 dfixed_init_half(2),
2828 dfixed_init(3),
2829 dfixed_init_half(3),
2830 dfixed_init(4),
2831 dfixed_init_half(4)
2832 };
2833 fixed20_12 memtrbs_r4xx[8] = {
2834 dfixed_init(4),
2835 dfixed_init(5),
2836 dfixed_init(6),
2837 dfixed_init(7),
2838 dfixed_init(8),
2839 dfixed_init(9),
2840 dfixed_init(10),
2841 dfixed_init(11)
2842 };
2843 fixed20_12 min_mem_eff;
2844 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2845 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2846 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2847 disp_drain_rate2, read_return_rate;
2848 fixed20_12 time_disp1_drop_priority;
2849 int c;
2850 int cur_size = 16; /* in octawords */
2851 int critical_point = 0, critical_point2;
2852 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2853 int stop_req, max_stop_req;
2854 struct drm_display_mode *mode1 = NULL;
2855 struct drm_display_mode *mode2 = NULL;
2856 uint32_t pixel_bytes1 = 0;
2857 uint32_t pixel_bytes2 = 0;
2858
2859 radeon_update_display_priority(rdev);
2860
2861 if (rdev->mode_info.crtcs[0]->base.enabled) {
2862 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2863 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2864 }
2865 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2866 if (rdev->mode_info.crtcs[1]->base.enabled) {
2867 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2868 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2869 }
2870 }
2871
2872 min_mem_eff.full = dfixed_const_8(0);
2873 /* get modes */
2874 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2875 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2876 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2877 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2878 /* check crtc enables */
2879 if (mode2)
2880 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2881 if (mode1)
2882 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2883 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2884 }
2885
2886 /*
2887 * determine is there is enough bw for current mode
2888 */
2889 sclk_ff = rdev->pm.sclk;
2890 mclk_ff = rdev->pm.mclk;
2891
2892 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2893 temp_ff.full = dfixed_const(temp);
2894 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2895
2896 pix_clk.full = 0;
2897 pix_clk2.full = 0;
2898 peak_disp_bw.full = 0;
2899 if (mode1) {
2900 temp_ff.full = dfixed_const(1000);
2901 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2902 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2903 temp_ff.full = dfixed_const(pixel_bytes1);
2904 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2905 }
2906 if (mode2) {
2907 temp_ff.full = dfixed_const(1000);
2908 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2909 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2910 temp_ff.full = dfixed_const(pixel_bytes2);
2911 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2912 }
2913
2914 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2915 if (peak_disp_bw.full >= mem_bw.full) {
2916 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2917 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2918 }
2919
2920 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2921 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2922 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2923 mem_trcd = ((temp >> 2) & 0x3) + 1;
2924 mem_trp = ((temp & 0x3)) + 1;
2925 mem_tras = ((temp & 0x70) >> 4) + 1;
2926 } else if (rdev->family == CHIP_R300 ||
2927 rdev->family == CHIP_R350) { /* r300, r350 */
2928 mem_trcd = (temp & 0x7) + 1;
2929 mem_trp = ((temp >> 8) & 0x7) + 1;
2930 mem_tras = ((temp >> 11) & 0xf) + 4;
2931 } else if (rdev->family == CHIP_RV350 ||
2932 rdev->family <= CHIP_RV380) {
2933 /* rv3x0 */
2934 mem_trcd = (temp & 0x7) + 3;
2935 mem_trp = ((temp >> 8) & 0x7) + 3;
2936 mem_tras = ((temp >> 11) & 0xf) + 6;
2937 } else if (rdev->family == CHIP_R420 ||
2938 rdev->family == CHIP_R423 ||
2939 rdev->family == CHIP_RV410) {
2940 /* r4xx */
2941 mem_trcd = (temp & 0xf) + 3;
2942 if (mem_trcd > 15)
2943 mem_trcd = 15;
2944 mem_trp = ((temp >> 8) & 0xf) + 3;
2945 if (mem_trp > 15)
2946 mem_trp = 15;
2947 mem_tras = ((temp >> 12) & 0x1f) + 6;
2948 if (mem_tras > 31)
2949 mem_tras = 31;
2950 } else { /* RV200, R200 */
2951 mem_trcd = (temp & 0x7) + 1;
2952 mem_trp = ((temp >> 8) & 0x7) + 1;
2953 mem_tras = ((temp >> 12) & 0xf) + 4;
2954 }
2955 /* convert to FF */
2956 trcd_ff.full = dfixed_const(mem_trcd);
2957 trp_ff.full = dfixed_const(mem_trp);
2958 tras_ff.full = dfixed_const(mem_tras);
2959
2960 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2961 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2962 data = (temp & (7 << 20)) >> 20;
2963 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2964 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2965 tcas_ff = memtcas_rs480_ff[data];
2966 else
2967 tcas_ff = memtcas_ff[data];
2968 } else
2969 tcas_ff = memtcas2_ff[data];
2970
2971 if (rdev->family == CHIP_RS400 ||
2972 rdev->family == CHIP_RS480) {
2973 /* extra cas latency stored in bits 23-25 0-4 clocks */
2974 data = (temp >> 23) & 0x7;
2975 if (data < 5)
2976 tcas_ff.full += dfixed_const(data);
2977 }
2978
2979 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2980 /* on the R300, Tcas is included in Trbs.
2981 */
2982 temp = RREG32(RADEON_MEM_CNTL);
2983 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2984 if (data == 1) {
2985 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2986 temp = RREG32(R300_MC_IND_INDEX);
2987 temp &= ~R300_MC_IND_ADDR_MASK;
2988 temp |= R300_MC_READ_CNTL_CD_mcind;
2989 WREG32(R300_MC_IND_INDEX, temp);
2990 temp = RREG32(R300_MC_IND_DATA);
2991 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2992 } else {
2993 temp = RREG32(R300_MC_READ_CNTL_AB);
2994 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2995 }
2996 } else {
2997 temp = RREG32(R300_MC_READ_CNTL_AB);
2998 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2999 }
3000 if (rdev->family == CHIP_RV410 ||
3001 rdev->family == CHIP_R420 ||
3002 rdev->family == CHIP_R423)
3003 trbs_ff = memtrbs_r4xx[data];
3004 else
3005 trbs_ff = memtrbs[data];
3006 tcas_ff.full += trbs_ff.full;
3007 }
3008
3009 sclk_eff_ff.full = sclk_ff.full;
3010
3011 if (rdev->flags & RADEON_IS_AGP) {
3012 fixed20_12 agpmode_ff;
3013 agpmode_ff.full = dfixed_const(radeon_agpmode);
3014 temp_ff.full = dfixed_const_666(16);
3015 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3016 }
3017 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3018
3019 if (ASIC_IS_R300(rdev)) {
3020 sclk_delay_ff.full = dfixed_const(250);
3021 } else {
3022 if ((rdev->family == CHIP_RV100) ||
3023 rdev->flags & RADEON_IS_IGP) {
3024 if (rdev->mc.vram_is_ddr)
3025 sclk_delay_ff.full = dfixed_const(41);
3026 else
3027 sclk_delay_ff.full = dfixed_const(33);
3028 } else {
3029 if (rdev->mc.vram_width == 128)
3030 sclk_delay_ff.full = dfixed_const(57);
3031 else
3032 sclk_delay_ff.full = dfixed_const(41);
3033 }
3034 }
3035
3036 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3037
3038 if (rdev->mc.vram_is_ddr) {
3039 if (rdev->mc.vram_width == 32) {
3040 k1.full = dfixed_const(40);
3041 c = 3;
3042 } else {
3043 k1.full = dfixed_const(20);
3044 c = 1;
3045 }
3046 } else {
3047 k1.full = dfixed_const(40);
3048 c = 3;
3049 }
3050
3051 temp_ff.full = dfixed_const(2);
3052 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3053 temp_ff.full = dfixed_const(c);
3054 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3055 temp_ff.full = dfixed_const(4);
3056 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3057 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3058 mc_latency_mclk.full += k1.full;
3059
3060 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3061 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3062
3063 /*
3064 HW cursor time assuming worst case of full size colour cursor.
3065 */
3066 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3067 temp_ff.full += trcd_ff.full;
3068 if (temp_ff.full < tras_ff.full)
3069 temp_ff.full = tras_ff.full;
3070 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3071
3072 temp_ff.full = dfixed_const(cur_size);
3073 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3074 /*
3075 Find the total latency for the display data.
3076 */
3077 disp_latency_overhead.full = dfixed_const(8);
3078 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3079 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3080 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3081
3082 if (mc_latency_mclk.full > mc_latency_sclk.full)
3083 disp_latency.full = mc_latency_mclk.full;
3084 else
3085 disp_latency.full = mc_latency_sclk.full;
3086
3087 /* setup Max GRPH_STOP_REQ default value */
3088 if (ASIC_IS_RV100(rdev))
3089 max_stop_req = 0x5c;
3090 else
3091 max_stop_req = 0x7c;
3092
3093 if (mode1) {
3094 /* CRTC1
3095 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3096 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3097 */
3098 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3099
3100 if (stop_req > max_stop_req)
3101 stop_req = max_stop_req;
3102
3103 /*
3104 Find the drain rate of the display buffer.
3105 */
3106 temp_ff.full = dfixed_const((16/pixel_bytes1));
3107 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3108
3109 /*
3110 Find the critical point of the display buffer.
3111 */
3112 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3113 crit_point_ff.full += dfixed_const_half(0);
3114
3115 critical_point = dfixed_trunc(crit_point_ff);
3116
3117 if (rdev->disp_priority == 2) {
3118 critical_point = 0;
3119 }
3120
3121 /*
3122 The critical point should never be above max_stop_req-4. Setting
3123 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3124 */
3125 if (max_stop_req - critical_point < 4)
3126 critical_point = 0;
3127
3128 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3129 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3130 critical_point = 0x10;
3131 }
3132
3133 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3134 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3135 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3136 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3137 if ((rdev->family == CHIP_R350) &&
3138 (stop_req > 0x15)) {
3139 stop_req -= 0x10;
3140 }
3141 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3142 temp |= RADEON_GRPH_BUFFER_SIZE;
3143 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3144 RADEON_GRPH_CRITICAL_AT_SOF |
3145 RADEON_GRPH_STOP_CNTL);
3146 /*
3147 Write the result into the register.
3148 */
3149 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3150 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3151
3152 #if 0
3153 if ((rdev->family == CHIP_RS400) ||
3154 (rdev->family == CHIP_RS480)) {
3155 /* attempt to program RS400 disp regs correctly ??? */
3156 temp = RREG32(RS400_DISP1_REG_CNTL);
3157 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3158 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3159 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3160 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3161 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3162 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3163 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3164 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3165 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3166 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3167 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3168 }
3169 #endif
3170
3171 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3172 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3173 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3174 }
3175
3176 if (mode2) {
3177 u32 grph2_cntl;
3178 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3179
3180 if (stop_req > max_stop_req)
3181 stop_req = max_stop_req;
3182
3183 /*
3184 Find the drain rate of the display buffer.
3185 */
3186 temp_ff.full = dfixed_const((16/pixel_bytes2));
3187 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3188
3189 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3190 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3191 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3192 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3193 if ((rdev->family == CHIP_R350) &&
3194 (stop_req > 0x15)) {
3195 stop_req -= 0x10;
3196 }
3197 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3198 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3199 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3200 RADEON_GRPH_CRITICAL_AT_SOF |
3201 RADEON_GRPH_STOP_CNTL);
3202
3203 if ((rdev->family == CHIP_RS100) ||
3204 (rdev->family == CHIP_RS200))
3205 critical_point2 = 0;
3206 else {
3207 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3208 temp_ff.full = dfixed_const(temp);
3209 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3210 if (sclk_ff.full < temp_ff.full)
3211 temp_ff.full = sclk_ff.full;
3212
3213 read_return_rate.full = temp_ff.full;
3214
3215 if (mode1) {
3216 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3217 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3218 } else {
3219 time_disp1_drop_priority.full = 0;
3220 }
3221 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3222 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3223 crit_point_ff.full += dfixed_const_half(0);
3224
3225 critical_point2 = dfixed_trunc(crit_point_ff);
3226
3227 if (rdev->disp_priority == 2) {
3228 critical_point2 = 0;
3229 }
3230
3231 if (max_stop_req - critical_point2 < 4)
3232 critical_point2 = 0;
3233
3234 }
3235
3236 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3237 /* some R300 cards have problem with this set to 0 */
3238 critical_point2 = 0x10;
3239 }
3240
3241 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3242 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3243
3244 if ((rdev->family == CHIP_RS400) ||
3245 (rdev->family == CHIP_RS480)) {
3246 #if 0
3247 /* attempt to program RS400 disp2 regs correctly ??? */
3248 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3249 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3250 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3251 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3252 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3253 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3254 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3255 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3256 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3257 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3258 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3259 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3260 #endif
3261 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3262 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3263 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3264 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3265 }
3266
3267 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3268 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3269 }
3270 }
3271
3272 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3273 {
3274 DRM_ERROR("pitch %d\n", t->pitch);
3275 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3276 DRM_ERROR("width %d\n", t->width);
3277 DRM_ERROR("width_11 %d\n", t->width_11);
3278 DRM_ERROR("height %d\n", t->height);
3279 DRM_ERROR("height_11 %d\n", t->height_11);
3280 DRM_ERROR("num levels %d\n", t->num_levels);
3281 DRM_ERROR("depth %d\n", t->txdepth);
3282 DRM_ERROR("bpp %d\n", t->cpp);
3283 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3284 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3285 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3286 DRM_ERROR("compress format %d\n", t->compress_format);
3287 }
3288
3289 static int r100_track_compress_size(int compress_format, int w, int h)
3290 {
3291 int block_width, block_height, block_bytes;
3292 int wblocks, hblocks;
3293 int min_wblocks;
3294 int sz;
3295
3296 block_width = 4;
3297 block_height = 4;
3298
3299 switch (compress_format) {
3300 case R100_TRACK_COMP_DXT1:
3301 block_bytes = 8;
3302 min_wblocks = 4;
3303 break;
3304 default:
3305 case R100_TRACK_COMP_DXT35:
3306 block_bytes = 16;
3307 min_wblocks = 2;
3308 break;
3309 }
3310
3311 hblocks = (h + block_height - 1) / block_height;
3312 wblocks = (w + block_width - 1) / block_width;
3313 if (wblocks < min_wblocks)
3314 wblocks = min_wblocks;
3315 sz = wblocks * hblocks * block_bytes;
3316 return sz;
3317 }
3318
3319 static int r100_cs_track_cube(struct radeon_device *rdev,
3320 struct r100_cs_track *track, unsigned idx)
3321 {
3322 unsigned face, w, h;
3323 struct radeon_bo *cube_robj;
3324 unsigned long size;
3325 unsigned compress_format = track->textures[idx].compress_format;
3326
3327 for (face = 0; face < 5; face++) {
3328 cube_robj = track->textures[idx].cube_info[face].robj;
3329 w = track->textures[idx].cube_info[face].width;
3330 h = track->textures[idx].cube_info[face].height;
3331
3332 if (compress_format) {
3333 size = r100_track_compress_size(compress_format, w, h);
3334 } else
3335 size = w * h;
3336 size *= track->textures[idx].cpp;
3337
3338 size += track->textures[idx].cube_info[face].offset;
3339
3340 if (size > radeon_bo_size(cube_robj)) {
3341 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3342 size, radeon_bo_size(cube_robj));
3343 r100_cs_track_texture_print(&track->textures[idx]);
3344 return -1;
3345 }
3346 }
3347 return 0;
3348 }
3349
3350 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3351 struct r100_cs_track *track)
3352 {
3353 struct radeon_bo *robj;
3354 unsigned long size;
3355 unsigned u, i, w, h, d;
3356 int ret;
3357
3358 for (u = 0; u < track->num_texture; u++) {
3359 if (!track->textures[u].enabled)
3360 continue;
3361 if (track->textures[u].lookup_disable)
3362 continue;
3363 robj = track->textures[u].robj;
3364 if (robj == NULL) {
3365 DRM_ERROR("No texture bound to unit %u\n", u);
3366 return -EINVAL;
3367 }
3368 size = 0;
3369 for (i = 0; i <= track->textures[u].num_levels; i++) {
3370 if (track->textures[u].use_pitch) {
3371 if (rdev->family < CHIP_R300)
3372 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3373 else
3374 w = track->textures[u].pitch / (1 << i);
3375 } else {
3376 w = track->textures[u].width;
3377 if (rdev->family >= CHIP_RV515)
3378 w |= track->textures[u].width_11;
3379 w = w / (1 << i);
3380 if (track->textures[u].roundup_w)
3381 w = roundup_pow_of_two(w);
3382 }
3383 h = track->textures[u].height;
3384 if (rdev->family >= CHIP_RV515)
3385 h |= track->textures[u].height_11;
3386 h = h / (1 << i);
3387 if (track->textures[u].roundup_h)
3388 h = roundup_pow_of_two(h);
3389 if (track->textures[u].tex_coord_type == 1) {
3390 d = (1 << track->textures[u].txdepth) / (1 << i);
3391 if (!d)
3392 d = 1;
3393 } else {
3394 d = 1;
3395 }
3396 if (track->textures[u].compress_format) {
3397
3398 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3399 /* compressed textures are block based */
3400 } else
3401 size += w * h * d;
3402 }
3403 size *= track->textures[u].cpp;
3404
3405 switch (track->textures[u].tex_coord_type) {
3406 case 0:
3407 case 1:
3408 break;
3409 case 2:
3410 if (track->separate_cube) {
3411 ret = r100_cs_track_cube(rdev, track, u);
3412 if (ret)
3413 return ret;
3414 } else
3415 size *= 6;
3416 break;
3417 default:
3418 DRM_ERROR("Invalid texture coordinate type %u for unit "
3419 "%u\n", track->textures[u].tex_coord_type, u);
3420 return -EINVAL;
3421 }
3422 if (size > radeon_bo_size(robj)) {
3423 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3424 "%lu\n", u, size, radeon_bo_size(robj));
3425 r100_cs_track_texture_print(&track->textures[u]);
3426 return -EINVAL;
3427 }
3428 }
3429 return 0;
3430 }
3431
3432 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3433 {
3434 unsigned i;
3435 unsigned long size;
3436 unsigned prim_walk;
3437 unsigned nverts;
3438 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3439
3440 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3441 !track->blend_read_enable)
3442 num_cb = 0;
3443
3444 for (i = 0; i < num_cb; i++) {
3445 if (track->cb[i].robj == NULL) {
3446 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3447 return -EINVAL;
3448 }
3449 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3450 size += track->cb[i].offset;
3451 if (size > radeon_bo_size(track->cb[i].robj)) {
3452 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3453 "(need %lu have %lu) !\n", i, size,
3454 radeon_bo_size(track->cb[i].robj));
3455 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3456 i, track->cb[i].pitch, track->cb[i].cpp,
3457 track->cb[i].offset, track->maxy);
3458 return -EINVAL;
3459 }
3460 }
3461 track->cb_dirty = false;
3462
3463 if (track->zb_dirty && track->z_enabled) {
3464 if (track->zb.robj == NULL) {
3465 DRM_ERROR("[drm] No buffer for z buffer !\n");
3466 return -EINVAL;
3467 }
3468 size = track->zb.pitch * track->zb.cpp * track->maxy;
3469 size += track->zb.offset;
3470 if (size > radeon_bo_size(track->zb.robj)) {
3471 DRM_ERROR("[drm] Buffer too small for z buffer "
3472 "(need %lu have %lu) !\n", size,
3473 radeon_bo_size(track->zb.robj));
3474 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3475 track->zb.pitch, track->zb.cpp,
3476 track->zb.offset, track->maxy);
3477 return -EINVAL;
3478 }
3479 }
3480 track->zb_dirty = false;
3481
3482 if (track->aa_dirty && track->aaresolve) {
3483 if (track->aa.robj == NULL) {
3484 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3485 return -EINVAL;
3486 }
3487 /* I believe the format comes from colorbuffer0. */
3488 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3489 size += track->aa.offset;
3490 if (size > radeon_bo_size(track->aa.robj)) {
3491 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3492 "(need %lu have %lu) !\n", i, size,
3493 radeon_bo_size(track->aa.robj));
3494 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3495 i, track->aa.pitch, track->cb[0].cpp,
3496 track->aa.offset, track->maxy);
3497 return -EINVAL;
3498 }
3499 }
3500 track->aa_dirty = false;
3501
3502 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3503 if (track->vap_vf_cntl & (1 << 14)) {
3504 nverts = track->vap_alt_nverts;
3505 } else {
3506 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3507 }
3508 switch (prim_walk) {
3509 case 1:
3510 for (i = 0; i < track->num_arrays; i++) {
3511 size = track->arrays[i].esize * track->max_indx * 4;
3512 if (track->arrays[i].robj == NULL) {
3513 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3514 "bound\n", prim_walk, i);
3515 return -EINVAL;
3516 }
3517 if (size > radeon_bo_size(track->arrays[i].robj)) {
3518 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3519 "need %lu dwords have %lu dwords\n",
3520 prim_walk, i, size >> 2,
3521 radeon_bo_size(track->arrays[i].robj)
3522 >> 2);
3523 DRM_ERROR("Max indices %u\n", track->max_indx);
3524 return -EINVAL;
3525 }
3526 }
3527 break;
3528 case 2:
3529 for (i = 0; i < track->num_arrays; i++) {
3530 size = track->arrays[i].esize * (nverts - 1) * 4;
3531 if (track->arrays[i].robj == NULL) {
3532 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3533 "bound\n", prim_walk, i);
3534 return -EINVAL;
3535 }
3536 if (size > radeon_bo_size(track->arrays[i].robj)) {
3537 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3538 "need %lu dwords have %lu dwords\n",
3539 prim_walk, i, size >> 2,
3540 radeon_bo_size(track->arrays[i].robj)
3541 >> 2);
3542 return -EINVAL;
3543 }
3544 }
3545 break;
3546 case 3:
3547 size = track->vtx_size * nverts;
3548 if (size != track->immd_dwords) {
3549 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3550 track->immd_dwords, size);
3551 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3552 nverts, track->vtx_size);
3553 return -EINVAL;
3554 }
3555 break;
3556 default:
3557 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3558 prim_walk);
3559 return -EINVAL;
3560 }
3561
3562 if (track->tex_dirty) {
3563 track->tex_dirty = false;
3564 return r100_cs_track_texture_check(rdev, track);
3565 }
3566 return 0;
3567 }
3568
3569 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3570 {
3571 unsigned i, face;
3572
3573 track->cb_dirty = true;
3574 track->zb_dirty = true;
3575 track->tex_dirty = true;
3576 track->aa_dirty = true;
3577
3578 if (rdev->family < CHIP_R300) {
3579 track->num_cb = 1;
3580 if (rdev->family <= CHIP_RS200)
3581 track->num_texture = 3;
3582 else
3583 track->num_texture = 6;
3584 track->maxy = 2048;
3585 track->separate_cube = 1;
3586 } else {
3587 track->num_cb = 4;
3588 track->num_texture = 16;
3589 track->maxy = 4096;
3590 track->separate_cube = 0;
3591 track->aaresolve = false;
3592 track->aa.robj = NULL;
3593 }
3594
3595 for (i = 0; i < track->num_cb; i++) {
3596 track->cb[i].robj = NULL;
3597 track->cb[i].pitch = 8192;
3598 track->cb[i].cpp = 16;
3599 track->cb[i].offset = 0;
3600 }
3601 track->z_enabled = true;
3602 track->zb.robj = NULL;
3603 track->zb.pitch = 8192;
3604 track->zb.cpp = 4;
3605 track->zb.offset = 0;
3606 track->vtx_size = 0x7F;
3607 track->immd_dwords = 0xFFFFFFFFUL;
3608 track->num_arrays = 11;
3609 track->max_indx = 0x00FFFFFFUL;
3610 for (i = 0; i < track->num_arrays; i++) {
3611 track->arrays[i].robj = NULL;
3612 track->arrays[i].esize = 0x7F;
3613 }
3614 for (i = 0; i < track->num_texture; i++) {
3615 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3616 track->textures[i].pitch = 16536;
3617 track->textures[i].width = 16536;
3618 track->textures[i].height = 16536;
3619 track->textures[i].width_11 = 1 << 11;
3620 track->textures[i].height_11 = 1 << 11;
3621 track->textures[i].num_levels = 12;
3622 if (rdev->family <= CHIP_RS200) {
3623 track->textures[i].tex_coord_type = 0;
3624 track->textures[i].txdepth = 0;
3625 } else {
3626 track->textures[i].txdepth = 16;
3627 track->textures[i].tex_coord_type = 1;
3628 }
3629 track->textures[i].cpp = 64;
3630 track->textures[i].robj = NULL;
3631 /* CS IB emission code makes sure texture unit are disabled */
3632 track->textures[i].enabled = false;
3633 track->textures[i].lookup_disable = false;
3634 track->textures[i].roundup_w = true;
3635 track->textures[i].roundup_h = true;
3636 if (track->separate_cube)
3637 for (face = 0; face < 5; face++) {
3638 track->textures[i].cube_info[face].robj = NULL;
3639 track->textures[i].cube_info[face].width = 16536;
3640 track->textures[i].cube_info[face].height = 16536;
3641 track->textures[i].cube_info[face].offset = 0;
3642 }
3643 }
3644 }
3645
3646 int r100_ring_test(struct radeon_device *rdev)
3647 {
3648 uint32_t scratch;
3649 uint32_t tmp = 0;
3650 unsigned i;
3651 int r;
3652
3653 r = radeon_scratch_get(rdev, &scratch);
3654 if (r) {
3655 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3656 return r;
3657 }
3658 WREG32(scratch, 0xCAFEDEAD);
3659 r = radeon_ring_lock(rdev, 2);
3660 if (r) {
3661 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3662 radeon_scratch_free(rdev, scratch);
3663 return r;
3664 }
3665 radeon_ring_write(rdev, PACKET0(scratch, 0));
3666 radeon_ring_write(rdev, 0xDEADBEEF);
3667 radeon_ring_unlock_commit(rdev);
3668 for (i = 0; i < rdev->usec_timeout; i++) {
3669 tmp = RREG32(scratch);
3670 if (tmp == 0xDEADBEEF) {
3671 break;
3672 }
3673 DRM_UDELAY(1);
3674 }
3675 if (i < rdev->usec_timeout) {
3676 DRM_INFO("ring test succeeded in %d usecs\n", i);
3677 } else {
3678 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3679 scratch, tmp);
3680 r = -EINVAL;
3681 }
3682 radeon_scratch_free(rdev, scratch);
3683 return r;
3684 }
3685
3686 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3687 {
3688 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3689 radeon_ring_write(rdev, ib->gpu_addr);
3690 radeon_ring_write(rdev, ib->length_dw);
3691 }
3692
3693 int r100_ib_test(struct radeon_device *rdev)
3694 {
3695 struct radeon_ib *ib;
3696 uint32_t scratch;
3697 uint32_t tmp = 0;
3698 unsigned i;
3699 int r;
3700
3701 r = radeon_scratch_get(rdev, &scratch);
3702 if (r) {
3703 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3704 return r;
3705 }
3706 WREG32(scratch, 0xCAFEDEAD);
3707 r = radeon_ib_get(rdev, &ib);
3708 if (r) {
3709 return r;
3710 }
3711 ib->ptr[0] = PACKET0(scratch, 0);
3712 ib->ptr[1] = 0xDEADBEEF;
3713 ib->ptr[2] = PACKET2(0);
3714 ib->ptr[3] = PACKET2(0);
3715 ib->ptr[4] = PACKET2(0);
3716 ib->ptr[5] = PACKET2(0);
3717 ib->ptr[6] = PACKET2(0);
3718 ib->ptr[7] = PACKET2(0);
3719 ib->length_dw = 8;
3720 r = radeon_ib_schedule(rdev, ib);
3721 if (r) {
3722 radeon_scratch_free(rdev, scratch);
3723 radeon_ib_free(rdev, &ib);
3724 return r;
3725 }
3726 r = radeon_fence_wait(ib->fence, false);
3727 if (r) {
3728 return r;
3729 }
3730 for (i = 0; i < rdev->usec_timeout; i++) {
3731 tmp = RREG32(scratch);
3732 if (tmp == 0xDEADBEEF) {
3733 break;
3734 }
3735 DRM_UDELAY(1);
3736 }
3737 if (i < rdev->usec_timeout) {
3738 DRM_INFO("ib test succeeded in %u usecs\n", i);
3739 } else {
3740 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3741 scratch, tmp);
3742 r = -EINVAL;
3743 }
3744 radeon_scratch_free(rdev, scratch);
3745 radeon_ib_free(rdev, &ib);
3746 return r;
3747 }
3748
3749 void r100_ib_fini(struct radeon_device *rdev)
3750 {
3751 radeon_ib_pool_fini(rdev);
3752 }
3753
3754 int r100_ib_init(struct radeon_device *rdev)
3755 {
3756 int r;
3757
3758 r = radeon_ib_pool_init(rdev);
3759 if (r) {
3760 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3761 r100_ib_fini(rdev);
3762 return r;
3763 }
3764 r = r100_ib_test(rdev);
3765 if (r) {
3766 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3767 r100_ib_fini(rdev);
3768 return r;
3769 }
3770 return 0;
3771 }
3772
3773 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3774 {
3775 /* Shutdown CP we shouldn't need to do that but better be safe than
3776 * sorry
3777 */
3778 rdev->cp.ready = false;
3779 WREG32(R_000740_CP_CSQ_CNTL, 0);
3780
3781 /* Save few CRTC registers */
3782 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3783 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3784 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3785 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3786 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3787 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3788 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3789 }
3790
3791 /* Disable VGA aperture access */
3792 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3793 /* Disable cursor, overlay, crtc */
3794 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3795 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3796 S_000054_CRTC_DISPLAY_DIS(1));
3797 WREG32(R_000050_CRTC_GEN_CNTL,
3798 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3799 S_000050_CRTC_DISP_REQ_EN_B(1));
3800 WREG32(R_000420_OV0_SCALE_CNTL,
3801 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3802 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3803 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3804 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3805 S_000360_CUR2_LOCK(1));
3806 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3807 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3808 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3809 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3810 WREG32(R_000360_CUR2_OFFSET,
3811 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3812 }
3813 }
3814
3815 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3816 {
3817 /* Update base address for crtc */
3818 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3819 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3820 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3821 }
3822 /* Restore CRTC registers */
3823 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3824 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3825 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3826 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3827 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3828 }
3829 }
3830
3831 void r100_vga_render_disable(struct radeon_device *rdev)
3832 {
3833 u32 tmp;
3834
3835 tmp = RREG8(R_0003C2_GENMO_WT);
3836 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3837 }
3838
3839 static void r100_debugfs(struct radeon_device *rdev)
3840 {
3841 int r;
3842
3843 r = r100_debugfs_mc_info_init(rdev);
3844 if (r)
3845 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3846 }
3847
3848 static void r100_mc_program(struct radeon_device *rdev)
3849 {
3850 struct r100_mc_save save;
3851
3852 /* Stops all mc clients */
3853 r100_mc_stop(rdev, &save);
3854 if (rdev->flags & RADEON_IS_AGP) {
3855 WREG32(R_00014C_MC_AGP_LOCATION,
3856 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3857 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3858 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3859 if (rdev->family > CHIP_RV200)
3860 WREG32(R_00015C_AGP_BASE_2,
3861 upper_32_bits(rdev->mc.agp_base) & 0xff);
3862 } else {
3863 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3864 WREG32(R_000170_AGP_BASE, 0);
3865 if (rdev->family > CHIP_RV200)
3866 WREG32(R_00015C_AGP_BASE_2, 0);
3867 }
3868 /* Wait for mc idle */
3869 if (r100_mc_wait_for_idle(rdev))
3870 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3871 /* Program MC, should be a 32bits limited address space */
3872 WREG32(R_000148_MC_FB_LOCATION,
3873 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3874 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3875 r100_mc_resume(rdev, &save);
3876 }
3877
3878 void r100_clock_startup(struct radeon_device *rdev)
3879 {
3880 u32 tmp;
3881
3882 if (radeon_dynclks != -1 && radeon_dynclks)
3883 radeon_legacy_set_clock_gating(rdev, 1);
3884 /* We need to force on some of the block */
3885 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3886 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3887 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3888 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3889 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3890 }
3891
3892 static int r100_startup(struct radeon_device *rdev)
3893 {
3894 int r;
3895
3896 /* set common regs */
3897 r100_set_common_regs(rdev);
3898 /* program mc */
3899 r100_mc_program(rdev);
3900 /* Resume clock */
3901 r100_clock_startup(rdev);
3902 /* Initialize GART (initialize after TTM so we can allocate
3903 * memory through TTM but finalize after TTM) */
3904 r100_enable_bm(rdev);
3905 if (rdev->flags & RADEON_IS_PCI) {
3906 r = r100_pci_gart_enable(rdev);
3907 if (r)
3908 return r;
3909 }
3910
3911 /* allocate wb buffer */
3912 r = radeon_wb_init(rdev);
3913 if (r)
3914 return r;
3915
3916 /* Enable IRQ */
3917 r100_irq_set(rdev);
3918 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3919 /* 1M ring buffer */
3920 r = r100_cp_init(rdev, 1024 * 1024);
3921 if (r) {
3922 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3923 return r;
3924 }
3925 r = r100_ib_init(rdev);
3926 if (r) {
3927 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3928 return r;
3929 }
3930 return 0;
3931 }
3932
3933 int r100_resume(struct radeon_device *rdev)
3934 {
3935 /* Make sur GART are not working */
3936 if (rdev->flags & RADEON_IS_PCI)
3937 r100_pci_gart_disable(rdev);
3938 /* Resume clock before doing reset */
3939 r100_clock_startup(rdev);
3940 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3941 if (radeon_asic_reset(rdev)) {
3942 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3943 RREG32(R_000E40_RBBM_STATUS),
3944 RREG32(R_0007C0_CP_STAT));
3945 }
3946 /* post */
3947 radeon_combios_asic_init(rdev->ddev);
3948 /* Resume clock after posting */
3949 r100_clock_startup(rdev);
3950 /* Initialize surface registers */
3951 radeon_surface_init(rdev);
3952 return r100_startup(rdev);
3953 }
3954
3955 int r100_suspend(struct radeon_device *rdev)
3956 {
3957 r100_cp_disable(rdev);
3958 radeon_wb_disable(rdev);
3959 r100_irq_disable(rdev);
3960 if (rdev->flags & RADEON_IS_PCI)
3961 r100_pci_gart_disable(rdev);
3962 return 0;
3963 }
3964
3965 void r100_fini(struct radeon_device *rdev)
3966 {
3967 r100_cp_fini(rdev);
3968 radeon_wb_fini(rdev);
3969 r100_ib_fini(rdev);
3970 radeon_gem_fini(rdev);
3971 if (rdev->flags & RADEON_IS_PCI)
3972 r100_pci_gart_fini(rdev);
3973 radeon_agp_fini(rdev);
3974 radeon_irq_kms_fini(rdev);
3975 radeon_fence_driver_fini(rdev);
3976 radeon_bo_fini(rdev);
3977 radeon_atombios_fini(rdev);
3978 kfree(rdev->bios);
3979 rdev->bios = NULL;
3980 }
3981
3982 /*
3983 * Due to how kexec works, it can leave the hw fully initialised when it
3984 * boots the new kernel. However doing our init sequence with the CP and
3985 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3986 * do some quick sanity checks and restore sane values to avoid this
3987 * problem.
3988 */
3989 void r100_restore_sanity(struct radeon_device *rdev)
3990 {
3991 u32 tmp;
3992
3993 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3994 if (tmp) {
3995 WREG32(RADEON_CP_CSQ_CNTL, 0);
3996 }
3997 tmp = RREG32(RADEON_CP_RB_CNTL);
3998 if (tmp) {
3999 WREG32(RADEON_CP_RB_CNTL, 0);
4000 }
4001 tmp = RREG32(RADEON_SCRATCH_UMSK);
4002 if (tmp) {
4003 WREG32(RADEON_SCRATCH_UMSK, 0);
4004 }
4005 }
4006
4007 int r100_init(struct radeon_device *rdev)
4008 {
4009 int r;
4010
4011 /* Register debugfs file specific to this group of asics */
4012 r100_debugfs(rdev);
4013 /* Disable VGA */
4014 r100_vga_render_disable(rdev);
4015 /* Initialize scratch registers */
4016 radeon_scratch_init(rdev);
4017 /* Initialize surface registers */
4018 radeon_surface_init(rdev);
4019 /* sanity check some register to avoid hangs like after kexec */
4020 r100_restore_sanity(rdev);
4021 /* TODO: disable VGA need to use VGA request */
4022 /* BIOS*/
4023 if (!radeon_get_bios(rdev)) {
4024 if (ASIC_IS_AVIVO(rdev))
4025 return -EINVAL;
4026 }
4027 if (rdev->is_atom_bios) {
4028 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4029 return -EINVAL;
4030 } else {
4031 r = radeon_combios_init(rdev);
4032 if (r)
4033 return r;
4034 }
4035 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4036 if (radeon_asic_reset(rdev)) {
4037 dev_warn(rdev->dev,
4038 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4039 RREG32(R_000E40_RBBM_STATUS),
4040 RREG32(R_0007C0_CP_STAT));
4041 }
4042 /* check if cards are posted or not */
4043 if (radeon_boot_test_post_card(rdev) == false)
4044 return -EINVAL;
4045 /* Set asic errata */
4046 r100_errata(rdev);
4047 /* Initialize clocks */
4048 radeon_get_clock_info(rdev->ddev);
4049 /* initialize AGP */
4050 if (rdev->flags & RADEON_IS_AGP) {
4051 r = radeon_agp_init(rdev);
4052 if (r) {
4053 radeon_agp_disable(rdev);
4054 }
4055 }
4056 /* initialize VRAM */
4057 r100_mc_init(rdev);
4058 /* Fence driver */
4059 r = radeon_fence_driver_init(rdev, 1);
4060 if (r)
4061 return r;
4062 r = radeon_irq_kms_init(rdev);
4063 if (r)
4064 return r;
4065 /* Memory manager */
4066 r = radeon_bo_init(rdev);
4067 if (r)
4068 return r;
4069 if (rdev->flags & RADEON_IS_PCI) {
4070 r = r100_pci_gart_init(rdev);
4071 if (r)
4072 return r;
4073 }
4074 r100_set_safe_registers(rdev);
4075 rdev->accel_working = true;
4076 r = r100_startup(rdev);
4077 if (r) {
4078 /* Somethings want wront with the accel init stop accel */
4079 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4080 r100_cp_fini(rdev);
4081 radeon_wb_fini(rdev);
4082 r100_ib_fini(rdev);
4083 radeon_irq_kms_fini(rdev);
4084 if (rdev->flags & RADEON_IS_PCI)
4085 r100_pci_gart_fini(rdev);
4086 rdev->accel_working = false;
4087 }
4088 return 0;
4089 }
4090
4091 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4092 {
4093 if (reg < rdev->rmmio_size)
4094 return readl(((void __iomem *)rdev->rmmio) + reg);
4095 else {
4096 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4097 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4098 }
4099 }
4100
4101 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4102 {
4103 if (reg < rdev->rmmio_size)
4104 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4105 else {
4106 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4107 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4108 }
4109 }
4110
4111 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4112 {
4113 if (reg < rdev->rio_mem_size)
4114 return ioread32(rdev->rio_mem + reg);
4115 else {
4116 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4117 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4118 }
4119 }
4120
4121 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4122 {
4123 if (reg < rdev->rio_mem_size)
4124 iowrite32(v, rdev->rio_mem + reg);
4125 else {
4126 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4127 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4128 }
4129 }
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