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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
45
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
48
49 /* Firmware Names */
50 #define FIRMWARE_R100 "radeon/R100_cp.bin"
51 #define FIRMWARE_R200 "radeon/R200_cp.bin"
52 #define FIRMWARE_R300 "radeon/R300_cp.bin"
53 #define FIRMWARE_R420 "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
65
66 #include "r100_track.h"
67
68 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
69 {
70 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
71 int i;
72
73 if (radeon_crtc->crtc_id == 0) {
74 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
75 for (i = 0; i < rdev->usec_timeout; i++) {
76 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
77 break;
78 udelay(1);
79 }
80 for (i = 0; i < rdev->usec_timeout; i++) {
81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
82 break;
83 udelay(1);
84 }
85 }
86 } else {
87 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
88 for (i = 0; i < rdev->usec_timeout; i++) {
89 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
90 break;
91 udelay(1);
92 }
93 for (i = 0; i < rdev->usec_timeout; i++) {
94 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
95 break;
96 udelay(1);
97 }
98 }
99 }
100 }
101
102 /* This files gather functions specifics to:
103 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
104 */
105
106 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
107 struct radeon_cs_packet *pkt,
108 unsigned idx,
109 unsigned reg)
110 {
111 int r;
112 u32 tile_flags = 0;
113 u32 tmp;
114 struct radeon_cs_reloc *reloc;
115 u32 value;
116
117 r = r100_cs_packet_next_reloc(p, &reloc);
118 if (r) {
119 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
120 idx, reg);
121 r100_cs_dump_packet(p, pkt);
122 return r;
123 }
124
125 value = radeon_get_ib_value(p, idx);
126 tmp = value & 0x003fffff;
127 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
128
129 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
130 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
131 tile_flags |= RADEON_DST_TILE_MACRO;
132 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
133 if (reg == RADEON_SRC_PITCH_OFFSET) {
134 DRM_ERROR("Cannot src blit from microtiled surface\n");
135 r100_cs_dump_packet(p, pkt);
136 return -EINVAL;
137 }
138 tile_flags |= RADEON_DST_TILE_MICRO;
139 }
140
141 tmp |= tile_flags;
142 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
143 } else
144 p->ib->ptr[idx] = (value & 0xffc00000) | tmp;
145 return 0;
146 }
147
148 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
149 struct radeon_cs_packet *pkt,
150 int idx)
151 {
152 unsigned c, i;
153 struct radeon_cs_reloc *reloc;
154 struct r100_cs_track *track;
155 int r = 0;
156 volatile uint32_t *ib;
157 u32 idx_value;
158
159 ib = p->ib->ptr;
160 track = (struct r100_cs_track *)p->track;
161 c = radeon_get_ib_value(p, idx++) & 0x1F;
162 if (c > 16) {
163 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
164 pkt->opcode);
165 r100_cs_dump_packet(p, pkt);
166 return -EINVAL;
167 }
168 track->num_arrays = c;
169 for (i = 0; i < (c - 1); i+=2, idx+=3) {
170 r = r100_cs_packet_next_reloc(p, &reloc);
171 if (r) {
172 DRM_ERROR("No reloc for packet3 %d\n",
173 pkt->opcode);
174 r100_cs_dump_packet(p, pkt);
175 return r;
176 }
177 idx_value = radeon_get_ib_value(p, idx);
178 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
179
180 track->arrays[i + 0].esize = idx_value >> 8;
181 track->arrays[i + 0].robj = reloc->robj;
182 track->arrays[i + 0].esize &= 0x7F;
183 r = r100_cs_packet_next_reloc(p, &reloc);
184 if (r) {
185 DRM_ERROR("No reloc for packet3 %d\n",
186 pkt->opcode);
187 r100_cs_dump_packet(p, pkt);
188 return r;
189 }
190 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
191 track->arrays[i + 1].robj = reloc->robj;
192 track->arrays[i + 1].esize = idx_value >> 24;
193 track->arrays[i + 1].esize &= 0x7F;
194 }
195 if (c & 1) {
196 r = r100_cs_packet_next_reloc(p, &reloc);
197 if (r) {
198 DRM_ERROR("No reloc for packet3 %d\n",
199 pkt->opcode);
200 r100_cs_dump_packet(p, pkt);
201 return r;
202 }
203 idx_value = radeon_get_ib_value(p, idx);
204 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
205 track->arrays[i + 0].robj = reloc->robj;
206 track->arrays[i + 0].esize = idx_value >> 8;
207 track->arrays[i + 0].esize &= 0x7F;
208 }
209 return r;
210 }
211
212 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
213 {
214 /* enable the pflip int */
215 radeon_irq_kms_pflip_irq_get(rdev, crtc);
216 }
217
218 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
219 {
220 /* disable the pflip int */
221 radeon_irq_kms_pflip_irq_put(rdev, crtc);
222 }
223
224 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
225 {
226 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
227 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
228 int i;
229
230 /* Lock the graphics update lock */
231 /* update the scanout addresses */
232 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
233
234 /* Wait for update_pending to go high. */
235 for (i = 0; i < rdev->usec_timeout; i++) {
236 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
237 break;
238 udelay(1);
239 }
240 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
241
242 /* Unlock the lock, so double-buffering can take place inside vblank */
243 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
244 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
245
246 /* Return current update_pending status: */
247 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
248 }
249
250 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
251 {
252 int i;
253 rdev->pm.dynpm_can_upclock = true;
254 rdev->pm.dynpm_can_downclock = true;
255
256 switch (rdev->pm.dynpm_planned_action) {
257 case DYNPM_ACTION_MINIMUM:
258 rdev->pm.requested_power_state_index = 0;
259 rdev->pm.dynpm_can_downclock = false;
260 break;
261 case DYNPM_ACTION_DOWNCLOCK:
262 if (rdev->pm.current_power_state_index == 0) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
264 rdev->pm.dynpm_can_downclock = false;
265 } else {
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = 0; i < rdev->pm.num_power_states; i++) {
268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
269 continue;
270 else if (i >= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
272 break;
273 } else {
274 rdev->pm.requested_power_state_index = i;
275 break;
276 }
277 }
278 } else
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index - 1;
281 }
282 /* don't use the power state if crtcs are active and no display flag is set */
283 if ((rdev->pm.active_crtc_count > 0) &&
284 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
285 RADEON_PM_MODE_NO_DISPLAY)) {
286 rdev->pm.requested_power_state_index++;
287 }
288 break;
289 case DYNPM_ACTION_UPCLOCK:
290 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
291 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
292 rdev->pm.dynpm_can_upclock = false;
293 } else {
294 if (rdev->pm.active_crtc_count > 1) {
295 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
296 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
297 continue;
298 else if (i <= rdev->pm.current_power_state_index) {
299 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
300 break;
301 } else {
302 rdev->pm.requested_power_state_index = i;
303 break;
304 }
305 }
306 } else
307 rdev->pm.requested_power_state_index =
308 rdev->pm.current_power_state_index + 1;
309 }
310 break;
311 case DYNPM_ACTION_DEFAULT:
312 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
313 rdev->pm.dynpm_can_upclock = false;
314 break;
315 case DYNPM_ACTION_NONE:
316 default:
317 DRM_ERROR("Requested mode for not defined action\n");
318 return;
319 }
320 /* only one clock mode per power state */
321 rdev->pm.requested_clock_mode_index = 0;
322
323 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
324 rdev->pm.power_state[rdev->pm.requested_power_state_index].
325 clock_info[rdev->pm.requested_clock_mode_index].sclk,
326 rdev->pm.power_state[rdev->pm.requested_power_state_index].
327 clock_info[rdev->pm.requested_clock_mode_index].mclk,
328 rdev->pm.power_state[rdev->pm.requested_power_state_index].
329 pcie_lanes);
330 }
331
332 void r100_pm_init_profile(struct radeon_device *rdev)
333 {
334 /* default */
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
336 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
339 /* low sh */
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
344 /* mid sh */
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
349 /* high sh */
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
354 /* low mh */
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
359 /* mid mh */
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
364 /* high mh */
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
369 }
370
371 void r100_pm_misc(struct radeon_device *rdev)
372 {
373 int requested_index = rdev->pm.requested_power_state_index;
374 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
375 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
376 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
377
378 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
379 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
380 tmp = RREG32(voltage->gpio.reg);
381 if (voltage->active_high)
382 tmp |= voltage->gpio.mask;
383 else
384 tmp &= ~(voltage->gpio.mask);
385 WREG32(voltage->gpio.reg, tmp);
386 if (voltage->delay)
387 udelay(voltage->delay);
388 } else {
389 tmp = RREG32(voltage->gpio.reg);
390 if (voltage->active_high)
391 tmp &= ~voltage->gpio.mask;
392 else
393 tmp |= voltage->gpio.mask;
394 WREG32(voltage->gpio.reg, tmp);
395 if (voltage->delay)
396 udelay(voltage->delay);
397 }
398 }
399
400 sclk_cntl = RREG32_PLL(SCLK_CNTL);
401 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
402 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
403 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
404 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
405 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
406 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
407 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
408 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
409 else
410 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
411 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
412 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
413 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
414 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
415 } else
416 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
417
418 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
419 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
420 if (voltage->delay) {
421 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
422 switch (voltage->delay) {
423 case 33:
424 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
425 break;
426 case 66:
427 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
428 break;
429 case 99:
430 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
431 break;
432 case 132:
433 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
434 break;
435 }
436 } else
437 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
438 } else
439 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
440
441 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
442 sclk_cntl &= ~FORCE_HDP;
443 else
444 sclk_cntl |= FORCE_HDP;
445
446 WREG32_PLL(SCLK_CNTL, sclk_cntl);
447 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
448 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
449
450 /* set pcie lanes */
451 if ((rdev->flags & RADEON_IS_PCIE) &&
452 !(rdev->flags & RADEON_IS_IGP) &&
453 rdev->asic->set_pcie_lanes &&
454 (ps->pcie_lanes !=
455 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
456 radeon_set_pcie_lanes(rdev,
457 ps->pcie_lanes);
458 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
459 }
460 }
461
462 void r100_pm_prepare(struct radeon_device *rdev)
463 {
464 struct drm_device *ddev = rdev->ddev;
465 struct drm_crtc *crtc;
466 struct radeon_crtc *radeon_crtc;
467 u32 tmp;
468
469 /* disable any active CRTCs */
470 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
471 radeon_crtc = to_radeon_crtc(crtc);
472 if (radeon_crtc->enabled) {
473 if (radeon_crtc->crtc_id) {
474 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
475 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
477 } else {
478 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
479 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
480 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
481 }
482 }
483 }
484 }
485
486 void r100_pm_finish(struct radeon_device *rdev)
487 {
488 struct drm_device *ddev = rdev->ddev;
489 struct drm_crtc *crtc;
490 struct radeon_crtc *radeon_crtc;
491 u32 tmp;
492
493 /* enable any active CRTCs */
494 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
495 radeon_crtc = to_radeon_crtc(crtc);
496 if (radeon_crtc->enabled) {
497 if (radeon_crtc->crtc_id) {
498 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
499 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
500 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
501 } else {
502 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
503 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
504 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
505 }
506 }
507 }
508 }
509
510 bool r100_gui_idle(struct radeon_device *rdev)
511 {
512 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
513 return false;
514 else
515 return true;
516 }
517
518 /* hpd for digital panel detect/disconnect */
519 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
520 {
521 bool connected = false;
522
523 switch (hpd) {
524 case RADEON_HPD_1:
525 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
526 connected = true;
527 break;
528 case RADEON_HPD_2:
529 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
530 connected = true;
531 break;
532 default:
533 break;
534 }
535 return connected;
536 }
537
538 void r100_hpd_set_polarity(struct radeon_device *rdev,
539 enum radeon_hpd_id hpd)
540 {
541 u32 tmp;
542 bool connected = r100_hpd_sense(rdev, hpd);
543
544 switch (hpd) {
545 case RADEON_HPD_1:
546 tmp = RREG32(RADEON_FP_GEN_CNTL);
547 if (connected)
548 tmp &= ~RADEON_FP_DETECT_INT_POL;
549 else
550 tmp |= RADEON_FP_DETECT_INT_POL;
551 WREG32(RADEON_FP_GEN_CNTL, tmp);
552 break;
553 case RADEON_HPD_2:
554 tmp = RREG32(RADEON_FP2_GEN_CNTL);
555 if (connected)
556 tmp &= ~RADEON_FP2_DETECT_INT_POL;
557 else
558 tmp |= RADEON_FP2_DETECT_INT_POL;
559 WREG32(RADEON_FP2_GEN_CNTL, tmp);
560 break;
561 default:
562 break;
563 }
564 }
565
566 void r100_hpd_init(struct radeon_device *rdev)
567 {
568 struct drm_device *dev = rdev->ddev;
569 struct drm_connector *connector;
570
571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
572 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
573 switch (radeon_connector->hpd.hpd) {
574 case RADEON_HPD_1:
575 rdev->irq.hpd[0] = true;
576 break;
577 case RADEON_HPD_2:
578 rdev->irq.hpd[1] = true;
579 break;
580 default:
581 break;
582 }
583 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
584 }
585 if (rdev->irq.installed)
586 r100_irq_set(rdev);
587 }
588
589 void r100_hpd_fini(struct radeon_device *rdev)
590 {
591 struct drm_device *dev = rdev->ddev;
592 struct drm_connector *connector;
593
594 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
595 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
596 switch (radeon_connector->hpd.hpd) {
597 case RADEON_HPD_1:
598 rdev->irq.hpd[0] = false;
599 break;
600 case RADEON_HPD_2:
601 rdev->irq.hpd[1] = false;
602 break;
603 default:
604 break;
605 }
606 }
607 }
608
609 /*
610 * PCI GART
611 */
612 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
613 {
614 /* TODO: can we do somethings here ? */
615 /* It seems hw only cache one entry so we should discard this
616 * entry otherwise if first GPU GART read hit this entry it
617 * could end up in wrong address. */
618 }
619
620 int r100_pci_gart_init(struct radeon_device *rdev)
621 {
622 int r;
623
624 if (rdev->gart.ptr) {
625 WARN(1, "R100 PCI GART already initialized\n");
626 return 0;
627 }
628 /* Initialize common gart structure */
629 r = radeon_gart_init(rdev);
630 if (r)
631 return r;
632 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
633 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
634 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
635 return radeon_gart_table_ram_alloc(rdev);
636 }
637
638 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
639 void r100_enable_bm(struct radeon_device *rdev)
640 {
641 uint32_t tmp;
642 /* Enable bus mastering */
643 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
644 WREG32(RADEON_BUS_CNTL, tmp);
645 }
646
647 int r100_pci_gart_enable(struct radeon_device *rdev)
648 {
649 uint32_t tmp;
650
651 radeon_gart_restore(rdev);
652 /* discard memory request outside of configured range */
653 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
654 WREG32(RADEON_AIC_CNTL, tmp);
655 /* set address range for PCI address translate */
656 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
657 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
658 /* set PCI GART page-table base address */
659 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
660 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
661 WREG32(RADEON_AIC_CNTL, tmp);
662 r100_pci_gart_tlb_flush(rdev);
663 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
664 (unsigned)(rdev->mc.gtt_size >> 20),
665 (unsigned long long)rdev->gart.table_addr);
666 rdev->gart.ready = true;
667 return 0;
668 }
669
670 void r100_pci_gart_disable(struct radeon_device *rdev)
671 {
672 uint32_t tmp;
673
674 /* discard memory request outside of configured range */
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
676 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
677 WREG32(RADEON_AIC_LO_ADDR, 0);
678 WREG32(RADEON_AIC_HI_ADDR, 0);
679 }
680
681 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
682 {
683 u32 *gtt = rdev->gart.ptr;
684
685 if (i < 0 || i > rdev->gart.num_gpu_pages) {
686 return -EINVAL;
687 }
688 gtt[i] = cpu_to_le32(lower_32_bits(addr));
689 return 0;
690 }
691
692 void r100_pci_gart_fini(struct radeon_device *rdev)
693 {
694 radeon_gart_fini(rdev);
695 r100_pci_gart_disable(rdev);
696 radeon_gart_table_ram_free(rdev);
697 }
698
699 int r100_irq_set(struct radeon_device *rdev)
700 {
701 uint32_t tmp = 0;
702
703 if (!rdev->irq.installed) {
704 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
705 WREG32(R_000040_GEN_INT_CNTL, 0);
706 return -EINVAL;
707 }
708 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
709 tmp |= RADEON_SW_INT_ENABLE;
710 }
711 if (rdev->irq.gui_idle) {
712 tmp |= RADEON_GUI_IDLE_MASK;
713 }
714 if (rdev->irq.crtc_vblank_int[0] ||
715 rdev->irq.pflip[0]) {
716 tmp |= RADEON_CRTC_VBLANK_MASK;
717 }
718 if (rdev->irq.crtc_vblank_int[1] ||
719 rdev->irq.pflip[1]) {
720 tmp |= RADEON_CRTC2_VBLANK_MASK;
721 }
722 if (rdev->irq.hpd[0]) {
723 tmp |= RADEON_FP_DETECT_MASK;
724 }
725 if (rdev->irq.hpd[1]) {
726 tmp |= RADEON_FP2_DETECT_MASK;
727 }
728 WREG32(RADEON_GEN_INT_CNTL, tmp);
729 return 0;
730 }
731
732 void r100_irq_disable(struct radeon_device *rdev)
733 {
734 u32 tmp;
735
736 WREG32(R_000040_GEN_INT_CNTL, 0);
737 /* Wait and acknowledge irq */
738 mdelay(1);
739 tmp = RREG32(R_000044_GEN_INT_STATUS);
740 WREG32(R_000044_GEN_INT_STATUS, tmp);
741 }
742
743 static uint32_t r100_irq_ack(struct radeon_device *rdev)
744 {
745 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
746 uint32_t irq_mask = RADEON_SW_INT_TEST |
747 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
748 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
749
750 /* the interrupt works, but the status bit is permanently asserted */
751 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
752 if (!rdev->irq.gui_idle_acked)
753 irq_mask |= RADEON_GUI_IDLE_STAT;
754 }
755
756 if (irqs) {
757 WREG32(RADEON_GEN_INT_STATUS, irqs);
758 }
759 return irqs & irq_mask;
760 }
761
762 int r100_irq_process(struct radeon_device *rdev)
763 {
764 uint32_t status, msi_rearm;
765 bool queue_hotplug = false;
766
767 /* reset gui idle ack. the status bit is broken */
768 rdev->irq.gui_idle_acked = false;
769
770 status = r100_irq_ack(rdev);
771 if (!status) {
772 return IRQ_NONE;
773 }
774 if (rdev->shutdown) {
775 return IRQ_NONE;
776 }
777 while (status) {
778 /* SW interrupt */
779 if (status & RADEON_SW_INT_TEST) {
780 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
781 }
782 /* gui idle interrupt */
783 if (status & RADEON_GUI_IDLE_STAT) {
784 rdev->irq.gui_idle_acked = true;
785 rdev->pm.gui_idle = true;
786 wake_up(&rdev->irq.idle_queue);
787 }
788 /* Vertical blank interrupts */
789 if (status & RADEON_CRTC_VBLANK_STAT) {
790 if (rdev->irq.crtc_vblank_int[0]) {
791 drm_handle_vblank(rdev->ddev, 0);
792 rdev->pm.vblank_sync = true;
793 wake_up(&rdev->irq.vblank_queue);
794 }
795 if (rdev->irq.pflip[0])
796 radeon_crtc_handle_flip(rdev, 0);
797 }
798 if (status & RADEON_CRTC2_VBLANK_STAT) {
799 if (rdev->irq.crtc_vblank_int[1]) {
800 drm_handle_vblank(rdev->ddev, 1);
801 rdev->pm.vblank_sync = true;
802 wake_up(&rdev->irq.vblank_queue);
803 }
804 if (rdev->irq.pflip[1])
805 radeon_crtc_handle_flip(rdev, 1);
806 }
807 if (status & RADEON_FP_DETECT_STAT) {
808 queue_hotplug = true;
809 DRM_DEBUG("HPD1\n");
810 }
811 if (status & RADEON_FP2_DETECT_STAT) {
812 queue_hotplug = true;
813 DRM_DEBUG("HPD2\n");
814 }
815 status = r100_irq_ack(rdev);
816 }
817 /* reset gui idle ack. the status bit is broken */
818 rdev->irq.gui_idle_acked = false;
819 if (queue_hotplug)
820 schedule_work(&rdev->hotplug_work);
821 if (rdev->msi_enabled) {
822 switch (rdev->family) {
823 case CHIP_RS400:
824 case CHIP_RS480:
825 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
826 WREG32(RADEON_AIC_CNTL, msi_rearm);
827 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
828 break;
829 default:
830 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
831 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
832 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
833 break;
834 }
835 }
836 return IRQ_HANDLED;
837 }
838
839 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
840 {
841 if (crtc == 0)
842 return RREG32(RADEON_CRTC_CRNT_FRAME);
843 else
844 return RREG32(RADEON_CRTC2_CRNT_FRAME);
845 }
846
847 /* Who ever call radeon_fence_emit should call ring_lock and ask
848 * for enough space (today caller are ib schedule and buffer move) */
849 void r100_fence_ring_emit(struct radeon_device *rdev,
850 struct radeon_fence *fence)
851 {
852 struct radeon_ring *ring = &rdev->ring[fence->ring];
853
854 /* We have to make sure that caches are flushed before
855 * CPU might read something from VRAM. */
856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
857 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
858 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
859 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
860 /* Wait until IDLE & CLEAN */
861 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
862 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
865 RADEON_HDP_READ_BUFFER_INVALIDATE);
866 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
867 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
868 /* Emit fence sequence & fire IRQ */
869 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
870 radeon_ring_write(ring, fence->seq);
871 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
872 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
873 }
874
875 void r100_semaphore_ring_emit(struct radeon_device *rdev,
876 struct radeon_ring *ring,
877 struct radeon_semaphore *semaphore,
878 bool emit_wait)
879 {
880 /* Unused on older asics, since we don't have semaphores or multiple rings */
881 BUG();
882 }
883
884 int r100_copy_blit(struct radeon_device *rdev,
885 uint64_t src_offset,
886 uint64_t dst_offset,
887 unsigned num_gpu_pages,
888 struct radeon_fence *fence)
889 {
890 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
891 uint32_t cur_pages;
892 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
893 uint32_t pitch;
894 uint32_t stride_pixels;
895 unsigned ndw;
896 int num_loops;
897 int r = 0;
898
899 /* radeon limited to 16k stride */
900 stride_bytes &= 0x3fff;
901 /* radeon pitch is /64 */
902 pitch = stride_bytes / 64;
903 stride_pixels = stride_bytes / 4;
904 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
905
906 /* Ask for enough room for blit + flush + fence */
907 ndw = 64 + (10 * num_loops);
908 r = radeon_ring_lock(rdev, ring, ndw);
909 if (r) {
910 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
911 return -EINVAL;
912 }
913 while (num_gpu_pages > 0) {
914 cur_pages = num_gpu_pages;
915 if (cur_pages > 8191) {
916 cur_pages = 8191;
917 }
918 num_gpu_pages -= cur_pages;
919
920 /* pages are in Y direction - height
921 page width in X direction - width */
922 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
923 radeon_ring_write(ring,
924 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
925 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
926 RADEON_GMC_SRC_CLIPPING |
927 RADEON_GMC_DST_CLIPPING |
928 RADEON_GMC_BRUSH_NONE |
929 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
930 RADEON_GMC_SRC_DATATYPE_COLOR |
931 RADEON_ROP3_S |
932 RADEON_DP_SRC_SOURCE_MEMORY |
933 RADEON_GMC_CLR_CMP_CNTL_DIS |
934 RADEON_GMC_WR_MSK_DIS);
935 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
936 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
938 radeon_ring_write(ring, 0);
939 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
940 radeon_ring_write(ring, num_gpu_pages);
941 radeon_ring_write(ring, num_gpu_pages);
942 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
943 }
944 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
945 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
946 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
947 radeon_ring_write(ring,
948 RADEON_WAIT_2D_IDLECLEAN |
949 RADEON_WAIT_HOST_IDLECLEAN |
950 RADEON_WAIT_DMA_GUI_IDLE);
951 if (fence) {
952 r = radeon_fence_emit(rdev, fence);
953 }
954 radeon_ring_unlock_commit(rdev, ring);
955 return r;
956 }
957
958 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
959 {
960 unsigned i;
961 u32 tmp;
962
963 for (i = 0; i < rdev->usec_timeout; i++) {
964 tmp = RREG32(R_000E40_RBBM_STATUS);
965 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
966 return 0;
967 }
968 udelay(1);
969 }
970 return -1;
971 }
972
973 void r100_ring_start(struct radeon_device *rdev)
974 {
975 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
976 int r;
977
978 r = radeon_ring_lock(rdev, ring, 2);
979 if (r) {
980 return;
981 }
982 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
983 radeon_ring_write(ring,
984 RADEON_ISYNC_ANY2D_IDLE3D |
985 RADEON_ISYNC_ANY3D_IDLE2D |
986 RADEON_ISYNC_WAIT_IDLEGUI |
987 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
988 radeon_ring_unlock_commit(rdev, ring);
989 }
990
991
992 /* Load the microcode for the CP */
993 static int r100_cp_init_microcode(struct radeon_device *rdev)
994 {
995 struct platform_device *pdev;
996 const char *fw_name = NULL;
997 int err;
998
999 DRM_DEBUG_KMS("\n");
1000
1001 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1002 err = IS_ERR(pdev);
1003 if (err) {
1004 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1005 return -EINVAL;
1006 }
1007 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1008 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1009 (rdev->family == CHIP_RS200)) {
1010 DRM_INFO("Loading R100 Microcode\n");
1011 fw_name = FIRMWARE_R100;
1012 } else if ((rdev->family == CHIP_R200) ||
1013 (rdev->family == CHIP_RV250) ||
1014 (rdev->family == CHIP_RV280) ||
1015 (rdev->family == CHIP_RS300)) {
1016 DRM_INFO("Loading R200 Microcode\n");
1017 fw_name = FIRMWARE_R200;
1018 } else if ((rdev->family == CHIP_R300) ||
1019 (rdev->family == CHIP_R350) ||
1020 (rdev->family == CHIP_RV350) ||
1021 (rdev->family == CHIP_RV380) ||
1022 (rdev->family == CHIP_RS400) ||
1023 (rdev->family == CHIP_RS480)) {
1024 DRM_INFO("Loading R300 Microcode\n");
1025 fw_name = FIRMWARE_R300;
1026 } else if ((rdev->family == CHIP_R420) ||
1027 (rdev->family == CHIP_R423) ||
1028 (rdev->family == CHIP_RV410)) {
1029 DRM_INFO("Loading R400 Microcode\n");
1030 fw_name = FIRMWARE_R420;
1031 } else if ((rdev->family == CHIP_RS690) ||
1032 (rdev->family == CHIP_RS740)) {
1033 DRM_INFO("Loading RS690/RS740 Microcode\n");
1034 fw_name = FIRMWARE_RS690;
1035 } else if (rdev->family == CHIP_RS600) {
1036 DRM_INFO("Loading RS600 Microcode\n");
1037 fw_name = FIRMWARE_RS600;
1038 } else if ((rdev->family == CHIP_RV515) ||
1039 (rdev->family == CHIP_R520) ||
1040 (rdev->family == CHIP_RV530) ||
1041 (rdev->family == CHIP_R580) ||
1042 (rdev->family == CHIP_RV560) ||
1043 (rdev->family == CHIP_RV570)) {
1044 DRM_INFO("Loading R500 Microcode\n");
1045 fw_name = FIRMWARE_R520;
1046 }
1047
1048 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1049 platform_device_unregister(pdev);
1050 if (err) {
1051 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1052 fw_name);
1053 } else if (rdev->me_fw->size % 8) {
1054 printk(KERN_ERR
1055 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1056 rdev->me_fw->size, fw_name);
1057 err = -EINVAL;
1058 release_firmware(rdev->me_fw);
1059 rdev->me_fw = NULL;
1060 }
1061 return err;
1062 }
1063
1064 static void r100_cp_load_microcode(struct radeon_device *rdev)
1065 {
1066 const __be32 *fw_data;
1067 int i, size;
1068
1069 if (r100_gui_wait_for_idle(rdev)) {
1070 printk(KERN_WARNING "Failed to wait GUI idle while "
1071 "programming pipes. Bad things might happen.\n");
1072 }
1073
1074 if (rdev->me_fw) {
1075 size = rdev->me_fw->size / 4;
1076 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1077 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1078 for (i = 0; i < size; i += 2) {
1079 WREG32(RADEON_CP_ME_RAM_DATAH,
1080 be32_to_cpup(&fw_data[i]));
1081 WREG32(RADEON_CP_ME_RAM_DATAL,
1082 be32_to_cpup(&fw_data[i + 1]));
1083 }
1084 }
1085 }
1086
1087 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1088 {
1089 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1090 unsigned rb_bufsz;
1091 unsigned rb_blksz;
1092 unsigned max_fetch;
1093 unsigned pre_write_timer;
1094 unsigned pre_write_limit;
1095 unsigned indirect2_start;
1096 unsigned indirect1_start;
1097 uint32_t tmp;
1098 int r;
1099
1100 if (r100_debugfs_cp_init(rdev)) {
1101 DRM_ERROR("Failed to register debugfs file for CP !\n");
1102 }
1103 if (!rdev->me_fw) {
1104 r = r100_cp_init_microcode(rdev);
1105 if (r) {
1106 DRM_ERROR("Failed to load firmware!\n");
1107 return r;
1108 }
1109 }
1110
1111 /* Align ring size */
1112 rb_bufsz = drm_order(ring_size / 8);
1113 ring_size = (1 << (rb_bufsz + 1)) * 4;
1114 r100_cp_load_microcode(rdev);
1115 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1116 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1117 0, 0x7fffff, RADEON_CP_PACKET2);
1118 if (r) {
1119 return r;
1120 }
1121 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1122 * the rptr copy in system ram */
1123 rb_blksz = 9;
1124 /* cp will read 128bytes at a time (4 dwords) */
1125 max_fetch = 1;
1126 ring->align_mask = 16 - 1;
1127 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1128 pre_write_timer = 64;
1129 /* Force CP_RB_WPTR write if written more than one time before the
1130 * delay expire
1131 */
1132 pre_write_limit = 0;
1133 /* Setup the cp cache like this (cache size is 96 dwords) :
1134 * RING 0 to 15
1135 * INDIRECT1 16 to 79
1136 * INDIRECT2 80 to 95
1137 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1138 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1139 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1140 * Idea being that most of the gpu cmd will be through indirect1 buffer
1141 * so it gets the bigger cache.
1142 */
1143 indirect2_start = 80;
1144 indirect1_start = 16;
1145 /* cp setup */
1146 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1147 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1148 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1149 REG_SET(RADEON_MAX_FETCH, max_fetch));
1150 #ifdef __BIG_ENDIAN
1151 tmp |= RADEON_BUF_SWAP_32BIT;
1152 #endif
1153 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1154
1155 /* Set ring address */
1156 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1157 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1158 /* Force read & write ptr to 0 */
1159 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1160 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1161 ring->wptr = 0;
1162 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1163
1164 /* set the wb address whether it's enabled or not */
1165 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1166 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1167 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1168
1169 if (rdev->wb.enabled)
1170 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1171 else {
1172 tmp |= RADEON_RB_NO_UPDATE;
1173 WREG32(R_000770_SCRATCH_UMSK, 0);
1174 }
1175
1176 WREG32(RADEON_CP_RB_CNTL, tmp);
1177 udelay(10);
1178 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1179 /* Set cp mode to bus mastering & enable cp*/
1180 WREG32(RADEON_CP_CSQ_MODE,
1181 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1182 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1183 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1184 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1185 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1186 radeon_ring_start(rdev);
1187 r = radeon_ring_test(rdev, ring);
1188 if (r) {
1189 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1190 return r;
1191 }
1192 ring->ready = true;
1193 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1194 return 0;
1195 }
1196
1197 void r100_cp_fini(struct radeon_device *rdev)
1198 {
1199 if (r100_cp_wait_for_idle(rdev)) {
1200 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1201 }
1202 /* Disable ring */
1203 r100_cp_disable(rdev);
1204 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1205 DRM_INFO("radeon: cp finalized\n");
1206 }
1207
1208 void r100_cp_disable(struct radeon_device *rdev)
1209 {
1210 /* Disable ring */
1211 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1212 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1213 WREG32(RADEON_CP_CSQ_MODE, 0);
1214 WREG32(RADEON_CP_CSQ_CNTL, 0);
1215 WREG32(R_000770_SCRATCH_UMSK, 0);
1216 if (r100_gui_wait_for_idle(rdev)) {
1217 printk(KERN_WARNING "Failed to wait GUI idle while "
1218 "programming pipes. Bad things might happen.\n");
1219 }
1220 }
1221
1222 /*
1223 * CS functions
1224 */
1225 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1226 struct radeon_cs_packet *pkt,
1227 const unsigned *auth, unsigned n,
1228 radeon_packet0_check_t check)
1229 {
1230 unsigned reg;
1231 unsigned i, j, m;
1232 unsigned idx;
1233 int r;
1234
1235 idx = pkt->idx + 1;
1236 reg = pkt->reg;
1237 /* Check that register fall into register range
1238 * determined by the number of entry (n) in the
1239 * safe register bitmap.
1240 */
1241 if (pkt->one_reg_wr) {
1242 if ((reg >> 7) > n) {
1243 return -EINVAL;
1244 }
1245 } else {
1246 if (((reg + (pkt->count << 2)) >> 7) > n) {
1247 return -EINVAL;
1248 }
1249 }
1250 for (i = 0; i <= pkt->count; i++, idx++) {
1251 j = (reg >> 7);
1252 m = 1 << ((reg >> 2) & 31);
1253 if (auth[j] & m) {
1254 r = check(p, pkt, idx, reg);
1255 if (r) {
1256 return r;
1257 }
1258 }
1259 if (pkt->one_reg_wr) {
1260 if (!(auth[j] & m)) {
1261 break;
1262 }
1263 } else {
1264 reg += 4;
1265 }
1266 }
1267 return 0;
1268 }
1269
1270 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1271 struct radeon_cs_packet *pkt)
1272 {
1273 volatile uint32_t *ib;
1274 unsigned i;
1275 unsigned idx;
1276
1277 ib = p->ib->ptr;
1278 idx = pkt->idx;
1279 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1280 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1281 }
1282 }
1283
1284 /**
1285 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1286 * @parser: parser structure holding parsing context.
1287 * @pkt: where to store packet informations
1288 *
1289 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1290 * if packet is bigger than remaining ib size. or if packets is unknown.
1291 **/
1292 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1293 struct radeon_cs_packet *pkt,
1294 unsigned idx)
1295 {
1296 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1297 uint32_t header;
1298
1299 if (idx >= ib_chunk->length_dw) {
1300 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1301 idx, ib_chunk->length_dw);
1302 return -EINVAL;
1303 }
1304 header = radeon_get_ib_value(p, idx);
1305 pkt->idx = idx;
1306 pkt->type = CP_PACKET_GET_TYPE(header);
1307 pkt->count = CP_PACKET_GET_COUNT(header);
1308 switch (pkt->type) {
1309 case PACKET_TYPE0:
1310 pkt->reg = CP_PACKET0_GET_REG(header);
1311 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1312 break;
1313 case PACKET_TYPE3:
1314 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1315 break;
1316 case PACKET_TYPE2:
1317 pkt->count = -1;
1318 break;
1319 default:
1320 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1321 return -EINVAL;
1322 }
1323 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1324 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1325 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1326 return -EINVAL;
1327 }
1328 return 0;
1329 }
1330
1331 /**
1332 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1333 * @parser: parser structure holding parsing context.
1334 *
1335 * Userspace sends a special sequence for VLINE waits.
1336 * PACKET0 - VLINE_START_END + value
1337 * PACKET0 - WAIT_UNTIL +_value
1338 * RELOC (P3) - crtc_id in reloc.
1339 *
1340 * This function parses this and relocates the VLINE START END
1341 * and WAIT UNTIL packets to the correct crtc.
1342 * It also detects a switched off crtc and nulls out the
1343 * wait in that case.
1344 */
1345 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1346 {
1347 struct drm_mode_object *obj;
1348 struct drm_crtc *crtc;
1349 struct radeon_crtc *radeon_crtc;
1350 struct radeon_cs_packet p3reloc, waitreloc;
1351 int crtc_id;
1352 int r;
1353 uint32_t header, h_idx, reg;
1354 volatile uint32_t *ib;
1355
1356 ib = p->ib->ptr;
1357
1358 /* parse the wait until */
1359 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1360 if (r)
1361 return r;
1362
1363 /* check its a wait until and only 1 count */
1364 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1365 waitreloc.count != 0) {
1366 DRM_ERROR("vline wait had illegal wait until segment\n");
1367 return -EINVAL;
1368 }
1369
1370 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1371 DRM_ERROR("vline wait had illegal wait until\n");
1372 return -EINVAL;
1373 }
1374
1375 /* jump over the NOP */
1376 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1377 if (r)
1378 return r;
1379
1380 h_idx = p->idx - 2;
1381 p->idx += waitreloc.count + 2;
1382 p->idx += p3reloc.count + 2;
1383
1384 header = radeon_get_ib_value(p, h_idx);
1385 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1386 reg = CP_PACKET0_GET_REG(header);
1387 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1388 if (!obj) {
1389 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1390 return -EINVAL;
1391 }
1392 crtc = obj_to_crtc(obj);
1393 radeon_crtc = to_radeon_crtc(crtc);
1394 crtc_id = radeon_crtc->crtc_id;
1395
1396 if (!crtc->enabled) {
1397 /* if the CRTC isn't enabled - we need to nop out the wait until */
1398 ib[h_idx + 2] = PACKET2(0);
1399 ib[h_idx + 3] = PACKET2(0);
1400 } else if (crtc_id == 1) {
1401 switch (reg) {
1402 case AVIVO_D1MODE_VLINE_START_END:
1403 header &= ~R300_CP_PACKET0_REG_MASK;
1404 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1405 break;
1406 case RADEON_CRTC_GUI_TRIG_VLINE:
1407 header &= ~R300_CP_PACKET0_REG_MASK;
1408 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1409 break;
1410 default:
1411 DRM_ERROR("unknown crtc reloc\n");
1412 return -EINVAL;
1413 }
1414 ib[h_idx] = header;
1415 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1416 }
1417
1418 return 0;
1419 }
1420
1421 /**
1422 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1423 * @parser: parser structure holding parsing context.
1424 * @data: pointer to relocation data
1425 * @offset_start: starting offset
1426 * @offset_mask: offset mask (to align start offset on)
1427 * @reloc: reloc informations
1428 *
1429 * Check next packet is relocation packet3, do bo validation and compute
1430 * GPU offset using the provided start.
1431 **/
1432 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1433 struct radeon_cs_reloc **cs_reloc)
1434 {
1435 struct radeon_cs_chunk *relocs_chunk;
1436 struct radeon_cs_packet p3reloc;
1437 unsigned idx;
1438 int r;
1439
1440 if (p->chunk_relocs_idx == -1) {
1441 DRM_ERROR("No relocation chunk !\n");
1442 return -EINVAL;
1443 }
1444 *cs_reloc = NULL;
1445 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1446 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1447 if (r) {
1448 return r;
1449 }
1450 p->idx += p3reloc.count + 2;
1451 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1452 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1453 p3reloc.idx);
1454 r100_cs_dump_packet(p, &p3reloc);
1455 return -EINVAL;
1456 }
1457 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1458 if (idx >= relocs_chunk->length_dw) {
1459 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1460 idx, relocs_chunk->length_dw);
1461 r100_cs_dump_packet(p, &p3reloc);
1462 return -EINVAL;
1463 }
1464 /* FIXME: we assume reloc size is 4 dwords */
1465 *cs_reloc = p->relocs_ptr[(idx / 4)];
1466 return 0;
1467 }
1468
1469 static int r100_get_vtx_size(uint32_t vtx_fmt)
1470 {
1471 int vtx_size;
1472 vtx_size = 2;
1473 /* ordered according to bits in spec */
1474 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1475 vtx_size++;
1476 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1477 vtx_size += 3;
1478 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1479 vtx_size++;
1480 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1481 vtx_size++;
1482 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1483 vtx_size += 3;
1484 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1485 vtx_size++;
1486 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1487 vtx_size++;
1488 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1489 vtx_size += 2;
1490 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1491 vtx_size += 2;
1492 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1493 vtx_size++;
1494 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1495 vtx_size += 2;
1496 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1497 vtx_size++;
1498 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1499 vtx_size += 2;
1500 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1501 vtx_size++;
1502 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1503 vtx_size++;
1504 /* blend weight */
1505 if (vtx_fmt & (0x7 << 15))
1506 vtx_size += (vtx_fmt >> 15) & 0x7;
1507 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1508 vtx_size += 3;
1509 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1510 vtx_size += 2;
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1512 vtx_size++;
1513 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1514 vtx_size++;
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1516 vtx_size++;
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1518 vtx_size++;
1519 return vtx_size;
1520 }
1521
1522 static int r100_packet0_check(struct radeon_cs_parser *p,
1523 struct radeon_cs_packet *pkt,
1524 unsigned idx, unsigned reg)
1525 {
1526 struct radeon_cs_reloc *reloc;
1527 struct r100_cs_track *track;
1528 volatile uint32_t *ib;
1529 uint32_t tmp;
1530 int r;
1531 int i, face;
1532 u32 tile_flags = 0;
1533 u32 idx_value;
1534
1535 ib = p->ib->ptr;
1536 track = (struct r100_cs_track *)p->track;
1537
1538 idx_value = radeon_get_ib_value(p, idx);
1539
1540 switch (reg) {
1541 case RADEON_CRTC_GUI_TRIG_VLINE:
1542 r = r100_cs_packet_parse_vline(p);
1543 if (r) {
1544 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1545 idx, reg);
1546 r100_cs_dump_packet(p, pkt);
1547 return r;
1548 }
1549 break;
1550 /* FIXME: only allow PACKET3 blit? easier to check for out of
1551 * range access */
1552 case RADEON_DST_PITCH_OFFSET:
1553 case RADEON_SRC_PITCH_OFFSET:
1554 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1555 if (r)
1556 return r;
1557 break;
1558 case RADEON_RB3D_DEPTHOFFSET:
1559 r = r100_cs_packet_next_reloc(p, &reloc);
1560 if (r) {
1561 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1562 idx, reg);
1563 r100_cs_dump_packet(p, pkt);
1564 return r;
1565 }
1566 track->zb.robj = reloc->robj;
1567 track->zb.offset = idx_value;
1568 track->zb_dirty = true;
1569 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1570 break;
1571 case RADEON_RB3D_COLOROFFSET:
1572 r = r100_cs_packet_next_reloc(p, &reloc);
1573 if (r) {
1574 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1575 idx, reg);
1576 r100_cs_dump_packet(p, pkt);
1577 return r;
1578 }
1579 track->cb[0].robj = reloc->robj;
1580 track->cb[0].offset = idx_value;
1581 track->cb_dirty = true;
1582 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1583 break;
1584 case RADEON_PP_TXOFFSET_0:
1585 case RADEON_PP_TXOFFSET_1:
1586 case RADEON_PP_TXOFFSET_2:
1587 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1588 r = r100_cs_packet_next_reloc(p, &reloc);
1589 if (r) {
1590 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1591 idx, reg);
1592 r100_cs_dump_packet(p, pkt);
1593 return r;
1594 }
1595 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1596 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1597 tile_flags |= RADEON_TXO_MACRO_TILE;
1598 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1599 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1600
1601 tmp = idx_value & ~(0x7 << 2);
1602 tmp |= tile_flags;
1603 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1604 } else
1605 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1606 track->textures[i].robj = reloc->robj;
1607 track->tex_dirty = true;
1608 break;
1609 case RADEON_PP_CUBIC_OFFSET_T0_0:
1610 case RADEON_PP_CUBIC_OFFSET_T0_1:
1611 case RADEON_PP_CUBIC_OFFSET_T0_2:
1612 case RADEON_PP_CUBIC_OFFSET_T0_3:
1613 case RADEON_PP_CUBIC_OFFSET_T0_4:
1614 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1615 r = r100_cs_packet_next_reloc(p, &reloc);
1616 if (r) {
1617 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1618 idx, reg);
1619 r100_cs_dump_packet(p, pkt);
1620 return r;
1621 }
1622 track->textures[0].cube_info[i].offset = idx_value;
1623 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1624 track->textures[0].cube_info[i].robj = reloc->robj;
1625 track->tex_dirty = true;
1626 break;
1627 case RADEON_PP_CUBIC_OFFSET_T1_0:
1628 case RADEON_PP_CUBIC_OFFSET_T1_1:
1629 case RADEON_PP_CUBIC_OFFSET_T1_2:
1630 case RADEON_PP_CUBIC_OFFSET_T1_3:
1631 case RADEON_PP_CUBIC_OFFSET_T1_4:
1632 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1633 r = r100_cs_packet_next_reloc(p, &reloc);
1634 if (r) {
1635 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1636 idx, reg);
1637 r100_cs_dump_packet(p, pkt);
1638 return r;
1639 }
1640 track->textures[1].cube_info[i].offset = idx_value;
1641 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1642 track->textures[1].cube_info[i].robj = reloc->robj;
1643 track->tex_dirty = true;
1644 break;
1645 case RADEON_PP_CUBIC_OFFSET_T2_0:
1646 case RADEON_PP_CUBIC_OFFSET_T2_1:
1647 case RADEON_PP_CUBIC_OFFSET_T2_2:
1648 case RADEON_PP_CUBIC_OFFSET_T2_3:
1649 case RADEON_PP_CUBIC_OFFSET_T2_4:
1650 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1651 r = r100_cs_packet_next_reloc(p, &reloc);
1652 if (r) {
1653 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1654 idx, reg);
1655 r100_cs_dump_packet(p, pkt);
1656 return r;
1657 }
1658 track->textures[2].cube_info[i].offset = idx_value;
1659 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1660 track->textures[2].cube_info[i].robj = reloc->robj;
1661 track->tex_dirty = true;
1662 break;
1663 case RADEON_RE_WIDTH_HEIGHT:
1664 track->maxy = ((idx_value >> 16) & 0x7FF);
1665 track->cb_dirty = true;
1666 track->zb_dirty = true;
1667 break;
1668 case RADEON_RB3D_COLORPITCH:
1669 r = r100_cs_packet_next_reloc(p, &reloc);
1670 if (r) {
1671 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1672 idx, reg);
1673 r100_cs_dump_packet(p, pkt);
1674 return r;
1675 }
1676 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1677 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1678 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1679 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1680 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1681
1682 tmp = idx_value & ~(0x7 << 16);
1683 tmp |= tile_flags;
1684 ib[idx] = tmp;
1685 } else
1686 ib[idx] = idx_value;
1687
1688 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1689 track->cb_dirty = true;
1690 break;
1691 case RADEON_RB3D_DEPTHPITCH:
1692 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1693 track->zb_dirty = true;
1694 break;
1695 case RADEON_RB3D_CNTL:
1696 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1697 case 7:
1698 case 8:
1699 case 9:
1700 case 11:
1701 case 12:
1702 track->cb[0].cpp = 1;
1703 break;
1704 case 3:
1705 case 4:
1706 case 15:
1707 track->cb[0].cpp = 2;
1708 break;
1709 case 6:
1710 track->cb[0].cpp = 4;
1711 break;
1712 default:
1713 DRM_ERROR("Invalid color buffer format (%d) !\n",
1714 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1715 return -EINVAL;
1716 }
1717 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1718 track->cb_dirty = true;
1719 track->zb_dirty = true;
1720 break;
1721 case RADEON_RB3D_ZSTENCILCNTL:
1722 switch (idx_value & 0xf) {
1723 case 0:
1724 track->zb.cpp = 2;
1725 break;
1726 case 2:
1727 case 3:
1728 case 4:
1729 case 5:
1730 case 9:
1731 case 11:
1732 track->zb.cpp = 4;
1733 break;
1734 default:
1735 break;
1736 }
1737 track->zb_dirty = true;
1738 break;
1739 case RADEON_RB3D_ZPASS_ADDR:
1740 r = r100_cs_packet_next_reloc(p, &reloc);
1741 if (r) {
1742 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1743 idx, reg);
1744 r100_cs_dump_packet(p, pkt);
1745 return r;
1746 }
1747 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1748 break;
1749 case RADEON_PP_CNTL:
1750 {
1751 uint32_t temp = idx_value >> 4;
1752 for (i = 0; i < track->num_texture; i++)
1753 track->textures[i].enabled = !!(temp & (1 << i));
1754 track->tex_dirty = true;
1755 }
1756 break;
1757 case RADEON_SE_VF_CNTL:
1758 track->vap_vf_cntl = idx_value;
1759 break;
1760 case RADEON_SE_VTX_FMT:
1761 track->vtx_size = r100_get_vtx_size(idx_value);
1762 break;
1763 case RADEON_PP_TEX_SIZE_0:
1764 case RADEON_PP_TEX_SIZE_1:
1765 case RADEON_PP_TEX_SIZE_2:
1766 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1767 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1768 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1769 track->tex_dirty = true;
1770 break;
1771 case RADEON_PP_TEX_PITCH_0:
1772 case RADEON_PP_TEX_PITCH_1:
1773 case RADEON_PP_TEX_PITCH_2:
1774 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1775 track->textures[i].pitch = idx_value + 32;
1776 track->tex_dirty = true;
1777 break;
1778 case RADEON_PP_TXFILTER_0:
1779 case RADEON_PP_TXFILTER_1:
1780 case RADEON_PP_TXFILTER_2:
1781 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1782 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1783 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1784 tmp = (idx_value >> 23) & 0x7;
1785 if (tmp == 2 || tmp == 6)
1786 track->textures[i].roundup_w = false;
1787 tmp = (idx_value >> 27) & 0x7;
1788 if (tmp == 2 || tmp == 6)
1789 track->textures[i].roundup_h = false;
1790 track->tex_dirty = true;
1791 break;
1792 case RADEON_PP_TXFORMAT_0:
1793 case RADEON_PP_TXFORMAT_1:
1794 case RADEON_PP_TXFORMAT_2:
1795 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1796 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1797 track->textures[i].use_pitch = 1;
1798 } else {
1799 track->textures[i].use_pitch = 0;
1800 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1801 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1802 }
1803 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1804 track->textures[i].tex_coord_type = 2;
1805 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1806 case RADEON_TXFORMAT_I8:
1807 case RADEON_TXFORMAT_RGB332:
1808 case RADEON_TXFORMAT_Y8:
1809 track->textures[i].cpp = 1;
1810 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1811 break;
1812 case RADEON_TXFORMAT_AI88:
1813 case RADEON_TXFORMAT_ARGB1555:
1814 case RADEON_TXFORMAT_RGB565:
1815 case RADEON_TXFORMAT_ARGB4444:
1816 case RADEON_TXFORMAT_VYUY422:
1817 case RADEON_TXFORMAT_YVYU422:
1818 case RADEON_TXFORMAT_SHADOW16:
1819 case RADEON_TXFORMAT_LDUDV655:
1820 case RADEON_TXFORMAT_DUDV88:
1821 track->textures[i].cpp = 2;
1822 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1823 break;
1824 case RADEON_TXFORMAT_ARGB8888:
1825 case RADEON_TXFORMAT_RGBA8888:
1826 case RADEON_TXFORMAT_SHADOW32:
1827 case RADEON_TXFORMAT_LDUDUV8888:
1828 track->textures[i].cpp = 4;
1829 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1830 break;
1831 case RADEON_TXFORMAT_DXT1:
1832 track->textures[i].cpp = 1;
1833 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1834 break;
1835 case RADEON_TXFORMAT_DXT23:
1836 case RADEON_TXFORMAT_DXT45:
1837 track->textures[i].cpp = 1;
1838 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1839 break;
1840 }
1841 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1842 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1843 track->tex_dirty = true;
1844 break;
1845 case RADEON_PP_CUBIC_FACES_0:
1846 case RADEON_PP_CUBIC_FACES_1:
1847 case RADEON_PP_CUBIC_FACES_2:
1848 tmp = idx_value;
1849 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1850 for (face = 0; face < 4; face++) {
1851 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1852 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1853 }
1854 track->tex_dirty = true;
1855 break;
1856 default:
1857 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1858 reg, idx);
1859 return -EINVAL;
1860 }
1861 return 0;
1862 }
1863
1864 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1865 struct radeon_cs_packet *pkt,
1866 struct radeon_bo *robj)
1867 {
1868 unsigned idx;
1869 u32 value;
1870 idx = pkt->idx + 1;
1871 value = radeon_get_ib_value(p, idx + 2);
1872 if ((value + 1) > radeon_bo_size(robj)) {
1873 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1874 "(need %u have %lu) !\n",
1875 value + 1,
1876 radeon_bo_size(robj));
1877 return -EINVAL;
1878 }
1879 return 0;
1880 }
1881
1882 static int r100_packet3_check(struct radeon_cs_parser *p,
1883 struct radeon_cs_packet *pkt)
1884 {
1885 struct radeon_cs_reloc *reloc;
1886 struct r100_cs_track *track;
1887 unsigned idx;
1888 volatile uint32_t *ib;
1889 int r;
1890
1891 ib = p->ib->ptr;
1892 idx = pkt->idx + 1;
1893 track = (struct r100_cs_track *)p->track;
1894 switch (pkt->opcode) {
1895 case PACKET3_3D_LOAD_VBPNTR:
1896 r = r100_packet3_load_vbpntr(p, pkt, idx);
1897 if (r)
1898 return r;
1899 break;
1900 case PACKET3_INDX_BUFFER:
1901 r = r100_cs_packet_next_reloc(p, &reloc);
1902 if (r) {
1903 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1904 r100_cs_dump_packet(p, pkt);
1905 return r;
1906 }
1907 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1908 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1909 if (r) {
1910 return r;
1911 }
1912 break;
1913 case 0x23:
1914 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1915 r = r100_cs_packet_next_reloc(p, &reloc);
1916 if (r) {
1917 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1918 r100_cs_dump_packet(p, pkt);
1919 return r;
1920 }
1921 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1922 track->num_arrays = 1;
1923 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1924
1925 track->arrays[0].robj = reloc->robj;
1926 track->arrays[0].esize = track->vtx_size;
1927
1928 track->max_indx = radeon_get_ib_value(p, idx+1);
1929
1930 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1931 track->immd_dwords = pkt->count - 1;
1932 r = r100_cs_track_check(p->rdev, track);
1933 if (r)
1934 return r;
1935 break;
1936 case PACKET3_3D_DRAW_IMMD:
1937 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1938 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1939 return -EINVAL;
1940 }
1941 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1942 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1943 track->immd_dwords = pkt->count - 1;
1944 r = r100_cs_track_check(p->rdev, track);
1945 if (r)
1946 return r;
1947 break;
1948 /* triggers drawing using in-packet vertex data */
1949 case PACKET3_3D_DRAW_IMMD_2:
1950 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1951 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1952 return -EINVAL;
1953 }
1954 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1955 track->immd_dwords = pkt->count;
1956 r = r100_cs_track_check(p->rdev, track);
1957 if (r)
1958 return r;
1959 break;
1960 /* triggers drawing using in-packet vertex data */
1961 case PACKET3_3D_DRAW_VBUF_2:
1962 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1963 r = r100_cs_track_check(p->rdev, track);
1964 if (r)
1965 return r;
1966 break;
1967 /* triggers drawing of vertex buffers setup elsewhere */
1968 case PACKET3_3D_DRAW_INDX_2:
1969 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1970 r = r100_cs_track_check(p->rdev, track);
1971 if (r)
1972 return r;
1973 break;
1974 /* triggers drawing using indices to vertex buffer */
1975 case PACKET3_3D_DRAW_VBUF:
1976 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1977 r = r100_cs_track_check(p->rdev, track);
1978 if (r)
1979 return r;
1980 break;
1981 /* triggers drawing of vertex buffers setup elsewhere */
1982 case PACKET3_3D_DRAW_INDX:
1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1984 r = r100_cs_track_check(p->rdev, track);
1985 if (r)
1986 return r;
1987 break;
1988 /* triggers drawing using indices to vertex buffer */
1989 case PACKET3_3D_CLEAR_HIZ:
1990 case PACKET3_3D_CLEAR_ZMASK:
1991 if (p->rdev->hyperz_filp != p->filp)
1992 return -EINVAL;
1993 break;
1994 case PACKET3_NOP:
1995 break;
1996 default:
1997 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1998 return -EINVAL;
1999 }
2000 return 0;
2001 }
2002
2003 int r100_cs_parse(struct radeon_cs_parser *p)
2004 {
2005 struct radeon_cs_packet pkt;
2006 struct r100_cs_track *track;
2007 int r;
2008
2009 track = kzalloc(sizeof(*track), GFP_KERNEL);
2010 r100_cs_track_clear(p->rdev, track);
2011 p->track = track;
2012 do {
2013 r = r100_cs_packet_parse(p, &pkt, p->idx);
2014 if (r) {
2015 return r;
2016 }
2017 p->idx += pkt.count + 2;
2018 switch (pkt.type) {
2019 case PACKET_TYPE0:
2020 if (p->rdev->family >= CHIP_R200)
2021 r = r100_cs_parse_packet0(p, &pkt,
2022 p->rdev->config.r100.reg_safe_bm,
2023 p->rdev->config.r100.reg_safe_bm_size,
2024 &r200_packet0_check);
2025 else
2026 r = r100_cs_parse_packet0(p, &pkt,
2027 p->rdev->config.r100.reg_safe_bm,
2028 p->rdev->config.r100.reg_safe_bm_size,
2029 &r100_packet0_check);
2030 break;
2031 case PACKET_TYPE2:
2032 break;
2033 case PACKET_TYPE3:
2034 r = r100_packet3_check(p, &pkt);
2035 break;
2036 default:
2037 DRM_ERROR("Unknown packet type %d !\n",
2038 pkt.type);
2039 return -EINVAL;
2040 }
2041 if (r) {
2042 return r;
2043 }
2044 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2045 return 0;
2046 }
2047
2048
2049 /*
2050 * Global GPU functions
2051 */
2052 void r100_errata(struct radeon_device *rdev)
2053 {
2054 rdev->pll_errata = 0;
2055
2056 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2057 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2058 }
2059
2060 if (rdev->family == CHIP_RV100 ||
2061 rdev->family == CHIP_RS100 ||
2062 rdev->family == CHIP_RS200) {
2063 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2064 }
2065 }
2066
2067 /* Wait for vertical sync on primary CRTC */
2068 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2069 {
2070 uint32_t crtc_gen_cntl, tmp;
2071 int i;
2072
2073 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2074 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2075 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2076 return;
2077 }
2078 /* Clear the CRTC_VBLANK_SAVE bit */
2079 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2080 for (i = 0; i < rdev->usec_timeout; i++) {
2081 tmp = RREG32(RADEON_CRTC_STATUS);
2082 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2083 return;
2084 }
2085 DRM_UDELAY(1);
2086 }
2087 }
2088
2089 /* Wait for vertical sync on secondary CRTC */
2090 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2091 {
2092 uint32_t crtc2_gen_cntl, tmp;
2093 int i;
2094
2095 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2096 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2097 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2098 return;
2099
2100 /* Clear the CRTC_VBLANK_SAVE bit */
2101 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2102 for (i = 0; i < rdev->usec_timeout; i++) {
2103 tmp = RREG32(RADEON_CRTC2_STATUS);
2104 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2105 return;
2106 }
2107 DRM_UDELAY(1);
2108 }
2109 }
2110
2111 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2112 {
2113 unsigned i;
2114 uint32_t tmp;
2115
2116 for (i = 0; i < rdev->usec_timeout; i++) {
2117 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2118 if (tmp >= n) {
2119 return 0;
2120 }
2121 DRM_UDELAY(1);
2122 }
2123 return -1;
2124 }
2125
2126 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2127 {
2128 unsigned i;
2129 uint32_t tmp;
2130
2131 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2132 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2133 " Bad things might happen.\n");
2134 }
2135 for (i = 0; i < rdev->usec_timeout; i++) {
2136 tmp = RREG32(RADEON_RBBM_STATUS);
2137 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2138 return 0;
2139 }
2140 DRM_UDELAY(1);
2141 }
2142 return -1;
2143 }
2144
2145 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2146 {
2147 unsigned i;
2148 uint32_t tmp;
2149
2150 for (i = 0; i < rdev->usec_timeout; i++) {
2151 /* read MC_STATUS */
2152 tmp = RREG32(RADEON_MC_STATUS);
2153 if (tmp & RADEON_MC_IDLE) {
2154 return 0;
2155 }
2156 DRM_UDELAY(1);
2157 }
2158 return -1;
2159 }
2160
2161 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2162 {
2163 lockup->last_cp_rptr = ring->rptr;
2164 lockup->last_jiffies = jiffies;
2165 }
2166
2167 /**
2168 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2169 * @rdev: radeon device structure
2170 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2171 * @cp: radeon_cp structure holding CP information
2172 *
2173 * We don't need to initialize the lockup tracking information as we will either
2174 * have CP rptr to a different value of jiffies wrap around which will force
2175 * initialization of the lockup tracking informations.
2176 *
2177 * A possible false positivie is if we get call after while and last_cp_rptr ==
2178 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2179 * if the elapsed time since last call is bigger than 2 second than we return
2180 * false and update the tracking information. Due to this the caller must call
2181 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2182 * the fencing code should be cautious about that.
2183 *
2184 * Caller should write to the ring to force CP to do something so we don't get
2185 * false positive when CP is just gived nothing to do.
2186 *
2187 **/
2188 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2189 {
2190 unsigned long cjiffies, elapsed;
2191
2192 cjiffies = jiffies;
2193 if (!time_after(cjiffies, lockup->last_jiffies)) {
2194 /* likely a wrap around */
2195 lockup->last_cp_rptr = ring->rptr;
2196 lockup->last_jiffies = jiffies;
2197 return false;
2198 }
2199 if (ring->rptr != lockup->last_cp_rptr) {
2200 /* CP is still working no lockup */
2201 lockup->last_cp_rptr = ring->rptr;
2202 lockup->last_jiffies = jiffies;
2203 return false;
2204 }
2205 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2206 if (elapsed >= 10000) {
2207 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2208 return true;
2209 }
2210 /* give a chance to the GPU ... */
2211 return false;
2212 }
2213
2214 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2215 {
2216 u32 rbbm_status;
2217 int r;
2218
2219 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2220 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2221 r100_gpu_lockup_update(&rdev->config.r100.lockup, ring);
2222 return false;
2223 }
2224 /* force CP activities */
2225 r = radeon_ring_lock(rdev, ring, 2);
2226 if (!r) {
2227 /* PACKET2 NOP */
2228 radeon_ring_write(ring, 0x80000000);
2229 radeon_ring_write(ring, 0x80000000);
2230 radeon_ring_unlock_commit(rdev, ring);
2231 }
2232 ring->rptr = RREG32(ring->rptr_reg);
2233 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, ring);
2234 }
2235
2236 void r100_bm_disable(struct radeon_device *rdev)
2237 {
2238 u32 tmp;
2239
2240 /* disable bus mastering */
2241 tmp = RREG32(R_000030_BUS_CNTL);
2242 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2243 mdelay(1);
2244 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2245 mdelay(1);
2246 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2247 tmp = RREG32(RADEON_BUS_CNTL);
2248 mdelay(1);
2249 pci_clear_master(rdev->pdev);
2250 mdelay(1);
2251 }
2252
2253 int r100_asic_reset(struct radeon_device *rdev)
2254 {
2255 struct r100_mc_save save;
2256 u32 status, tmp;
2257 int ret = 0;
2258
2259 status = RREG32(R_000E40_RBBM_STATUS);
2260 if (!G_000E40_GUI_ACTIVE(status)) {
2261 return 0;
2262 }
2263 r100_mc_stop(rdev, &save);
2264 status = RREG32(R_000E40_RBBM_STATUS);
2265 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2266 /* stop CP */
2267 WREG32(RADEON_CP_CSQ_CNTL, 0);
2268 tmp = RREG32(RADEON_CP_RB_CNTL);
2269 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2270 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2271 WREG32(RADEON_CP_RB_WPTR, 0);
2272 WREG32(RADEON_CP_RB_CNTL, tmp);
2273 /* save PCI state */
2274 pci_save_state(rdev->pdev);
2275 /* disable bus mastering */
2276 r100_bm_disable(rdev);
2277 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2278 S_0000F0_SOFT_RESET_RE(1) |
2279 S_0000F0_SOFT_RESET_PP(1) |
2280 S_0000F0_SOFT_RESET_RB(1));
2281 RREG32(R_0000F0_RBBM_SOFT_RESET);
2282 mdelay(500);
2283 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2284 mdelay(1);
2285 status = RREG32(R_000E40_RBBM_STATUS);
2286 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2287 /* reset CP */
2288 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2289 RREG32(R_0000F0_RBBM_SOFT_RESET);
2290 mdelay(500);
2291 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2292 mdelay(1);
2293 status = RREG32(R_000E40_RBBM_STATUS);
2294 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2295 /* restore PCI & busmastering */
2296 pci_restore_state(rdev->pdev);
2297 r100_enable_bm(rdev);
2298 /* Check if GPU is idle */
2299 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2300 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2301 dev_err(rdev->dev, "failed to reset GPU\n");
2302 rdev->gpu_lockup = true;
2303 ret = -1;
2304 } else
2305 dev_info(rdev->dev, "GPU reset succeed\n");
2306 r100_mc_resume(rdev, &save);
2307 return ret;
2308 }
2309
2310 void r100_set_common_regs(struct radeon_device *rdev)
2311 {
2312 struct drm_device *dev = rdev->ddev;
2313 bool force_dac2 = false;
2314 u32 tmp;
2315
2316 /* set these so they don't interfere with anything */
2317 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2318 WREG32(RADEON_SUBPIC_CNTL, 0);
2319 WREG32(RADEON_VIPH_CONTROL, 0);
2320 WREG32(RADEON_I2C_CNTL_1, 0);
2321 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2322 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2323 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2324
2325 /* always set up dac2 on rn50 and some rv100 as lots
2326 * of servers seem to wire it up to a VGA port but
2327 * don't report it in the bios connector
2328 * table.
2329 */
2330 switch (dev->pdev->device) {
2331 /* RN50 */
2332 case 0x515e:
2333 case 0x5969:
2334 force_dac2 = true;
2335 break;
2336 /* RV100*/
2337 case 0x5159:
2338 case 0x515a:
2339 /* DELL triple head servers */
2340 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2341 ((dev->pdev->subsystem_device == 0x016c) ||
2342 (dev->pdev->subsystem_device == 0x016d) ||
2343 (dev->pdev->subsystem_device == 0x016e) ||
2344 (dev->pdev->subsystem_device == 0x016f) ||
2345 (dev->pdev->subsystem_device == 0x0170) ||
2346 (dev->pdev->subsystem_device == 0x017d) ||
2347 (dev->pdev->subsystem_device == 0x017e) ||
2348 (dev->pdev->subsystem_device == 0x0183) ||
2349 (dev->pdev->subsystem_device == 0x018a) ||
2350 (dev->pdev->subsystem_device == 0x019a)))
2351 force_dac2 = true;
2352 break;
2353 }
2354
2355 if (force_dac2) {
2356 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2357 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2358 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2359
2360 /* For CRT on DAC2, don't turn it on if BIOS didn't
2361 enable it, even it's detected.
2362 */
2363
2364 /* force it to crtc0 */
2365 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2366 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2367 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2368
2369 /* set up the TV DAC */
2370 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2371 RADEON_TV_DAC_STD_MASK |
2372 RADEON_TV_DAC_RDACPD |
2373 RADEON_TV_DAC_GDACPD |
2374 RADEON_TV_DAC_BDACPD |
2375 RADEON_TV_DAC_BGADJ_MASK |
2376 RADEON_TV_DAC_DACADJ_MASK);
2377 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2378 RADEON_TV_DAC_NHOLD |
2379 RADEON_TV_DAC_STD_PS2 |
2380 (0x58 << 16));
2381
2382 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2383 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2384 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2385 }
2386
2387 /* switch PM block to ACPI mode */
2388 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2389 tmp &= ~RADEON_PM_MODE_SEL;
2390 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2391
2392 }
2393
2394 /*
2395 * VRAM info
2396 */
2397 static void r100_vram_get_type(struct radeon_device *rdev)
2398 {
2399 uint32_t tmp;
2400
2401 rdev->mc.vram_is_ddr = false;
2402 if (rdev->flags & RADEON_IS_IGP)
2403 rdev->mc.vram_is_ddr = true;
2404 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2405 rdev->mc.vram_is_ddr = true;
2406 if ((rdev->family == CHIP_RV100) ||
2407 (rdev->family == CHIP_RS100) ||
2408 (rdev->family == CHIP_RS200)) {
2409 tmp = RREG32(RADEON_MEM_CNTL);
2410 if (tmp & RV100_HALF_MODE) {
2411 rdev->mc.vram_width = 32;
2412 } else {
2413 rdev->mc.vram_width = 64;
2414 }
2415 if (rdev->flags & RADEON_SINGLE_CRTC) {
2416 rdev->mc.vram_width /= 4;
2417 rdev->mc.vram_is_ddr = true;
2418 }
2419 } else if (rdev->family <= CHIP_RV280) {
2420 tmp = RREG32(RADEON_MEM_CNTL);
2421 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2422 rdev->mc.vram_width = 128;
2423 } else {
2424 rdev->mc.vram_width = 64;
2425 }
2426 } else {
2427 /* newer IGPs */
2428 rdev->mc.vram_width = 128;
2429 }
2430 }
2431
2432 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2433 {
2434 u32 aper_size;
2435 u8 byte;
2436
2437 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2438
2439 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2440 * that is has the 2nd generation multifunction PCI interface
2441 */
2442 if (rdev->family == CHIP_RV280 ||
2443 rdev->family >= CHIP_RV350) {
2444 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2445 ~RADEON_HDP_APER_CNTL);
2446 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2447 return aper_size * 2;
2448 }
2449
2450 /* Older cards have all sorts of funny issues to deal with. First
2451 * check if it's a multifunction card by reading the PCI config
2452 * header type... Limit those to one aperture size
2453 */
2454 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2455 if (byte & 0x80) {
2456 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2457 DRM_INFO("Limiting VRAM to one aperture\n");
2458 return aper_size;
2459 }
2460
2461 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2462 * have set it up. We don't write this as it's broken on some ASICs but
2463 * we expect the BIOS to have done the right thing (might be too optimistic...)
2464 */
2465 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2466 return aper_size * 2;
2467 return aper_size;
2468 }
2469
2470 void r100_vram_init_sizes(struct radeon_device *rdev)
2471 {
2472 u64 config_aper_size;
2473
2474 /* work out accessible VRAM */
2475 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2476 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2477 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2478 /* FIXME we don't use the second aperture yet when we could use it */
2479 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2480 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2481 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2482 if (rdev->flags & RADEON_IS_IGP) {
2483 uint32_t tom;
2484 /* read NB_TOM to get the amount of ram stolen for the GPU */
2485 tom = RREG32(RADEON_NB_TOM);
2486 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2487 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2488 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2489 } else {
2490 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2491 /* Some production boards of m6 will report 0
2492 * if it's 8 MB
2493 */
2494 if (rdev->mc.real_vram_size == 0) {
2495 rdev->mc.real_vram_size = 8192 * 1024;
2496 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2497 }
2498 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2499 * Novell bug 204882 + along with lots of ubuntu ones
2500 */
2501 if (rdev->mc.aper_size > config_aper_size)
2502 config_aper_size = rdev->mc.aper_size;
2503
2504 if (config_aper_size > rdev->mc.real_vram_size)
2505 rdev->mc.mc_vram_size = config_aper_size;
2506 else
2507 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2508 }
2509 }
2510
2511 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2512 {
2513 uint32_t temp;
2514
2515 temp = RREG32(RADEON_CONFIG_CNTL);
2516 if (state == false) {
2517 temp &= ~RADEON_CFG_VGA_RAM_EN;
2518 temp |= RADEON_CFG_VGA_IO_DIS;
2519 } else {
2520 temp &= ~RADEON_CFG_VGA_IO_DIS;
2521 }
2522 WREG32(RADEON_CONFIG_CNTL, temp);
2523 }
2524
2525 void r100_mc_init(struct radeon_device *rdev)
2526 {
2527 u64 base;
2528
2529 r100_vram_get_type(rdev);
2530 r100_vram_init_sizes(rdev);
2531 base = rdev->mc.aper_base;
2532 if (rdev->flags & RADEON_IS_IGP)
2533 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2534 radeon_vram_location(rdev, &rdev->mc, base);
2535 rdev->mc.gtt_base_align = 0;
2536 if (!(rdev->flags & RADEON_IS_AGP))
2537 radeon_gtt_location(rdev, &rdev->mc);
2538 radeon_update_bandwidth_info(rdev);
2539 }
2540
2541
2542 /*
2543 * Indirect registers accessor
2544 */
2545 void r100_pll_errata_after_index(struct radeon_device *rdev)
2546 {
2547 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2548 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2549 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2550 }
2551 }
2552
2553 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2554 {
2555 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2556 * or the chip could hang on a subsequent access
2557 */
2558 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2559 udelay(5000);
2560 }
2561
2562 /* This function is required to workaround a hardware bug in some (all?)
2563 * revisions of the R300. This workaround should be called after every
2564 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2565 * may not be correct.
2566 */
2567 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2568 uint32_t save, tmp;
2569
2570 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2571 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2572 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2573 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2574 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2575 }
2576 }
2577
2578 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2579 {
2580 uint32_t data;
2581
2582 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2583 r100_pll_errata_after_index(rdev);
2584 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2585 r100_pll_errata_after_data(rdev);
2586 return data;
2587 }
2588
2589 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2590 {
2591 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2592 r100_pll_errata_after_index(rdev);
2593 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2594 r100_pll_errata_after_data(rdev);
2595 }
2596
2597 void r100_set_safe_registers(struct radeon_device *rdev)
2598 {
2599 if (ASIC_IS_RN50(rdev)) {
2600 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2601 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2602 } else if (rdev->family < CHIP_R200) {
2603 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2604 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2605 } else {
2606 r200_set_safe_registers(rdev);
2607 }
2608 }
2609
2610 /*
2611 * Debugfs info
2612 */
2613 #if defined(CONFIG_DEBUG_FS)
2614 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2615 {
2616 struct drm_info_node *node = (struct drm_info_node *) m->private;
2617 struct drm_device *dev = node->minor->dev;
2618 struct radeon_device *rdev = dev->dev_private;
2619 uint32_t reg, value;
2620 unsigned i;
2621
2622 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2623 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2624 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2625 for (i = 0; i < 64; i++) {
2626 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2627 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2628 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2629 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2630 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2631 }
2632 return 0;
2633 }
2634
2635 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2636 {
2637 struct drm_info_node *node = (struct drm_info_node *) m->private;
2638 struct drm_device *dev = node->minor->dev;
2639 struct radeon_device *rdev = dev->dev_private;
2640 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2641 uint32_t rdp, wdp;
2642 unsigned count, i, j;
2643
2644 radeon_ring_free_size(rdev, ring);
2645 rdp = RREG32(RADEON_CP_RB_RPTR);
2646 wdp = RREG32(RADEON_CP_RB_WPTR);
2647 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2648 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2649 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2650 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2651 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2652 seq_printf(m, "%u dwords in ring\n", count);
2653 for (j = 0; j <= count; j++) {
2654 i = (rdp + j) & ring->ptr_mask;
2655 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2656 }
2657 return 0;
2658 }
2659
2660
2661 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2662 {
2663 struct drm_info_node *node = (struct drm_info_node *) m->private;
2664 struct drm_device *dev = node->minor->dev;
2665 struct radeon_device *rdev = dev->dev_private;
2666 uint32_t csq_stat, csq2_stat, tmp;
2667 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2668 unsigned i;
2669
2670 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2671 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2672 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2673 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2674 r_rptr = (csq_stat >> 0) & 0x3ff;
2675 r_wptr = (csq_stat >> 10) & 0x3ff;
2676 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2677 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2678 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2679 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2680 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2681 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2682 seq_printf(m, "Ring rptr %u\n", r_rptr);
2683 seq_printf(m, "Ring wptr %u\n", r_wptr);
2684 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2685 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2686 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2687 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2688 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2689 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2690 seq_printf(m, "Ring fifo:\n");
2691 for (i = 0; i < 256; i++) {
2692 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2693 tmp = RREG32(RADEON_CP_CSQ_DATA);
2694 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2695 }
2696 seq_printf(m, "Indirect1 fifo:\n");
2697 for (i = 256; i <= 512; i++) {
2698 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2699 tmp = RREG32(RADEON_CP_CSQ_DATA);
2700 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2701 }
2702 seq_printf(m, "Indirect2 fifo:\n");
2703 for (i = 640; i < ib1_wptr; i++) {
2704 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2705 tmp = RREG32(RADEON_CP_CSQ_DATA);
2706 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2707 }
2708 return 0;
2709 }
2710
2711 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2712 {
2713 struct drm_info_node *node = (struct drm_info_node *) m->private;
2714 struct drm_device *dev = node->minor->dev;
2715 struct radeon_device *rdev = dev->dev_private;
2716 uint32_t tmp;
2717
2718 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2719 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2720 tmp = RREG32(RADEON_MC_FB_LOCATION);
2721 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2722 tmp = RREG32(RADEON_BUS_CNTL);
2723 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2724 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2725 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2726 tmp = RREG32(RADEON_AGP_BASE);
2727 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2728 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2729 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2730 tmp = RREG32(0x01D0);
2731 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2732 tmp = RREG32(RADEON_AIC_LO_ADDR);
2733 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2734 tmp = RREG32(RADEON_AIC_HI_ADDR);
2735 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2736 tmp = RREG32(0x01E4);
2737 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2738 return 0;
2739 }
2740
2741 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2742 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2743 };
2744
2745 static struct drm_info_list r100_debugfs_cp_list[] = {
2746 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2747 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2748 };
2749
2750 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2751 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2752 };
2753 #endif
2754
2755 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2756 {
2757 #if defined(CONFIG_DEBUG_FS)
2758 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2759 #else
2760 return 0;
2761 #endif
2762 }
2763
2764 int r100_debugfs_cp_init(struct radeon_device *rdev)
2765 {
2766 #if defined(CONFIG_DEBUG_FS)
2767 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2768 #else
2769 return 0;
2770 #endif
2771 }
2772
2773 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2774 {
2775 #if defined(CONFIG_DEBUG_FS)
2776 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2777 #else
2778 return 0;
2779 #endif
2780 }
2781
2782 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2783 uint32_t tiling_flags, uint32_t pitch,
2784 uint32_t offset, uint32_t obj_size)
2785 {
2786 int surf_index = reg * 16;
2787 int flags = 0;
2788
2789 if (rdev->family <= CHIP_RS200) {
2790 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2791 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2792 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2793 if (tiling_flags & RADEON_TILING_MACRO)
2794 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2795 } else if (rdev->family <= CHIP_RV280) {
2796 if (tiling_flags & (RADEON_TILING_MACRO))
2797 flags |= R200_SURF_TILE_COLOR_MACRO;
2798 if (tiling_flags & RADEON_TILING_MICRO)
2799 flags |= R200_SURF_TILE_COLOR_MICRO;
2800 } else {
2801 if (tiling_flags & RADEON_TILING_MACRO)
2802 flags |= R300_SURF_TILE_MACRO;
2803 if (tiling_flags & RADEON_TILING_MICRO)
2804 flags |= R300_SURF_TILE_MICRO;
2805 }
2806
2807 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2808 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2809 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2810 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2811
2812 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2813 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2814 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2815 if (ASIC_IS_RN50(rdev))
2816 pitch /= 16;
2817 }
2818
2819 /* r100/r200 divide by 16 */
2820 if (rdev->family < CHIP_R300)
2821 flags |= pitch / 16;
2822 else
2823 flags |= pitch / 8;
2824
2825
2826 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2827 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2828 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2829 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2830 return 0;
2831 }
2832
2833 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2834 {
2835 int surf_index = reg * 16;
2836 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2837 }
2838
2839 void r100_bandwidth_update(struct radeon_device *rdev)
2840 {
2841 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2842 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2843 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2844 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2845 fixed20_12 memtcas_ff[8] = {
2846 dfixed_init(1),
2847 dfixed_init(2),
2848 dfixed_init(3),
2849 dfixed_init(0),
2850 dfixed_init_half(1),
2851 dfixed_init_half(2),
2852 dfixed_init(0),
2853 };
2854 fixed20_12 memtcas_rs480_ff[8] = {
2855 dfixed_init(0),
2856 dfixed_init(1),
2857 dfixed_init(2),
2858 dfixed_init(3),
2859 dfixed_init(0),
2860 dfixed_init_half(1),
2861 dfixed_init_half(2),
2862 dfixed_init_half(3),
2863 };
2864 fixed20_12 memtcas2_ff[8] = {
2865 dfixed_init(0),
2866 dfixed_init(1),
2867 dfixed_init(2),
2868 dfixed_init(3),
2869 dfixed_init(4),
2870 dfixed_init(5),
2871 dfixed_init(6),
2872 dfixed_init(7),
2873 };
2874 fixed20_12 memtrbs[8] = {
2875 dfixed_init(1),
2876 dfixed_init_half(1),
2877 dfixed_init(2),
2878 dfixed_init_half(2),
2879 dfixed_init(3),
2880 dfixed_init_half(3),
2881 dfixed_init(4),
2882 dfixed_init_half(4)
2883 };
2884 fixed20_12 memtrbs_r4xx[8] = {
2885 dfixed_init(4),
2886 dfixed_init(5),
2887 dfixed_init(6),
2888 dfixed_init(7),
2889 dfixed_init(8),
2890 dfixed_init(9),
2891 dfixed_init(10),
2892 dfixed_init(11)
2893 };
2894 fixed20_12 min_mem_eff;
2895 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2896 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2897 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2898 disp_drain_rate2, read_return_rate;
2899 fixed20_12 time_disp1_drop_priority;
2900 int c;
2901 int cur_size = 16; /* in octawords */
2902 int critical_point = 0, critical_point2;
2903 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2904 int stop_req, max_stop_req;
2905 struct drm_display_mode *mode1 = NULL;
2906 struct drm_display_mode *mode2 = NULL;
2907 uint32_t pixel_bytes1 = 0;
2908 uint32_t pixel_bytes2 = 0;
2909
2910 radeon_update_display_priority(rdev);
2911
2912 if (rdev->mode_info.crtcs[0]->base.enabled) {
2913 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2914 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2915 }
2916 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2917 if (rdev->mode_info.crtcs[1]->base.enabled) {
2918 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2919 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2920 }
2921 }
2922
2923 min_mem_eff.full = dfixed_const_8(0);
2924 /* get modes */
2925 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2926 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2927 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2928 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2929 /* check crtc enables */
2930 if (mode2)
2931 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2932 if (mode1)
2933 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2934 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2935 }
2936
2937 /*
2938 * determine is there is enough bw for current mode
2939 */
2940 sclk_ff = rdev->pm.sclk;
2941 mclk_ff = rdev->pm.mclk;
2942
2943 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2944 temp_ff.full = dfixed_const(temp);
2945 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2946
2947 pix_clk.full = 0;
2948 pix_clk2.full = 0;
2949 peak_disp_bw.full = 0;
2950 if (mode1) {
2951 temp_ff.full = dfixed_const(1000);
2952 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2953 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2954 temp_ff.full = dfixed_const(pixel_bytes1);
2955 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2956 }
2957 if (mode2) {
2958 temp_ff.full = dfixed_const(1000);
2959 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2960 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2961 temp_ff.full = dfixed_const(pixel_bytes2);
2962 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2963 }
2964
2965 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2966 if (peak_disp_bw.full >= mem_bw.full) {
2967 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2968 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2969 }
2970
2971 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2972 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2973 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2974 mem_trcd = ((temp >> 2) & 0x3) + 1;
2975 mem_trp = ((temp & 0x3)) + 1;
2976 mem_tras = ((temp & 0x70) >> 4) + 1;
2977 } else if (rdev->family == CHIP_R300 ||
2978 rdev->family == CHIP_R350) { /* r300, r350 */
2979 mem_trcd = (temp & 0x7) + 1;
2980 mem_trp = ((temp >> 8) & 0x7) + 1;
2981 mem_tras = ((temp >> 11) & 0xf) + 4;
2982 } else if (rdev->family == CHIP_RV350 ||
2983 rdev->family <= CHIP_RV380) {
2984 /* rv3x0 */
2985 mem_trcd = (temp & 0x7) + 3;
2986 mem_trp = ((temp >> 8) & 0x7) + 3;
2987 mem_tras = ((temp >> 11) & 0xf) + 6;
2988 } else if (rdev->family == CHIP_R420 ||
2989 rdev->family == CHIP_R423 ||
2990 rdev->family == CHIP_RV410) {
2991 /* r4xx */
2992 mem_trcd = (temp & 0xf) + 3;
2993 if (mem_trcd > 15)
2994 mem_trcd = 15;
2995 mem_trp = ((temp >> 8) & 0xf) + 3;
2996 if (mem_trp > 15)
2997 mem_trp = 15;
2998 mem_tras = ((temp >> 12) & 0x1f) + 6;
2999 if (mem_tras > 31)
3000 mem_tras = 31;
3001 } else { /* RV200, R200 */
3002 mem_trcd = (temp & 0x7) + 1;
3003 mem_trp = ((temp >> 8) & 0x7) + 1;
3004 mem_tras = ((temp >> 12) & 0xf) + 4;
3005 }
3006 /* convert to FF */
3007 trcd_ff.full = dfixed_const(mem_trcd);
3008 trp_ff.full = dfixed_const(mem_trp);
3009 tras_ff.full = dfixed_const(mem_tras);
3010
3011 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3012 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3013 data = (temp & (7 << 20)) >> 20;
3014 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3015 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3016 tcas_ff = memtcas_rs480_ff[data];
3017 else
3018 tcas_ff = memtcas_ff[data];
3019 } else
3020 tcas_ff = memtcas2_ff[data];
3021
3022 if (rdev->family == CHIP_RS400 ||
3023 rdev->family == CHIP_RS480) {
3024 /* extra cas latency stored in bits 23-25 0-4 clocks */
3025 data = (temp >> 23) & 0x7;
3026 if (data < 5)
3027 tcas_ff.full += dfixed_const(data);
3028 }
3029
3030 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3031 /* on the R300, Tcas is included in Trbs.
3032 */
3033 temp = RREG32(RADEON_MEM_CNTL);
3034 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3035 if (data == 1) {
3036 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3037 temp = RREG32(R300_MC_IND_INDEX);
3038 temp &= ~R300_MC_IND_ADDR_MASK;
3039 temp |= R300_MC_READ_CNTL_CD_mcind;
3040 WREG32(R300_MC_IND_INDEX, temp);
3041 temp = RREG32(R300_MC_IND_DATA);
3042 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3043 } else {
3044 temp = RREG32(R300_MC_READ_CNTL_AB);
3045 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3046 }
3047 } else {
3048 temp = RREG32(R300_MC_READ_CNTL_AB);
3049 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3050 }
3051 if (rdev->family == CHIP_RV410 ||
3052 rdev->family == CHIP_R420 ||
3053 rdev->family == CHIP_R423)
3054 trbs_ff = memtrbs_r4xx[data];
3055 else
3056 trbs_ff = memtrbs[data];
3057 tcas_ff.full += trbs_ff.full;
3058 }
3059
3060 sclk_eff_ff.full = sclk_ff.full;
3061
3062 if (rdev->flags & RADEON_IS_AGP) {
3063 fixed20_12 agpmode_ff;
3064 agpmode_ff.full = dfixed_const(radeon_agpmode);
3065 temp_ff.full = dfixed_const_666(16);
3066 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3067 }
3068 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3069
3070 if (ASIC_IS_R300(rdev)) {
3071 sclk_delay_ff.full = dfixed_const(250);
3072 } else {
3073 if ((rdev->family == CHIP_RV100) ||
3074 rdev->flags & RADEON_IS_IGP) {
3075 if (rdev->mc.vram_is_ddr)
3076 sclk_delay_ff.full = dfixed_const(41);
3077 else
3078 sclk_delay_ff.full = dfixed_const(33);
3079 } else {
3080 if (rdev->mc.vram_width == 128)
3081 sclk_delay_ff.full = dfixed_const(57);
3082 else
3083 sclk_delay_ff.full = dfixed_const(41);
3084 }
3085 }
3086
3087 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3088
3089 if (rdev->mc.vram_is_ddr) {
3090 if (rdev->mc.vram_width == 32) {
3091 k1.full = dfixed_const(40);
3092 c = 3;
3093 } else {
3094 k1.full = dfixed_const(20);
3095 c = 1;
3096 }
3097 } else {
3098 k1.full = dfixed_const(40);
3099 c = 3;
3100 }
3101
3102 temp_ff.full = dfixed_const(2);
3103 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3104 temp_ff.full = dfixed_const(c);
3105 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3106 temp_ff.full = dfixed_const(4);
3107 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3108 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3109 mc_latency_mclk.full += k1.full;
3110
3111 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3112 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3113
3114 /*
3115 HW cursor time assuming worst case of full size colour cursor.
3116 */
3117 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3118 temp_ff.full += trcd_ff.full;
3119 if (temp_ff.full < tras_ff.full)
3120 temp_ff.full = tras_ff.full;
3121 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3122
3123 temp_ff.full = dfixed_const(cur_size);
3124 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3125 /*
3126 Find the total latency for the display data.
3127 */
3128 disp_latency_overhead.full = dfixed_const(8);
3129 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3130 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3131 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3132
3133 if (mc_latency_mclk.full > mc_latency_sclk.full)
3134 disp_latency.full = mc_latency_mclk.full;
3135 else
3136 disp_latency.full = mc_latency_sclk.full;
3137
3138 /* setup Max GRPH_STOP_REQ default value */
3139 if (ASIC_IS_RV100(rdev))
3140 max_stop_req = 0x5c;
3141 else
3142 max_stop_req = 0x7c;
3143
3144 if (mode1) {
3145 /* CRTC1
3146 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3147 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3148 */
3149 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3150
3151 if (stop_req > max_stop_req)
3152 stop_req = max_stop_req;
3153
3154 /*
3155 Find the drain rate of the display buffer.
3156 */
3157 temp_ff.full = dfixed_const((16/pixel_bytes1));
3158 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3159
3160 /*
3161 Find the critical point of the display buffer.
3162 */
3163 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3164 crit_point_ff.full += dfixed_const_half(0);
3165
3166 critical_point = dfixed_trunc(crit_point_ff);
3167
3168 if (rdev->disp_priority == 2) {
3169 critical_point = 0;
3170 }
3171
3172 /*
3173 The critical point should never be above max_stop_req-4. Setting
3174 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3175 */
3176 if (max_stop_req - critical_point < 4)
3177 critical_point = 0;
3178
3179 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3180 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3181 critical_point = 0x10;
3182 }
3183
3184 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3185 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3186 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3187 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3188 if ((rdev->family == CHIP_R350) &&
3189 (stop_req > 0x15)) {
3190 stop_req -= 0x10;
3191 }
3192 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3193 temp |= RADEON_GRPH_BUFFER_SIZE;
3194 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3195 RADEON_GRPH_CRITICAL_AT_SOF |
3196 RADEON_GRPH_STOP_CNTL);
3197 /*
3198 Write the result into the register.
3199 */
3200 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3201 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3202
3203 #if 0
3204 if ((rdev->family == CHIP_RS400) ||
3205 (rdev->family == CHIP_RS480)) {
3206 /* attempt to program RS400 disp regs correctly ??? */
3207 temp = RREG32(RS400_DISP1_REG_CNTL);
3208 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3209 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3210 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3211 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3212 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3213 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3214 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3215 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3216 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3217 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3218 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3219 }
3220 #endif
3221
3222 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3223 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3224 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3225 }
3226
3227 if (mode2) {
3228 u32 grph2_cntl;
3229 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3230
3231 if (stop_req > max_stop_req)
3232 stop_req = max_stop_req;
3233
3234 /*
3235 Find the drain rate of the display buffer.
3236 */
3237 temp_ff.full = dfixed_const((16/pixel_bytes2));
3238 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3239
3240 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3241 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3242 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3243 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3244 if ((rdev->family == CHIP_R350) &&
3245 (stop_req > 0x15)) {
3246 stop_req -= 0x10;
3247 }
3248 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3249 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3250 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3251 RADEON_GRPH_CRITICAL_AT_SOF |
3252 RADEON_GRPH_STOP_CNTL);
3253
3254 if ((rdev->family == CHIP_RS100) ||
3255 (rdev->family == CHIP_RS200))
3256 critical_point2 = 0;
3257 else {
3258 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3259 temp_ff.full = dfixed_const(temp);
3260 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3261 if (sclk_ff.full < temp_ff.full)
3262 temp_ff.full = sclk_ff.full;
3263
3264 read_return_rate.full = temp_ff.full;
3265
3266 if (mode1) {
3267 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3268 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3269 } else {
3270 time_disp1_drop_priority.full = 0;
3271 }
3272 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3273 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3274 crit_point_ff.full += dfixed_const_half(0);
3275
3276 critical_point2 = dfixed_trunc(crit_point_ff);
3277
3278 if (rdev->disp_priority == 2) {
3279 critical_point2 = 0;
3280 }
3281
3282 if (max_stop_req - critical_point2 < 4)
3283 critical_point2 = 0;
3284
3285 }
3286
3287 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3288 /* some R300 cards have problem with this set to 0 */
3289 critical_point2 = 0x10;
3290 }
3291
3292 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3293 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3294
3295 if ((rdev->family == CHIP_RS400) ||
3296 (rdev->family == CHIP_RS480)) {
3297 #if 0
3298 /* attempt to program RS400 disp2 regs correctly ??? */
3299 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3300 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3301 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3302 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3303 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3304 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3305 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3306 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3307 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3308 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3309 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3310 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3311 #endif
3312 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3313 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3314 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3315 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3316 }
3317
3318 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3319 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3320 }
3321 }
3322
3323 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3324 {
3325 DRM_ERROR("pitch %d\n", t->pitch);
3326 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3327 DRM_ERROR("width %d\n", t->width);
3328 DRM_ERROR("width_11 %d\n", t->width_11);
3329 DRM_ERROR("height %d\n", t->height);
3330 DRM_ERROR("height_11 %d\n", t->height_11);
3331 DRM_ERROR("num levels %d\n", t->num_levels);
3332 DRM_ERROR("depth %d\n", t->txdepth);
3333 DRM_ERROR("bpp %d\n", t->cpp);
3334 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3335 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3336 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3337 DRM_ERROR("compress format %d\n", t->compress_format);
3338 }
3339
3340 static int r100_track_compress_size(int compress_format, int w, int h)
3341 {
3342 int block_width, block_height, block_bytes;
3343 int wblocks, hblocks;
3344 int min_wblocks;
3345 int sz;
3346
3347 block_width = 4;
3348 block_height = 4;
3349
3350 switch (compress_format) {
3351 case R100_TRACK_COMP_DXT1:
3352 block_bytes = 8;
3353 min_wblocks = 4;
3354 break;
3355 default:
3356 case R100_TRACK_COMP_DXT35:
3357 block_bytes = 16;
3358 min_wblocks = 2;
3359 break;
3360 }
3361
3362 hblocks = (h + block_height - 1) / block_height;
3363 wblocks = (w + block_width - 1) / block_width;
3364 if (wblocks < min_wblocks)
3365 wblocks = min_wblocks;
3366 sz = wblocks * hblocks * block_bytes;
3367 return sz;
3368 }
3369
3370 static int r100_cs_track_cube(struct radeon_device *rdev,
3371 struct r100_cs_track *track, unsigned idx)
3372 {
3373 unsigned face, w, h;
3374 struct radeon_bo *cube_robj;
3375 unsigned long size;
3376 unsigned compress_format = track->textures[idx].compress_format;
3377
3378 for (face = 0; face < 5; face++) {
3379 cube_robj = track->textures[idx].cube_info[face].robj;
3380 w = track->textures[idx].cube_info[face].width;
3381 h = track->textures[idx].cube_info[face].height;
3382
3383 if (compress_format) {
3384 size = r100_track_compress_size(compress_format, w, h);
3385 } else
3386 size = w * h;
3387 size *= track->textures[idx].cpp;
3388
3389 size += track->textures[idx].cube_info[face].offset;
3390
3391 if (size > radeon_bo_size(cube_robj)) {
3392 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3393 size, radeon_bo_size(cube_robj));
3394 r100_cs_track_texture_print(&track->textures[idx]);
3395 return -1;
3396 }
3397 }
3398 return 0;
3399 }
3400
3401 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3402 struct r100_cs_track *track)
3403 {
3404 struct radeon_bo *robj;
3405 unsigned long size;
3406 unsigned u, i, w, h, d;
3407 int ret;
3408
3409 for (u = 0; u < track->num_texture; u++) {
3410 if (!track->textures[u].enabled)
3411 continue;
3412 if (track->textures[u].lookup_disable)
3413 continue;
3414 robj = track->textures[u].robj;
3415 if (robj == NULL) {
3416 DRM_ERROR("No texture bound to unit %u\n", u);
3417 return -EINVAL;
3418 }
3419 size = 0;
3420 for (i = 0; i <= track->textures[u].num_levels; i++) {
3421 if (track->textures[u].use_pitch) {
3422 if (rdev->family < CHIP_R300)
3423 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3424 else
3425 w = track->textures[u].pitch / (1 << i);
3426 } else {
3427 w = track->textures[u].width;
3428 if (rdev->family >= CHIP_RV515)
3429 w |= track->textures[u].width_11;
3430 w = w / (1 << i);
3431 if (track->textures[u].roundup_w)
3432 w = roundup_pow_of_two(w);
3433 }
3434 h = track->textures[u].height;
3435 if (rdev->family >= CHIP_RV515)
3436 h |= track->textures[u].height_11;
3437 h = h / (1 << i);
3438 if (track->textures[u].roundup_h)
3439 h = roundup_pow_of_two(h);
3440 if (track->textures[u].tex_coord_type == 1) {
3441 d = (1 << track->textures[u].txdepth) / (1 << i);
3442 if (!d)
3443 d = 1;
3444 } else {
3445 d = 1;
3446 }
3447 if (track->textures[u].compress_format) {
3448
3449 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3450 /* compressed textures are block based */
3451 } else
3452 size += w * h * d;
3453 }
3454 size *= track->textures[u].cpp;
3455
3456 switch (track->textures[u].tex_coord_type) {
3457 case 0:
3458 case 1:
3459 break;
3460 case 2:
3461 if (track->separate_cube) {
3462 ret = r100_cs_track_cube(rdev, track, u);
3463 if (ret)
3464 return ret;
3465 } else
3466 size *= 6;
3467 break;
3468 default:
3469 DRM_ERROR("Invalid texture coordinate type %u for unit "
3470 "%u\n", track->textures[u].tex_coord_type, u);
3471 return -EINVAL;
3472 }
3473 if (size > radeon_bo_size(robj)) {
3474 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3475 "%lu\n", u, size, radeon_bo_size(robj));
3476 r100_cs_track_texture_print(&track->textures[u]);
3477 return -EINVAL;
3478 }
3479 }
3480 return 0;
3481 }
3482
3483 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3484 {
3485 unsigned i;
3486 unsigned long size;
3487 unsigned prim_walk;
3488 unsigned nverts;
3489 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3490
3491 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3492 !track->blend_read_enable)
3493 num_cb = 0;
3494
3495 for (i = 0; i < num_cb; i++) {
3496 if (track->cb[i].robj == NULL) {
3497 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3498 return -EINVAL;
3499 }
3500 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3501 size += track->cb[i].offset;
3502 if (size > radeon_bo_size(track->cb[i].robj)) {
3503 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3504 "(need %lu have %lu) !\n", i, size,
3505 radeon_bo_size(track->cb[i].robj));
3506 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3507 i, track->cb[i].pitch, track->cb[i].cpp,
3508 track->cb[i].offset, track->maxy);
3509 return -EINVAL;
3510 }
3511 }
3512 track->cb_dirty = false;
3513
3514 if (track->zb_dirty && track->z_enabled) {
3515 if (track->zb.robj == NULL) {
3516 DRM_ERROR("[drm] No buffer for z buffer !\n");
3517 return -EINVAL;
3518 }
3519 size = track->zb.pitch * track->zb.cpp * track->maxy;
3520 size += track->zb.offset;
3521 if (size > radeon_bo_size(track->zb.robj)) {
3522 DRM_ERROR("[drm] Buffer too small for z buffer "
3523 "(need %lu have %lu) !\n", size,
3524 radeon_bo_size(track->zb.robj));
3525 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3526 track->zb.pitch, track->zb.cpp,
3527 track->zb.offset, track->maxy);
3528 return -EINVAL;
3529 }
3530 }
3531 track->zb_dirty = false;
3532
3533 if (track->aa_dirty && track->aaresolve) {
3534 if (track->aa.robj == NULL) {
3535 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3536 return -EINVAL;
3537 }
3538 /* I believe the format comes from colorbuffer0. */
3539 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3540 size += track->aa.offset;
3541 if (size > radeon_bo_size(track->aa.robj)) {
3542 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3543 "(need %lu have %lu) !\n", i, size,
3544 radeon_bo_size(track->aa.robj));
3545 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3546 i, track->aa.pitch, track->cb[0].cpp,
3547 track->aa.offset, track->maxy);
3548 return -EINVAL;
3549 }
3550 }
3551 track->aa_dirty = false;
3552
3553 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3554 if (track->vap_vf_cntl & (1 << 14)) {
3555 nverts = track->vap_alt_nverts;
3556 } else {
3557 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3558 }
3559 switch (prim_walk) {
3560 case 1:
3561 for (i = 0; i < track->num_arrays; i++) {
3562 size = track->arrays[i].esize * track->max_indx * 4;
3563 if (track->arrays[i].robj == NULL) {
3564 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3565 "bound\n", prim_walk, i);
3566 return -EINVAL;
3567 }
3568 if (size > radeon_bo_size(track->arrays[i].robj)) {
3569 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3570 "need %lu dwords have %lu dwords\n",
3571 prim_walk, i, size >> 2,
3572 radeon_bo_size(track->arrays[i].robj)
3573 >> 2);
3574 DRM_ERROR("Max indices %u\n", track->max_indx);
3575 return -EINVAL;
3576 }
3577 }
3578 break;
3579 case 2:
3580 for (i = 0; i < track->num_arrays; i++) {
3581 size = track->arrays[i].esize * (nverts - 1) * 4;
3582 if (track->arrays[i].robj == NULL) {
3583 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3584 "bound\n", prim_walk, i);
3585 return -EINVAL;
3586 }
3587 if (size > radeon_bo_size(track->arrays[i].robj)) {
3588 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3589 "need %lu dwords have %lu dwords\n",
3590 prim_walk, i, size >> 2,
3591 radeon_bo_size(track->arrays[i].robj)
3592 >> 2);
3593 return -EINVAL;
3594 }
3595 }
3596 break;
3597 case 3:
3598 size = track->vtx_size * nverts;
3599 if (size != track->immd_dwords) {
3600 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3601 track->immd_dwords, size);
3602 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3603 nverts, track->vtx_size);
3604 return -EINVAL;
3605 }
3606 break;
3607 default:
3608 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3609 prim_walk);
3610 return -EINVAL;
3611 }
3612
3613 if (track->tex_dirty) {
3614 track->tex_dirty = false;
3615 return r100_cs_track_texture_check(rdev, track);
3616 }
3617 return 0;
3618 }
3619
3620 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3621 {
3622 unsigned i, face;
3623
3624 track->cb_dirty = true;
3625 track->zb_dirty = true;
3626 track->tex_dirty = true;
3627 track->aa_dirty = true;
3628
3629 if (rdev->family < CHIP_R300) {
3630 track->num_cb = 1;
3631 if (rdev->family <= CHIP_RS200)
3632 track->num_texture = 3;
3633 else
3634 track->num_texture = 6;
3635 track->maxy = 2048;
3636 track->separate_cube = 1;
3637 } else {
3638 track->num_cb = 4;
3639 track->num_texture = 16;
3640 track->maxy = 4096;
3641 track->separate_cube = 0;
3642 track->aaresolve = false;
3643 track->aa.robj = NULL;
3644 }
3645
3646 for (i = 0; i < track->num_cb; i++) {
3647 track->cb[i].robj = NULL;
3648 track->cb[i].pitch = 8192;
3649 track->cb[i].cpp = 16;
3650 track->cb[i].offset = 0;
3651 }
3652 track->z_enabled = true;
3653 track->zb.robj = NULL;
3654 track->zb.pitch = 8192;
3655 track->zb.cpp = 4;
3656 track->zb.offset = 0;
3657 track->vtx_size = 0x7F;
3658 track->immd_dwords = 0xFFFFFFFFUL;
3659 track->num_arrays = 11;
3660 track->max_indx = 0x00FFFFFFUL;
3661 for (i = 0; i < track->num_arrays; i++) {
3662 track->arrays[i].robj = NULL;
3663 track->arrays[i].esize = 0x7F;
3664 }
3665 for (i = 0; i < track->num_texture; i++) {
3666 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3667 track->textures[i].pitch = 16536;
3668 track->textures[i].width = 16536;
3669 track->textures[i].height = 16536;
3670 track->textures[i].width_11 = 1 << 11;
3671 track->textures[i].height_11 = 1 << 11;
3672 track->textures[i].num_levels = 12;
3673 if (rdev->family <= CHIP_RS200) {
3674 track->textures[i].tex_coord_type = 0;
3675 track->textures[i].txdepth = 0;
3676 } else {
3677 track->textures[i].txdepth = 16;
3678 track->textures[i].tex_coord_type = 1;
3679 }
3680 track->textures[i].cpp = 64;
3681 track->textures[i].robj = NULL;
3682 /* CS IB emission code makes sure texture unit are disabled */
3683 track->textures[i].enabled = false;
3684 track->textures[i].lookup_disable = false;
3685 track->textures[i].roundup_w = true;
3686 track->textures[i].roundup_h = true;
3687 if (track->separate_cube)
3688 for (face = 0; face < 5; face++) {
3689 track->textures[i].cube_info[face].robj = NULL;
3690 track->textures[i].cube_info[face].width = 16536;
3691 track->textures[i].cube_info[face].height = 16536;
3692 track->textures[i].cube_info[face].offset = 0;
3693 }
3694 }
3695 }
3696
3697 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3698 {
3699 uint32_t scratch;
3700 uint32_t tmp = 0;
3701 unsigned i;
3702 int r;
3703
3704 r = radeon_scratch_get(rdev, &scratch);
3705 if (r) {
3706 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3707 return r;
3708 }
3709 WREG32(scratch, 0xCAFEDEAD);
3710 r = radeon_ring_lock(rdev, ring, 2);
3711 if (r) {
3712 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3713 radeon_scratch_free(rdev, scratch);
3714 return r;
3715 }
3716 radeon_ring_write(ring, PACKET0(scratch, 0));
3717 radeon_ring_write(ring, 0xDEADBEEF);
3718 radeon_ring_unlock_commit(rdev, ring);
3719 for (i = 0; i < rdev->usec_timeout; i++) {
3720 tmp = RREG32(scratch);
3721 if (tmp == 0xDEADBEEF) {
3722 break;
3723 }
3724 DRM_UDELAY(1);
3725 }
3726 if (i < rdev->usec_timeout) {
3727 DRM_INFO("ring test succeeded in %d usecs\n", i);
3728 } else {
3729 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3730 scratch, tmp);
3731 r = -EINVAL;
3732 }
3733 radeon_scratch_free(rdev, scratch);
3734 return r;
3735 }
3736
3737 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3738 {
3739 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3740
3741 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3742 radeon_ring_write(ring, ib->gpu_addr);
3743 radeon_ring_write(ring, ib->length_dw);
3744 }
3745
3746 int r100_ib_test(struct radeon_device *rdev)
3747 {
3748 struct radeon_ib *ib;
3749 uint32_t scratch;
3750 uint32_t tmp = 0;
3751 unsigned i;
3752 int r;
3753
3754 r = radeon_scratch_get(rdev, &scratch);
3755 if (r) {
3756 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3757 return r;
3758 }
3759 WREG32(scratch, 0xCAFEDEAD);
3760 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3761 if (r) {
3762 return r;
3763 }
3764 ib->ptr[0] = PACKET0(scratch, 0);
3765 ib->ptr[1] = 0xDEADBEEF;
3766 ib->ptr[2] = PACKET2(0);
3767 ib->ptr[3] = PACKET2(0);
3768 ib->ptr[4] = PACKET2(0);
3769 ib->ptr[5] = PACKET2(0);
3770 ib->ptr[6] = PACKET2(0);
3771 ib->ptr[7] = PACKET2(0);
3772 ib->length_dw = 8;
3773 r = radeon_ib_schedule(rdev, ib);
3774 if (r) {
3775 radeon_scratch_free(rdev, scratch);
3776 radeon_ib_free(rdev, &ib);
3777 return r;
3778 }
3779 r = radeon_fence_wait(ib->fence, false);
3780 if (r) {
3781 return r;
3782 }
3783 for (i = 0; i < rdev->usec_timeout; i++) {
3784 tmp = RREG32(scratch);
3785 if (tmp == 0xDEADBEEF) {
3786 break;
3787 }
3788 DRM_UDELAY(1);
3789 }
3790 if (i < rdev->usec_timeout) {
3791 DRM_INFO("ib test succeeded in %u usecs\n", i);
3792 } else {
3793 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3794 scratch, tmp);
3795 r = -EINVAL;
3796 }
3797 radeon_scratch_free(rdev, scratch);
3798 radeon_ib_free(rdev, &ib);
3799 return r;
3800 }
3801
3802 void r100_ib_fini(struct radeon_device *rdev)
3803 {
3804 radeon_ib_pool_suspend(rdev);
3805 radeon_ib_pool_fini(rdev);
3806 }
3807
3808 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3809 {
3810 /* Shutdown CP we shouldn't need to do that but better be safe than
3811 * sorry
3812 */
3813 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3814 WREG32(R_000740_CP_CSQ_CNTL, 0);
3815
3816 /* Save few CRTC registers */
3817 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3818 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3819 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3820 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3821 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3822 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3823 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3824 }
3825
3826 /* Disable VGA aperture access */
3827 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3828 /* Disable cursor, overlay, crtc */
3829 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3830 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3831 S_000054_CRTC_DISPLAY_DIS(1));
3832 WREG32(R_000050_CRTC_GEN_CNTL,
3833 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3834 S_000050_CRTC_DISP_REQ_EN_B(1));
3835 WREG32(R_000420_OV0_SCALE_CNTL,
3836 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3837 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3838 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3839 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3840 S_000360_CUR2_LOCK(1));
3841 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3842 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3843 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3844 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3845 WREG32(R_000360_CUR2_OFFSET,
3846 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3847 }
3848 }
3849
3850 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3851 {
3852 /* Update base address for crtc */
3853 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3854 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3855 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3856 }
3857 /* Restore CRTC registers */
3858 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3859 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3860 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3861 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3862 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3863 }
3864 }
3865
3866 void r100_vga_render_disable(struct radeon_device *rdev)
3867 {
3868 u32 tmp;
3869
3870 tmp = RREG8(R_0003C2_GENMO_WT);
3871 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3872 }
3873
3874 static void r100_debugfs(struct radeon_device *rdev)
3875 {
3876 int r;
3877
3878 r = r100_debugfs_mc_info_init(rdev);
3879 if (r)
3880 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3881 }
3882
3883 static void r100_mc_program(struct radeon_device *rdev)
3884 {
3885 struct r100_mc_save save;
3886
3887 /* Stops all mc clients */
3888 r100_mc_stop(rdev, &save);
3889 if (rdev->flags & RADEON_IS_AGP) {
3890 WREG32(R_00014C_MC_AGP_LOCATION,
3891 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3892 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3893 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3894 if (rdev->family > CHIP_RV200)
3895 WREG32(R_00015C_AGP_BASE_2,
3896 upper_32_bits(rdev->mc.agp_base) & 0xff);
3897 } else {
3898 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3899 WREG32(R_000170_AGP_BASE, 0);
3900 if (rdev->family > CHIP_RV200)
3901 WREG32(R_00015C_AGP_BASE_2, 0);
3902 }
3903 /* Wait for mc idle */
3904 if (r100_mc_wait_for_idle(rdev))
3905 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3906 /* Program MC, should be a 32bits limited address space */
3907 WREG32(R_000148_MC_FB_LOCATION,
3908 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3909 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3910 r100_mc_resume(rdev, &save);
3911 }
3912
3913 void r100_clock_startup(struct radeon_device *rdev)
3914 {
3915 u32 tmp;
3916
3917 if (radeon_dynclks != -1 && radeon_dynclks)
3918 radeon_legacy_set_clock_gating(rdev, 1);
3919 /* We need to force on some of the block */
3920 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3921 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3922 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3923 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3924 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3925 }
3926
3927 static int r100_startup(struct radeon_device *rdev)
3928 {
3929 int r;
3930
3931 /* set common regs */
3932 r100_set_common_regs(rdev);
3933 /* program mc */
3934 r100_mc_program(rdev);
3935 /* Resume clock */
3936 r100_clock_startup(rdev);
3937 /* Initialize GART (initialize after TTM so we can allocate
3938 * memory through TTM but finalize after TTM) */
3939 r100_enable_bm(rdev);
3940 if (rdev->flags & RADEON_IS_PCI) {
3941 r = r100_pci_gart_enable(rdev);
3942 if (r)
3943 return r;
3944 }
3945
3946 /* allocate wb buffer */
3947 r = radeon_wb_init(rdev);
3948 if (r)
3949 return r;
3950
3951 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3952 if (r) {
3953 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3954 return r;
3955 }
3956
3957 /* Enable IRQ */
3958 r100_irq_set(rdev);
3959 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3960 /* 1M ring buffer */
3961 r = r100_cp_init(rdev, 1024 * 1024);
3962 if (r) {
3963 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3964 return r;
3965 }
3966
3967 r = radeon_ib_pool_start(rdev);
3968 if (r)
3969 return r;
3970
3971 r = r100_ib_test(rdev);
3972 if (r) {
3973 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3974 rdev->accel_working = false;
3975 return r;
3976 }
3977
3978 return 0;
3979 }
3980
3981 int r100_resume(struct radeon_device *rdev)
3982 {
3983 /* Make sur GART are not working */
3984 if (rdev->flags & RADEON_IS_PCI)
3985 r100_pci_gart_disable(rdev);
3986 /* Resume clock before doing reset */
3987 r100_clock_startup(rdev);
3988 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3989 if (radeon_asic_reset(rdev)) {
3990 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3991 RREG32(R_000E40_RBBM_STATUS),
3992 RREG32(R_0007C0_CP_STAT));
3993 }
3994 /* post */
3995 radeon_combios_asic_init(rdev->ddev);
3996 /* Resume clock after posting */
3997 r100_clock_startup(rdev);
3998 /* Initialize surface registers */
3999 radeon_surface_init(rdev);
4000
4001 rdev->accel_working = true;
4002 return r100_startup(rdev);
4003 }
4004
4005 int r100_suspend(struct radeon_device *rdev)
4006 {
4007 radeon_ib_pool_suspend(rdev);
4008 r100_cp_disable(rdev);
4009 radeon_wb_disable(rdev);
4010 r100_irq_disable(rdev);
4011 if (rdev->flags & RADEON_IS_PCI)
4012 r100_pci_gart_disable(rdev);
4013 return 0;
4014 }
4015
4016 void r100_fini(struct radeon_device *rdev)
4017 {
4018 r100_cp_fini(rdev);
4019 radeon_wb_fini(rdev);
4020 r100_ib_fini(rdev);
4021 radeon_gem_fini(rdev);
4022 if (rdev->flags & RADEON_IS_PCI)
4023 r100_pci_gart_fini(rdev);
4024 radeon_agp_fini(rdev);
4025 radeon_irq_kms_fini(rdev);
4026 radeon_fence_driver_fini(rdev);
4027 radeon_bo_fini(rdev);
4028 radeon_atombios_fini(rdev);
4029 kfree(rdev->bios);
4030 rdev->bios = NULL;
4031 }
4032
4033 /*
4034 * Due to how kexec works, it can leave the hw fully initialised when it
4035 * boots the new kernel. However doing our init sequence with the CP and
4036 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4037 * do some quick sanity checks and restore sane values to avoid this
4038 * problem.
4039 */
4040 void r100_restore_sanity(struct radeon_device *rdev)
4041 {
4042 u32 tmp;
4043
4044 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4045 if (tmp) {
4046 WREG32(RADEON_CP_CSQ_CNTL, 0);
4047 }
4048 tmp = RREG32(RADEON_CP_RB_CNTL);
4049 if (tmp) {
4050 WREG32(RADEON_CP_RB_CNTL, 0);
4051 }
4052 tmp = RREG32(RADEON_SCRATCH_UMSK);
4053 if (tmp) {
4054 WREG32(RADEON_SCRATCH_UMSK, 0);
4055 }
4056 }
4057
4058 int r100_init(struct radeon_device *rdev)
4059 {
4060 int r;
4061
4062 /* Register debugfs file specific to this group of asics */
4063 r100_debugfs(rdev);
4064 /* Disable VGA */
4065 r100_vga_render_disable(rdev);
4066 /* Initialize scratch registers */
4067 radeon_scratch_init(rdev);
4068 /* Initialize surface registers */
4069 radeon_surface_init(rdev);
4070 /* sanity check some register to avoid hangs like after kexec */
4071 r100_restore_sanity(rdev);
4072 /* TODO: disable VGA need to use VGA request */
4073 /* BIOS*/
4074 if (!radeon_get_bios(rdev)) {
4075 if (ASIC_IS_AVIVO(rdev))
4076 return -EINVAL;
4077 }
4078 if (rdev->is_atom_bios) {
4079 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4080 return -EINVAL;
4081 } else {
4082 r = radeon_combios_init(rdev);
4083 if (r)
4084 return r;
4085 }
4086 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4087 if (radeon_asic_reset(rdev)) {
4088 dev_warn(rdev->dev,
4089 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4090 RREG32(R_000E40_RBBM_STATUS),
4091 RREG32(R_0007C0_CP_STAT));
4092 }
4093 /* check if cards are posted or not */
4094 if (radeon_boot_test_post_card(rdev) == false)
4095 return -EINVAL;
4096 /* Set asic errata */
4097 r100_errata(rdev);
4098 /* Initialize clocks */
4099 radeon_get_clock_info(rdev->ddev);
4100 /* initialize AGP */
4101 if (rdev->flags & RADEON_IS_AGP) {
4102 r = radeon_agp_init(rdev);
4103 if (r) {
4104 radeon_agp_disable(rdev);
4105 }
4106 }
4107 /* initialize VRAM */
4108 r100_mc_init(rdev);
4109 /* Fence driver */
4110 r = radeon_fence_driver_init(rdev);
4111 if (r)
4112 return r;
4113 r = radeon_irq_kms_init(rdev);
4114 if (r)
4115 return r;
4116 /* Memory manager */
4117 r = radeon_bo_init(rdev);
4118 if (r)
4119 return r;
4120 if (rdev->flags & RADEON_IS_PCI) {
4121 r = r100_pci_gart_init(rdev);
4122 if (r)
4123 return r;
4124 }
4125 r100_set_safe_registers(rdev);
4126
4127 r = radeon_ib_pool_init(rdev);
4128 rdev->accel_working = true;
4129 if (r) {
4130 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4131 rdev->accel_working = false;
4132 }
4133
4134 r = r100_startup(rdev);
4135 if (r) {
4136 /* Somethings want wront with the accel init stop accel */
4137 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4138 r100_cp_fini(rdev);
4139 radeon_wb_fini(rdev);
4140 r100_ib_fini(rdev);
4141 radeon_irq_kms_fini(rdev);
4142 if (rdev->flags & RADEON_IS_PCI)
4143 r100_pci_gart_fini(rdev);
4144 rdev->accel_working = false;
4145 }
4146 return 0;
4147 }
4148
4149 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4150 {
4151 if (reg < rdev->rmmio_size)
4152 return readl(((void __iomem *)rdev->rmmio) + reg);
4153 else {
4154 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4155 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4156 }
4157 }
4158
4159 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4160 {
4161 if (reg < rdev->rmmio_size)
4162 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4163 else {
4164 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4165 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4166 }
4167 }
4168
4169 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4170 {
4171 if (reg < rdev->rio_mem_size)
4172 return ioread32(rdev->rio_mem + reg);
4173 else {
4174 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4175 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4176 }
4177 }
4178
4179 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4180 {
4181 if (reg < rdev->rio_mem_size)
4182 iowrite32(v, rdev->rio_mem + reg);
4183 else {
4184 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4185 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4186 }
4187 }
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