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drm/radeon/kms: make ring_start, ring_test, and ib_test per ring
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
45
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
48
49 /* Firmware Names */
50 #define FIRMWARE_R100 "radeon/R100_cp.bin"
51 #define FIRMWARE_R200 "radeon/R200_cp.bin"
52 #define FIRMWARE_R300 "radeon/R300_cp.bin"
53 #define FIRMWARE_R420 "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
65
66 #include "r100_track.h"
67
68 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
69 {
70 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
71 int i;
72
73 if (radeon_crtc->crtc_id == 0) {
74 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
75 for (i = 0; i < rdev->usec_timeout; i++) {
76 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
77 break;
78 udelay(1);
79 }
80 for (i = 0; i < rdev->usec_timeout; i++) {
81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
82 break;
83 udelay(1);
84 }
85 }
86 } else {
87 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
88 for (i = 0; i < rdev->usec_timeout; i++) {
89 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
90 break;
91 udelay(1);
92 }
93 for (i = 0; i < rdev->usec_timeout; i++) {
94 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
95 break;
96 udelay(1);
97 }
98 }
99 }
100 }
101
102 /* This files gather functions specifics to:
103 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
104 */
105
106 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
107 struct radeon_cs_packet *pkt,
108 unsigned idx,
109 unsigned reg)
110 {
111 int r;
112 u32 tile_flags = 0;
113 u32 tmp;
114 struct radeon_cs_reloc *reloc;
115 u32 value;
116
117 r = r100_cs_packet_next_reloc(p, &reloc);
118 if (r) {
119 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
120 idx, reg);
121 r100_cs_dump_packet(p, pkt);
122 return r;
123 }
124
125 value = radeon_get_ib_value(p, idx);
126 tmp = value & 0x003fffff;
127 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
128
129 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
130 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
131 tile_flags |= RADEON_DST_TILE_MACRO;
132 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
133 if (reg == RADEON_SRC_PITCH_OFFSET) {
134 DRM_ERROR("Cannot src blit from microtiled surface\n");
135 r100_cs_dump_packet(p, pkt);
136 return -EINVAL;
137 }
138 tile_flags |= RADEON_DST_TILE_MICRO;
139 }
140
141 tmp |= tile_flags;
142 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
143 } else
144 p->ib->ptr[idx] = (value & 0xffc00000) | tmp;
145 return 0;
146 }
147
148 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
149 struct radeon_cs_packet *pkt,
150 int idx)
151 {
152 unsigned c, i;
153 struct radeon_cs_reloc *reloc;
154 struct r100_cs_track *track;
155 int r = 0;
156 volatile uint32_t *ib;
157 u32 idx_value;
158
159 ib = p->ib->ptr;
160 track = (struct r100_cs_track *)p->track;
161 c = radeon_get_ib_value(p, idx++) & 0x1F;
162 if (c > 16) {
163 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
164 pkt->opcode);
165 r100_cs_dump_packet(p, pkt);
166 return -EINVAL;
167 }
168 track->num_arrays = c;
169 for (i = 0; i < (c - 1); i+=2, idx+=3) {
170 r = r100_cs_packet_next_reloc(p, &reloc);
171 if (r) {
172 DRM_ERROR("No reloc for packet3 %d\n",
173 pkt->opcode);
174 r100_cs_dump_packet(p, pkt);
175 return r;
176 }
177 idx_value = radeon_get_ib_value(p, idx);
178 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
179
180 track->arrays[i + 0].esize = idx_value >> 8;
181 track->arrays[i + 0].robj = reloc->robj;
182 track->arrays[i + 0].esize &= 0x7F;
183 r = r100_cs_packet_next_reloc(p, &reloc);
184 if (r) {
185 DRM_ERROR("No reloc for packet3 %d\n",
186 pkt->opcode);
187 r100_cs_dump_packet(p, pkt);
188 return r;
189 }
190 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
191 track->arrays[i + 1].robj = reloc->robj;
192 track->arrays[i + 1].esize = idx_value >> 24;
193 track->arrays[i + 1].esize &= 0x7F;
194 }
195 if (c & 1) {
196 r = r100_cs_packet_next_reloc(p, &reloc);
197 if (r) {
198 DRM_ERROR("No reloc for packet3 %d\n",
199 pkt->opcode);
200 r100_cs_dump_packet(p, pkt);
201 return r;
202 }
203 idx_value = radeon_get_ib_value(p, idx);
204 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
205 track->arrays[i + 0].robj = reloc->robj;
206 track->arrays[i + 0].esize = idx_value >> 8;
207 track->arrays[i + 0].esize &= 0x7F;
208 }
209 return r;
210 }
211
212 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
213 {
214 /* enable the pflip int */
215 radeon_irq_kms_pflip_irq_get(rdev, crtc);
216 }
217
218 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
219 {
220 /* disable the pflip int */
221 radeon_irq_kms_pflip_irq_put(rdev, crtc);
222 }
223
224 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
225 {
226 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
227 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
228 int i;
229
230 /* Lock the graphics update lock */
231 /* update the scanout addresses */
232 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
233
234 /* Wait for update_pending to go high. */
235 for (i = 0; i < rdev->usec_timeout; i++) {
236 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
237 break;
238 udelay(1);
239 }
240 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
241
242 /* Unlock the lock, so double-buffering can take place inside vblank */
243 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
244 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
245
246 /* Return current update_pending status: */
247 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
248 }
249
250 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
251 {
252 int i;
253 rdev->pm.dynpm_can_upclock = true;
254 rdev->pm.dynpm_can_downclock = true;
255
256 switch (rdev->pm.dynpm_planned_action) {
257 case DYNPM_ACTION_MINIMUM:
258 rdev->pm.requested_power_state_index = 0;
259 rdev->pm.dynpm_can_downclock = false;
260 break;
261 case DYNPM_ACTION_DOWNCLOCK:
262 if (rdev->pm.current_power_state_index == 0) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
264 rdev->pm.dynpm_can_downclock = false;
265 } else {
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = 0; i < rdev->pm.num_power_states; i++) {
268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
269 continue;
270 else if (i >= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
272 break;
273 } else {
274 rdev->pm.requested_power_state_index = i;
275 break;
276 }
277 }
278 } else
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index - 1;
281 }
282 /* don't use the power state if crtcs are active and no display flag is set */
283 if ((rdev->pm.active_crtc_count > 0) &&
284 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
285 RADEON_PM_MODE_NO_DISPLAY)) {
286 rdev->pm.requested_power_state_index++;
287 }
288 break;
289 case DYNPM_ACTION_UPCLOCK:
290 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
291 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
292 rdev->pm.dynpm_can_upclock = false;
293 } else {
294 if (rdev->pm.active_crtc_count > 1) {
295 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
296 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
297 continue;
298 else if (i <= rdev->pm.current_power_state_index) {
299 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
300 break;
301 } else {
302 rdev->pm.requested_power_state_index = i;
303 break;
304 }
305 }
306 } else
307 rdev->pm.requested_power_state_index =
308 rdev->pm.current_power_state_index + 1;
309 }
310 break;
311 case DYNPM_ACTION_DEFAULT:
312 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
313 rdev->pm.dynpm_can_upclock = false;
314 break;
315 case DYNPM_ACTION_NONE:
316 default:
317 DRM_ERROR("Requested mode for not defined action\n");
318 return;
319 }
320 /* only one clock mode per power state */
321 rdev->pm.requested_clock_mode_index = 0;
322
323 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
324 rdev->pm.power_state[rdev->pm.requested_power_state_index].
325 clock_info[rdev->pm.requested_clock_mode_index].sclk,
326 rdev->pm.power_state[rdev->pm.requested_power_state_index].
327 clock_info[rdev->pm.requested_clock_mode_index].mclk,
328 rdev->pm.power_state[rdev->pm.requested_power_state_index].
329 pcie_lanes);
330 }
331
332 void r100_pm_init_profile(struct radeon_device *rdev)
333 {
334 /* default */
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
336 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
339 /* low sh */
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
344 /* mid sh */
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
349 /* high sh */
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
354 /* low mh */
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
359 /* mid mh */
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
364 /* high mh */
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
369 }
370
371 void r100_pm_misc(struct radeon_device *rdev)
372 {
373 int requested_index = rdev->pm.requested_power_state_index;
374 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
375 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
376 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
377
378 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
379 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
380 tmp = RREG32(voltage->gpio.reg);
381 if (voltage->active_high)
382 tmp |= voltage->gpio.mask;
383 else
384 tmp &= ~(voltage->gpio.mask);
385 WREG32(voltage->gpio.reg, tmp);
386 if (voltage->delay)
387 udelay(voltage->delay);
388 } else {
389 tmp = RREG32(voltage->gpio.reg);
390 if (voltage->active_high)
391 tmp &= ~voltage->gpio.mask;
392 else
393 tmp |= voltage->gpio.mask;
394 WREG32(voltage->gpio.reg, tmp);
395 if (voltage->delay)
396 udelay(voltage->delay);
397 }
398 }
399
400 sclk_cntl = RREG32_PLL(SCLK_CNTL);
401 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
402 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
403 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
404 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
405 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
406 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
407 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
408 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
409 else
410 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
411 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
412 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
413 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
414 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
415 } else
416 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
417
418 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
419 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
420 if (voltage->delay) {
421 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
422 switch (voltage->delay) {
423 case 33:
424 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
425 break;
426 case 66:
427 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
428 break;
429 case 99:
430 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
431 break;
432 case 132:
433 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
434 break;
435 }
436 } else
437 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
438 } else
439 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
440
441 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
442 sclk_cntl &= ~FORCE_HDP;
443 else
444 sclk_cntl |= FORCE_HDP;
445
446 WREG32_PLL(SCLK_CNTL, sclk_cntl);
447 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
448 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
449
450 /* set pcie lanes */
451 if ((rdev->flags & RADEON_IS_PCIE) &&
452 !(rdev->flags & RADEON_IS_IGP) &&
453 rdev->asic->set_pcie_lanes &&
454 (ps->pcie_lanes !=
455 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
456 radeon_set_pcie_lanes(rdev,
457 ps->pcie_lanes);
458 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
459 }
460 }
461
462 void r100_pm_prepare(struct radeon_device *rdev)
463 {
464 struct drm_device *ddev = rdev->ddev;
465 struct drm_crtc *crtc;
466 struct radeon_crtc *radeon_crtc;
467 u32 tmp;
468
469 /* disable any active CRTCs */
470 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
471 radeon_crtc = to_radeon_crtc(crtc);
472 if (radeon_crtc->enabled) {
473 if (radeon_crtc->crtc_id) {
474 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
475 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
477 } else {
478 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
479 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
480 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
481 }
482 }
483 }
484 }
485
486 void r100_pm_finish(struct radeon_device *rdev)
487 {
488 struct drm_device *ddev = rdev->ddev;
489 struct drm_crtc *crtc;
490 struct radeon_crtc *radeon_crtc;
491 u32 tmp;
492
493 /* enable any active CRTCs */
494 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
495 radeon_crtc = to_radeon_crtc(crtc);
496 if (radeon_crtc->enabled) {
497 if (radeon_crtc->crtc_id) {
498 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
499 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
500 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
501 } else {
502 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
503 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
504 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
505 }
506 }
507 }
508 }
509
510 bool r100_gui_idle(struct radeon_device *rdev)
511 {
512 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
513 return false;
514 else
515 return true;
516 }
517
518 /* hpd for digital panel detect/disconnect */
519 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
520 {
521 bool connected = false;
522
523 switch (hpd) {
524 case RADEON_HPD_1:
525 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
526 connected = true;
527 break;
528 case RADEON_HPD_2:
529 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
530 connected = true;
531 break;
532 default:
533 break;
534 }
535 return connected;
536 }
537
538 void r100_hpd_set_polarity(struct radeon_device *rdev,
539 enum radeon_hpd_id hpd)
540 {
541 u32 tmp;
542 bool connected = r100_hpd_sense(rdev, hpd);
543
544 switch (hpd) {
545 case RADEON_HPD_1:
546 tmp = RREG32(RADEON_FP_GEN_CNTL);
547 if (connected)
548 tmp &= ~RADEON_FP_DETECT_INT_POL;
549 else
550 tmp |= RADEON_FP_DETECT_INT_POL;
551 WREG32(RADEON_FP_GEN_CNTL, tmp);
552 break;
553 case RADEON_HPD_2:
554 tmp = RREG32(RADEON_FP2_GEN_CNTL);
555 if (connected)
556 tmp &= ~RADEON_FP2_DETECT_INT_POL;
557 else
558 tmp |= RADEON_FP2_DETECT_INT_POL;
559 WREG32(RADEON_FP2_GEN_CNTL, tmp);
560 break;
561 default:
562 break;
563 }
564 }
565
566 void r100_hpd_init(struct radeon_device *rdev)
567 {
568 struct drm_device *dev = rdev->ddev;
569 struct drm_connector *connector;
570
571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
572 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
573 switch (radeon_connector->hpd.hpd) {
574 case RADEON_HPD_1:
575 rdev->irq.hpd[0] = true;
576 break;
577 case RADEON_HPD_2:
578 rdev->irq.hpd[1] = true;
579 break;
580 default:
581 break;
582 }
583 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
584 }
585 if (rdev->irq.installed)
586 r100_irq_set(rdev);
587 }
588
589 void r100_hpd_fini(struct radeon_device *rdev)
590 {
591 struct drm_device *dev = rdev->ddev;
592 struct drm_connector *connector;
593
594 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
595 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
596 switch (radeon_connector->hpd.hpd) {
597 case RADEON_HPD_1:
598 rdev->irq.hpd[0] = false;
599 break;
600 case RADEON_HPD_2:
601 rdev->irq.hpd[1] = false;
602 break;
603 default:
604 break;
605 }
606 }
607 }
608
609 /*
610 * PCI GART
611 */
612 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
613 {
614 /* TODO: can we do somethings here ? */
615 /* It seems hw only cache one entry so we should discard this
616 * entry otherwise if first GPU GART read hit this entry it
617 * could end up in wrong address. */
618 }
619
620 int r100_pci_gart_init(struct radeon_device *rdev)
621 {
622 int r;
623
624 if (rdev->gart.ptr) {
625 WARN(1, "R100 PCI GART already initialized\n");
626 return 0;
627 }
628 /* Initialize common gart structure */
629 r = radeon_gart_init(rdev);
630 if (r)
631 return r;
632 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
633 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
634 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
635 return radeon_gart_table_ram_alloc(rdev);
636 }
637
638 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
639 void r100_enable_bm(struct radeon_device *rdev)
640 {
641 uint32_t tmp;
642 /* Enable bus mastering */
643 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
644 WREG32(RADEON_BUS_CNTL, tmp);
645 }
646
647 int r100_pci_gart_enable(struct radeon_device *rdev)
648 {
649 uint32_t tmp;
650
651 radeon_gart_restore(rdev);
652 /* discard memory request outside of configured range */
653 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
654 WREG32(RADEON_AIC_CNTL, tmp);
655 /* set address range for PCI address translate */
656 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
657 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
658 /* set PCI GART page-table base address */
659 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
660 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
661 WREG32(RADEON_AIC_CNTL, tmp);
662 r100_pci_gart_tlb_flush(rdev);
663 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
664 (unsigned)(rdev->mc.gtt_size >> 20),
665 (unsigned long long)rdev->gart.table_addr);
666 rdev->gart.ready = true;
667 return 0;
668 }
669
670 void r100_pci_gart_disable(struct radeon_device *rdev)
671 {
672 uint32_t tmp;
673
674 /* discard memory request outside of configured range */
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
676 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
677 WREG32(RADEON_AIC_LO_ADDR, 0);
678 WREG32(RADEON_AIC_HI_ADDR, 0);
679 }
680
681 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
682 {
683 u32 *gtt = rdev->gart.ptr;
684
685 if (i < 0 || i > rdev->gart.num_gpu_pages) {
686 return -EINVAL;
687 }
688 gtt[i] = cpu_to_le32(lower_32_bits(addr));
689 return 0;
690 }
691
692 void r100_pci_gart_fini(struct radeon_device *rdev)
693 {
694 radeon_gart_fini(rdev);
695 r100_pci_gart_disable(rdev);
696 radeon_gart_table_ram_free(rdev);
697 }
698
699 int r100_irq_set(struct radeon_device *rdev)
700 {
701 uint32_t tmp = 0;
702
703 if (!rdev->irq.installed) {
704 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
705 WREG32(R_000040_GEN_INT_CNTL, 0);
706 return -EINVAL;
707 }
708 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
709 tmp |= RADEON_SW_INT_ENABLE;
710 }
711 if (rdev->irq.gui_idle) {
712 tmp |= RADEON_GUI_IDLE_MASK;
713 }
714 if (rdev->irq.crtc_vblank_int[0] ||
715 rdev->irq.pflip[0]) {
716 tmp |= RADEON_CRTC_VBLANK_MASK;
717 }
718 if (rdev->irq.crtc_vblank_int[1] ||
719 rdev->irq.pflip[1]) {
720 tmp |= RADEON_CRTC2_VBLANK_MASK;
721 }
722 if (rdev->irq.hpd[0]) {
723 tmp |= RADEON_FP_DETECT_MASK;
724 }
725 if (rdev->irq.hpd[1]) {
726 tmp |= RADEON_FP2_DETECT_MASK;
727 }
728 WREG32(RADEON_GEN_INT_CNTL, tmp);
729 return 0;
730 }
731
732 void r100_irq_disable(struct radeon_device *rdev)
733 {
734 u32 tmp;
735
736 WREG32(R_000040_GEN_INT_CNTL, 0);
737 /* Wait and acknowledge irq */
738 mdelay(1);
739 tmp = RREG32(R_000044_GEN_INT_STATUS);
740 WREG32(R_000044_GEN_INT_STATUS, tmp);
741 }
742
743 static uint32_t r100_irq_ack(struct radeon_device *rdev)
744 {
745 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
746 uint32_t irq_mask = RADEON_SW_INT_TEST |
747 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
748 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
749
750 /* the interrupt works, but the status bit is permanently asserted */
751 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
752 if (!rdev->irq.gui_idle_acked)
753 irq_mask |= RADEON_GUI_IDLE_STAT;
754 }
755
756 if (irqs) {
757 WREG32(RADEON_GEN_INT_STATUS, irqs);
758 }
759 return irqs & irq_mask;
760 }
761
762 int r100_irq_process(struct radeon_device *rdev)
763 {
764 uint32_t status, msi_rearm;
765 bool queue_hotplug = false;
766
767 /* reset gui idle ack. the status bit is broken */
768 rdev->irq.gui_idle_acked = false;
769
770 status = r100_irq_ack(rdev);
771 if (!status) {
772 return IRQ_NONE;
773 }
774 if (rdev->shutdown) {
775 return IRQ_NONE;
776 }
777 while (status) {
778 /* SW interrupt */
779 if (status & RADEON_SW_INT_TEST) {
780 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
781 }
782 /* gui idle interrupt */
783 if (status & RADEON_GUI_IDLE_STAT) {
784 rdev->irq.gui_idle_acked = true;
785 rdev->pm.gui_idle = true;
786 wake_up(&rdev->irq.idle_queue);
787 }
788 /* Vertical blank interrupts */
789 if (status & RADEON_CRTC_VBLANK_STAT) {
790 if (rdev->irq.crtc_vblank_int[0]) {
791 drm_handle_vblank(rdev->ddev, 0);
792 rdev->pm.vblank_sync = true;
793 wake_up(&rdev->irq.vblank_queue);
794 }
795 if (rdev->irq.pflip[0])
796 radeon_crtc_handle_flip(rdev, 0);
797 }
798 if (status & RADEON_CRTC2_VBLANK_STAT) {
799 if (rdev->irq.crtc_vblank_int[1]) {
800 drm_handle_vblank(rdev->ddev, 1);
801 rdev->pm.vblank_sync = true;
802 wake_up(&rdev->irq.vblank_queue);
803 }
804 if (rdev->irq.pflip[1])
805 radeon_crtc_handle_flip(rdev, 1);
806 }
807 if (status & RADEON_FP_DETECT_STAT) {
808 queue_hotplug = true;
809 DRM_DEBUG("HPD1\n");
810 }
811 if (status & RADEON_FP2_DETECT_STAT) {
812 queue_hotplug = true;
813 DRM_DEBUG("HPD2\n");
814 }
815 status = r100_irq_ack(rdev);
816 }
817 /* reset gui idle ack. the status bit is broken */
818 rdev->irq.gui_idle_acked = false;
819 if (queue_hotplug)
820 schedule_work(&rdev->hotplug_work);
821 if (rdev->msi_enabled) {
822 switch (rdev->family) {
823 case CHIP_RS400:
824 case CHIP_RS480:
825 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
826 WREG32(RADEON_AIC_CNTL, msi_rearm);
827 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
828 break;
829 default:
830 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
831 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
832 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
833 break;
834 }
835 }
836 return IRQ_HANDLED;
837 }
838
839 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
840 {
841 if (crtc == 0)
842 return RREG32(RADEON_CRTC_CRNT_FRAME);
843 else
844 return RREG32(RADEON_CRTC2_CRNT_FRAME);
845 }
846
847 /* Who ever call radeon_fence_emit should call ring_lock and ask
848 * for enough space (today caller are ib schedule and buffer move) */
849 void r100_fence_ring_emit(struct radeon_device *rdev,
850 struct radeon_fence *fence)
851 {
852 struct radeon_ring *ring = &rdev->ring[fence->ring];
853
854 /* We have to make sure that caches are flushed before
855 * CPU might read something from VRAM. */
856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
857 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
858 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
859 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
860 /* Wait until IDLE & CLEAN */
861 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
862 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
865 RADEON_HDP_READ_BUFFER_INVALIDATE);
866 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
867 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
868 /* Emit fence sequence & fire IRQ */
869 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
870 radeon_ring_write(ring, fence->seq);
871 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
872 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
873 }
874
875 void r100_semaphore_ring_emit(struct radeon_device *rdev,
876 struct radeon_ring *ring,
877 struct radeon_semaphore *semaphore,
878 bool emit_wait)
879 {
880 /* Unused on older asics, since we don't have semaphores or multiple rings */
881 BUG();
882 }
883
884 int r100_copy_blit(struct radeon_device *rdev,
885 uint64_t src_offset,
886 uint64_t dst_offset,
887 unsigned num_gpu_pages,
888 struct radeon_fence *fence)
889 {
890 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
891 uint32_t cur_pages;
892 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
893 uint32_t pitch;
894 uint32_t stride_pixels;
895 unsigned ndw;
896 int num_loops;
897 int r = 0;
898
899 /* radeon limited to 16k stride */
900 stride_bytes &= 0x3fff;
901 /* radeon pitch is /64 */
902 pitch = stride_bytes / 64;
903 stride_pixels = stride_bytes / 4;
904 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
905
906 /* Ask for enough room for blit + flush + fence */
907 ndw = 64 + (10 * num_loops);
908 r = radeon_ring_lock(rdev, ring, ndw);
909 if (r) {
910 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
911 return -EINVAL;
912 }
913 while (num_gpu_pages > 0) {
914 cur_pages = num_gpu_pages;
915 if (cur_pages > 8191) {
916 cur_pages = 8191;
917 }
918 num_gpu_pages -= cur_pages;
919
920 /* pages are in Y direction - height
921 page width in X direction - width */
922 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
923 radeon_ring_write(ring,
924 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
925 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
926 RADEON_GMC_SRC_CLIPPING |
927 RADEON_GMC_DST_CLIPPING |
928 RADEON_GMC_BRUSH_NONE |
929 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
930 RADEON_GMC_SRC_DATATYPE_COLOR |
931 RADEON_ROP3_S |
932 RADEON_DP_SRC_SOURCE_MEMORY |
933 RADEON_GMC_CLR_CMP_CNTL_DIS |
934 RADEON_GMC_WR_MSK_DIS);
935 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
936 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
938 radeon_ring_write(ring, 0);
939 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
940 radeon_ring_write(ring, num_gpu_pages);
941 radeon_ring_write(ring, num_gpu_pages);
942 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
943 }
944 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
945 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
946 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
947 radeon_ring_write(ring,
948 RADEON_WAIT_2D_IDLECLEAN |
949 RADEON_WAIT_HOST_IDLECLEAN |
950 RADEON_WAIT_DMA_GUI_IDLE);
951 if (fence) {
952 r = radeon_fence_emit(rdev, fence);
953 }
954 radeon_ring_unlock_commit(rdev, ring);
955 return r;
956 }
957
958 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
959 {
960 unsigned i;
961 u32 tmp;
962
963 for (i = 0; i < rdev->usec_timeout; i++) {
964 tmp = RREG32(R_000E40_RBBM_STATUS);
965 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
966 return 0;
967 }
968 udelay(1);
969 }
970 return -1;
971 }
972
973 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
974 {
975 int r;
976
977 r = radeon_ring_lock(rdev, ring, 2);
978 if (r) {
979 return;
980 }
981 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
982 radeon_ring_write(ring,
983 RADEON_ISYNC_ANY2D_IDLE3D |
984 RADEON_ISYNC_ANY3D_IDLE2D |
985 RADEON_ISYNC_WAIT_IDLEGUI |
986 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
987 radeon_ring_unlock_commit(rdev, ring);
988 }
989
990
991 /* Load the microcode for the CP */
992 static int r100_cp_init_microcode(struct radeon_device *rdev)
993 {
994 struct platform_device *pdev;
995 const char *fw_name = NULL;
996 int err;
997
998 DRM_DEBUG_KMS("\n");
999
1000 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1001 err = IS_ERR(pdev);
1002 if (err) {
1003 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1004 return -EINVAL;
1005 }
1006 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1007 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1008 (rdev->family == CHIP_RS200)) {
1009 DRM_INFO("Loading R100 Microcode\n");
1010 fw_name = FIRMWARE_R100;
1011 } else if ((rdev->family == CHIP_R200) ||
1012 (rdev->family == CHIP_RV250) ||
1013 (rdev->family == CHIP_RV280) ||
1014 (rdev->family == CHIP_RS300)) {
1015 DRM_INFO("Loading R200 Microcode\n");
1016 fw_name = FIRMWARE_R200;
1017 } else if ((rdev->family == CHIP_R300) ||
1018 (rdev->family == CHIP_R350) ||
1019 (rdev->family == CHIP_RV350) ||
1020 (rdev->family == CHIP_RV380) ||
1021 (rdev->family == CHIP_RS400) ||
1022 (rdev->family == CHIP_RS480)) {
1023 DRM_INFO("Loading R300 Microcode\n");
1024 fw_name = FIRMWARE_R300;
1025 } else if ((rdev->family == CHIP_R420) ||
1026 (rdev->family == CHIP_R423) ||
1027 (rdev->family == CHIP_RV410)) {
1028 DRM_INFO("Loading R400 Microcode\n");
1029 fw_name = FIRMWARE_R420;
1030 } else if ((rdev->family == CHIP_RS690) ||
1031 (rdev->family == CHIP_RS740)) {
1032 DRM_INFO("Loading RS690/RS740 Microcode\n");
1033 fw_name = FIRMWARE_RS690;
1034 } else if (rdev->family == CHIP_RS600) {
1035 DRM_INFO("Loading RS600 Microcode\n");
1036 fw_name = FIRMWARE_RS600;
1037 } else if ((rdev->family == CHIP_RV515) ||
1038 (rdev->family == CHIP_R520) ||
1039 (rdev->family == CHIP_RV530) ||
1040 (rdev->family == CHIP_R580) ||
1041 (rdev->family == CHIP_RV560) ||
1042 (rdev->family == CHIP_RV570)) {
1043 DRM_INFO("Loading R500 Microcode\n");
1044 fw_name = FIRMWARE_R520;
1045 }
1046
1047 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1048 platform_device_unregister(pdev);
1049 if (err) {
1050 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1051 fw_name);
1052 } else if (rdev->me_fw->size % 8) {
1053 printk(KERN_ERR
1054 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1055 rdev->me_fw->size, fw_name);
1056 err = -EINVAL;
1057 release_firmware(rdev->me_fw);
1058 rdev->me_fw = NULL;
1059 }
1060 return err;
1061 }
1062
1063 static void r100_cp_load_microcode(struct radeon_device *rdev)
1064 {
1065 const __be32 *fw_data;
1066 int i, size;
1067
1068 if (r100_gui_wait_for_idle(rdev)) {
1069 printk(KERN_WARNING "Failed to wait GUI idle while "
1070 "programming pipes. Bad things might happen.\n");
1071 }
1072
1073 if (rdev->me_fw) {
1074 size = rdev->me_fw->size / 4;
1075 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1076 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1077 for (i = 0; i < size; i += 2) {
1078 WREG32(RADEON_CP_ME_RAM_DATAH,
1079 be32_to_cpup(&fw_data[i]));
1080 WREG32(RADEON_CP_ME_RAM_DATAL,
1081 be32_to_cpup(&fw_data[i + 1]));
1082 }
1083 }
1084 }
1085
1086 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1087 {
1088 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1089 unsigned rb_bufsz;
1090 unsigned rb_blksz;
1091 unsigned max_fetch;
1092 unsigned pre_write_timer;
1093 unsigned pre_write_limit;
1094 unsigned indirect2_start;
1095 unsigned indirect1_start;
1096 uint32_t tmp;
1097 int r;
1098
1099 if (r100_debugfs_cp_init(rdev)) {
1100 DRM_ERROR("Failed to register debugfs file for CP !\n");
1101 }
1102 if (!rdev->me_fw) {
1103 r = r100_cp_init_microcode(rdev);
1104 if (r) {
1105 DRM_ERROR("Failed to load firmware!\n");
1106 return r;
1107 }
1108 }
1109
1110 /* Align ring size */
1111 rb_bufsz = drm_order(ring_size / 8);
1112 ring_size = (1 << (rb_bufsz + 1)) * 4;
1113 r100_cp_load_microcode(rdev);
1114 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1115 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1116 0, 0x7fffff, RADEON_CP_PACKET2);
1117 if (r) {
1118 return r;
1119 }
1120 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1121 * the rptr copy in system ram */
1122 rb_blksz = 9;
1123 /* cp will read 128bytes at a time (4 dwords) */
1124 max_fetch = 1;
1125 ring->align_mask = 16 - 1;
1126 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1127 pre_write_timer = 64;
1128 /* Force CP_RB_WPTR write if written more than one time before the
1129 * delay expire
1130 */
1131 pre_write_limit = 0;
1132 /* Setup the cp cache like this (cache size is 96 dwords) :
1133 * RING 0 to 15
1134 * INDIRECT1 16 to 79
1135 * INDIRECT2 80 to 95
1136 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1137 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1138 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1139 * Idea being that most of the gpu cmd will be through indirect1 buffer
1140 * so it gets the bigger cache.
1141 */
1142 indirect2_start = 80;
1143 indirect1_start = 16;
1144 /* cp setup */
1145 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1146 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1147 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1148 REG_SET(RADEON_MAX_FETCH, max_fetch));
1149 #ifdef __BIG_ENDIAN
1150 tmp |= RADEON_BUF_SWAP_32BIT;
1151 #endif
1152 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1153
1154 /* Set ring address */
1155 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1156 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1157 /* Force read & write ptr to 0 */
1158 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1159 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1160 ring->wptr = 0;
1161 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1162
1163 /* set the wb address whether it's enabled or not */
1164 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1165 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1166 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1167
1168 if (rdev->wb.enabled)
1169 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1170 else {
1171 tmp |= RADEON_RB_NO_UPDATE;
1172 WREG32(R_000770_SCRATCH_UMSK, 0);
1173 }
1174
1175 WREG32(RADEON_CP_RB_CNTL, tmp);
1176 udelay(10);
1177 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1178 /* Set cp mode to bus mastering & enable cp*/
1179 WREG32(RADEON_CP_CSQ_MODE,
1180 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1181 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1182 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1183 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1184 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1185 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1186 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1187 if (r) {
1188 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1189 return r;
1190 }
1191 ring->ready = true;
1192 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1193 return 0;
1194 }
1195
1196 void r100_cp_fini(struct radeon_device *rdev)
1197 {
1198 if (r100_cp_wait_for_idle(rdev)) {
1199 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1200 }
1201 /* Disable ring */
1202 r100_cp_disable(rdev);
1203 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1204 DRM_INFO("radeon: cp finalized\n");
1205 }
1206
1207 void r100_cp_disable(struct radeon_device *rdev)
1208 {
1209 /* Disable ring */
1210 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1211 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1212 WREG32(RADEON_CP_CSQ_MODE, 0);
1213 WREG32(RADEON_CP_CSQ_CNTL, 0);
1214 WREG32(R_000770_SCRATCH_UMSK, 0);
1215 if (r100_gui_wait_for_idle(rdev)) {
1216 printk(KERN_WARNING "Failed to wait GUI idle while "
1217 "programming pipes. Bad things might happen.\n");
1218 }
1219 }
1220
1221 /*
1222 * CS functions
1223 */
1224 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1225 struct radeon_cs_packet *pkt,
1226 const unsigned *auth, unsigned n,
1227 radeon_packet0_check_t check)
1228 {
1229 unsigned reg;
1230 unsigned i, j, m;
1231 unsigned idx;
1232 int r;
1233
1234 idx = pkt->idx + 1;
1235 reg = pkt->reg;
1236 /* Check that register fall into register range
1237 * determined by the number of entry (n) in the
1238 * safe register bitmap.
1239 */
1240 if (pkt->one_reg_wr) {
1241 if ((reg >> 7) > n) {
1242 return -EINVAL;
1243 }
1244 } else {
1245 if (((reg + (pkt->count << 2)) >> 7) > n) {
1246 return -EINVAL;
1247 }
1248 }
1249 for (i = 0; i <= pkt->count; i++, idx++) {
1250 j = (reg >> 7);
1251 m = 1 << ((reg >> 2) & 31);
1252 if (auth[j] & m) {
1253 r = check(p, pkt, idx, reg);
1254 if (r) {
1255 return r;
1256 }
1257 }
1258 if (pkt->one_reg_wr) {
1259 if (!(auth[j] & m)) {
1260 break;
1261 }
1262 } else {
1263 reg += 4;
1264 }
1265 }
1266 return 0;
1267 }
1268
1269 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1270 struct radeon_cs_packet *pkt)
1271 {
1272 volatile uint32_t *ib;
1273 unsigned i;
1274 unsigned idx;
1275
1276 ib = p->ib->ptr;
1277 idx = pkt->idx;
1278 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1279 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1280 }
1281 }
1282
1283 /**
1284 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1285 * @parser: parser structure holding parsing context.
1286 * @pkt: where to store packet informations
1287 *
1288 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1289 * if packet is bigger than remaining ib size. or if packets is unknown.
1290 **/
1291 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1292 struct radeon_cs_packet *pkt,
1293 unsigned idx)
1294 {
1295 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1296 uint32_t header;
1297
1298 if (idx >= ib_chunk->length_dw) {
1299 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1300 idx, ib_chunk->length_dw);
1301 return -EINVAL;
1302 }
1303 header = radeon_get_ib_value(p, idx);
1304 pkt->idx = idx;
1305 pkt->type = CP_PACKET_GET_TYPE(header);
1306 pkt->count = CP_PACKET_GET_COUNT(header);
1307 switch (pkt->type) {
1308 case PACKET_TYPE0:
1309 pkt->reg = CP_PACKET0_GET_REG(header);
1310 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1311 break;
1312 case PACKET_TYPE3:
1313 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1314 break;
1315 case PACKET_TYPE2:
1316 pkt->count = -1;
1317 break;
1318 default:
1319 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1320 return -EINVAL;
1321 }
1322 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1323 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1324 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1325 return -EINVAL;
1326 }
1327 return 0;
1328 }
1329
1330 /**
1331 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1332 * @parser: parser structure holding parsing context.
1333 *
1334 * Userspace sends a special sequence for VLINE waits.
1335 * PACKET0 - VLINE_START_END + value
1336 * PACKET0 - WAIT_UNTIL +_value
1337 * RELOC (P3) - crtc_id in reloc.
1338 *
1339 * This function parses this and relocates the VLINE START END
1340 * and WAIT UNTIL packets to the correct crtc.
1341 * It also detects a switched off crtc and nulls out the
1342 * wait in that case.
1343 */
1344 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1345 {
1346 struct drm_mode_object *obj;
1347 struct drm_crtc *crtc;
1348 struct radeon_crtc *radeon_crtc;
1349 struct radeon_cs_packet p3reloc, waitreloc;
1350 int crtc_id;
1351 int r;
1352 uint32_t header, h_idx, reg;
1353 volatile uint32_t *ib;
1354
1355 ib = p->ib->ptr;
1356
1357 /* parse the wait until */
1358 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1359 if (r)
1360 return r;
1361
1362 /* check its a wait until and only 1 count */
1363 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1364 waitreloc.count != 0) {
1365 DRM_ERROR("vline wait had illegal wait until segment\n");
1366 return -EINVAL;
1367 }
1368
1369 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1370 DRM_ERROR("vline wait had illegal wait until\n");
1371 return -EINVAL;
1372 }
1373
1374 /* jump over the NOP */
1375 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1376 if (r)
1377 return r;
1378
1379 h_idx = p->idx - 2;
1380 p->idx += waitreloc.count + 2;
1381 p->idx += p3reloc.count + 2;
1382
1383 header = radeon_get_ib_value(p, h_idx);
1384 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1385 reg = CP_PACKET0_GET_REG(header);
1386 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1387 if (!obj) {
1388 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1389 return -EINVAL;
1390 }
1391 crtc = obj_to_crtc(obj);
1392 radeon_crtc = to_radeon_crtc(crtc);
1393 crtc_id = radeon_crtc->crtc_id;
1394
1395 if (!crtc->enabled) {
1396 /* if the CRTC isn't enabled - we need to nop out the wait until */
1397 ib[h_idx + 2] = PACKET2(0);
1398 ib[h_idx + 3] = PACKET2(0);
1399 } else if (crtc_id == 1) {
1400 switch (reg) {
1401 case AVIVO_D1MODE_VLINE_START_END:
1402 header &= ~R300_CP_PACKET0_REG_MASK;
1403 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1404 break;
1405 case RADEON_CRTC_GUI_TRIG_VLINE:
1406 header &= ~R300_CP_PACKET0_REG_MASK;
1407 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1408 break;
1409 default:
1410 DRM_ERROR("unknown crtc reloc\n");
1411 return -EINVAL;
1412 }
1413 ib[h_idx] = header;
1414 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1415 }
1416
1417 return 0;
1418 }
1419
1420 /**
1421 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1422 * @parser: parser structure holding parsing context.
1423 * @data: pointer to relocation data
1424 * @offset_start: starting offset
1425 * @offset_mask: offset mask (to align start offset on)
1426 * @reloc: reloc informations
1427 *
1428 * Check next packet is relocation packet3, do bo validation and compute
1429 * GPU offset using the provided start.
1430 **/
1431 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1432 struct radeon_cs_reloc **cs_reloc)
1433 {
1434 struct radeon_cs_chunk *relocs_chunk;
1435 struct radeon_cs_packet p3reloc;
1436 unsigned idx;
1437 int r;
1438
1439 if (p->chunk_relocs_idx == -1) {
1440 DRM_ERROR("No relocation chunk !\n");
1441 return -EINVAL;
1442 }
1443 *cs_reloc = NULL;
1444 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1445 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1446 if (r) {
1447 return r;
1448 }
1449 p->idx += p3reloc.count + 2;
1450 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1451 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1452 p3reloc.idx);
1453 r100_cs_dump_packet(p, &p3reloc);
1454 return -EINVAL;
1455 }
1456 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1457 if (idx >= relocs_chunk->length_dw) {
1458 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1459 idx, relocs_chunk->length_dw);
1460 r100_cs_dump_packet(p, &p3reloc);
1461 return -EINVAL;
1462 }
1463 /* FIXME: we assume reloc size is 4 dwords */
1464 *cs_reloc = p->relocs_ptr[(idx / 4)];
1465 return 0;
1466 }
1467
1468 static int r100_get_vtx_size(uint32_t vtx_fmt)
1469 {
1470 int vtx_size;
1471 vtx_size = 2;
1472 /* ordered according to bits in spec */
1473 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1474 vtx_size++;
1475 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1476 vtx_size += 3;
1477 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1478 vtx_size++;
1479 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1480 vtx_size++;
1481 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1482 vtx_size += 3;
1483 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1484 vtx_size++;
1485 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1486 vtx_size++;
1487 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1488 vtx_size += 2;
1489 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1490 vtx_size += 2;
1491 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1492 vtx_size++;
1493 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1494 vtx_size += 2;
1495 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1496 vtx_size++;
1497 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1498 vtx_size += 2;
1499 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1500 vtx_size++;
1501 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1502 vtx_size++;
1503 /* blend weight */
1504 if (vtx_fmt & (0x7 << 15))
1505 vtx_size += (vtx_fmt >> 15) & 0x7;
1506 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1507 vtx_size += 3;
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1509 vtx_size += 2;
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1511 vtx_size++;
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1513 vtx_size++;
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1515 vtx_size++;
1516 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1517 vtx_size++;
1518 return vtx_size;
1519 }
1520
1521 static int r100_packet0_check(struct radeon_cs_parser *p,
1522 struct radeon_cs_packet *pkt,
1523 unsigned idx, unsigned reg)
1524 {
1525 struct radeon_cs_reloc *reloc;
1526 struct r100_cs_track *track;
1527 volatile uint32_t *ib;
1528 uint32_t tmp;
1529 int r;
1530 int i, face;
1531 u32 tile_flags = 0;
1532 u32 idx_value;
1533
1534 ib = p->ib->ptr;
1535 track = (struct r100_cs_track *)p->track;
1536
1537 idx_value = radeon_get_ib_value(p, idx);
1538
1539 switch (reg) {
1540 case RADEON_CRTC_GUI_TRIG_VLINE:
1541 r = r100_cs_packet_parse_vline(p);
1542 if (r) {
1543 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1544 idx, reg);
1545 r100_cs_dump_packet(p, pkt);
1546 return r;
1547 }
1548 break;
1549 /* FIXME: only allow PACKET3 blit? easier to check for out of
1550 * range access */
1551 case RADEON_DST_PITCH_OFFSET:
1552 case RADEON_SRC_PITCH_OFFSET:
1553 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1554 if (r)
1555 return r;
1556 break;
1557 case RADEON_RB3D_DEPTHOFFSET:
1558 r = r100_cs_packet_next_reloc(p, &reloc);
1559 if (r) {
1560 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1561 idx, reg);
1562 r100_cs_dump_packet(p, pkt);
1563 return r;
1564 }
1565 track->zb.robj = reloc->robj;
1566 track->zb.offset = idx_value;
1567 track->zb_dirty = true;
1568 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1569 break;
1570 case RADEON_RB3D_COLOROFFSET:
1571 r = r100_cs_packet_next_reloc(p, &reloc);
1572 if (r) {
1573 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1574 idx, reg);
1575 r100_cs_dump_packet(p, pkt);
1576 return r;
1577 }
1578 track->cb[0].robj = reloc->robj;
1579 track->cb[0].offset = idx_value;
1580 track->cb_dirty = true;
1581 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1582 break;
1583 case RADEON_PP_TXOFFSET_0:
1584 case RADEON_PP_TXOFFSET_1:
1585 case RADEON_PP_TXOFFSET_2:
1586 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1587 r = r100_cs_packet_next_reloc(p, &reloc);
1588 if (r) {
1589 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1590 idx, reg);
1591 r100_cs_dump_packet(p, pkt);
1592 return r;
1593 }
1594 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1595 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1596 tile_flags |= RADEON_TXO_MACRO_TILE;
1597 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1598 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1599
1600 tmp = idx_value & ~(0x7 << 2);
1601 tmp |= tile_flags;
1602 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1603 } else
1604 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1605 track->textures[i].robj = reloc->robj;
1606 track->tex_dirty = true;
1607 break;
1608 case RADEON_PP_CUBIC_OFFSET_T0_0:
1609 case RADEON_PP_CUBIC_OFFSET_T0_1:
1610 case RADEON_PP_CUBIC_OFFSET_T0_2:
1611 case RADEON_PP_CUBIC_OFFSET_T0_3:
1612 case RADEON_PP_CUBIC_OFFSET_T0_4:
1613 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1614 r = r100_cs_packet_next_reloc(p, &reloc);
1615 if (r) {
1616 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1617 idx, reg);
1618 r100_cs_dump_packet(p, pkt);
1619 return r;
1620 }
1621 track->textures[0].cube_info[i].offset = idx_value;
1622 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1623 track->textures[0].cube_info[i].robj = reloc->robj;
1624 track->tex_dirty = true;
1625 break;
1626 case RADEON_PP_CUBIC_OFFSET_T1_0:
1627 case RADEON_PP_CUBIC_OFFSET_T1_1:
1628 case RADEON_PP_CUBIC_OFFSET_T1_2:
1629 case RADEON_PP_CUBIC_OFFSET_T1_3:
1630 case RADEON_PP_CUBIC_OFFSET_T1_4:
1631 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1632 r = r100_cs_packet_next_reloc(p, &reloc);
1633 if (r) {
1634 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1635 idx, reg);
1636 r100_cs_dump_packet(p, pkt);
1637 return r;
1638 }
1639 track->textures[1].cube_info[i].offset = idx_value;
1640 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1641 track->textures[1].cube_info[i].robj = reloc->robj;
1642 track->tex_dirty = true;
1643 break;
1644 case RADEON_PP_CUBIC_OFFSET_T2_0:
1645 case RADEON_PP_CUBIC_OFFSET_T2_1:
1646 case RADEON_PP_CUBIC_OFFSET_T2_2:
1647 case RADEON_PP_CUBIC_OFFSET_T2_3:
1648 case RADEON_PP_CUBIC_OFFSET_T2_4:
1649 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1650 r = r100_cs_packet_next_reloc(p, &reloc);
1651 if (r) {
1652 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1653 idx, reg);
1654 r100_cs_dump_packet(p, pkt);
1655 return r;
1656 }
1657 track->textures[2].cube_info[i].offset = idx_value;
1658 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1659 track->textures[2].cube_info[i].robj = reloc->robj;
1660 track->tex_dirty = true;
1661 break;
1662 case RADEON_RE_WIDTH_HEIGHT:
1663 track->maxy = ((idx_value >> 16) & 0x7FF);
1664 track->cb_dirty = true;
1665 track->zb_dirty = true;
1666 break;
1667 case RADEON_RB3D_COLORPITCH:
1668 r = r100_cs_packet_next_reloc(p, &reloc);
1669 if (r) {
1670 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1671 idx, reg);
1672 r100_cs_dump_packet(p, pkt);
1673 return r;
1674 }
1675 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1676 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1677 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1678 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1679 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1680
1681 tmp = idx_value & ~(0x7 << 16);
1682 tmp |= tile_flags;
1683 ib[idx] = tmp;
1684 } else
1685 ib[idx] = idx_value;
1686
1687 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1688 track->cb_dirty = true;
1689 break;
1690 case RADEON_RB3D_DEPTHPITCH:
1691 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1692 track->zb_dirty = true;
1693 break;
1694 case RADEON_RB3D_CNTL:
1695 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1696 case 7:
1697 case 8:
1698 case 9:
1699 case 11:
1700 case 12:
1701 track->cb[0].cpp = 1;
1702 break;
1703 case 3:
1704 case 4:
1705 case 15:
1706 track->cb[0].cpp = 2;
1707 break;
1708 case 6:
1709 track->cb[0].cpp = 4;
1710 break;
1711 default:
1712 DRM_ERROR("Invalid color buffer format (%d) !\n",
1713 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1714 return -EINVAL;
1715 }
1716 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1717 track->cb_dirty = true;
1718 track->zb_dirty = true;
1719 break;
1720 case RADEON_RB3D_ZSTENCILCNTL:
1721 switch (idx_value & 0xf) {
1722 case 0:
1723 track->zb.cpp = 2;
1724 break;
1725 case 2:
1726 case 3:
1727 case 4:
1728 case 5:
1729 case 9:
1730 case 11:
1731 track->zb.cpp = 4;
1732 break;
1733 default:
1734 break;
1735 }
1736 track->zb_dirty = true;
1737 break;
1738 case RADEON_RB3D_ZPASS_ADDR:
1739 r = r100_cs_packet_next_reloc(p, &reloc);
1740 if (r) {
1741 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1742 idx, reg);
1743 r100_cs_dump_packet(p, pkt);
1744 return r;
1745 }
1746 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1747 break;
1748 case RADEON_PP_CNTL:
1749 {
1750 uint32_t temp = idx_value >> 4;
1751 for (i = 0; i < track->num_texture; i++)
1752 track->textures[i].enabled = !!(temp & (1 << i));
1753 track->tex_dirty = true;
1754 }
1755 break;
1756 case RADEON_SE_VF_CNTL:
1757 track->vap_vf_cntl = idx_value;
1758 break;
1759 case RADEON_SE_VTX_FMT:
1760 track->vtx_size = r100_get_vtx_size(idx_value);
1761 break;
1762 case RADEON_PP_TEX_SIZE_0:
1763 case RADEON_PP_TEX_SIZE_1:
1764 case RADEON_PP_TEX_SIZE_2:
1765 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1766 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1767 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1768 track->tex_dirty = true;
1769 break;
1770 case RADEON_PP_TEX_PITCH_0:
1771 case RADEON_PP_TEX_PITCH_1:
1772 case RADEON_PP_TEX_PITCH_2:
1773 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1774 track->textures[i].pitch = idx_value + 32;
1775 track->tex_dirty = true;
1776 break;
1777 case RADEON_PP_TXFILTER_0:
1778 case RADEON_PP_TXFILTER_1:
1779 case RADEON_PP_TXFILTER_2:
1780 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1781 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1782 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1783 tmp = (idx_value >> 23) & 0x7;
1784 if (tmp == 2 || tmp == 6)
1785 track->textures[i].roundup_w = false;
1786 tmp = (idx_value >> 27) & 0x7;
1787 if (tmp == 2 || tmp == 6)
1788 track->textures[i].roundup_h = false;
1789 track->tex_dirty = true;
1790 break;
1791 case RADEON_PP_TXFORMAT_0:
1792 case RADEON_PP_TXFORMAT_1:
1793 case RADEON_PP_TXFORMAT_2:
1794 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1795 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1796 track->textures[i].use_pitch = 1;
1797 } else {
1798 track->textures[i].use_pitch = 0;
1799 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1800 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1801 }
1802 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1803 track->textures[i].tex_coord_type = 2;
1804 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1805 case RADEON_TXFORMAT_I8:
1806 case RADEON_TXFORMAT_RGB332:
1807 case RADEON_TXFORMAT_Y8:
1808 track->textures[i].cpp = 1;
1809 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1810 break;
1811 case RADEON_TXFORMAT_AI88:
1812 case RADEON_TXFORMAT_ARGB1555:
1813 case RADEON_TXFORMAT_RGB565:
1814 case RADEON_TXFORMAT_ARGB4444:
1815 case RADEON_TXFORMAT_VYUY422:
1816 case RADEON_TXFORMAT_YVYU422:
1817 case RADEON_TXFORMAT_SHADOW16:
1818 case RADEON_TXFORMAT_LDUDV655:
1819 case RADEON_TXFORMAT_DUDV88:
1820 track->textures[i].cpp = 2;
1821 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1822 break;
1823 case RADEON_TXFORMAT_ARGB8888:
1824 case RADEON_TXFORMAT_RGBA8888:
1825 case RADEON_TXFORMAT_SHADOW32:
1826 case RADEON_TXFORMAT_LDUDUV8888:
1827 track->textures[i].cpp = 4;
1828 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1829 break;
1830 case RADEON_TXFORMAT_DXT1:
1831 track->textures[i].cpp = 1;
1832 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1833 break;
1834 case RADEON_TXFORMAT_DXT23:
1835 case RADEON_TXFORMAT_DXT45:
1836 track->textures[i].cpp = 1;
1837 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1838 break;
1839 }
1840 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1841 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1842 track->tex_dirty = true;
1843 break;
1844 case RADEON_PP_CUBIC_FACES_0:
1845 case RADEON_PP_CUBIC_FACES_1:
1846 case RADEON_PP_CUBIC_FACES_2:
1847 tmp = idx_value;
1848 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1849 for (face = 0; face < 4; face++) {
1850 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1851 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1852 }
1853 track->tex_dirty = true;
1854 break;
1855 default:
1856 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1857 reg, idx);
1858 return -EINVAL;
1859 }
1860 return 0;
1861 }
1862
1863 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1864 struct radeon_cs_packet *pkt,
1865 struct radeon_bo *robj)
1866 {
1867 unsigned idx;
1868 u32 value;
1869 idx = pkt->idx + 1;
1870 value = radeon_get_ib_value(p, idx + 2);
1871 if ((value + 1) > radeon_bo_size(robj)) {
1872 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1873 "(need %u have %lu) !\n",
1874 value + 1,
1875 radeon_bo_size(robj));
1876 return -EINVAL;
1877 }
1878 return 0;
1879 }
1880
1881 static int r100_packet3_check(struct radeon_cs_parser *p,
1882 struct radeon_cs_packet *pkt)
1883 {
1884 struct radeon_cs_reloc *reloc;
1885 struct r100_cs_track *track;
1886 unsigned idx;
1887 volatile uint32_t *ib;
1888 int r;
1889
1890 ib = p->ib->ptr;
1891 idx = pkt->idx + 1;
1892 track = (struct r100_cs_track *)p->track;
1893 switch (pkt->opcode) {
1894 case PACKET3_3D_LOAD_VBPNTR:
1895 r = r100_packet3_load_vbpntr(p, pkt, idx);
1896 if (r)
1897 return r;
1898 break;
1899 case PACKET3_INDX_BUFFER:
1900 r = r100_cs_packet_next_reloc(p, &reloc);
1901 if (r) {
1902 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1903 r100_cs_dump_packet(p, pkt);
1904 return r;
1905 }
1906 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1907 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1908 if (r) {
1909 return r;
1910 }
1911 break;
1912 case 0x23:
1913 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1914 r = r100_cs_packet_next_reloc(p, &reloc);
1915 if (r) {
1916 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1917 r100_cs_dump_packet(p, pkt);
1918 return r;
1919 }
1920 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1921 track->num_arrays = 1;
1922 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1923
1924 track->arrays[0].robj = reloc->robj;
1925 track->arrays[0].esize = track->vtx_size;
1926
1927 track->max_indx = radeon_get_ib_value(p, idx+1);
1928
1929 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1930 track->immd_dwords = pkt->count - 1;
1931 r = r100_cs_track_check(p->rdev, track);
1932 if (r)
1933 return r;
1934 break;
1935 case PACKET3_3D_DRAW_IMMD:
1936 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1937 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1938 return -EINVAL;
1939 }
1940 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1941 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1942 track->immd_dwords = pkt->count - 1;
1943 r = r100_cs_track_check(p->rdev, track);
1944 if (r)
1945 return r;
1946 break;
1947 /* triggers drawing using in-packet vertex data */
1948 case PACKET3_3D_DRAW_IMMD_2:
1949 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1950 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1951 return -EINVAL;
1952 }
1953 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1954 track->immd_dwords = pkt->count;
1955 r = r100_cs_track_check(p->rdev, track);
1956 if (r)
1957 return r;
1958 break;
1959 /* triggers drawing using in-packet vertex data */
1960 case PACKET3_3D_DRAW_VBUF_2:
1961 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1962 r = r100_cs_track_check(p->rdev, track);
1963 if (r)
1964 return r;
1965 break;
1966 /* triggers drawing of vertex buffers setup elsewhere */
1967 case PACKET3_3D_DRAW_INDX_2:
1968 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1969 r = r100_cs_track_check(p->rdev, track);
1970 if (r)
1971 return r;
1972 break;
1973 /* triggers drawing using indices to vertex buffer */
1974 case PACKET3_3D_DRAW_VBUF:
1975 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1976 r = r100_cs_track_check(p->rdev, track);
1977 if (r)
1978 return r;
1979 break;
1980 /* triggers drawing of vertex buffers setup elsewhere */
1981 case PACKET3_3D_DRAW_INDX:
1982 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1983 r = r100_cs_track_check(p->rdev, track);
1984 if (r)
1985 return r;
1986 break;
1987 /* triggers drawing using indices to vertex buffer */
1988 case PACKET3_3D_CLEAR_HIZ:
1989 case PACKET3_3D_CLEAR_ZMASK:
1990 if (p->rdev->hyperz_filp != p->filp)
1991 return -EINVAL;
1992 break;
1993 case PACKET3_NOP:
1994 break;
1995 default:
1996 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1997 return -EINVAL;
1998 }
1999 return 0;
2000 }
2001
2002 int r100_cs_parse(struct radeon_cs_parser *p)
2003 {
2004 struct radeon_cs_packet pkt;
2005 struct r100_cs_track *track;
2006 int r;
2007
2008 track = kzalloc(sizeof(*track), GFP_KERNEL);
2009 r100_cs_track_clear(p->rdev, track);
2010 p->track = track;
2011 do {
2012 r = r100_cs_packet_parse(p, &pkt, p->idx);
2013 if (r) {
2014 return r;
2015 }
2016 p->idx += pkt.count + 2;
2017 switch (pkt.type) {
2018 case PACKET_TYPE0:
2019 if (p->rdev->family >= CHIP_R200)
2020 r = r100_cs_parse_packet0(p, &pkt,
2021 p->rdev->config.r100.reg_safe_bm,
2022 p->rdev->config.r100.reg_safe_bm_size,
2023 &r200_packet0_check);
2024 else
2025 r = r100_cs_parse_packet0(p, &pkt,
2026 p->rdev->config.r100.reg_safe_bm,
2027 p->rdev->config.r100.reg_safe_bm_size,
2028 &r100_packet0_check);
2029 break;
2030 case PACKET_TYPE2:
2031 break;
2032 case PACKET_TYPE3:
2033 r = r100_packet3_check(p, &pkt);
2034 break;
2035 default:
2036 DRM_ERROR("Unknown packet type %d !\n",
2037 pkt.type);
2038 return -EINVAL;
2039 }
2040 if (r) {
2041 return r;
2042 }
2043 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2044 return 0;
2045 }
2046
2047
2048 /*
2049 * Global GPU functions
2050 */
2051 void r100_errata(struct radeon_device *rdev)
2052 {
2053 rdev->pll_errata = 0;
2054
2055 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2056 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2057 }
2058
2059 if (rdev->family == CHIP_RV100 ||
2060 rdev->family == CHIP_RS100 ||
2061 rdev->family == CHIP_RS200) {
2062 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2063 }
2064 }
2065
2066 /* Wait for vertical sync on primary CRTC */
2067 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2068 {
2069 uint32_t crtc_gen_cntl, tmp;
2070 int i;
2071
2072 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2073 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2074 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2075 return;
2076 }
2077 /* Clear the CRTC_VBLANK_SAVE bit */
2078 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2079 for (i = 0; i < rdev->usec_timeout; i++) {
2080 tmp = RREG32(RADEON_CRTC_STATUS);
2081 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2082 return;
2083 }
2084 DRM_UDELAY(1);
2085 }
2086 }
2087
2088 /* Wait for vertical sync on secondary CRTC */
2089 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2090 {
2091 uint32_t crtc2_gen_cntl, tmp;
2092 int i;
2093
2094 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2095 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2096 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2097 return;
2098
2099 /* Clear the CRTC_VBLANK_SAVE bit */
2100 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2101 for (i = 0; i < rdev->usec_timeout; i++) {
2102 tmp = RREG32(RADEON_CRTC2_STATUS);
2103 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2104 return;
2105 }
2106 DRM_UDELAY(1);
2107 }
2108 }
2109
2110 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2111 {
2112 unsigned i;
2113 uint32_t tmp;
2114
2115 for (i = 0; i < rdev->usec_timeout; i++) {
2116 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2117 if (tmp >= n) {
2118 return 0;
2119 }
2120 DRM_UDELAY(1);
2121 }
2122 return -1;
2123 }
2124
2125 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2126 {
2127 unsigned i;
2128 uint32_t tmp;
2129
2130 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2131 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2132 " Bad things might happen.\n");
2133 }
2134 for (i = 0; i < rdev->usec_timeout; i++) {
2135 tmp = RREG32(RADEON_RBBM_STATUS);
2136 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2137 return 0;
2138 }
2139 DRM_UDELAY(1);
2140 }
2141 return -1;
2142 }
2143
2144 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2145 {
2146 unsigned i;
2147 uint32_t tmp;
2148
2149 for (i = 0; i < rdev->usec_timeout; i++) {
2150 /* read MC_STATUS */
2151 tmp = RREG32(RADEON_MC_STATUS);
2152 if (tmp & RADEON_MC_IDLE) {
2153 return 0;
2154 }
2155 DRM_UDELAY(1);
2156 }
2157 return -1;
2158 }
2159
2160 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2161 {
2162 lockup->last_cp_rptr = ring->rptr;
2163 lockup->last_jiffies = jiffies;
2164 }
2165
2166 /**
2167 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2168 * @rdev: radeon device structure
2169 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2170 * @cp: radeon_cp structure holding CP information
2171 *
2172 * We don't need to initialize the lockup tracking information as we will either
2173 * have CP rptr to a different value of jiffies wrap around which will force
2174 * initialization of the lockup tracking informations.
2175 *
2176 * A possible false positivie is if we get call after while and last_cp_rptr ==
2177 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2178 * if the elapsed time since last call is bigger than 2 second than we return
2179 * false and update the tracking information. Due to this the caller must call
2180 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2181 * the fencing code should be cautious about that.
2182 *
2183 * Caller should write to the ring to force CP to do something so we don't get
2184 * false positive when CP is just gived nothing to do.
2185 *
2186 **/
2187 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2188 {
2189 unsigned long cjiffies, elapsed;
2190
2191 cjiffies = jiffies;
2192 if (!time_after(cjiffies, lockup->last_jiffies)) {
2193 /* likely a wrap around */
2194 lockup->last_cp_rptr = ring->rptr;
2195 lockup->last_jiffies = jiffies;
2196 return false;
2197 }
2198 if (ring->rptr != lockup->last_cp_rptr) {
2199 /* CP is still working no lockup */
2200 lockup->last_cp_rptr = ring->rptr;
2201 lockup->last_jiffies = jiffies;
2202 return false;
2203 }
2204 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2205 if (elapsed >= 10000) {
2206 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2207 return true;
2208 }
2209 /* give a chance to the GPU ... */
2210 return false;
2211 }
2212
2213 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2214 {
2215 u32 rbbm_status;
2216 int r;
2217
2218 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2219 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2220 r100_gpu_lockup_update(&rdev->config.r100.lockup, ring);
2221 return false;
2222 }
2223 /* force CP activities */
2224 r = radeon_ring_lock(rdev, ring, 2);
2225 if (!r) {
2226 /* PACKET2 NOP */
2227 radeon_ring_write(ring, 0x80000000);
2228 radeon_ring_write(ring, 0x80000000);
2229 radeon_ring_unlock_commit(rdev, ring);
2230 }
2231 ring->rptr = RREG32(ring->rptr_reg);
2232 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, ring);
2233 }
2234
2235 void r100_bm_disable(struct radeon_device *rdev)
2236 {
2237 u32 tmp;
2238
2239 /* disable bus mastering */
2240 tmp = RREG32(R_000030_BUS_CNTL);
2241 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2242 mdelay(1);
2243 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2244 mdelay(1);
2245 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2246 tmp = RREG32(RADEON_BUS_CNTL);
2247 mdelay(1);
2248 pci_clear_master(rdev->pdev);
2249 mdelay(1);
2250 }
2251
2252 int r100_asic_reset(struct radeon_device *rdev)
2253 {
2254 struct r100_mc_save save;
2255 u32 status, tmp;
2256 int ret = 0;
2257
2258 status = RREG32(R_000E40_RBBM_STATUS);
2259 if (!G_000E40_GUI_ACTIVE(status)) {
2260 return 0;
2261 }
2262 r100_mc_stop(rdev, &save);
2263 status = RREG32(R_000E40_RBBM_STATUS);
2264 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2265 /* stop CP */
2266 WREG32(RADEON_CP_CSQ_CNTL, 0);
2267 tmp = RREG32(RADEON_CP_RB_CNTL);
2268 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2269 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2270 WREG32(RADEON_CP_RB_WPTR, 0);
2271 WREG32(RADEON_CP_RB_CNTL, tmp);
2272 /* save PCI state */
2273 pci_save_state(rdev->pdev);
2274 /* disable bus mastering */
2275 r100_bm_disable(rdev);
2276 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2277 S_0000F0_SOFT_RESET_RE(1) |
2278 S_0000F0_SOFT_RESET_PP(1) |
2279 S_0000F0_SOFT_RESET_RB(1));
2280 RREG32(R_0000F0_RBBM_SOFT_RESET);
2281 mdelay(500);
2282 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2283 mdelay(1);
2284 status = RREG32(R_000E40_RBBM_STATUS);
2285 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2286 /* reset CP */
2287 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2288 RREG32(R_0000F0_RBBM_SOFT_RESET);
2289 mdelay(500);
2290 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2291 mdelay(1);
2292 status = RREG32(R_000E40_RBBM_STATUS);
2293 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2294 /* restore PCI & busmastering */
2295 pci_restore_state(rdev->pdev);
2296 r100_enable_bm(rdev);
2297 /* Check if GPU is idle */
2298 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2299 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2300 dev_err(rdev->dev, "failed to reset GPU\n");
2301 rdev->gpu_lockup = true;
2302 ret = -1;
2303 } else
2304 dev_info(rdev->dev, "GPU reset succeed\n");
2305 r100_mc_resume(rdev, &save);
2306 return ret;
2307 }
2308
2309 void r100_set_common_regs(struct radeon_device *rdev)
2310 {
2311 struct drm_device *dev = rdev->ddev;
2312 bool force_dac2 = false;
2313 u32 tmp;
2314
2315 /* set these so they don't interfere with anything */
2316 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2317 WREG32(RADEON_SUBPIC_CNTL, 0);
2318 WREG32(RADEON_VIPH_CONTROL, 0);
2319 WREG32(RADEON_I2C_CNTL_1, 0);
2320 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2321 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2322 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2323
2324 /* always set up dac2 on rn50 and some rv100 as lots
2325 * of servers seem to wire it up to a VGA port but
2326 * don't report it in the bios connector
2327 * table.
2328 */
2329 switch (dev->pdev->device) {
2330 /* RN50 */
2331 case 0x515e:
2332 case 0x5969:
2333 force_dac2 = true;
2334 break;
2335 /* RV100*/
2336 case 0x5159:
2337 case 0x515a:
2338 /* DELL triple head servers */
2339 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2340 ((dev->pdev->subsystem_device == 0x016c) ||
2341 (dev->pdev->subsystem_device == 0x016d) ||
2342 (dev->pdev->subsystem_device == 0x016e) ||
2343 (dev->pdev->subsystem_device == 0x016f) ||
2344 (dev->pdev->subsystem_device == 0x0170) ||
2345 (dev->pdev->subsystem_device == 0x017d) ||
2346 (dev->pdev->subsystem_device == 0x017e) ||
2347 (dev->pdev->subsystem_device == 0x0183) ||
2348 (dev->pdev->subsystem_device == 0x018a) ||
2349 (dev->pdev->subsystem_device == 0x019a)))
2350 force_dac2 = true;
2351 break;
2352 }
2353
2354 if (force_dac2) {
2355 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2356 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2357 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2358
2359 /* For CRT on DAC2, don't turn it on if BIOS didn't
2360 enable it, even it's detected.
2361 */
2362
2363 /* force it to crtc0 */
2364 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2365 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2366 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2367
2368 /* set up the TV DAC */
2369 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2370 RADEON_TV_DAC_STD_MASK |
2371 RADEON_TV_DAC_RDACPD |
2372 RADEON_TV_DAC_GDACPD |
2373 RADEON_TV_DAC_BDACPD |
2374 RADEON_TV_DAC_BGADJ_MASK |
2375 RADEON_TV_DAC_DACADJ_MASK);
2376 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2377 RADEON_TV_DAC_NHOLD |
2378 RADEON_TV_DAC_STD_PS2 |
2379 (0x58 << 16));
2380
2381 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2382 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2383 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2384 }
2385
2386 /* switch PM block to ACPI mode */
2387 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2388 tmp &= ~RADEON_PM_MODE_SEL;
2389 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2390
2391 }
2392
2393 /*
2394 * VRAM info
2395 */
2396 static void r100_vram_get_type(struct radeon_device *rdev)
2397 {
2398 uint32_t tmp;
2399
2400 rdev->mc.vram_is_ddr = false;
2401 if (rdev->flags & RADEON_IS_IGP)
2402 rdev->mc.vram_is_ddr = true;
2403 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2404 rdev->mc.vram_is_ddr = true;
2405 if ((rdev->family == CHIP_RV100) ||
2406 (rdev->family == CHIP_RS100) ||
2407 (rdev->family == CHIP_RS200)) {
2408 tmp = RREG32(RADEON_MEM_CNTL);
2409 if (tmp & RV100_HALF_MODE) {
2410 rdev->mc.vram_width = 32;
2411 } else {
2412 rdev->mc.vram_width = 64;
2413 }
2414 if (rdev->flags & RADEON_SINGLE_CRTC) {
2415 rdev->mc.vram_width /= 4;
2416 rdev->mc.vram_is_ddr = true;
2417 }
2418 } else if (rdev->family <= CHIP_RV280) {
2419 tmp = RREG32(RADEON_MEM_CNTL);
2420 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2421 rdev->mc.vram_width = 128;
2422 } else {
2423 rdev->mc.vram_width = 64;
2424 }
2425 } else {
2426 /* newer IGPs */
2427 rdev->mc.vram_width = 128;
2428 }
2429 }
2430
2431 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2432 {
2433 u32 aper_size;
2434 u8 byte;
2435
2436 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2437
2438 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2439 * that is has the 2nd generation multifunction PCI interface
2440 */
2441 if (rdev->family == CHIP_RV280 ||
2442 rdev->family >= CHIP_RV350) {
2443 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2444 ~RADEON_HDP_APER_CNTL);
2445 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2446 return aper_size * 2;
2447 }
2448
2449 /* Older cards have all sorts of funny issues to deal with. First
2450 * check if it's a multifunction card by reading the PCI config
2451 * header type... Limit those to one aperture size
2452 */
2453 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2454 if (byte & 0x80) {
2455 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2456 DRM_INFO("Limiting VRAM to one aperture\n");
2457 return aper_size;
2458 }
2459
2460 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2461 * have set it up. We don't write this as it's broken on some ASICs but
2462 * we expect the BIOS to have done the right thing (might be too optimistic...)
2463 */
2464 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2465 return aper_size * 2;
2466 return aper_size;
2467 }
2468
2469 void r100_vram_init_sizes(struct radeon_device *rdev)
2470 {
2471 u64 config_aper_size;
2472
2473 /* work out accessible VRAM */
2474 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2475 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2476 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2477 /* FIXME we don't use the second aperture yet when we could use it */
2478 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2479 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2480 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2481 if (rdev->flags & RADEON_IS_IGP) {
2482 uint32_t tom;
2483 /* read NB_TOM to get the amount of ram stolen for the GPU */
2484 tom = RREG32(RADEON_NB_TOM);
2485 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2486 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2487 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2488 } else {
2489 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2490 /* Some production boards of m6 will report 0
2491 * if it's 8 MB
2492 */
2493 if (rdev->mc.real_vram_size == 0) {
2494 rdev->mc.real_vram_size = 8192 * 1024;
2495 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2496 }
2497 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2498 * Novell bug 204882 + along with lots of ubuntu ones
2499 */
2500 if (rdev->mc.aper_size > config_aper_size)
2501 config_aper_size = rdev->mc.aper_size;
2502
2503 if (config_aper_size > rdev->mc.real_vram_size)
2504 rdev->mc.mc_vram_size = config_aper_size;
2505 else
2506 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2507 }
2508 }
2509
2510 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2511 {
2512 uint32_t temp;
2513
2514 temp = RREG32(RADEON_CONFIG_CNTL);
2515 if (state == false) {
2516 temp &= ~RADEON_CFG_VGA_RAM_EN;
2517 temp |= RADEON_CFG_VGA_IO_DIS;
2518 } else {
2519 temp &= ~RADEON_CFG_VGA_IO_DIS;
2520 }
2521 WREG32(RADEON_CONFIG_CNTL, temp);
2522 }
2523
2524 void r100_mc_init(struct radeon_device *rdev)
2525 {
2526 u64 base;
2527
2528 r100_vram_get_type(rdev);
2529 r100_vram_init_sizes(rdev);
2530 base = rdev->mc.aper_base;
2531 if (rdev->flags & RADEON_IS_IGP)
2532 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2533 radeon_vram_location(rdev, &rdev->mc, base);
2534 rdev->mc.gtt_base_align = 0;
2535 if (!(rdev->flags & RADEON_IS_AGP))
2536 radeon_gtt_location(rdev, &rdev->mc);
2537 radeon_update_bandwidth_info(rdev);
2538 }
2539
2540
2541 /*
2542 * Indirect registers accessor
2543 */
2544 void r100_pll_errata_after_index(struct radeon_device *rdev)
2545 {
2546 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2547 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2548 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2549 }
2550 }
2551
2552 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2553 {
2554 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2555 * or the chip could hang on a subsequent access
2556 */
2557 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2558 udelay(5000);
2559 }
2560
2561 /* This function is required to workaround a hardware bug in some (all?)
2562 * revisions of the R300. This workaround should be called after every
2563 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2564 * may not be correct.
2565 */
2566 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2567 uint32_t save, tmp;
2568
2569 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2570 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2571 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2572 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2573 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2574 }
2575 }
2576
2577 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2578 {
2579 uint32_t data;
2580
2581 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2582 r100_pll_errata_after_index(rdev);
2583 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2584 r100_pll_errata_after_data(rdev);
2585 return data;
2586 }
2587
2588 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2589 {
2590 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2591 r100_pll_errata_after_index(rdev);
2592 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2593 r100_pll_errata_after_data(rdev);
2594 }
2595
2596 void r100_set_safe_registers(struct radeon_device *rdev)
2597 {
2598 if (ASIC_IS_RN50(rdev)) {
2599 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2600 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2601 } else if (rdev->family < CHIP_R200) {
2602 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2603 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2604 } else {
2605 r200_set_safe_registers(rdev);
2606 }
2607 }
2608
2609 /*
2610 * Debugfs info
2611 */
2612 #if defined(CONFIG_DEBUG_FS)
2613 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2614 {
2615 struct drm_info_node *node = (struct drm_info_node *) m->private;
2616 struct drm_device *dev = node->minor->dev;
2617 struct radeon_device *rdev = dev->dev_private;
2618 uint32_t reg, value;
2619 unsigned i;
2620
2621 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2622 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2623 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2624 for (i = 0; i < 64; i++) {
2625 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2626 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2627 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2628 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2629 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2630 }
2631 return 0;
2632 }
2633
2634 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2635 {
2636 struct drm_info_node *node = (struct drm_info_node *) m->private;
2637 struct drm_device *dev = node->minor->dev;
2638 struct radeon_device *rdev = dev->dev_private;
2639 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2640 uint32_t rdp, wdp;
2641 unsigned count, i, j;
2642
2643 radeon_ring_free_size(rdev, ring);
2644 rdp = RREG32(RADEON_CP_RB_RPTR);
2645 wdp = RREG32(RADEON_CP_RB_WPTR);
2646 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2647 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2648 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2649 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2650 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2651 seq_printf(m, "%u dwords in ring\n", count);
2652 for (j = 0; j <= count; j++) {
2653 i = (rdp + j) & ring->ptr_mask;
2654 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2655 }
2656 return 0;
2657 }
2658
2659
2660 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2661 {
2662 struct drm_info_node *node = (struct drm_info_node *) m->private;
2663 struct drm_device *dev = node->minor->dev;
2664 struct radeon_device *rdev = dev->dev_private;
2665 uint32_t csq_stat, csq2_stat, tmp;
2666 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2667 unsigned i;
2668
2669 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2670 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2671 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2672 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2673 r_rptr = (csq_stat >> 0) & 0x3ff;
2674 r_wptr = (csq_stat >> 10) & 0x3ff;
2675 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2676 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2677 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2678 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2679 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2680 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2681 seq_printf(m, "Ring rptr %u\n", r_rptr);
2682 seq_printf(m, "Ring wptr %u\n", r_wptr);
2683 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2684 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2685 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2686 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2687 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2688 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2689 seq_printf(m, "Ring fifo:\n");
2690 for (i = 0; i < 256; i++) {
2691 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2692 tmp = RREG32(RADEON_CP_CSQ_DATA);
2693 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2694 }
2695 seq_printf(m, "Indirect1 fifo:\n");
2696 for (i = 256; i <= 512; i++) {
2697 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2698 tmp = RREG32(RADEON_CP_CSQ_DATA);
2699 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2700 }
2701 seq_printf(m, "Indirect2 fifo:\n");
2702 for (i = 640; i < ib1_wptr; i++) {
2703 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2704 tmp = RREG32(RADEON_CP_CSQ_DATA);
2705 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2706 }
2707 return 0;
2708 }
2709
2710 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2711 {
2712 struct drm_info_node *node = (struct drm_info_node *) m->private;
2713 struct drm_device *dev = node->minor->dev;
2714 struct radeon_device *rdev = dev->dev_private;
2715 uint32_t tmp;
2716
2717 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2718 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2719 tmp = RREG32(RADEON_MC_FB_LOCATION);
2720 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2721 tmp = RREG32(RADEON_BUS_CNTL);
2722 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2723 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2724 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2725 tmp = RREG32(RADEON_AGP_BASE);
2726 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2727 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2728 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2729 tmp = RREG32(0x01D0);
2730 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2731 tmp = RREG32(RADEON_AIC_LO_ADDR);
2732 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2733 tmp = RREG32(RADEON_AIC_HI_ADDR);
2734 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2735 tmp = RREG32(0x01E4);
2736 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2737 return 0;
2738 }
2739
2740 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2741 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2742 };
2743
2744 static struct drm_info_list r100_debugfs_cp_list[] = {
2745 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2746 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2747 };
2748
2749 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2750 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2751 };
2752 #endif
2753
2754 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2755 {
2756 #if defined(CONFIG_DEBUG_FS)
2757 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2758 #else
2759 return 0;
2760 #endif
2761 }
2762
2763 int r100_debugfs_cp_init(struct radeon_device *rdev)
2764 {
2765 #if defined(CONFIG_DEBUG_FS)
2766 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2767 #else
2768 return 0;
2769 #endif
2770 }
2771
2772 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2773 {
2774 #if defined(CONFIG_DEBUG_FS)
2775 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2776 #else
2777 return 0;
2778 #endif
2779 }
2780
2781 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2782 uint32_t tiling_flags, uint32_t pitch,
2783 uint32_t offset, uint32_t obj_size)
2784 {
2785 int surf_index = reg * 16;
2786 int flags = 0;
2787
2788 if (rdev->family <= CHIP_RS200) {
2789 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2790 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2791 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2792 if (tiling_flags & RADEON_TILING_MACRO)
2793 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2794 } else if (rdev->family <= CHIP_RV280) {
2795 if (tiling_flags & (RADEON_TILING_MACRO))
2796 flags |= R200_SURF_TILE_COLOR_MACRO;
2797 if (tiling_flags & RADEON_TILING_MICRO)
2798 flags |= R200_SURF_TILE_COLOR_MICRO;
2799 } else {
2800 if (tiling_flags & RADEON_TILING_MACRO)
2801 flags |= R300_SURF_TILE_MACRO;
2802 if (tiling_flags & RADEON_TILING_MICRO)
2803 flags |= R300_SURF_TILE_MICRO;
2804 }
2805
2806 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2807 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2808 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2809 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2810
2811 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2812 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2813 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2814 if (ASIC_IS_RN50(rdev))
2815 pitch /= 16;
2816 }
2817
2818 /* r100/r200 divide by 16 */
2819 if (rdev->family < CHIP_R300)
2820 flags |= pitch / 16;
2821 else
2822 flags |= pitch / 8;
2823
2824
2825 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2826 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2827 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2828 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2829 return 0;
2830 }
2831
2832 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2833 {
2834 int surf_index = reg * 16;
2835 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2836 }
2837
2838 void r100_bandwidth_update(struct radeon_device *rdev)
2839 {
2840 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2841 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2842 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2843 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2844 fixed20_12 memtcas_ff[8] = {
2845 dfixed_init(1),
2846 dfixed_init(2),
2847 dfixed_init(3),
2848 dfixed_init(0),
2849 dfixed_init_half(1),
2850 dfixed_init_half(2),
2851 dfixed_init(0),
2852 };
2853 fixed20_12 memtcas_rs480_ff[8] = {
2854 dfixed_init(0),
2855 dfixed_init(1),
2856 dfixed_init(2),
2857 dfixed_init(3),
2858 dfixed_init(0),
2859 dfixed_init_half(1),
2860 dfixed_init_half(2),
2861 dfixed_init_half(3),
2862 };
2863 fixed20_12 memtcas2_ff[8] = {
2864 dfixed_init(0),
2865 dfixed_init(1),
2866 dfixed_init(2),
2867 dfixed_init(3),
2868 dfixed_init(4),
2869 dfixed_init(5),
2870 dfixed_init(6),
2871 dfixed_init(7),
2872 };
2873 fixed20_12 memtrbs[8] = {
2874 dfixed_init(1),
2875 dfixed_init_half(1),
2876 dfixed_init(2),
2877 dfixed_init_half(2),
2878 dfixed_init(3),
2879 dfixed_init_half(3),
2880 dfixed_init(4),
2881 dfixed_init_half(4)
2882 };
2883 fixed20_12 memtrbs_r4xx[8] = {
2884 dfixed_init(4),
2885 dfixed_init(5),
2886 dfixed_init(6),
2887 dfixed_init(7),
2888 dfixed_init(8),
2889 dfixed_init(9),
2890 dfixed_init(10),
2891 dfixed_init(11)
2892 };
2893 fixed20_12 min_mem_eff;
2894 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2895 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2896 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2897 disp_drain_rate2, read_return_rate;
2898 fixed20_12 time_disp1_drop_priority;
2899 int c;
2900 int cur_size = 16; /* in octawords */
2901 int critical_point = 0, critical_point2;
2902 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2903 int stop_req, max_stop_req;
2904 struct drm_display_mode *mode1 = NULL;
2905 struct drm_display_mode *mode2 = NULL;
2906 uint32_t pixel_bytes1 = 0;
2907 uint32_t pixel_bytes2 = 0;
2908
2909 radeon_update_display_priority(rdev);
2910
2911 if (rdev->mode_info.crtcs[0]->base.enabled) {
2912 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2913 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2914 }
2915 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2916 if (rdev->mode_info.crtcs[1]->base.enabled) {
2917 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2918 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2919 }
2920 }
2921
2922 min_mem_eff.full = dfixed_const_8(0);
2923 /* get modes */
2924 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2925 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2926 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2927 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2928 /* check crtc enables */
2929 if (mode2)
2930 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2931 if (mode1)
2932 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2933 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2934 }
2935
2936 /*
2937 * determine is there is enough bw for current mode
2938 */
2939 sclk_ff = rdev->pm.sclk;
2940 mclk_ff = rdev->pm.mclk;
2941
2942 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2943 temp_ff.full = dfixed_const(temp);
2944 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2945
2946 pix_clk.full = 0;
2947 pix_clk2.full = 0;
2948 peak_disp_bw.full = 0;
2949 if (mode1) {
2950 temp_ff.full = dfixed_const(1000);
2951 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2952 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2953 temp_ff.full = dfixed_const(pixel_bytes1);
2954 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2955 }
2956 if (mode2) {
2957 temp_ff.full = dfixed_const(1000);
2958 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2959 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2960 temp_ff.full = dfixed_const(pixel_bytes2);
2961 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2962 }
2963
2964 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2965 if (peak_disp_bw.full >= mem_bw.full) {
2966 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2967 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2968 }
2969
2970 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2971 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2972 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2973 mem_trcd = ((temp >> 2) & 0x3) + 1;
2974 mem_trp = ((temp & 0x3)) + 1;
2975 mem_tras = ((temp & 0x70) >> 4) + 1;
2976 } else if (rdev->family == CHIP_R300 ||
2977 rdev->family == CHIP_R350) { /* r300, r350 */
2978 mem_trcd = (temp & 0x7) + 1;
2979 mem_trp = ((temp >> 8) & 0x7) + 1;
2980 mem_tras = ((temp >> 11) & 0xf) + 4;
2981 } else if (rdev->family == CHIP_RV350 ||
2982 rdev->family <= CHIP_RV380) {
2983 /* rv3x0 */
2984 mem_trcd = (temp & 0x7) + 3;
2985 mem_trp = ((temp >> 8) & 0x7) + 3;
2986 mem_tras = ((temp >> 11) & 0xf) + 6;
2987 } else if (rdev->family == CHIP_R420 ||
2988 rdev->family == CHIP_R423 ||
2989 rdev->family == CHIP_RV410) {
2990 /* r4xx */
2991 mem_trcd = (temp & 0xf) + 3;
2992 if (mem_trcd > 15)
2993 mem_trcd = 15;
2994 mem_trp = ((temp >> 8) & 0xf) + 3;
2995 if (mem_trp > 15)
2996 mem_trp = 15;
2997 mem_tras = ((temp >> 12) & 0x1f) + 6;
2998 if (mem_tras > 31)
2999 mem_tras = 31;
3000 } else { /* RV200, R200 */
3001 mem_trcd = (temp & 0x7) + 1;
3002 mem_trp = ((temp >> 8) & 0x7) + 1;
3003 mem_tras = ((temp >> 12) & 0xf) + 4;
3004 }
3005 /* convert to FF */
3006 trcd_ff.full = dfixed_const(mem_trcd);
3007 trp_ff.full = dfixed_const(mem_trp);
3008 tras_ff.full = dfixed_const(mem_tras);
3009
3010 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3011 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3012 data = (temp & (7 << 20)) >> 20;
3013 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3014 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3015 tcas_ff = memtcas_rs480_ff[data];
3016 else
3017 tcas_ff = memtcas_ff[data];
3018 } else
3019 tcas_ff = memtcas2_ff[data];
3020
3021 if (rdev->family == CHIP_RS400 ||
3022 rdev->family == CHIP_RS480) {
3023 /* extra cas latency stored in bits 23-25 0-4 clocks */
3024 data = (temp >> 23) & 0x7;
3025 if (data < 5)
3026 tcas_ff.full += dfixed_const(data);
3027 }
3028
3029 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3030 /* on the R300, Tcas is included in Trbs.
3031 */
3032 temp = RREG32(RADEON_MEM_CNTL);
3033 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3034 if (data == 1) {
3035 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3036 temp = RREG32(R300_MC_IND_INDEX);
3037 temp &= ~R300_MC_IND_ADDR_MASK;
3038 temp |= R300_MC_READ_CNTL_CD_mcind;
3039 WREG32(R300_MC_IND_INDEX, temp);
3040 temp = RREG32(R300_MC_IND_DATA);
3041 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3042 } else {
3043 temp = RREG32(R300_MC_READ_CNTL_AB);
3044 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3045 }
3046 } else {
3047 temp = RREG32(R300_MC_READ_CNTL_AB);
3048 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3049 }
3050 if (rdev->family == CHIP_RV410 ||
3051 rdev->family == CHIP_R420 ||
3052 rdev->family == CHIP_R423)
3053 trbs_ff = memtrbs_r4xx[data];
3054 else
3055 trbs_ff = memtrbs[data];
3056 tcas_ff.full += trbs_ff.full;
3057 }
3058
3059 sclk_eff_ff.full = sclk_ff.full;
3060
3061 if (rdev->flags & RADEON_IS_AGP) {
3062 fixed20_12 agpmode_ff;
3063 agpmode_ff.full = dfixed_const(radeon_agpmode);
3064 temp_ff.full = dfixed_const_666(16);
3065 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3066 }
3067 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3068
3069 if (ASIC_IS_R300(rdev)) {
3070 sclk_delay_ff.full = dfixed_const(250);
3071 } else {
3072 if ((rdev->family == CHIP_RV100) ||
3073 rdev->flags & RADEON_IS_IGP) {
3074 if (rdev->mc.vram_is_ddr)
3075 sclk_delay_ff.full = dfixed_const(41);
3076 else
3077 sclk_delay_ff.full = dfixed_const(33);
3078 } else {
3079 if (rdev->mc.vram_width == 128)
3080 sclk_delay_ff.full = dfixed_const(57);
3081 else
3082 sclk_delay_ff.full = dfixed_const(41);
3083 }
3084 }
3085
3086 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3087
3088 if (rdev->mc.vram_is_ddr) {
3089 if (rdev->mc.vram_width == 32) {
3090 k1.full = dfixed_const(40);
3091 c = 3;
3092 } else {
3093 k1.full = dfixed_const(20);
3094 c = 1;
3095 }
3096 } else {
3097 k1.full = dfixed_const(40);
3098 c = 3;
3099 }
3100
3101 temp_ff.full = dfixed_const(2);
3102 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3103 temp_ff.full = dfixed_const(c);
3104 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3105 temp_ff.full = dfixed_const(4);
3106 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3107 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3108 mc_latency_mclk.full += k1.full;
3109
3110 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3111 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3112
3113 /*
3114 HW cursor time assuming worst case of full size colour cursor.
3115 */
3116 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3117 temp_ff.full += trcd_ff.full;
3118 if (temp_ff.full < tras_ff.full)
3119 temp_ff.full = tras_ff.full;
3120 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3121
3122 temp_ff.full = dfixed_const(cur_size);
3123 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3124 /*
3125 Find the total latency for the display data.
3126 */
3127 disp_latency_overhead.full = dfixed_const(8);
3128 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3129 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3130 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3131
3132 if (mc_latency_mclk.full > mc_latency_sclk.full)
3133 disp_latency.full = mc_latency_mclk.full;
3134 else
3135 disp_latency.full = mc_latency_sclk.full;
3136
3137 /* setup Max GRPH_STOP_REQ default value */
3138 if (ASIC_IS_RV100(rdev))
3139 max_stop_req = 0x5c;
3140 else
3141 max_stop_req = 0x7c;
3142
3143 if (mode1) {
3144 /* CRTC1
3145 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3146 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3147 */
3148 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3149
3150 if (stop_req > max_stop_req)
3151 stop_req = max_stop_req;
3152
3153 /*
3154 Find the drain rate of the display buffer.
3155 */
3156 temp_ff.full = dfixed_const((16/pixel_bytes1));
3157 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3158
3159 /*
3160 Find the critical point of the display buffer.
3161 */
3162 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3163 crit_point_ff.full += dfixed_const_half(0);
3164
3165 critical_point = dfixed_trunc(crit_point_ff);
3166
3167 if (rdev->disp_priority == 2) {
3168 critical_point = 0;
3169 }
3170
3171 /*
3172 The critical point should never be above max_stop_req-4. Setting
3173 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3174 */
3175 if (max_stop_req - critical_point < 4)
3176 critical_point = 0;
3177
3178 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3179 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3180 critical_point = 0x10;
3181 }
3182
3183 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3184 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3185 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3186 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3187 if ((rdev->family == CHIP_R350) &&
3188 (stop_req > 0x15)) {
3189 stop_req -= 0x10;
3190 }
3191 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3192 temp |= RADEON_GRPH_BUFFER_SIZE;
3193 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3194 RADEON_GRPH_CRITICAL_AT_SOF |
3195 RADEON_GRPH_STOP_CNTL);
3196 /*
3197 Write the result into the register.
3198 */
3199 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3200 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3201
3202 #if 0
3203 if ((rdev->family == CHIP_RS400) ||
3204 (rdev->family == CHIP_RS480)) {
3205 /* attempt to program RS400 disp regs correctly ??? */
3206 temp = RREG32(RS400_DISP1_REG_CNTL);
3207 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3208 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3209 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3210 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3211 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3212 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3213 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3214 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3215 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3216 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3217 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3218 }
3219 #endif
3220
3221 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3222 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3223 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3224 }
3225
3226 if (mode2) {
3227 u32 grph2_cntl;
3228 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3229
3230 if (stop_req > max_stop_req)
3231 stop_req = max_stop_req;
3232
3233 /*
3234 Find the drain rate of the display buffer.
3235 */
3236 temp_ff.full = dfixed_const((16/pixel_bytes2));
3237 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3238
3239 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3240 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3241 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3242 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3243 if ((rdev->family == CHIP_R350) &&
3244 (stop_req > 0x15)) {
3245 stop_req -= 0x10;
3246 }
3247 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3248 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3249 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3250 RADEON_GRPH_CRITICAL_AT_SOF |
3251 RADEON_GRPH_STOP_CNTL);
3252
3253 if ((rdev->family == CHIP_RS100) ||
3254 (rdev->family == CHIP_RS200))
3255 critical_point2 = 0;
3256 else {
3257 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3258 temp_ff.full = dfixed_const(temp);
3259 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3260 if (sclk_ff.full < temp_ff.full)
3261 temp_ff.full = sclk_ff.full;
3262
3263 read_return_rate.full = temp_ff.full;
3264
3265 if (mode1) {
3266 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3267 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3268 } else {
3269 time_disp1_drop_priority.full = 0;
3270 }
3271 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3272 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3273 crit_point_ff.full += dfixed_const_half(0);
3274
3275 critical_point2 = dfixed_trunc(crit_point_ff);
3276
3277 if (rdev->disp_priority == 2) {
3278 critical_point2 = 0;
3279 }
3280
3281 if (max_stop_req - critical_point2 < 4)
3282 critical_point2 = 0;
3283
3284 }
3285
3286 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3287 /* some R300 cards have problem with this set to 0 */
3288 critical_point2 = 0x10;
3289 }
3290
3291 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3292 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3293
3294 if ((rdev->family == CHIP_RS400) ||
3295 (rdev->family == CHIP_RS480)) {
3296 #if 0
3297 /* attempt to program RS400 disp2 regs correctly ??? */
3298 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3299 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3300 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3301 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3302 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3303 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3304 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3305 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3306 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3307 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3308 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3309 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3310 #endif
3311 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3312 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3313 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3314 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3315 }
3316
3317 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3318 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3319 }
3320 }
3321
3322 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3323 {
3324 DRM_ERROR("pitch %d\n", t->pitch);
3325 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3326 DRM_ERROR("width %d\n", t->width);
3327 DRM_ERROR("width_11 %d\n", t->width_11);
3328 DRM_ERROR("height %d\n", t->height);
3329 DRM_ERROR("height_11 %d\n", t->height_11);
3330 DRM_ERROR("num levels %d\n", t->num_levels);
3331 DRM_ERROR("depth %d\n", t->txdepth);
3332 DRM_ERROR("bpp %d\n", t->cpp);
3333 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3334 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3335 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3336 DRM_ERROR("compress format %d\n", t->compress_format);
3337 }
3338
3339 static int r100_track_compress_size(int compress_format, int w, int h)
3340 {
3341 int block_width, block_height, block_bytes;
3342 int wblocks, hblocks;
3343 int min_wblocks;
3344 int sz;
3345
3346 block_width = 4;
3347 block_height = 4;
3348
3349 switch (compress_format) {
3350 case R100_TRACK_COMP_DXT1:
3351 block_bytes = 8;
3352 min_wblocks = 4;
3353 break;
3354 default:
3355 case R100_TRACK_COMP_DXT35:
3356 block_bytes = 16;
3357 min_wblocks = 2;
3358 break;
3359 }
3360
3361 hblocks = (h + block_height - 1) / block_height;
3362 wblocks = (w + block_width - 1) / block_width;
3363 if (wblocks < min_wblocks)
3364 wblocks = min_wblocks;
3365 sz = wblocks * hblocks * block_bytes;
3366 return sz;
3367 }
3368
3369 static int r100_cs_track_cube(struct radeon_device *rdev,
3370 struct r100_cs_track *track, unsigned idx)
3371 {
3372 unsigned face, w, h;
3373 struct radeon_bo *cube_robj;
3374 unsigned long size;
3375 unsigned compress_format = track->textures[idx].compress_format;
3376
3377 for (face = 0; face < 5; face++) {
3378 cube_robj = track->textures[idx].cube_info[face].robj;
3379 w = track->textures[idx].cube_info[face].width;
3380 h = track->textures[idx].cube_info[face].height;
3381
3382 if (compress_format) {
3383 size = r100_track_compress_size(compress_format, w, h);
3384 } else
3385 size = w * h;
3386 size *= track->textures[idx].cpp;
3387
3388 size += track->textures[idx].cube_info[face].offset;
3389
3390 if (size > radeon_bo_size(cube_robj)) {
3391 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3392 size, radeon_bo_size(cube_robj));
3393 r100_cs_track_texture_print(&track->textures[idx]);
3394 return -1;
3395 }
3396 }
3397 return 0;
3398 }
3399
3400 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3401 struct r100_cs_track *track)
3402 {
3403 struct radeon_bo *robj;
3404 unsigned long size;
3405 unsigned u, i, w, h, d;
3406 int ret;
3407
3408 for (u = 0; u < track->num_texture; u++) {
3409 if (!track->textures[u].enabled)
3410 continue;
3411 if (track->textures[u].lookup_disable)
3412 continue;
3413 robj = track->textures[u].robj;
3414 if (robj == NULL) {
3415 DRM_ERROR("No texture bound to unit %u\n", u);
3416 return -EINVAL;
3417 }
3418 size = 0;
3419 for (i = 0; i <= track->textures[u].num_levels; i++) {
3420 if (track->textures[u].use_pitch) {
3421 if (rdev->family < CHIP_R300)
3422 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3423 else
3424 w = track->textures[u].pitch / (1 << i);
3425 } else {
3426 w = track->textures[u].width;
3427 if (rdev->family >= CHIP_RV515)
3428 w |= track->textures[u].width_11;
3429 w = w / (1 << i);
3430 if (track->textures[u].roundup_w)
3431 w = roundup_pow_of_two(w);
3432 }
3433 h = track->textures[u].height;
3434 if (rdev->family >= CHIP_RV515)
3435 h |= track->textures[u].height_11;
3436 h = h / (1 << i);
3437 if (track->textures[u].roundup_h)
3438 h = roundup_pow_of_two(h);
3439 if (track->textures[u].tex_coord_type == 1) {
3440 d = (1 << track->textures[u].txdepth) / (1 << i);
3441 if (!d)
3442 d = 1;
3443 } else {
3444 d = 1;
3445 }
3446 if (track->textures[u].compress_format) {
3447
3448 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3449 /* compressed textures are block based */
3450 } else
3451 size += w * h * d;
3452 }
3453 size *= track->textures[u].cpp;
3454
3455 switch (track->textures[u].tex_coord_type) {
3456 case 0:
3457 case 1:
3458 break;
3459 case 2:
3460 if (track->separate_cube) {
3461 ret = r100_cs_track_cube(rdev, track, u);
3462 if (ret)
3463 return ret;
3464 } else
3465 size *= 6;
3466 break;
3467 default:
3468 DRM_ERROR("Invalid texture coordinate type %u for unit "
3469 "%u\n", track->textures[u].tex_coord_type, u);
3470 return -EINVAL;
3471 }
3472 if (size > radeon_bo_size(robj)) {
3473 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3474 "%lu\n", u, size, radeon_bo_size(robj));
3475 r100_cs_track_texture_print(&track->textures[u]);
3476 return -EINVAL;
3477 }
3478 }
3479 return 0;
3480 }
3481
3482 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3483 {
3484 unsigned i;
3485 unsigned long size;
3486 unsigned prim_walk;
3487 unsigned nverts;
3488 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3489
3490 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3491 !track->blend_read_enable)
3492 num_cb = 0;
3493
3494 for (i = 0; i < num_cb; i++) {
3495 if (track->cb[i].robj == NULL) {
3496 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3497 return -EINVAL;
3498 }
3499 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3500 size += track->cb[i].offset;
3501 if (size > radeon_bo_size(track->cb[i].robj)) {
3502 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3503 "(need %lu have %lu) !\n", i, size,
3504 radeon_bo_size(track->cb[i].robj));
3505 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3506 i, track->cb[i].pitch, track->cb[i].cpp,
3507 track->cb[i].offset, track->maxy);
3508 return -EINVAL;
3509 }
3510 }
3511 track->cb_dirty = false;
3512
3513 if (track->zb_dirty && track->z_enabled) {
3514 if (track->zb.robj == NULL) {
3515 DRM_ERROR("[drm] No buffer for z buffer !\n");
3516 return -EINVAL;
3517 }
3518 size = track->zb.pitch * track->zb.cpp * track->maxy;
3519 size += track->zb.offset;
3520 if (size > radeon_bo_size(track->zb.robj)) {
3521 DRM_ERROR("[drm] Buffer too small for z buffer "
3522 "(need %lu have %lu) !\n", size,
3523 radeon_bo_size(track->zb.robj));
3524 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3525 track->zb.pitch, track->zb.cpp,
3526 track->zb.offset, track->maxy);
3527 return -EINVAL;
3528 }
3529 }
3530 track->zb_dirty = false;
3531
3532 if (track->aa_dirty && track->aaresolve) {
3533 if (track->aa.robj == NULL) {
3534 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3535 return -EINVAL;
3536 }
3537 /* I believe the format comes from colorbuffer0. */
3538 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3539 size += track->aa.offset;
3540 if (size > radeon_bo_size(track->aa.robj)) {
3541 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3542 "(need %lu have %lu) !\n", i, size,
3543 radeon_bo_size(track->aa.robj));
3544 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3545 i, track->aa.pitch, track->cb[0].cpp,
3546 track->aa.offset, track->maxy);
3547 return -EINVAL;
3548 }
3549 }
3550 track->aa_dirty = false;
3551
3552 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3553 if (track->vap_vf_cntl & (1 << 14)) {
3554 nverts = track->vap_alt_nverts;
3555 } else {
3556 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3557 }
3558 switch (prim_walk) {
3559 case 1:
3560 for (i = 0; i < track->num_arrays; i++) {
3561 size = track->arrays[i].esize * track->max_indx * 4;
3562 if (track->arrays[i].robj == NULL) {
3563 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3564 "bound\n", prim_walk, i);
3565 return -EINVAL;
3566 }
3567 if (size > radeon_bo_size(track->arrays[i].robj)) {
3568 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3569 "need %lu dwords have %lu dwords\n",
3570 prim_walk, i, size >> 2,
3571 radeon_bo_size(track->arrays[i].robj)
3572 >> 2);
3573 DRM_ERROR("Max indices %u\n", track->max_indx);
3574 return -EINVAL;
3575 }
3576 }
3577 break;
3578 case 2:
3579 for (i = 0; i < track->num_arrays; i++) {
3580 size = track->arrays[i].esize * (nverts - 1) * 4;
3581 if (track->arrays[i].robj == NULL) {
3582 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3583 "bound\n", prim_walk, i);
3584 return -EINVAL;
3585 }
3586 if (size > radeon_bo_size(track->arrays[i].robj)) {
3587 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3588 "need %lu dwords have %lu dwords\n",
3589 prim_walk, i, size >> 2,
3590 radeon_bo_size(track->arrays[i].robj)
3591 >> 2);
3592 return -EINVAL;
3593 }
3594 }
3595 break;
3596 case 3:
3597 size = track->vtx_size * nverts;
3598 if (size != track->immd_dwords) {
3599 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3600 track->immd_dwords, size);
3601 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3602 nverts, track->vtx_size);
3603 return -EINVAL;
3604 }
3605 break;
3606 default:
3607 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3608 prim_walk);
3609 return -EINVAL;
3610 }
3611
3612 if (track->tex_dirty) {
3613 track->tex_dirty = false;
3614 return r100_cs_track_texture_check(rdev, track);
3615 }
3616 return 0;
3617 }
3618
3619 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3620 {
3621 unsigned i, face;
3622
3623 track->cb_dirty = true;
3624 track->zb_dirty = true;
3625 track->tex_dirty = true;
3626 track->aa_dirty = true;
3627
3628 if (rdev->family < CHIP_R300) {
3629 track->num_cb = 1;
3630 if (rdev->family <= CHIP_RS200)
3631 track->num_texture = 3;
3632 else
3633 track->num_texture = 6;
3634 track->maxy = 2048;
3635 track->separate_cube = 1;
3636 } else {
3637 track->num_cb = 4;
3638 track->num_texture = 16;
3639 track->maxy = 4096;
3640 track->separate_cube = 0;
3641 track->aaresolve = false;
3642 track->aa.robj = NULL;
3643 }
3644
3645 for (i = 0; i < track->num_cb; i++) {
3646 track->cb[i].robj = NULL;
3647 track->cb[i].pitch = 8192;
3648 track->cb[i].cpp = 16;
3649 track->cb[i].offset = 0;
3650 }
3651 track->z_enabled = true;
3652 track->zb.robj = NULL;
3653 track->zb.pitch = 8192;
3654 track->zb.cpp = 4;
3655 track->zb.offset = 0;
3656 track->vtx_size = 0x7F;
3657 track->immd_dwords = 0xFFFFFFFFUL;
3658 track->num_arrays = 11;
3659 track->max_indx = 0x00FFFFFFUL;
3660 for (i = 0; i < track->num_arrays; i++) {
3661 track->arrays[i].robj = NULL;
3662 track->arrays[i].esize = 0x7F;
3663 }
3664 for (i = 0; i < track->num_texture; i++) {
3665 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3666 track->textures[i].pitch = 16536;
3667 track->textures[i].width = 16536;
3668 track->textures[i].height = 16536;
3669 track->textures[i].width_11 = 1 << 11;
3670 track->textures[i].height_11 = 1 << 11;
3671 track->textures[i].num_levels = 12;
3672 if (rdev->family <= CHIP_RS200) {
3673 track->textures[i].tex_coord_type = 0;
3674 track->textures[i].txdepth = 0;
3675 } else {
3676 track->textures[i].txdepth = 16;
3677 track->textures[i].tex_coord_type = 1;
3678 }
3679 track->textures[i].cpp = 64;
3680 track->textures[i].robj = NULL;
3681 /* CS IB emission code makes sure texture unit are disabled */
3682 track->textures[i].enabled = false;
3683 track->textures[i].lookup_disable = false;
3684 track->textures[i].roundup_w = true;
3685 track->textures[i].roundup_h = true;
3686 if (track->separate_cube)
3687 for (face = 0; face < 5; face++) {
3688 track->textures[i].cube_info[face].robj = NULL;
3689 track->textures[i].cube_info[face].width = 16536;
3690 track->textures[i].cube_info[face].height = 16536;
3691 track->textures[i].cube_info[face].offset = 0;
3692 }
3693 }
3694 }
3695
3696 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3697 {
3698 uint32_t scratch;
3699 uint32_t tmp = 0;
3700 unsigned i;
3701 int r;
3702
3703 r = radeon_scratch_get(rdev, &scratch);
3704 if (r) {
3705 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3706 return r;
3707 }
3708 WREG32(scratch, 0xCAFEDEAD);
3709 r = radeon_ring_lock(rdev, ring, 2);
3710 if (r) {
3711 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3712 radeon_scratch_free(rdev, scratch);
3713 return r;
3714 }
3715 radeon_ring_write(ring, PACKET0(scratch, 0));
3716 radeon_ring_write(ring, 0xDEADBEEF);
3717 radeon_ring_unlock_commit(rdev, ring);
3718 for (i = 0; i < rdev->usec_timeout; i++) {
3719 tmp = RREG32(scratch);
3720 if (tmp == 0xDEADBEEF) {
3721 break;
3722 }
3723 DRM_UDELAY(1);
3724 }
3725 if (i < rdev->usec_timeout) {
3726 DRM_INFO("ring test succeeded in %d usecs\n", i);
3727 } else {
3728 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3729 scratch, tmp);
3730 r = -EINVAL;
3731 }
3732 radeon_scratch_free(rdev, scratch);
3733 return r;
3734 }
3735
3736 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3737 {
3738 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3739
3740 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3741 radeon_ring_write(ring, ib->gpu_addr);
3742 radeon_ring_write(ring, ib->length_dw);
3743 }
3744
3745 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3746 {
3747 struct radeon_ib *ib;
3748 uint32_t scratch;
3749 uint32_t tmp = 0;
3750 unsigned i;
3751 int r;
3752
3753 r = radeon_scratch_get(rdev, &scratch);
3754 if (r) {
3755 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3756 return r;
3757 }
3758 WREG32(scratch, 0xCAFEDEAD);
3759 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3760 if (r) {
3761 return r;
3762 }
3763 ib->ptr[0] = PACKET0(scratch, 0);
3764 ib->ptr[1] = 0xDEADBEEF;
3765 ib->ptr[2] = PACKET2(0);
3766 ib->ptr[3] = PACKET2(0);
3767 ib->ptr[4] = PACKET2(0);
3768 ib->ptr[5] = PACKET2(0);
3769 ib->ptr[6] = PACKET2(0);
3770 ib->ptr[7] = PACKET2(0);
3771 ib->length_dw = 8;
3772 r = radeon_ib_schedule(rdev, ib);
3773 if (r) {
3774 radeon_scratch_free(rdev, scratch);
3775 radeon_ib_free(rdev, &ib);
3776 return r;
3777 }
3778 r = radeon_fence_wait(ib->fence, false);
3779 if (r) {
3780 return r;
3781 }
3782 for (i = 0; i < rdev->usec_timeout; i++) {
3783 tmp = RREG32(scratch);
3784 if (tmp == 0xDEADBEEF) {
3785 break;
3786 }
3787 DRM_UDELAY(1);
3788 }
3789 if (i < rdev->usec_timeout) {
3790 DRM_INFO("ib test succeeded in %u usecs\n", i);
3791 } else {
3792 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3793 scratch, tmp);
3794 r = -EINVAL;
3795 }
3796 radeon_scratch_free(rdev, scratch);
3797 radeon_ib_free(rdev, &ib);
3798 return r;
3799 }
3800
3801 void r100_ib_fini(struct radeon_device *rdev)
3802 {
3803 radeon_ib_pool_suspend(rdev);
3804 radeon_ib_pool_fini(rdev);
3805 }
3806
3807 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3808 {
3809 /* Shutdown CP we shouldn't need to do that but better be safe than
3810 * sorry
3811 */
3812 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3813 WREG32(R_000740_CP_CSQ_CNTL, 0);
3814
3815 /* Save few CRTC registers */
3816 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3817 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3818 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3819 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3820 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3821 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3822 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3823 }
3824
3825 /* Disable VGA aperture access */
3826 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3827 /* Disable cursor, overlay, crtc */
3828 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3829 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3830 S_000054_CRTC_DISPLAY_DIS(1));
3831 WREG32(R_000050_CRTC_GEN_CNTL,
3832 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3833 S_000050_CRTC_DISP_REQ_EN_B(1));
3834 WREG32(R_000420_OV0_SCALE_CNTL,
3835 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3836 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3837 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3838 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3839 S_000360_CUR2_LOCK(1));
3840 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3841 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3842 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3843 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3844 WREG32(R_000360_CUR2_OFFSET,
3845 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3846 }
3847 }
3848
3849 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3850 {
3851 /* Update base address for crtc */
3852 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3853 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3854 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3855 }
3856 /* Restore CRTC registers */
3857 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3858 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3859 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3860 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3861 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3862 }
3863 }
3864
3865 void r100_vga_render_disable(struct radeon_device *rdev)
3866 {
3867 u32 tmp;
3868
3869 tmp = RREG8(R_0003C2_GENMO_WT);
3870 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3871 }
3872
3873 static void r100_debugfs(struct radeon_device *rdev)
3874 {
3875 int r;
3876
3877 r = r100_debugfs_mc_info_init(rdev);
3878 if (r)
3879 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3880 }
3881
3882 static void r100_mc_program(struct radeon_device *rdev)
3883 {
3884 struct r100_mc_save save;
3885
3886 /* Stops all mc clients */
3887 r100_mc_stop(rdev, &save);
3888 if (rdev->flags & RADEON_IS_AGP) {
3889 WREG32(R_00014C_MC_AGP_LOCATION,
3890 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3891 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3892 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3893 if (rdev->family > CHIP_RV200)
3894 WREG32(R_00015C_AGP_BASE_2,
3895 upper_32_bits(rdev->mc.agp_base) & 0xff);
3896 } else {
3897 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3898 WREG32(R_000170_AGP_BASE, 0);
3899 if (rdev->family > CHIP_RV200)
3900 WREG32(R_00015C_AGP_BASE_2, 0);
3901 }
3902 /* Wait for mc idle */
3903 if (r100_mc_wait_for_idle(rdev))
3904 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3905 /* Program MC, should be a 32bits limited address space */
3906 WREG32(R_000148_MC_FB_LOCATION,
3907 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3908 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3909 r100_mc_resume(rdev, &save);
3910 }
3911
3912 void r100_clock_startup(struct radeon_device *rdev)
3913 {
3914 u32 tmp;
3915
3916 if (radeon_dynclks != -1 && radeon_dynclks)
3917 radeon_legacy_set_clock_gating(rdev, 1);
3918 /* We need to force on some of the block */
3919 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3920 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3921 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3922 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3923 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3924 }
3925
3926 static int r100_startup(struct radeon_device *rdev)
3927 {
3928 int r;
3929
3930 /* set common regs */
3931 r100_set_common_regs(rdev);
3932 /* program mc */
3933 r100_mc_program(rdev);
3934 /* Resume clock */
3935 r100_clock_startup(rdev);
3936 /* Initialize GART (initialize after TTM so we can allocate
3937 * memory through TTM but finalize after TTM) */
3938 r100_enable_bm(rdev);
3939 if (rdev->flags & RADEON_IS_PCI) {
3940 r = r100_pci_gart_enable(rdev);
3941 if (r)
3942 return r;
3943 }
3944
3945 /* allocate wb buffer */
3946 r = radeon_wb_init(rdev);
3947 if (r)
3948 return r;
3949
3950 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3951 if (r) {
3952 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3953 return r;
3954 }
3955
3956 /* Enable IRQ */
3957 r100_irq_set(rdev);
3958 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3959 /* 1M ring buffer */
3960 r = r100_cp_init(rdev, 1024 * 1024);
3961 if (r) {
3962 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3963 return r;
3964 }
3965
3966 r = radeon_ib_pool_start(rdev);
3967 if (r)
3968 return r;
3969
3970 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3971 if (r) {
3972 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3973 rdev->accel_working = false;
3974 return r;
3975 }
3976
3977 return 0;
3978 }
3979
3980 int r100_resume(struct radeon_device *rdev)
3981 {
3982 /* Make sur GART are not working */
3983 if (rdev->flags & RADEON_IS_PCI)
3984 r100_pci_gart_disable(rdev);
3985 /* Resume clock before doing reset */
3986 r100_clock_startup(rdev);
3987 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3988 if (radeon_asic_reset(rdev)) {
3989 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3990 RREG32(R_000E40_RBBM_STATUS),
3991 RREG32(R_0007C0_CP_STAT));
3992 }
3993 /* post */
3994 radeon_combios_asic_init(rdev->ddev);
3995 /* Resume clock after posting */
3996 r100_clock_startup(rdev);
3997 /* Initialize surface registers */
3998 radeon_surface_init(rdev);
3999
4000 rdev->accel_working = true;
4001 return r100_startup(rdev);
4002 }
4003
4004 int r100_suspend(struct radeon_device *rdev)
4005 {
4006 radeon_ib_pool_suspend(rdev);
4007 r100_cp_disable(rdev);
4008 radeon_wb_disable(rdev);
4009 r100_irq_disable(rdev);
4010 if (rdev->flags & RADEON_IS_PCI)
4011 r100_pci_gart_disable(rdev);
4012 return 0;
4013 }
4014
4015 void r100_fini(struct radeon_device *rdev)
4016 {
4017 r100_cp_fini(rdev);
4018 radeon_wb_fini(rdev);
4019 r100_ib_fini(rdev);
4020 radeon_gem_fini(rdev);
4021 if (rdev->flags & RADEON_IS_PCI)
4022 r100_pci_gart_fini(rdev);
4023 radeon_agp_fini(rdev);
4024 radeon_irq_kms_fini(rdev);
4025 radeon_fence_driver_fini(rdev);
4026 radeon_bo_fini(rdev);
4027 radeon_atombios_fini(rdev);
4028 kfree(rdev->bios);
4029 rdev->bios = NULL;
4030 }
4031
4032 /*
4033 * Due to how kexec works, it can leave the hw fully initialised when it
4034 * boots the new kernel. However doing our init sequence with the CP and
4035 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4036 * do some quick sanity checks and restore sane values to avoid this
4037 * problem.
4038 */
4039 void r100_restore_sanity(struct radeon_device *rdev)
4040 {
4041 u32 tmp;
4042
4043 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4044 if (tmp) {
4045 WREG32(RADEON_CP_CSQ_CNTL, 0);
4046 }
4047 tmp = RREG32(RADEON_CP_RB_CNTL);
4048 if (tmp) {
4049 WREG32(RADEON_CP_RB_CNTL, 0);
4050 }
4051 tmp = RREG32(RADEON_SCRATCH_UMSK);
4052 if (tmp) {
4053 WREG32(RADEON_SCRATCH_UMSK, 0);
4054 }
4055 }
4056
4057 int r100_init(struct radeon_device *rdev)
4058 {
4059 int r;
4060
4061 /* Register debugfs file specific to this group of asics */
4062 r100_debugfs(rdev);
4063 /* Disable VGA */
4064 r100_vga_render_disable(rdev);
4065 /* Initialize scratch registers */
4066 radeon_scratch_init(rdev);
4067 /* Initialize surface registers */
4068 radeon_surface_init(rdev);
4069 /* sanity check some register to avoid hangs like after kexec */
4070 r100_restore_sanity(rdev);
4071 /* TODO: disable VGA need to use VGA request */
4072 /* BIOS*/
4073 if (!radeon_get_bios(rdev)) {
4074 if (ASIC_IS_AVIVO(rdev))
4075 return -EINVAL;
4076 }
4077 if (rdev->is_atom_bios) {
4078 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4079 return -EINVAL;
4080 } else {
4081 r = radeon_combios_init(rdev);
4082 if (r)
4083 return r;
4084 }
4085 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4086 if (radeon_asic_reset(rdev)) {
4087 dev_warn(rdev->dev,
4088 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4089 RREG32(R_000E40_RBBM_STATUS),
4090 RREG32(R_0007C0_CP_STAT));
4091 }
4092 /* check if cards are posted or not */
4093 if (radeon_boot_test_post_card(rdev) == false)
4094 return -EINVAL;
4095 /* Set asic errata */
4096 r100_errata(rdev);
4097 /* Initialize clocks */
4098 radeon_get_clock_info(rdev->ddev);
4099 /* initialize AGP */
4100 if (rdev->flags & RADEON_IS_AGP) {
4101 r = radeon_agp_init(rdev);
4102 if (r) {
4103 radeon_agp_disable(rdev);
4104 }
4105 }
4106 /* initialize VRAM */
4107 r100_mc_init(rdev);
4108 /* Fence driver */
4109 r = radeon_fence_driver_init(rdev);
4110 if (r)
4111 return r;
4112 r = radeon_irq_kms_init(rdev);
4113 if (r)
4114 return r;
4115 /* Memory manager */
4116 r = radeon_bo_init(rdev);
4117 if (r)
4118 return r;
4119 if (rdev->flags & RADEON_IS_PCI) {
4120 r = r100_pci_gart_init(rdev);
4121 if (r)
4122 return r;
4123 }
4124 r100_set_safe_registers(rdev);
4125
4126 r = radeon_ib_pool_init(rdev);
4127 rdev->accel_working = true;
4128 if (r) {
4129 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4130 rdev->accel_working = false;
4131 }
4132
4133 r = r100_startup(rdev);
4134 if (r) {
4135 /* Somethings want wront with the accel init stop accel */
4136 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4137 r100_cp_fini(rdev);
4138 radeon_wb_fini(rdev);
4139 r100_ib_fini(rdev);
4140 radeon_irq_kms_fini(rdev);
4141 if (rdev->flags & RADEON_IS_PCI)
4142 r100_pci_gart_fini(rdev);
4143 rdev->accel_working = false;
4144 }
4145 return 0;
4146 }
4147
4148 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4149 {
4150 if (reg < rdev->rmmio_size)
4151 return readl(((void __iomem *)rdev->rmmio) + reg);
4152 else {
4153 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4154 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4155 }
4156 }
4157
4158 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4159 {
4160 if (reg < rdev->rmmio_size)
4161 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4162 else {
4163 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4164 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4165 }
4166 }
4167
4168 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4169 {
4170 if (reg < rdev->rio_mem_size)
4171 return ioread32(rdev->rio_mem + reg);
4172 else {
4173 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4174 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4175 }
4176 }
4177
4178 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4179 {
4180 if (reg < rdev->rio_mem_size)
4181 iowrite32(v, rdev->rio_mem + reg);
4182 else {
4183 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4184 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4185 }
4186 }
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