2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
54 MODULE_FIRMWARE(FIRMWARE_R100
);
55 MODULE_FIRMWARE(FIRMWARE_R200
);
56 MODULE_FIRMWARE(FIRMWARE_R300
);
57 MODULE_FIRMWARE(FIRMWARE_R420
);
58 MODULE_FIRMWARE(FIRMWARE_RS690
);
59 MODULE_FIRMWARE(FIRMWARE_RS600
);
60 MODULE_FIRMWARE(FIRMWARE_R520
);
62 #include "r100_track.h"
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 /* hpd for digital panel detect/disconnect */
69 bool r100_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
71 bool connected
= false;
75 if (RREG32(RADEON_FP_GEN_CNTL
) & RADEON_FP_DETECT_SENSE
)
79 if (RREG32(RADEON_FP2_GEN_CNTL
) & RADEON_FP2_DETECT_SENSE
)
88 void r100_hpd_set_polarity(struct radeon_device
*rdev
,
89 enum radeon_hpd_id hpd
)
92 bool connected
= r100_hpd_sense(rdev
, hpd
);
96 tmp
= RREG32(RADEON_FP_GEN_CNTL
);
98 tmp
&= ~RADEON_FP_DETECT_INT_POL
;
100 tmp
|= RADEON_FP_DETECT_INT_POL
;
101 WREG32(RADEON_FP_GEN_CNTL
, tmp
);
104 tmp
= RREG32(RADEON_FP2_GEN_CNTL
);
106 tmp
&= ~RADEON_FP2_DETECT_INT_POL
;
108 tmp
|= RADEON_FP2_DETECT_INT_POL
;
109 WREG32(RADEON_FP2_GEN_CNTL
, tmp
);
116 void r100_hpd_init(struct radeon_device
*rdev
)
118 struct drm_device
*dev
= rdev
->ddev
;
119 struct drm_connector
*connector
;
121 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
122 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
123 switch (radeon_connector
->hpd
.hpd
) {
125 rdev
->irq
.hpd
[0] = true;
128 rdev
->irq
.hpd
[1] = true;
134 if (rdev
->irq
.installed
)
138 void r100_hpd_fini(struct radeon_device
*rdev
)
140 struct drm_device
*dev
= rdev
->ddev
;
141 struct drm_connector
*connector
;
143 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
144 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
145 switch (radeon_connector
->hpd
.hpd
) {
147 rdev
->irq
.hpd
[0] = false;
150 rdev
->irq
.hpd
[1] = false;
161 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
)
163 /* TODO: can we do somethings here ? */
164 /* It seems hw only cache one entry so we should discard this
165 * entry otherwise if first GPU GART read hit this entry it
166 * could end up in wrong address. */
169 int r100_pci_gart_init(struct radeon_device
*rdev
)
173 if (rdev
->gart
.table
.ram
.ptr
) {
174 WARN(1, "R100 PCI GART already initialized.\n");
177 /* Initialize common gart structure */
178 r
= radeon_gart_init(rdev
);
181 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
182 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
183 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
184 return radeon_gart_table_ram_alloc(rdev
);
187 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
188 void r100_enable_bm(struct radeon_device
*rdev
)
191 /* Enable bus mastering */
192 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
193 WREG32(RADEON_BUS_CNTL
, tmp
);
196 int r100_pci_gart_enable(struct radeon_device
*rdev
)
200 radeon_gart_restore(rdev
);
201 /* discard memory request outside of configured range */
202 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
203 WREG32(RADEON_AIC_CNTL
, tmp
);
204 /* set address range for PCI address translate */
205 WREG32(RADEON_AIC_LO_ADDR
, rdev
->mc
.gtt_location
);
206 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
207 WREG32(RADEON_AIC_HI_ADDR
, tmp
);
208 /* set PCI GART page-table base address */
209 WREG32(RADEON_AIC_PT_BASE
, rdev
->gart
.table_addr
);
210 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_PCIGART_TRANSLATE_EN
;
211 WREG32(RADEON_AIC_CNTL
, tmp
);
212 r100_pci_gart_tlb_flush(rdev
);
213 rdev
->gart
.ready
= true;
217 void r100_pci_gart_disable(struct radeon_device
*rdev
)
221 /* discard memory request outside of configured range */
222 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
223 WREG32(RADEON_AIC_CNTL
, tmp
& ~RADEON_PCIGART_TRANSLATE_EN
);
224 WREG32(RADEON_AIC_LO_ADDR
, 0);
225 WREG32(RADEON_AIC_HI_ADDR
, 0);
228 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
230 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
233 rdev
->gart
.table
.ram
.ptr
[i
] = cpu_to_le32(lower_32_bits(addr
));
237 void r100_pci_gart_fini(struct radeon_device
*rdev
)
239 r100_pci_gart_disable(rdev
);
240 radeon_gart_table_ram_free(rdev
);
241 radeon_gart_fini(rdev
);
244 int r100_irq_set(struct radeon_device
*rdev
)
248 if (!rdev
->irq
.installed
) {
249 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
250 WREG32(R_000040_GEN_INT_CNTL
, 0);
253 if (rdev
->irq
.sw_int
) {
254 tmp
|= RADEON_SW_INT_ENABLE
;
256 if (rdev
->irq
.crtc_vblank_int
[0]) {
257 tmp
|= RADEON_CRTC_VBLANK_MASK
;
259 if (rdev
->irq
.crtc_vblank_int
[1]) {
260 tmp
|= RADEON_CRTC2_VBLANK_MASK
;
262 if (rdev
->irq
.hpd
[0]) {
263 tmp
|= RADEON_FP_DETECT_MASK
;
265 if (rdev
->irq
.hpd
[1]) {
266 tmp
|= RADEON_FP2_DETECT_MASK
;
268 WREG32(RADEON_GEN_INT_CNTL
, tmp
);
272 void r100_irq_disable(struct radeon_device
*rdev
)
276 WREG32(R_000040_GEN_INT_CNTL
, 0);
277 /* Wait and acknowledge irq */
279 tmp
= RREG32(R_000044_GEN_INT_STATUS
);
280 WREG32(R_000044_GEN_INT_STATUS
, tmp
);
283 static inline uint32_t r100_irq_ack(struct radeon_device
*rdev
)
285 uint32_t irqs
= RREG32(RADEON_GEN_INT_STATUS
);
286 uint32_t irq_mask
= RADEON_SW_INT_TEST
|
287 RADEON_CRTC_VBLANK_STAT
| RADEON_CRTC2_VBLANK_STAT
|
288 RADEON_FP_DETECT_STAT
| RADEON_FP2_DETECT_STAT
;
291 WREG32(RADEON_GEN_INT_STATUS
, irqs
);
293 return irqs
& irq_mask
;
296 int r100_irq_process(struct radeon_device
*rdev
)
298 uint32_t status
, msi_rearm
;
299 bool queue_hotplug
= false;
301 status
= r100_irq_ack(rdev
);
305 if (rdev
->shutdown
) {
310 if (status
& RADEON_SW_INT_TEST
) {
311 radeon_fence_process(rdev
);
313 /* Vertical blank interrupts */
314 if (status
& RADEON_CRTC_VBLANK_STAT
) {
315 drm_handle_vblank(rdev
->ddev
, 0);
316 wake_up(&rdev
->irq
.vblank_queue
);
318 if (status
& RADEON_CRTC2_VBLANK_STAT
) {
319 drm_handle_vblank(rdev
->ddev
, 1);
320 wake_up(&rdev
->irq
.vblank_queue
);
322 if (status
& RADEON_FP_DETECT_STAT
) {
323 queue_hotplug
= true;
326 if (status
& RADEON_FP2_DETECT_STAT
) {
327 queue_hotplug
= true;
330 status
= r100_irq_ack(rdev
);
333 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
334 if (rdev
->msi_enabled
) {
335 switch (rdev
->family
) {
338 msi_rearm
= RREG32(RADEON_AIC_CNTL
) & ~RS400_MSI_REARM
;
339 WREG32(RADEON_AIC_CNTL
, msi_rearm
);
340 WREG32(RADEON_AIC_CNTL
, msi_rearm
| RS400_MSI_REARM
);
343 msi_rearm
= RREG32(RADEON_MSI_REARM_EN
) & ~RV370_MSI_REARM_EN
;
344 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
);
345 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
| RV370_MSI_REARM_EN
);
352 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
355 return RREG32(RADEON_CRTC_CRNT_FRAME
);
357 return RREG32(RADEON_CRTC2_CRNT_FRAME
);
360 /* Who ever call radeon_fence_emit should call ring_lock and ask
361 * for enough space (today caller are ib schedule and buffer move) */
362 void r100_fence_ring_emit(struct radeon_device
*rdev
,
363 struct radeon_fence
*fence
)
365 /* We have to make sure that caches are flushed before
366 * CPU might read something from VRAM. */
367 radeon_ring_write(rdev
, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT
, 0));
368 radeon_ring_write(rdev
, RADEON_RB3D_DC_FLUSH_ALL
);
369 radeon_ring_write(rdev
, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT
, 0));
370 radeon_ring_write(rdev
, RADEON_RB3D_ZC_FLUSH_ALL
);
371 /* Wait until IDLE & CLEAN */
372 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
373 radeon_ring_write(rdev
, RADEON_WAIT_2D_IDLECLEAN
| RADEON_WAIT_3D_IDLECLEAN
);
374 radeon_ring_write(rdev
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
375 radeon_ring_write(rdev
, rdev
->config
.r100
.hdp_cntl
|
376 RADEON_HDP_READ_BUFFER_INVALIDATE
);
377 radeon_ring_write(rdev
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
378 radeon_ring_write(rdev
, rdev
->config
.r100
.hdp_cntl
);
379 /* Emit fence sequence & fire IRQ */
380 radeon_ring_write(rdev
, PACKET0(rdev
->fence_drv
.scratch_reg
, 0));
381 radeon_ring_write(rdev
, fence
->seq
);
382 radeon_ring_write(rdev
, PACKET0(RADEON_GEN_INT_STATUS
, 0));
383 radeon_ring_write(rdev
, RADEON_SW_INT_FIRE
);
386 int r100_wb_init(struct radeon_device
*rdev
)
390 if (rdev
->wb
.wb_obj
== NULL
) {
391 r
= radeon_bo_create(rdev
, NULL
, RADEON_GPU_PAGE_SIZE
, true,
392 RADEON_GEM_DOMAIN_GTT
,
395 dev_err(rdev
->dev
, "(%d) create WB buffer failed\n", r
);
398 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
399 if (unlikely(r
!= 0))
401 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
404 dev_err(rdev
->dev
, "(%d) pin WB buffer failed\n", r
);
405 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
408 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
409 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
411 dev_err(rdev
->dev
, "(%d) map WB buffer failed\n", r
);
415 WREG32(R_000774_SCRATCH_ADDR
, rdev
->wb
.gpu_addr
);
416 WREG32(R_00070C_CP_RB_RPTR_ADDR
,
417 S_00070C_RB_RPTR_ADDR((rdev
->wb
.gpu_addr
+ 1024) >> 2));
418 WREG32(R_000770_SCRATCH_UMSK
, 0xff);
422 void r100_wb_disable(struct radeon_device
*rdev
)
424 WREG32(R_000770_SCRATCH_UMSK
, 0);
427 void r100_wb_fini(struct radeon_device
*rdev
)
431 r100_wb_disable(rdev
);
432 if (rdev
->wb
.wb_obj
) {
433 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
434 if (unlikely(r
!= 0)) {
435 dev_err(rdev
->dev
, "(%d) can't finish WB\n", r
);
438 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
439 radeon_bo_unpin(rdev
->wb
.wb_obj
);
440 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
441 radeon_bo_unref(&rdev
->wb
.wb_obj
);
443 rdev
->wb
.wb_obj
= NULL
;
447 int r100_copy_blit(struct radeon_device
*rdev
,
451 struct radeon_fence
*fence
)
454 uint32_t stride_bytes
= PAGE_SIZE
;
456 uint32_t stride_pixels
;
461 /* radeon limited to 16k stride */
462 stride_bytes
&= 0x3fff;
463 /* radeon pitch is /64 */
464 pitch
= stride_bytes
/ 64;
465 stride_pixels
= stride_bytes
/ 4;
466 num_loops
= DIV_ROUND_UP(num_pages
, 8191);
468 /* Ask for enough room for blit + flush + fence */
469 ndw
= 64 + (10 * num_loops
);
470 r
= radeon_ring_lock(rdev
, ndw
);
472 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r
, ndw
);
475 while (num_pages
> 0) {
476 cur_pages
= num_pages
;
477 if (cur_pages
> 8191) {
480 num_pages
-= cur_pages
;
482 /* pages are in Y direction - height
483 page width in X direction - width */
484 radeon_ring_write(rdev
, PACKET3(PACKET3_BITBLT_MULTI
, 8));
485 radeon_ring_write(rdev
,
486 RADEON_GMC_SRC_PITCH_OFFSET_CNTL
|
487 RADEON_GMC_DST_PITCH_OFFSET_CNTL
|
488 RADEON_GMC_SRC_CLIPPING
|
489 RADEON_GMC_DST_CLIPPING
|
490 RADEON_GMC_BRUSH_NONE
|
491 (RADEON_COLOR_FORMAT_ARGB8888
<< 8) |
492 RADEON_GMC_SRC_DATATYPE_COLOR
|
494 RADEON_DP_SRC_SOURCE_MEMORY
|
495 RADEON_GMC_CLR_CMP_CNTL_DIS
|
496 RADEON_GMC_WR_MSK_DIS
);
497 radeon_ring_write(rdev
, (pitch
<< 22) | (src_offset
>> 10));
498 radeon_ring_write(rdev
, (pitch
<< 22) | (dst_offset
>> 10));
499 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
500 radeon_ring_write(rdev
, 0);
501 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
502 radeon_ring_write(rdev
, num_pages
);
503 radeon_ring_write(rdev
, num_pages
);
504 radeon_ring_write(rdev
, cur_pages
| (stride_pixels
<< 16));
506 radeon_ring_write(rdev
, PACKET0(RADEON_DSTCACHE_CTLSTAT
, 0));
507 radeon_ring_write(rdev
, RADEON_RB2D_DC_FLUSH_ALL
);
508 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
509 radeon_ring_write(rdev
,
510 RADEON_WAIT_2D_IDLECLEAN
|
511 RADEON_WAIT_HOST_IDLECLEAN
|
512 RADEON_WAIT_DMA_GUI_IDLE
);
514 r
= radeon_fence_emit(rdev
, fence
);
516 radeon_ring_unlock_commit(rdev
);
520 static int r100_cp_wait_for_idle(struct radeon_device
*rdev
)
525 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
526 tmp
= RREG32(R_000E40_RBBM_STATUS
);
527 if (!G_000E40_CP_CMDSTRM_BUSY(tmp
)) {
535 void r100_ring_start(struct radeon_device
*rdev
)
539 r
= radeon_ring_lock(rdev
, 2);
543 radeon_ring_write(rdev
, PACKET0(RADEON_ISYNC_CNTL
, 0));
544 radeon_ring_write(rdev
,
545 RADEON_ISYNC_ANY2D_IDLE3D
|
546 RADEON_ISYNC_ANY3D_IDLE2D
|
547 RADEON_ISYNC_WAIT_IDLEGUI
|
548 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
549 radeon_ring_unlock_commit(rdev
);
553 /* Load the microcode for the CP */
554 static int r100_cp_init_microcode(struct radeon_device
*rdev
)
556 struct platform_device
*pdev
;
557 const char *fw_name
= NULL
;
562 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
565 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
568 if ((rdev
->family
== CHIP_R100
) || (rdev
->family
== CHIP_RV100
) ||
569 (rdev
->family
== CHIP_RV200
) || (rdev
->family
== CHIP_RS100
) ||
570 (rdev
->family
== CHIP_RS200
)) {
571 DRM_INFO("Loading R100 Microcode\n");
572 fw_name
= FIRMWARE_R100
;
573 } else if ((rdev
->family
== CHIP_R200
) ||
574 (rdev
->family
== CHIP_RV250
) ||
575 (rdev
->family
== CHIP_RV280
) ||
576 (rdev
->family
== CHIP_RS300
)) {
577 DRM_INFO("Loading R200 Microcode\n");
578 fw_name
= FIRMWARE_R200
;
579 } else if ((rdev
->family
== CHIP_R300
) ||
580 (rdev
->family
== CHIP_R350
) ||
581 (rdev
->family
== CHIP_RV350
) ||
582 (rdev
->family
== CHIP_RV380
) ||
583 (rdev
->family
== CHIP_RS400
) ||
584 (rdev
->family
== CHIP_RS480
)) {
585 DRM_INFO("Loading R300 Microcode\n");
586 fw_name
= FIRMWARE_R300
;
587 } else if ((rdev
->family
== CHIP_R420
) ||
588 (rdev
->family
== CHIP_R423
) ||
589 (rdev
->family
== CHIP_RV410
)) {
590 DRM_INFO("Loading R400 Microcode\n");
591 fw_name
= FIRMWARE_R420
;
592 } else if ((rdev
->family
== CHIP_RS690
) ||
593 (rdev
->family
== CHIP_RS740
)) {
594 DRM_INFO("Loading RS690/RS740 Microcode\n");
595 fw_name
= FIRMWARE_RS690
;
596 } else if (rdev
->family
== CHIP_RS600
) {
597 DRM_INFO("Loading RS600 Microcode\n");
598 fw_name
= FIRMWARE_RS600
;
599 } else if ((rdev
->family
== CHIP_RV515
) ||
600 (rdev
->family
== CHIP_R520
) ||
601 (rdev
->family
== CHIP_RV530
) ||
602 (rdev
->family
== CHIP_R580
) ||
603 (rdev
->family
== CHIP_RV560
) ||
604 (rdev
->family
== CHIP_RV570
)) {
605 DRM_INFO("Loading R500 Microcode\n");
606 fw_name
= FIRMWARE_R520
;
609 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
610 platform_device_unregister(pdev
);
612 printk(KERN_ERR
"radeon_cp: Failed to load firmware \"%s\"\n",
614 } else if (rdev
->me_fw
->size
% 8) {
616 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
617 rdev
->me_fw
->size
, fw_name
);
619 release_firmware(rdev
->me_fw
);
625 static void r100_cp_load_microcode(struct radeon_device
*rdev
)
627 const __be32
*fw_data
;
630 if (r100_gui_wait_for_idle(rdev
)) {
631 printk(KERN_WARNING
"Failed to wait GUI idle while "
632 "programming pipes. Bad things might happen.\n");
636 size
= rdev
->me_fw
->size
/ 4;
637 fw_data
= (const __be32
*)&rdev
->me_fw
->data
[0];
638 WREG32(RADEON_CP_ME_RAM_ADDR
, 0);
639 for (i
= 0; i
< size
; i
+= 2) {
640 WREG32(RADEON_CP_ME_RAM_DATAH
,
641 be32_to_cpup(&fw_data
[i
]));
642 WREG32(RADEON_CP_ME_RAM_DATAL
,
643 be32_to_cpup(&fw_data
[i
+ 1]));
648 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
)
653 unsigned pre_write_timer
;
654 unsigned pre_write_limit
;
655 unsigned indirect2_start
;
656 unsigned indirect1_start
;
660 if (r100_debugfs_cp_init(rdev
)) {
661 DRM_ERROR("Failed to register debugfs file for CP !\n");
664 tmp
= RREG32(RADEON_CP_CSQ_STAT
);
665 if ((tmp
& (1 << 31))) {
666 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp
);
667 WREG32(RADEON_CP_CSQ_MODE
, 0);
668 WREG32(RADEON_CP_CSQ_CNTL
, 0);
669 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_CP
);
670 tmp
= RREG32(RADEON_RBBM_SOFT_RESET
);
672 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
673 tmp
= RREG32(RADEON_RBBM_SOFT_RESET
);
675 tmp
= RREG32(RADEON_CP_CSQ_STAT
);
676 if ((tmp
& (1 << 31))) {
677 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp
);
680 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp
);
684 r
= r100_cp_init_microcode(rdev
);
686 DRM_ERROR("Failed to load firmware!\n");
691 /* Align ring size */
692 rb_bufsz
= drm_order(ring_size
/ 8);
693 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
694 r100_cp_load_microcode(rdev
);
695 r
= radeon_ring_init(rdev
, ring_size
);
699 /* Each time the cp read 1024 bytes (16 dword/quadword) update
700 * the rptr copy in system ram */
702 /* cp will read 128bytes at a time (4 dwords) */
704 rdev
->cp
.align_mask
= 16 - 1;
705 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
706 pre_write_timer
= 64;
707 /* Force CP_RB_WPTR write if written more than one time before the
711 /* Setup the cp cache like this (cache size is 96 dwords) :
715 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
716 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
717 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
718 * Idea being that most of the gpu cmd will be through indirect1 buffer
719 * so it gets the bigger cache.
721 indirect2_start
= 80;
722 indirect1_start
= 16;
724 WREG32(0x718, pre_write_timer
| (pre_write_limit
<< 28));
725 tmp
= (REG_SET(RADEON_RB_BUFSZ
, rb_bufsz
) |
726 REG_SET(RADEON_RB_BLKSZ
, rb_blksz
) |
727 REG_SET(RADEON_MAX_FETCH
, max_fetch
) |
728 RADEON_RB_NO_UPDATE
);
730 tmp
|= RADEON_BUF_SWAP_32BIT
;
732 WREG32(RADEON_CP_RB_CNTL
, tmp
);
734 /* Set ring address */
735 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev
->cp
.gpu_addr
);
736 WREG32(RADEON_CP_RB_BASE
, rdev
->cp
.gpu_addr
);
737 /* Force read & write ptr to 0 */
738 WREG32(RADEON_CP_RB_CNTL
, tmp
| RADEON_RB_RPTR_WR_ENA
);
739 WREG32(RADEON_CP_RB_RPTR_WR
, 0);
740 WREG32(RADEON_CP_RB_WPTR
, 0);
741 WREG32(RADEON_CP_RB_CNTL
, tmp
);
743 rdev
->cp
.rptr
= RREG32(RADEON_CP_RB_RPTR
);
744 rdev
->cp
.wptr
= RREG32(RADEON_CP_RB_WPTR
);
745 /* Set cp mode to bus mastering & enable cp*/
746 WREG32(RADEON_CP_CSQ_MODE
,
747 REG_SET(RADEON_INDIRECT2_START
, indirect2_start
) |
748 REG_SET(RADEON_INDIRECT1_START
, indirect1_start
));
750 WREG32(0x744, 0x00004D4D);
751 WREG32(RADEON_CP_CSQ_CNTL
, RADEON_CSQ_PRIBM_INDBM
);
752 radeon_ring_start(rdev
);
753 r
= radeon_ring_test(rdev
);
755 DRM_ERROR("radeon: cp isn't working (%d).\n", r
);
758 rdev
->cp
.ready
= true;
762 void r100_cp_fini(struct radeon_device
*rdev
)
764 if (r100_cp_wait_for_idle(rdev
)) {
765 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
768 r100_cp_disable(rdev
);
769 radeon_ring_fini(rdev
);
770 DRM_INFO("radeon: cp finalized\n");
773 void r100_cp_disable(struct radeon_device
*rdev
)
776 rdev
->cp
.ready
= false;
777 WREG32(RADEON_CP_CSQ_MODE
, 0);
778 WREG32(RADEON_CP_CSQ_CNTL
, 0);
779 if (r100_gui_wait_for_idle(rdev
)) {
780 printk(KERN_WARNING
"Failed to wait GUI idle while "
781 "programming pipes. Bad things might happen.\n");
785 int r100_cp_reset(struct radeon_device
*rdev
)
791 reinit_cp
= rdev
->cp
.ready
;
792 rdev
->cp
.ready
= false;
793 WREG32(RADEON_CP_CSQ_MODE
, 0);
794 WREG32(RADEON_CP_CSQ_CNTL
, 0);
795 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_CP
);
796 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
798 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
799 /* Wait to prevent race in RBBM_STATUS */
801 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
802 tmp
= RREG32(RADEON_RBBM_STATUS
);
803 if (!(tmp
& (1 << 16))) {
804 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
807 return r100_cp_init(rdev
, rdev
->cp
.ring_size
);
813 tmp
= RREG32(RADEON_RBBM_STATUS
);
814 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp
);
818 void r100_cp_commit(struct radeon_device
*rdev
)
820 WREG32(RADEON_CP_RB_WPTR
, rdev
->cp
.wptr
);
821 (void)RREG32(RADEON_CP_RB_WPTR
);
828 int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
829 struct radeon_cs_packet
*pkt
,
830 const unsigned *auth
, unsigned n
,
831 radeon_packet0_check_t check
)
840 /* Check that register fall into register range
841 * determined by the number of entry (n) in the
842 * safe register bitmap.
844 if (pkt
->one_reg_wr
) {
845 if ((reg
>> 7) > n
) {
849 if (((reg
+ (pkt
->count
<< 2)) >> 7) > n
) {
853 for (i
= 0; i
<= pkt
->count
; i
++, idx
++) {
855 m
= 1 << ((reg
>> 2) & 31);
857 r
= check(p
, pkt
, idx
, reg
);
862 if (pkt
->one_reg_wr
) {
863 if (!(auth
[j
] & m
)) {
873 void r100_cs_dump_packet(struct radeon_cs_parser
*p
,
874 struct radeon_cs_packet
*pkt
)
876 volatile uint32_t *ib
;
882 for (i
= 0; i
<= (pkt
->count
+ 1); i
++, idx
++) {
883 DRM_INFO("ib[%d]=0x%08X\n", idx
, ib
[idx
]);
888 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
889 * @parser: parser structure holding parsing context.
890 * @pkt: where to store packet informations
892 * Assume that chunk_ib_index is properly set. Will return -EINVAL
893 * if packet is bigger than remaining ib size. or if packets is unknown.
895 int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
896 struct radeon_cs_packet
*pkt
,
899 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
902 if (idx
>= ib_chunk
->length_dw
) {
903 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
904 idx
, ib_chunk
->length_dw
);
907 header
= radeon_get_ib_value(p
, idx
);
909 pkt
->type
= CP_PACKET_GET_TYPE(header
);
910 pkt
->count
= CP_PACKET_GET_COUNT(header
);
913 pkt
->reg
= CP_PACKET0_GET_REG(header
);
914 pkt
->one_reg_wr
= CP_PACKET0_GET_ONE_REG_WR(header
);
917 pkt
->opcode
= CP_PACKET3_GET_OPCODE(header
);
923 DRM_ERROR("Unknown packet type %d at %d !\n", pkt
->type
, idx
);
926 if ((pkt
->count
+ 1 + pkt
->idx
) >= ib_chunk
->length_dw
) {
927 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
928 pkt
->idx
, pkt
->type
, pkt
->count
, ib_chunk
->length_dw
);
935 * r100_cs_packet_next_vline() - parse userspace VLINE packet
936 * @parser: parser structure holding parsing context.
938 * Userspace sends a special sequence for VLINE waits.
939 * PACKET0 - VLINE_START_END + value
940 * PACKET0 - WAIT_UNTIL +_value
941 * RELOC (P3) - crtc_id in reloc.
943 * This function parses this and relocates the VLINE START END
944 * and WAIT UNTIL packets to the correct crtc.
945 * It also detects a switched off crtc and nulls out the
948 int r100_cs_packet_parse_vline(struct radeon_cs_parser
*p
)
950 struct drm_mode_object
*obj
;
951 struct drm_crtc
*crtc
;
952 struct radeon_crtc
*radeon_crtc
;
953 struct radeon_cs_packet p3reloc
, waitreloc
;
956 uint32_t header
, h_idx
, reg
;
957 volatile uint32_t *ib
;
961 /* parse the wait until */
962 r
= r100_cs_packet_parse(p
, &waitreloc
, p
->idx
);
966 /* check its a wait until and only 1 count */
967 if (waitreloc
.reg
!= RADEON_WAIT_UNTIL
||
968 waitreloc
.count
!= 0) {
969 DRM_ERROR("vline wait had illegal wait until segment\n");
974 if (radeon_get_ib_value(p
, waitreloc
.idx
+ 1) != RADEON_WAIT_CRTC_VLINE
) {
975 DRM_ERROR("vline wait had illegal wait until\n");
980 /* jump over the NOP */
981 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
+ waitreloc
.count
+ 2);
986 p
->idx
+= waitreloc
.count
+ 2;
987 p
->idx
+= p3reloc
.count
+ 2;
989 header
= radeon_get_ib_value(p
, h_idx
);
990 crtc_id
= radeon_get_ib_value(p
, h_idx
+ 5);
991 reg
= CP_PACKET0_GET_REG(header
);
992 mutex_lock(&p
->rdev
->ddev
->mode_config
.mutex
);
993 obj
= drm_mode_object_find(p
->rdev
->ddev
, crtc_id
, DRM_MODE_OBJECT_CRTC
);
995 DRM_ERROR("cannot find crtc %d\n", crtc_id
);
999 crtc
= obj_to_crtc(obj
);
1000 radeon_crtc
= to_radeon_crtc(crtc
);
1001 crtc_id
= radeon_crtc
->crtc_id
;
1003 if (!crtc
->enabled
) {
1004 /* if the CRTC isn't enabled - we need to nop out the wait until */
1005 ib
[h_idx
+ 2] = PACKET2(0);
1006 ib
[h_idx
+ 3] = PACKET2(0);
1007 } else if (crtc_id
== 1) {
1009 case AVIVO_D1MODE_VLINE_START_END
:
1010 header
&= ~R300_CP_PACKET0_REG_MASK
;
1011 header
|= AVIVO_D2MODE_VLINE_START_END
>> 2;
1013 case RADEON_CRTC_GUI_TRIG_VLINE
:
1014 header
&= ~R300_CP_PACKET0_REG_MASK
;
1015 header
|= RADEON_CRTC2_GUI_TRIG_VLINE
>> 2;
1018 DRM_ERROR("unknown crtc reloc\n");
1023 ib
[h_idx
+ 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1
;
1026 mutex_unlock(&p
->rdev
->ddev
->mode_config
.mutex
);
1031 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1032 * @parser: parser structure holding parsing context.
1033 * @data: pointer to relocation data
1034 * @offset_start: starting offset
1035 * @offset_mask: offset mask (to align start offset on)
1036 * @reloc: reloc informations
1038 * Check next packet is relocation packet3, do bo validation and compute
1039 * GPU offset using the provided start.
1041 int r100_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
1042 struct radeon_cs_reloc
**cs_reloc
)
1044 struct radeon_cs_chunk
*relocs_chunk
;
1045 struct radeon_cs_packet p3reloc
;
1049 if (p
->chunk_relocs_idx
== -1) {
1050 DRM_ERROR("No relocation chunk !\n");
1054 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
1055 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
);
1059 p
->idx
+= p3reloc
.count
+ 2;
1060 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
1061 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1063 r100_cs_dump_packet(p
, &p3reloc
);
1066 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
1067 if (idx
>= relocs_chunk
->length_dw
) {
1068 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1069 idx
, relocs_chunk
->length_dw
);
1070 r100_cs_dump_packet(p
, &p3reloc
);
1073 /* FIXME: we assume reloc size is 4 dwords */
1074 *cs_reloc
= p
->relocs_ptr
[(idx
/ 4)];
1078 static int r100_get_vtx_size(uint32_t vtx_fmt
)
1082 /* ordered according to bits in spec */
1083 if (vtx_fmt
& RADEON_SE_VTX_FMT_W0
)
1085 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPCOLOR
)
1087 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPALPHA
)
1089 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKCOLOR
)
1091 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPSPEC
)
1093 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPFOG
)
1095 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKSPEC
)
1097 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST0
)
1099 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST1
)
1101 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q1
)
1103 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST2
)
1105 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q2
)
1107 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST3
)
1109 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q3
)
1111 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q0
)
1114 if (vtx_fmt
& (0x7 << 15))
1115 vtx_size
+= (vtx_fmt
>> 15) & 0x7;
1116 if (vtx_fmt
& RADEON_SE_VTX_FMT_N0
)
1118 if (vtx_fmt
& RADEON_SE_VTX_FMT_XY1
)
1120 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z1
)
1122 if (vtx_fmt
& RADEON_SE_VTX_FMT_W1
)
1124 if (vtx_fmt
& RADEON_SE_VTX_FMT_N1
)
1126 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z
)
1131 static int r100_packet0_check(struct radeon_cs_parser
*p
,
1132 struct radeon_cs_packet
*pkt
,
1133 unsigned idx
, unsigned reg
)
1135 struct radeon_cs_reloc
*reloc
;
1136 struct r100_cs_track
*track
;
1137 volatile uint32_t *ib
;
1145 track
= (struct r100_cs_track
*)p
->track
;
1147 idx_value
= radeon_get_ib_value(p
, idx
);
1150 case RADEON_CRTC_GUI_TRIG_VLINE
:
1151 r
= r100_cs_packet_parse_vline(p
);
1153 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1155 r100_cs_dump_packet(p
, pkt
);
1159 /* FIXME: only allow PACKET3 blit? easier to check for out of
1161 case RADEON_DST_PITCH_OFFSET
:
1162 case RADEON_SRC_PITCH_OFFSET
:
1163 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
1167 case RADEON_RB3D_DEPTHOFFSET
:
1168 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1170 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1172 r100_cs_dump_packet(p
, pkt
);
1175 track
->zb
.robj
= reloc
->robj
;
1176 track
->zb
.offset
= idx_value
;
1177 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1179 case RADEON_RB3D_COLOROFFSET
:
1180 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1182 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1184 r100_cs_dump_packet(p
, pkt
);
1187 track
->cb
[0].robj
= reloc
->robj
;
1188 track
->cb
[0].offset
= idx_value
;
1189 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1191 case RADEON_PP_TXOFFSET_0
:
1192 case RADEON_PP_TXOFFSET_1
:
1193 case RADEON_PP_TXOFFSET_2
:
1194 i
= (reg
- RADEON_PP_TXOFFSET_0
) / 24;
1195 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1197 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1199 r100_cs_dump_packet(p
, pkt
);
1202 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1203 track
->textures
[i
].robj
= reloc
->robj
;
1205 case RADEON_PP_CUBIC_OFFSET_T0_0
:
1206 case RADEON_PP_CUBIC_OFFSET_T0_1
:
1207 case RADEON_PP_CUBIC_OFFSET_T0_2
:
1208 case RADEON_PP_CUBIC_OFFSET_T0_3
:
1209 case RADEON_PP_CUBIC_OFFSET_T0_4
:
1210 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T0_0
) / 4;
1211 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1213 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1215 r100_cs_dump_packet(p
, pkt
);
1218 track
->textures
[0].cube_info
[i
].offset
= idx_value
;
1219 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1220 track
->textures
[0].cube_info
[i
].robj
= reloc
->robj
;
1222 case RADEON_PP_CUBIC_OFFSET_T1_0
:
1223 case RADEON_PP_CUBIC_OFFSET_T1_1
:
1224 case RADEON_PP_CUBIC_OFFSET_T1_2
:
1225 case RADEON_PP_CUBIC_OFFSET_T1_3
:
1226 case RADEON_PP_CUBIC_OFFSET_T1_4
:
1227 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T1_0
) / 4;
1228 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1230 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1232 r100_cs_dump_packet(p
, pkt
);
1235 track
->textures
[1].cube_info
[i
].offset
= idx_value
;
1236 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1237 track
->textures
[1].cube_info
[i
].robj
= reloc
->robj
;
1239 case RADEON_PP_CUBIC_OFFSET_T2_0
:
1240 case RADEON_PP_CUBIC_OFFSET_T2_1
:
1241 case RADEON_PP_CUBIC_OFFSET_T2_2
:
1242 case RADEON_PP_CUBIC_OFFSET_T2_3
:
1243 case RADEON_PP_CUBIC_OFFSET_T2_4
:
1244 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T2_0
) / 4;
1245 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1247 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1249 r100_cs_dump_packet(p
, pkt
);
1252 track
->textures
[2].cube_info
[i
].offset
= idx_value
;
1253 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1254 track
->textures
[2].cube_info
[i
].robj
= reloc
->robj
;
1256 case RADEON_RE_WIDTH_HEIGHT
:
1257 track
->maxy
= ((idx_value
>> 16) & 0x7FF);
1259 case RADEON_RB3D_COLORPITCH
:
1260 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1262 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1264 r100_cs_dump_packet(p
, pkt
);
1268 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
1269 tile_flags
|= RADEON_COLOR_TILE_ENABLE
;
1270 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
1271 tile_flags
|= RADEON_COLOR_MICROTILE_ENABLE
;
1273 tmp
= idx_value
& ~(0x7 << 16);
1277 track
->cb
[0].pitch
= idx_value
& RADEON_COLORPITCH_MASK
;
1279 case RADEON_RB3D_DEPTHPITCH
:
1280 track
->zb
.pitch
= idx_value
& RADEON_DEPTHPITCH_MASK
;
1282 case RADEON_RB3D_CNTL
:
1283 switch ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f) {
1289 track
->cb
[0].cpp
= 1;
1294 track
->cb
[0].cpp
= 2;
1297 track
->cb
[0].cpp
= 4;
1300 DRM_ERROR("Invalid color buffer format (%d) !\n",
1301 ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f));
1304 track
->z_enabled
= !!(idx_value
& RADEON_Z_ENABLE
);
1306 case RADEON_RB3D_ZSTENCILCNTL
:
1307 switch (idx_value
& 0xf) {
1323 case RADEON_RB3D_ZPASS_ADDR
:
1324 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1326 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1328 r100_cs_dump_packet(p
, pkt
);
1331 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1333 case RADEON_PP_CNTL
:
1335 uint32_t temp
= idx_value
>> 4;
1336 for (i
= 0; i
< track
->num_texture
; i
++)
1337 track
->textures
[i
].enabled
= !!(temp
& (1 << i
));
1340 case RADEON_SE_VF_CNTL
:
1341 track
->vap_vf_cntl
= idx_value
;
1343 case RADEON_SE_VTX_FMT
:
1344 track
->vtx_size
= r100_get_vtx_size(idx_value
);
1346 case RADEON_PP_TEX_SIZE_0
:
1347 case RADEON_PP_TEX_SIZE_1
:
1348 case RADEON_PP_TEX_SIZE_2
:
1349 i
= (reg
- RADEON_PP_TEX_SIZE_0
) / 8;
1350 track
->textures
[i
].width
= (idx_value
& RADEON_TEX_USIZE_MASK
) + 1;
1351 track
->textures
[i
].height
= ((idx_value
& RADEON_TEX_VSIZE_MASK
) >> RADEON_TEX_VSIZE_SHIFT
) + 1;
1353 case RADEON_PP_TEX_PITCH_0
:
1354 case RADEON_PP_TEX_PITCH_1
:
1355 case RADEON_PP_TEX_PITCH_2
:
1356 i
= (reg
- RADEON_PP_TEX_PITCH_0
) / 8;
1357 track
->textures
[i
].pitch
= idx_value
+ 32;
1359 case RADEON_PP_TXFILTER_0
:
1360 case RADEON_PP_TXFILTER_1
:
1361 case RADEON_PP_TXFILTER_2
:
1362 i
= (reg
- RADEON_PP_TXFILTER_0
) / 24;
1363 track
->textures
[i
].num_levels
= ((idx_value
& RADEON_MAX_MIP_LEVEL_MASK
)
1364 >> RADEON_MAX_MIP_LEVEL_SHIFT
);
1365 tmp
= (idx_value
>> 23) & 0x7;
1366 if (tmp
== 2 || tmp
== 6)
1367 track
->textures
[i
].roundup_w
= false;
1368 tmp
= (idx_value
>> 27) & 0x7;
1369 if (tmp
== 2 || tmp
== 6)
1370 track
->textures
[i
].roundup_h
= false;
1372 case RADEON_PP_TXFORMAT_0
:
1373 case RADEON_PP_TXFORMAT_1
:
1374 case RADEON_PP_TXFORMAT_2
:
1375 i
= (reg
- RADEON_PP_TXFORMAT_0
) / 24;
1376 if (idx_value
& RADEON_TXFORMAT_NON_POWER2
) {
1377 track
->textures
[i
].use_pitch
= 1;
1379 track
->textures
[i
].use_pitch
= 0;
1380 track
->textures
[i
].width
= 1 << ((idx_value
>> RADEON_TXFORMAT_WIDTH_SHIFT
) & RADEON_TXFORMAT_WIDTH_MASK
);
1381 track
->textures
[i
].height
= 1 << ((idx_value
>> RADEON_TXFORMAT_HEIGHT_SHIFT
) & RADEON_TXFORMAT_HEIGHT_MASK
);
1383 if (idx_value
& RADEON_TXFORMAT_CUBIC_MAP_ENABLE
)
1384 track
->textures
[i
].tex_coord_type
= 2;
1385 switch ((idx_value
& RADEON_TXFORMAT_FORMAT_MASK
)) {
1386 case RADEON_TXFORMAT_I8
:
1387 case RADEON_TXFORMAT_RGB332
:
1388 case RADEON_TXFORMAT_Y8
:
1389 track
->textures
[i
].cpp
= 1;
1391 case RADEON_TXFORMAT_AI88
:
1392 case RADEON_TXFORMAT_ARGB1555
:
1393 case RADEON_TXFORMAT_RGB565
:
1394 case RADEON_TXFORMAT_ARGB4444
:
1395 case RADEON_TXFORMAT_VYUY422
:
1396 case RADEON_TXFORMAT_YVYU422
:
1397 case RADEON_TXFORMAT_SHADOW16
:
1398 case RADEON_TXFORMAT_LDUDV655
:
1399 case RADEON_TXFORMAT_DUDV88
:
1400 track
->textures
[i
].cpp
= 2;
1402 case RADEON_TXFORMAT_ARGB8888
:
1403 case RADEON_TXFORMAT_RGBA8888
:
1404 case RADEON_TXFORMAT_SHADOW32
:
1405 case RADEON_TXFORMAT_LDUDUV8888
:
1406 track
->textures
[i
].cpp
= 4;
1408 case RADEON_TXFORMAT_DXT1
:
1409 track
->textures
[i
].cpp
= 1;
1410 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT1
;
1412 case RADEON_TXFORMAT_DXT23
:
1413 case RADEON_TXFORMAT_DXT45
:
1414 track
->textures
[i
].cpp
= 1;
1415 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT35
;
1418 track
->textures
[i
].cube_info
[4].width
= 1 << ((idx_value
>> 16) & 0xf);
1419 track
->textures
[i
].cube_info
[4].height
= 1 << ((idx_value
>> 20) & 0xf);
1421 case RADEON_PP_CUBIC_FACES_0
:
1422 case RADEON_PP_CUBIC_FACES_1
:
1423 case RADEON_PP_CUBIC_FACES_2
:
1425 i
= (reg
- RADEON_PP_CUBIC_FACES_0
) / 4;
1426 for (face
= 0; face
< 4; face
++) {
1427 track
->textures
[i
].cube_info
[face
].width
= 1 << ((tmp
>> (face
* 8)) & 0xf);
1428 track
->textures
[i
].cube_info
[face
].height
= 1 << ((tmp
>> ((face
* 8) + 4)) & 0xf);
1432 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
1439 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
1440 struct radeon_cs_packet
*pkt
,
1441 struct radeon_bo
*robj
)
1446 value
= radeon_get_ib_value(p
, idx
+ 2);
1447 if ((value
+ 1) > radeon_bo_size(robj
)) {
1448 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1449 "(need %u have %lu) !\n",
1451 radeon_bo_size(robj
));
1457 static int r100_packet3_check(struct radeon_cs_parser
*p
,
1458 struct radeon_cs_packet
*pkt
)
1460 struct radeon_cs_reloc
*reloc
;
1461 struct r100_cs_track
*track
;
1463 volatile uint32_t *ib
;
1468 track
= (struct r100_cs_track
*)p
->track
;
1469 switch (pkt
->opcode
) {
1470 case PACKET3_3D_LOAD_VBPNTR
:
1471 r
= r100_packet3_load_vbpntr(p
, pkt
, idx
);
1475 case PACKET3_INDX_BUFFER
:
1476 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1478 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1479 r100_cs_dump_packet(p
, pkt
);
1482 ib
[idx
+1] = radeon_get_ib_value(p
, idx
+1) + ((u32
)reloc
->lobj
.gpu_offset
);
1483 r
= r100_cs_track_check_pkt3_indx_buffer(p
, pkt
, reloc
->robj
);
1489 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1490 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1492 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1493 r100_cs_dump_packet(p
, pkt
);
1496 ib
[idx
] = radeon_get_ib_value(p
, idx
) + ((u32
)reloc
->lobj
.gpu_offset
);
1497 track
->num_arrays
= 1;
1498 track
->vtx_size
= r100_get_vtx_size(radeon_get_ib_value(p
, idx
+ 2));
1500 track
->arrays
[0].robj
= reloc
->robj
;
1501 track
->arrays
[0].esize
= track
->vtx_size
;
1503 track
->max_indx
= radeon_get_ib_value(p
, idx
+1);
1505 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+3);
1506 track
->immd_dwords
= pkt
->count
- 1;
1507 r
= r100_cs_track_check(p
->rdev
, track
);
1511 case PACKET3_3D_DRAW_IMMD
:
1512 if (((radeon_get_ib_value(p
, idx
+ 1) >> 4) & 0x3) != 3) {
1513 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1516 track
->vtx_size
= r100_get_vtx_size(radeon_get_ib_value(p
, idx
+ 0));
1517 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1518 track
->immd_dwords
= pkt
->count
- 1;
1519 r
= r100_cs_track_check(p
->rdev
, track
);
1523 /* triggers drawing using in-packet vertex data */
1524 case PACKET3_3D_DRAW_IMMD_2
:
1525 if (((radeon_get_ib_value(p
, idx
) >> 4) & 0x3) != 3) {
1526 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1529 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1530 track
->immd_dwords
= pkt
->count
;
1531 r
= r100_cs_track_check(p
->rdev
, track
);
1535 /* triggers drawing using in-packet vertex data */
1536 case PACKET3_3D_DRAW_VBUF_2
:
1537 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1538 r
= r100_cs_track_check(p
->rdev
, track
);
1542 /* triggers drawing of vertex buffers setup elsewhere */
1543 case PACKET3_3D_DRAW_INDX_2
:
1544 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1545 r
= r100_cs_track_check(p
->rdev
, track
);
1549 /* triggers drawing using indices to vertex buffer */
1550 case PACKET3_3D_DRAW_VBUF
:
1551 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1552 r
= r100_cs_track_check(p
->rdev
, track
);
1556 /* triggers drawing of vertex buffers setup elsewhere */
1557 case PACKET3_3D_DRAW_INDX
:
1558 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1559 r
= r100_cs_track_check(p
->rdev
, track
);
1563 /* triggers drawing using indices to vertex buffer */
1567 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1573 int r100_cs_parse(struct radeon_cs_parser
*p
)
1575 struct radeon_cs_packet pkt
;
1576 struct r100_cs_track
*track
;
1579 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1580 r100_cs_track_clear(p
->rdev
, track
);
1583 r
= r100_cs_packet_parse(p
, &pkt
, p
->idx
);
1587 p
->idx
+= pkt
.count
+ 2;
1590 if (p
->rdev
->family
>= CHIP_R200
)
1591 r
= r100_cs_parse_packet0(p
, &pkt
,
1592 p
->rdev
->config
.r100
.reg_safe_bm
,
1593 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1594 &r200_packet0_check
);
1596 r
= r100_cs_parse_packet0(p
, &pkt
,
1597 p
->rdev
->config
.r100
.reg_safe_bm
,
1598 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1599 &r100_packet0_check
);
1604 r
= r100_packet3_check(p
, &pkt
);
1607 DRM_ERROR("Unknown packet type %d !\n",
1614 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1620 * Global GPU functions
1622 void r100_errata(struct radeon_device
*rdev
)
1624 rdev
->pll_errata
= 0;
1626 if (rdev
->family
== CHIP_RV200
|| rdev
->family
== CHIP_RS200
) {
1627 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DUMMYREADS
;
1630 if (rdev
->family
== CHIP_RV100
||
1631 rdev
->family
== CHIP_RS100
||
1632 rdev
->family
== CHIP_RS200
) {
1633 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DELAY
;
1637 /* Wait for vertical sync on primary CRTC */
1638 void r100_gpu_wait_for_vsync(struct radeon_device
*rdev
)
1640 uint32_t crtc_gen_cntl
, tmp
;
1643 crtc_gen_cntl
= RREG32(RADEON_CRTC_GEN_CNTL
);
1644 if ((crtc_gen_cntl
& RADEON_CRTC_DISP_REQ_EN_B
) ||
1645 !(crtc_gen_cntl
& RADEON_CRTC_EN
)) {
1648 /* Clear the CRTC_VBLANK_SAVE bit */
1649 WREG32(RADEON_CRTC_STATUS
, RADEON_CRTC_VBLANK_SAVE_CLEAR
);
1650 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1651 tmp
= RREG32(RADEON_CRTC_STATUS
);
1652 if (tmp
& RADEON_CRTC_VBLANK_SAVE
) {
1659 /* Wait for vertical sync on secondary CRTC */
1660 void r100_gpu_wait_for_vsync2(struct radeon_device
*rdev
)
1662 uint32_t crtc2_gen_cntl
, tmp
;
1665 crtc2_gen_cntl
= RREG32(RADEON_CRTC2_GEN_CNTL
);
1666 if ((crtc2_gen_cntl
& RADEON_CRTC2_DISP_REQ_EN_B
) ||
1667 !(crtc2_gen_cntl
& RADEON_CRTC2_EN
))
1670 /* Clear the CRTC_VBLANK_SAVE bit */
1671 WREG32(RADEON_CRTC2_STATUS
, RADEON_CRTC2_VBLANK_SAVE_CLEAR
);
1672 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1673 tmp
= RREG32(RADEON_CRTC2_STATUS
);
1674 if (tmp
& RADEON_CRTC2_VBLANK_SAVE
) {
1681 int r100_rbbm_fifo_wait_for_entry(struct radeon_device
*rdev
, unsigned n
)
1686 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1687 tmp
= RREG32(RADEON_RBBM_STATUS
) & RADEON_RBBM_FIFOCNT_MASK
;
1696 int r100_gui_wait_for_idle(struct radeon_device
*rdev
)
1701 if (r100_rbbm_fifo_wait_for_entry(rdev
, 64)) {
1702 printk(KERN_WARNING
"radeon: wait for empty RBBM fifo failed !"
1703 " Bad things might happen.\n");
1705 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1706 tmp
= RREG32(RADEON_RBBM_STATUS
);
1707 if (!(tmp
& RADEON_RBBM_ACTIVE
)) {
1715 int r100_mc_wait_for_idle(struct radeon_device
*rdev
)
1720 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1721 /* read MC_STATUS */
1722 tmp
= RREG32(RADEON_MC_STATUS
);
1723 if (tmp
& RADEON_MC_IDLE
) {
1731 void r100_gpu_init(struct radeon_device
*rdev
)
1733 /* TODO: anythings to do here ? pipes ? */
1734 r100_hdp_reset(rdev
);
1737 void r100_hdp_reset(struct radeon_device
*rdev
)
1741 tmp
= RREG32(RADEON_HOST_PATH_CNTL
) & RADEON_HDP_APER_CNTL
;
1743 WREG32(RADEON_HOST_PATH_CNTL
, tmp
| RADEON_HDP_SOFT_RESET
| RADEON_HDP_READ_BUFFER_INVALIDATE
);
1744 (void)RREG32(RADEON_HOST_PATH_CNTL
);
1746 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
1747 WREG32(RADEON_HOST_PATH_CNTL
, tmp
);
1748 (void)RREG32(RADEON_HOST_PATH_CNTL
);
1751 int r100_rb2d_reset(struct radeon_device
*rdev
)
1756 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_E2
);
1757 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
1759 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
1760 /* Wait to prevent race in RBBM_STATUS */
1762 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1763 tmp
= RREG32(RADEON_RBBM_STATUS
);
1764 if (!(tmp
& (1 << 26))) {
1765 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1771 tmp
= RREG32(RADEON_RBBM_STATUS
);
1772 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp
);
1776 int r100_gpu_reset(struct radeon_device
*rdev
)
1780 /* reset order likely matter */
1781 status
= RREG32(RADEON_RBBM_STATUS
);
1783 r100_hdp_reset(rdev
);
1785 if (status
& ((1 << 17) | (1 << 18) | (1 << 27))) {
1786 r100_rb2d_reset(rdev
);
1788 /* TODO: reset 3D engine */
1790 status
= RREG32(RADEON_RBBM_STATUS
);
1791 if (status
& (1 << 16)) {
1792 r100_cp_reset(rdev
);
1794 /* Check if GPU is idle */
1795 status
= RREG32(RADEON_RBBM_STATUS
);
1796 if (status
& RADEON_RBBM_ACTIVE
) {
1797 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status
);
1800 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status
);
1804 void r100_set_common_regs(struct radeon_device
*rdev
)
1806 struct drm_device
*dev
= rdev
->ddev
;
1807 bool force_dac2
= false;
1809 /* set these so they don't interfere with anything */
1810 WREG32(RADEON_OV0_SCALE_CNTL
, 0);
1811 WREG32(RADEON_SUBPIC_CNTL
, 0);
1812 WREG32(RADEON_VIPH_CONTROL
, 0);
1813 WREG32(RADEON_I2C_CNTL_1
, 0);
1814 WREG32(RADEON_DVI_I2C_CNTL_1
, 0);
1815 WREG32(RADEON_CAP0_TRIG_CNTL
, 0);
1816 WREG32(RADEON_CAP1_TRIG_CNTL
, 0);
1818 /* always set up dac2 on rn50 and some rv100 as lots
1819 * of servers seem to wire it up to a VGA port but
1820 * don't report it in the bios connector
1823 switch (dev
->pdev
->device
) {
1832 /* DELL triple head servers */
1833 if ((dev
->pdev
->subsystem_vendor
== 0x1028 /* DELL */) &&
1834 ((dev
->pdev
->subsystem_device
== 0x016c) ||
1835 (dev
->pdev
->subsystem_device
== 0x016d) ||
1836 (dev
->pdev
->subsystem_device
== 0x016e) ||
1837 (dev
->pdev
->subsystem_device
== 0x016f) ||
1838 (dev
->pdev
->subsystem_device
== 0x0170) ||
1839 (dev
->pdev
->subsystem_device
== 0x017d) ||
1840 (dev
->pdev
->subsystem_device
== 0x017e) ||
1841 (dev
->pdev
->subsystem_device
== 0x0183) ||
1842 (dev
->pdev
->subsystem_device
== 0x018a) ||
1843 (dev
->pdev
->subsystem_device
== 0x019a)))
1849 u32 disp_hw_debug
= RREG32(RADEON_DISP_HW_DEBUG
);
1850 u32 tv_dac_cntl
= RREG32(RADEON_TV_DAC_CNTL
);
1851 u32 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
1853 /* For CRT on DAC2, don't turn it on if BIOS didn't
1854 enable it, even it's detected.
1857 /* force it to crtc0 */
1858 dac2_cntl
&= ~RADEON_DAC2_DAC_CLK_SEL
;
1859 dac2_cntl
|= RADEON_DAC2_DAC2_CLK_SEL
;
1860 disp_hw_debug
|= RADEON_CRT2_DISP1_SEL
;
1862 /* set up the TV DAC */
1863 tv_dac_cntl
&= ~(RADEON_TV_DAC_PEDESTAL
|
1864 RADEON_TV_DAC_STD_MASK
|
1865 RADEON_TV_DAC_RDACPD
|
1866 RADEON_TV_DAC_GDACPD
|
1867 RADEON_TV_DAC_BDACPD
|
1868 RADEON_TV_DAC_BGADJ_MASK
|
1869 RADEON_TV_DAC_DACADJ_MASK
);
1870 tv_dac_cntl
|= (RADEON_TV_DAC_NBLANK
|
1871 RADEON_TV_DAC_NHOLD
|
1872 RADEON_TV_DAC_STD_PS2
|
1875 WREG32(RADEON_TV_DAC_CNTL
, tv_dac_cntl
);
1876 WREG32(RADEON_DISP_HW_DEBUG
, disp_hw_debug
);
1877 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
1884 static void r100_vram_get_type(struct radeon_device
*rdev
)
1888 rdev
->mc
.vram_is_ddr
= false;
1889 if (rdev
->flags
& RADEON_IS_IGP
)
1890 rdev
->mc
.vram_is_ddr
= true;
1891 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG
) & RADEON_MEM_CFG_TYPE_DDR
)
1892 rdev
->mc
.vram_is_ddr
= true;
1893 if ((rdev
->family
== CHIP_RV100
) ||
1894 (rdev
->family
== CHIP_RS100
) ||
1895 (rdev
->family
== CHIP_RS200
)) {
1896 tmp
= RREG32(RADEON_MEM_CNTL
);
1897 if (tmp
& RV100_HALF_MODE
) {
1898 rdev
->mc
.vram_width
= 32;
1900 rdev
->mc
.vram_width
= 64;
1902 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1903 rdev
->mc
.vram_width
/= 4;
1904 rdev
->mc
.vram_is_ddr
= true;
1906 } else if (rdev
->family
<= CHIP_RV280
) {
1907 tmp
= RREG32(RADEON_MEM_CNTL
);
1908 if (tmp
& RADEON_MEM_NUM_CHANNELS_MASK
) {
1909 rdev
->mc
.vram_width
= 128;
1911 rdev
->mc
.vram_width
= 64;
1915 rdev
->mc
.vram_width
= 128;
1919 static u32
r100_get_accessible_vram(struct radeon_device
*rdev
)
1924 aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
1926 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1927 * that is has the 2nd generation multifunction PCI interface
1929 if (rdev
->family
== CHIP_RV280
||
1930 rdev
->family
>= CHIP_RV350
) {
1931 WREG32_P(RADEON_HOST_PATH_CNTL
, RADEON_HDP_APER_CNTL
,
1932 ~RADEON_HDP_APER_CNTL
);
1933 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1934 return aper_size
* 2;
1937 /* Older cards have all sorts of funny issues to deal with. First
1938 * check if it's a multifunction card by reading the PCI config
1939 * header type... Limit those to one aperture size
1941 pci_read_config_byte(rdev
->pdev
, 0xe, &byte
);
1943 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1944 DRM_INFO("Limiting VRAM to one aperture\n");
1948 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1949 * have set it up. We don't write this as it's broken on some ASICs but
1950 * we expect the BIOS to have done the right thing (might be too optimistic...)
1952 if (RREG32(RADEON_HOST_PATH_CNTL
) & RADEON_HDP_APER_CNTL
)
1953 return aper_size
* 2;
1957 void r100_vram_init_sizes(struct radeon_device
*rdev
)
1959 u64 config_aper_size
;
1962 config_aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
1964 if (rdev
->flags
& RADEON_IS_IGP
) {
1966 /* read NB_TOM to get the amount of ram stolen for the GPU */
1967 tom
= RREG32(RADEON_NB_TOM
);
1968 rdev
->mc
.real_vram_size
= (((tom
>> 16) - (tom
& 0xffff) + 1) << 16);
1969 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1970 rdev
->mc
.vram_location
= (tom
& 0xffff) << 16;
1971 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
1972 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
1974 rdev
->mc
.real_vram_size
= RREG32(RADEON_CONFIG_MEMSIZE
);
1975 /* Some production boards of m6 will report 0
1978 if (rdev
->mc
.real_vram_size
== 0) {
1979 rdev
->mc
.real_vram_size
= 8192 * 1024;
1980 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
1982 /* let driver place VRAM */
1983 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
1984 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1985 * Novell bug 204882 + along with lots of ubuntu ones */
1986 if (config_aper_size
> rdev
->mc
.real_vram_size
)
1987 rdev
->mc
.mc_vram_size
= config_aper_size
;
1989 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
1992 /* work out accessible VRAM */
1993 accessible
= r100_get_accessible_vram(rdev
);
1995 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
1996 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
1998 if (accessible
> rdev
->mc
.aper_size
)
1999 accessible
= rdev
->mc
.aper_size
;
2001 if (rdev
->mc
.mc_vram_size
> rdev
->mc
.aper_size
)
2002 rdev
->mc
.mc_vram_size
= rdev
->mc
.aper_size
;
2004 if (rdev
->mc
.real_vram_size
> rdev
->mc
.aper_size
)
2005 rdev
->mc
.real_vram_size
= rdev
->mc
.aper_size
;
2008 void r100_vga_set_state(struct radeon_device
*rdev
, bool state
)
2012 temp
= RREG32(RADEON_CONFIG_CNTL
);
2013 if (state
== false) {
2019 WREG32(RADEON_CONFIG_CNTL
, temp
);
2022 void r100_vram_info(struct radeon_device
*rdev
)
2024 r100_vram_get_type(rdev
);
2026 r100_vram_init_sizes(rdev
);
2031 * Indirect registers accessor
2033 void r100_pll_errata_after_index(struct radeon_device
*rdev
)
2035 if (!(rdev
->pll_errata
& CHIP_ERRATA_PLL_DUMMYREADS
)) {
2038 (void)RREG32(RADEON_CLOCK_CNTL_DATA
);
2039 (void)RREG32(RADEON_CRTC_GEN_CNTL
);
2042 static void r100_pll_errata_after_data(struct radeon_device
*rdev
)
2044 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2045 * or the chip could hang on a subsequent access
2047 if (rdev
->pll_errata
& CHIP_ERRATA_PLL_DELAY
) {
2051 /* This function is required to workaround a hardware bug in some (all?)
2052 * revisions of the R300. This workaround should be called after every
2053 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2054 * may not be correct.
2056 if (rdev
->pll_errata
& CHIP_ERRATA_R300_CG
) {
2059 save
= RREG32(RADEON_CLOCK_CNTL_INDEX
);
2060 tmp
= save
& ~(0x3f | RADEON_PLL_WR_EN
);
2061 WREG32(RADEON_CLOCK_CNTL_INDEX
, tmp
);
2062 tmp
= RREG32(RADEON_CLOCK_CNTL_DATA
);
2063 WREG32(RADEON_CLOCK_CNTL_INDEX
, save
);
2067 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
)
2071 WREG8(RADEON_CLOCK_CNTL_INDEX
, reg
& 0x3f);
2072 r100_pll_errata_after_index(rdev
);
2073 data
= RREG32(RADEON_CLOCK_CNTL_DATA
);
2074 r100_pll_errata_after_data(rdev
);
2078 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
2080 WREG8(RADEON_CLOCK_CNTL_INDEX
, ((reg
& 0x3f) | RADEON_PLL_WR_EN
));
2081 r100_pll_errata_after_index(rdev
);
2082 WREG32(RADEON_CLOCK_CNTL_DATA
, v
);
2083 r100_pll_errata_after_data(rdev
);
2086 void r100_set_safe_registers(struct radeon_device
*rdev
)
2088 if (ASIC_IS_RN50(rdev
)) {
2089 rdev
->config
.r100
.reg_safe_bm
= rn50_reg_safe_bm
;
2090 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(rn50_reg_safe_bm
);
2091 } else if (rdev
->family
< CHIP_R200
) {
2092 rdev
->config
.r100
.reg_safe_bm
= r100_reg_safe_bm
;
2093 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(r100_reg_safe_bm
);
2095 r200_set_safe_registers(rdev
);
2102 #if defined(CONFIG_DEBUG_FS)
2103 static int r100_debugfs_rbbm_info(struct seq_file
*m
, void *data
)
2105 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2106 struct drm_device
*dev
= node
->minor
->dev
;
2107 struct radeon_device
*rdev
= dev
->dev_private
;
2108 uint32_t reg
, value
;
2111 seq_printf(m
, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS
));
2112 seq_printf(m
, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2113 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2114 for (i
= 0; i
< 64; i
++) {
2115 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
| 0x100);
2116 reg
= (RREG32(RADEON_RBBM_CMDFIFO_DATA
) - 1) >> 2;
2117 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
);
2118 value
= RREG32(RADEON_RBBM_CMDFIFO_DATA
);
2119 seq_printf(m
, "[0x%03X] 0x%04X=0x%08X\n", i
, reg
, value
);
2124 static int r100_debugfs_cp_ring_info(struct seq_file
*m
, void *data
)
2126 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2127 struct drm_device
*dev
= node
->minor
->dev
;
2128 struct radeon_device
*rdev
= dev
->dev_private
;
2130 unsigned count
, i
, j
;
2132 radeon_ring_free_size(rdev
);
2133 rdp
= RREG32(RADEON_CP_RB_RPTR
);
2134 wdp
= RREG32(RADEON_CP_RB_WPTR
);
2135 count
= (rdp
+ rdev
->cp
.ring_size
- wdp
) & rdev
->cp
.ptr_mask
;
2136 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2137 seq_printf(m
, "CP_RB_WPTR 0x%08x\n", wdp
);
2138 seq_printf(m
, "CP_RB_RPTR 0x%08x\n", rdp
);
2139 seq_printf(m
, "%u free dwords in ring\n", rdev
->cp
.ring_free_dw
);
2140 seq_printf(m
, "%u dwords in ring\n", count
);
2141 for (j
= 0; j
<= count
; j
++) {
2142 i
= (rdp
+ j
) & rdev
->cp
.ptr_mask
;
2143 seq_printf(m
, "r[%04d]=0x%08x\n", i
, rdev
->cp
.ring
[i
]);
2149 static int r100_debugfs_cp_csq_fifo(struct seq_file
*m
, void *data
)
2151 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2152 struct drm_device
*dev
= node
->minor
->dev
;
2153 struct radeon_device
*rdev
= dev
->dev_private
;
2154 uint32_t csq_stat
, csq2_stat
, tmp
;
2155 unsigned r_rptr
, r_wptr
, ib1_rptr
, ib1_wptr
, ib2_rptr
, ib2_wptr
;
2158 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2159 seq_printf(m
, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE
));
2160 csq_stat
= RREG32(RADEON_CP_CSQ_STAT
);
2161 csq2_stat
= RREG32(RADEON_CP_CSQ2_STAT
);
2162 r_rptr
= (csq_stat
>> 0) & 0x3ff;
2163 r_wptr
= (csq_stat
>> 10) & 0x3ff;
2164 ib1_rptr
= (csq_stat
>> 20) & 0x3ff;
2165 ib1_wptr
= (csq2_stat
>> 0) & 0x3ff;
2166 ib2_rptr
= (csq2_stat
>> 10) & 0x3ff;
2167 ib2_wptr
= (csq2_stat
>> 20) & 0x3ff;
2168 seq_printf(m
, "CP_CSQ_STAT 0x%08x\n", csq_stat
);
2169 seq_printf(m
, "CP_CSQ2_STAT 0x%08x\n", csq2_stat
);
2170 seq_printf(m
, "Ring rptr %u\n", r_rptr
);
2171 seq_printf(m
, "Ring wptr %u\n", r_wptr
);
2172 seq_printf(m
, "Indirect1 rptr %u\n", ib1_rptr
);
2173 seq_printf(m
, "Indirect1 wptr %u\n", ib1_wptr
);
2174 seq_printf(m
, "Indirect2 rptr %u\n", ib2_rptr
);
2175 seq_printf(m
, "Indirect2 wptr %u\n", ib2_wptr
);
2176 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2177 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2178 seq_printf(m
, "Ring fifo:\n");
2179 for (i
= 0; i
< 256; i
++) {
2180 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2181 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2182 seq_printf(m
, "rfifo[%04d]=0x%08X\n", i
, tmp
);
2184 seq_printf(m
, "Indirect1 fifo:\n");
2185 for (i
= 256; i
<= 512; i
++) {
2186 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2187 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2188 seq_printf(m
, "ib1fifo[%04d]=0x%08X\n", i
, tmp
);
2190 seq_printf(m
, "Indirect2 fifo:\n");
2191 for (i
= 640; i
< ib1_wptr
; i
++) {
2192 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2193 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2194 seq_printf(m
, "ib2fifo[%04d]=0x%08X\n", i
, tmp
);
2199 static int r100_debugfs_mc_info(struct seq_file
*m
, void *data
)
2201 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2202 struct drm_device
*dev
= node
->minor
->dev
;
2203 struct radeon_device
*rdev
= dev
->dev_private
;
2206 tmp
= RREG32(RADEON_CONFIG_MEMSIZE
);
2207 seq_printf(m
, "CONFIG_MEMSIZE 0x%08x\n", tmp
);
2208 tmp
= RREG32(RADEON_MC_FB_LOCATION
);
2209 seq_printf(m
, "MC_FB_LOCATION 0x%08x\n", tmp
);
2210 tmp
= RREG32(RADEON_BUS_CNTL
);
2211 seq_printf(m
, "BUS_CNTL 0x%08x\n", tmp
);
2212 tmp
= RREG32(RADEON_MC_AGP_LOCATION
);
2213 seq_printf(m
, "MC_AGP_LOCATION 0x%08x\n", tmp
);
2214 tmp
= RREG32(RADEON_AGP_BASE
);
2215 seq_printf(m
, "AGP_BASE 0x%08x\n", tmp
);
2216 tmp
= RREG32(RADEON_HOST_PATH_CNTL
);
2217 seq_printf(m
, "HOST_PATH_CNTL 0x%08x\n", tmp
);
2218 tmp
= RREG32(0x01D0);
2219 seq_printf(m
, "AIC_CTRL 0x%08x\n", tmp
);
2220 tmp
= RREG32(RADEON_AIC_LO_ADDR
);
2221 seq_printf(m
, "AIC_LO_ADDR 0x%08x\n", tmp
);
2222 tmp
= RREG32(RADEON_AIC_HI_ADDR
);
2223 seq_printf(m
, "AIC_HI_ADDR 0x%08x\n", tmp
);
2224 tmp
= RREG32(0x01E4);
2225 seq_printf(m
, "AIC_TLB_ADDR 0x%08x\n", tmp
);
2229 static struct drm_info_list r100_debugfs_rbbm_list
[] = {
2230 {"r100_rbbm_info", r100_debugfs_rbbm_info
, 0, NULL
},
2233 static struct drm_info_list r100_debugfs_cp_list
[] = {
2234 {"r100_cp_ring_info", r100_debugfs_cp_ring_info
, 0, NULL
},
2235 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo
, 0, NULL
},
2238 static struct drm_info_list r100_debugfs_mc_info_list
[] = {
2239 {"r100_mc_info", r100_debugfs_mc_info
, 0, NULL
},
2243 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
)
2245 #if defined(CONFIG_DEBUG_FS)
2246 return radeon_debugfs_add_files(rdev
, r100_debugfs_rbbm_list
, 1);
2252 int r100_debugfs_cp_init(struct radeon_device
*rdev
)
2254 #if defined(CONFIG_DEBUG_FS)
2255 return radeon_debugfs_add_files(rdev
, r100_debugfs_cp_list
, 2);
2261 int r100_debugfs_mc_info_init(struct radeon_device
*rdev
)
2263 #if defined(CONFIG_DEBUG_FS)
2264 return radeon_debugfs_add_files(rdev
, r100_debugfs_mc_info_list
, 1);
2270 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
2271 uint32_t tiling_flags
, uint32_t pitch
,
2272 uint32_t offset
, uint32_t obj_size
)
2274 int surf_index
= reg
* 16;
2277 /* r100/r200 divide by 16 */
2278 if (rdev
->family
< CHIP_R300
)
2283 if (rdev
->family
<= CHIP_RS200
) {
2284 if ((tiling_flags
& (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2285 == (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2286 flags
|= RADEON_SURF_TILE_COLOR_BOTH
;
2287 if (tiling_flags
& RADEON_TILING_MACRO
)
2288 flags
|= RADEON_SURF_TILE_COLOR_MACRO
;
2289 } else if (rdev
->family
<= CHIP_RV280
) {
2290 if (tiling_flags
& (RADEON_TILING_MACRO
))
2291 flags
|= R200_SURF_TILE_COLOR_MACRO
;
2292 if (tiling_flags
& RADEON_TILING_MICRO
)
2293 flags
|= R200_SURF_TILE_COLOR_MICRO
;
2295 if (tiling_flags
& RADEON_TILING_MACRO
)
2296 flags
|= R300_SURF_TILE_MACRO
;
2297 if (tiling_flags
& RADEON_TILING_MICRO
)
2298 flags
|= R300_SURF_TILE_MICRO
;
2301 if (tiling_flags
& RADEON_TILING_SWAP_16BIT
)
2302 flags
|= RADEON_SURF_AP0_SWP_16BPP
| RADEON_SURF_AP1_SWP_16BPP
;
2303 if (tiling_flags
& RADEON_TILING_SWAP_32BIT
)
2304 flags
|= RADEON_SURF_AP0_SWP_32BPP
| RADEON_SURF_AP1_SWP_32BPP
;
2306 DRM_DEBUG("writing surface %d %d %x %x\n", reg
, flags
, offset
, offset
+obj_size
-1);
2307 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, flags
);
2308 WREG32(RADEON_SURFACE0_LOWER_BOUND
+ surf_index
, offset
);
2309 WREG32(RADEON_SURFACE0_UPPER_BOUND
+ surf_index
, offset
+ obj_size
- 1);
2313 void r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
2315 int surf_index
= reg
* 16;
2316 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, 0);
2319 void r100_bandwidth_update(struct radeon_device
*rdev
)
2321 fixed20_12 trcd_ff
, trp_ff
, tras_ff
, trbs_ff
, tcas_ff
;
2322 fixed20_12 sclk_ff
, mclk_ff
, sclk_eff_ff
, sclk_delay_ff
;
2323 fixed20_12 peak_disp_bw
, mem_bw
, pix_clk
, pix_clk2
, temp_ff
, crit_point_ff
;
2324 uint32_t temp
, data
, mem_trcd
, mem_trp
, mem_tras
;
2325 fixed20_12 memtcas_ff
[8] = {
2334 fixed20_12 memtcas_rs480_ff
[8] = {
2344 fixed20_12 memtcas2_ff
[8] = {
2354 fixed20_12 memtrbs
[8] = {
2364 fixed20_12 memtrbs_r4xx
[8] = {
2374 fixed20_12 min_mem_eff
;
2375 fixed20_12 mc_latency_sclk
, mc_latency_mclk
, k1
;
2376 fixed20_12 cur_latency_mclk
, cur_latency_sclk
;
2377 fixed20_12 disp_latency
, disp_latency_overhead
, disp_drain_rate
,
2378 disp_drain_rate2
, read_return_rate
;
2379 fixed20_12 time_disp1_drop_priority
;
2381 int cur_size
= 16; /* in octawords */
2382 int critical_point
= 0, critical_point2
;
2383 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2384 int stop_req
, max_stop_req
;
2385 struct drm_display_mode
*mode1
= NULL
;
2386 struct drm_display_mode
*mode2
= NULL
;
2387 uint32_t pixel_bytes1
= 0;
2388 uint32_t pixel_bytes2
= 0;
2390 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
) {
2391 mode1
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
2392 pixel_bytes1
= rdev
->mode_info
.crtcs
[0]->base
.fb
->bits_per_pixel
/ 8;
2394 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
2395 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
) {
2396 mode2
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
2397 pixel_bytes2
= rdev
->mode_info
.crtcs
[1]->base
.fb
->bits_per_pixel
/ 8;
2401 min_mem_eff
.full
= rfixed_const_8(0);
2403 if ((rdev
->disp_priority
== 2) && ASIC_IS_R300(rdev
)) {
2404 uint32_t mc_init_misc_lat_timer
= RREG32(R300_MC_INIT_MISC_LAT_TIMER
);
2405 mc_init_misc_lat_timer
&= ~(R300_MC_DISP1R_INIT_LAT_MASK
<< R300_MC_DISP1R_INIT_LAT_SHIFT
);
2406 mc_init_misc_lat_timer
&= ~(R300_MC_DISP0R_INIT_LAT_MASK
<< R300_MC_DISP0R_INIT_LAT_SHIFT
);
2407 /* check crtc enables */
2409 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT
);
2411 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT
);
2412 WREG32(R300_MC_INIT_MISC_LAT_TIMER
, mc_init_misc_lat_timer
);
2416 * determine is there is enough bw for current mode
2418 mclk_ff
.full
= rfixed_const(rdev
->clock
.default_mclk
);
2419 temp_ff
.full
= rfixed_const(100);
2420 mclk_ff
.full
= rfixed_div(mclk_ff
, temp_ff
);
2421 sclk_ff
.full
= rfixed_const(rdev
->clock
.default_sclk
);
2422 sclk_ff
.full
= rfixed_div(sclk_ff
, temp_ff
);
2424 temp
= (rdev
->mc
.vram_width
/ 8) * (rdev
->mc
.vram_is_ddr
? 2 : 1);
2425 temp_ff
.full
= rfixed_const(temp
);
2426 mem_bw
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2430 peak_disp_bw
.full
= 0;
2432 temp_ff
.full
= rfixed_const(1000);
2433 pix_clk
.full
= rfixed_const(mode1
->clock
); /* convert to fixed point */
2434 pix_clk
.full
= rfixed_div(pix_clk
, temp_ff
);
2435 temp_ff
.full
= rfixed_const(pixel_bytes1
);
2436 peak_disp_bw
.full
+= rfixed_mul(pix_clk
, temp_ff
);
2439 temp_ff
.full
= rfixed_const(1000);
2440 pix_clk2
.full
= rfixed_const(mode2
->clock
); /* convert to fixed point */
2441 pix_clk2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2442 temp_ff
.full
= rfixed_const(pixel_bytes2
);
2443 peak_disp_bw
.full
+= rfixed_mul(pix_clk2
, temp_ff
);
2446 mem_bw
.full
= rfixed_mul(mem_bw
, min_mem_eff
);
2447 if (peak_disp_bw
.full
>= mem_bw
.full
) {
2448 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2449 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2452 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2453 temp
= RREG32(RADEON_MEM_TIMING_CNTL
);
2454 if ((rdev
->family
== CHIP_RV100
) || (rdev
->flags
& RADEON_IS_IGP
)) { /* RV100, M6, IGPs */
2455 mem_trcd
= ((temp
>> 2) & 0x3) + 1;
2456 mem_trp
= ((temp
& 0x3)) + 1;
2457 mem_tras
= ((temp
& 0x70) >> 4) + 1;
2458 } else if (rdev
->family
== CHIP_R300
||
2459 rdev
->family
== CHIP_R350
) { /* r300, r350 */
2460 mem_trcd
= (temp
& 0x7) + 1;
2461 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2462 mem_tras
= ((temp
>> 11) & 0xf) + 4;
2463 } else if (rdev
->family
== CHIP_RV350
||
2464 rdev
->family
<= CHIP_RV380
) {
2466 mem_trcd
= (temp
& 0x7) + 3;
2467 mem_trp
= ((temp
>> 8) & 0x7) + 3;
2468 mem_tras
= ((temp
>> 11) & 0xf) + 6;
2469 } else if (rdev
->family
== CHIP_R420
||
2470 rdev
->family
== CHIP_R423
||
2471 rdev
->family
== CHIP_RV410
) {
2473 mem_trcd
= (temp
& 0xf) + 3;
2476 mem_trp
= ((temp
>> 8) & 0xf) + 3;
2479 mem_tras
= ((temp
>> 12) & 0x1f) + 6;
2482 } else { /* RV200, R200 */
2483 mem_trcd
= (temp
& 0x7) + 1;
2484 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2485 mem_tras
= ((temp
>> 12) & 0xf) + 4;
2488 trcd_ff
.full
= rfixed_const(mem_trcd
);
2489 trp_ff
.full
= rfixed_const(mem_trp
);
2490 tras_ff
.full
= rfixed_const(mem_tras
);
2492 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2493 temp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2494 data
= (temp
& (7 << 20)) >> 20;
2495 if ((rdev
->family
== CHIP_RV100
) || rdev
->flags
& RADEON_IS_IGP
) {
2496 if (rdev
->family
== CHIP_RS480
) /* don't think rs400 */
2497 tcas_ff
= memtcas_rs480_ff
[data
];
2499 tcas_ff
= memtcas_ff
[data
];
2501 tcas_ff
= memtcas2_ff
[data
];
2503 if (rdev
->family
== CHIP_RS400
||
2504 rdev
->family
== CHIP_RS480
) {
2505 /* extra cas latency stored in bits 23-25 0-4 clocks */
2506 data
= (temp
>> 23) & 0x7;
2508 tcas_ff
.full
+= rfixed_const(data
);
2511 if (ASIC_IS_R300(rdev
) && !(rdev
->flags
& RADEON_IS_IGP
)) {
2512 /* on the R300, Tcas is included in Trbs.
2514 temp
= RREG32(RADEON_MEM_CNTL
);
2515 data
= (R300_MEM_NUM_CHANNELS_MASK
& temp
);
2517 if (R300_MEM_USE_CD_CH_ONLY
& temp
) {
2518 temp
= RREG32(R300_MC_IND_INDEX
);
2519 temp
&= ~R300_MC_IND_ADDR_MASK
;
2520 temp
|= R300_MC_READ_CNTL_CD_mcind
;
2521 WREG32(R300_MC_IND_INDEX
, temp
);
2522 temp
= RREG32(R300_MC_IND_DATA
);
2523 data
= (R300_MEM_RBS_POSITION_C_MASK
& temp
);
2525 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2526 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2529 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2530 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2532 if (rdev
->family
== CHIP_RV410
||
2533 rdev
->family
== CHIP_R420
||
2534 rdev
->family
== CHIP_R423
)
2535 trbs_ff
= memtrbs_r4xx
[data
];
2537 trbs_ff
= memtrbs
[data
];
2538 tcas_ff
.full
+= trbs_ff
.full
;
2541 sclk_eff_ff
.full
= sclk_ff
.full
;
2543 if (rdev
->flags
& RADEON_IS_AGP
) {
2544 fixed20_12 agpmode_ff
;
2545 agpmode_ff
.full
= rfixed_const(radeon_agpmode
);
2546 temp_ff
.full
= rfixed_const_666(16);
2547 sclk_eff_ff
.full
-= rfixed_mul(agpmode_ff
, temp_ff
);
2549 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2551 if (ASIC_IS_R300(rdev
)) {
2552 sclk_delay_ff
.full
= rfixed_const(250);
2554 if ((rdev
->family
== CHIP_RV100
) ||
2555 rdev
->flags
& RADEON_IS_IGP
) {
2556 if (rdev
->mc
.vram_is_ddr
)
2557 sclk_delay_ff
.full
= rfixed_const(41);
2559 sclk_delay_ff
.full
= rfixed_const(33);
2561 if (rdev
->mc
.vram_width
== 128)
2562 sclk_delay_ff
.full
= rfixed_const(57);
2564 sclk_delay_ff
.full
= rfixed_const(41);
2568 mc_latency_sclk
.full
= rfixed_div(sclk_delay_ff
, sclk_eff_ff
);
2570 if (rdev
->mc
.vram_is_ddr
) {
2571 if (rdev
->mc
.vram_width
== 32) {
2572 k1
.full
= rfixed_const(40);
2575 k1
.full
= rfixed_const(20);
2579 k1
.full
= rfixed_const(40);
2583 temp_ff
.full
= rfixed_const(2);
2584 mc_latency_mclk
.full
= rfixed_mul(trcd_ff
, temp_ff
);
2585 temp_ff
.full
= rfixed_const(c
);
2586 mc_latency_mclk
.full
+= rfixed_mul(tcas_ff
, temp_ff
);
2587 temp_ff
.full
= rfixed_const(4);
2588 mc_latency_mclk
.full
+= rfixed_mul(tras_ff
, temp_ff
);
2589 mc_latency_mclk
.full
+= rfixed_mul(trp_ff
, temp_ff
);
2590 mc_latency_mclk
.full
+= k1
.full
;
2592 mc_latency_mclk
.full
= rfixed_div(mc_latency_mclk
, mclk_ff
);
2593 mc_latency_mclk
.full
+= rfixed_div(temp_ff
, sclk_eff_ff
);
2596 HW cursor time assuming worst case of full size colour cursor.
2598 temp_ff
.full
= rfixed_const((2 * (cur_size
- (rdev
->mc
.vram_is_ddr
+ 1))));
2599 temp_ff
.full
+= trcd_ff
.full
;
2600 if (temp_ff
.full
< tras_ff
.full
)
2601 temp_ff
.full
= tras_ff
.full
;
2602 cur_latency_mclk
.full
= rfixed_div(temp_ff
, mclk_ff
);
2604 temp_ff
.full
= rfixed_const(cur_size
);
2605 cur_latency_sclk
.full
= rfixed_div(temp_ff
, sclk_eff_ff
);
2607 Find the total latency for the display data.
2609 disp_latency_overhead
.full
= rfixed_const(8);
2610 disp_latency_overhead
.full
= rfixed_div(disp_latency_overhead
, sclk_ff
);
2611 mc_latency_mclk
.full
+= disp_latency_overhead
.full
+ cur_latency_mclk
.full
;
2612 mc_latency_sclk
.full
+= disp_latency_overhead
.full
+ cur_latency_sclk
.full
;
2614 if (mc_latency_mclk
.full
> mc_latency_sclk
.full
)
2615 disp_latency
.full
= mc_latency_mclk
.full
;
2617 disp_latency
.full
= mc_latency_sclk
.full
;
2619 /* setup Max GRPH_STOP_REQ default value */
2620 if (ASIC_IS_RV100(rdev
))
2621 max_stop_req
= 0x5c;
2623 max_stop_req
= 0x7c;
2627 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2628 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2630 stop_req
= mode1
->hdisplay
* pixel_bytes1
/ 16;
2632 if (stop_req
> max_stop_req
)
2633 stop_req
= max_stop_req
;
2636 Find the drain rate of the display buffer.
2638 temp_ff
.full
= rfixed_const((16/pixel_bytes1
));
2639 disp_drain_rate
.full
= rfixed_div(pix_clk
, temp_ff
);
2642 Find the critical point of the display buffer.
2644 crit_point_ff
.full
= rfixed_mul(disp_drain_rate
, disp_latency
);
2645 crit_point_ff
.full
+= rfixed_const_half(0);
2647 critical_point
= rfixed_trunc(crit_point_ff
);
2649 if (rdev
->disp_priority
== 2) {
2654 The critical point should never be above max_stop_req-4. Setting
2655 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2657 if (max_stop_req
- critical_point
< 4)
2660 if (critical_point
== 0 && mode2
&& rdev
->family
== CHIP_R300
) {
2661 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2662 critical_point
= 0x10;
2665 temp
= RREG32(RADEON_GRPH_BUFFER_CNTL
);
2666 temp
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2667 temp
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2668 temp
&= ~(RADEON_GRPH_START_REQ_MASK
);
2669 if ((rdev
->family
== CHIP_R350
) &&
2670 (stop_req
> 0x15)) {
2673 temp
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2674 temp
|= RADEON_GRPH_BUFFER_SIZE
;
2675 temp
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2676 RADEON_GRPH_CRITICAL_AT_SOF
|
2677 RADEON_GRPH_STOP_CNTL
);
2679 Write the result into the register.
2681 WREG32(RADEON_GRPH_BUFFER_CNTL
, ((temp
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2682 (critical_point
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2685 if ((rdev
->family
== CHIP_RS400
) ||
2686 (rdev
->family
== CHIP_RS480
)) {
2687 /* attempt to program RS400 disp regs correctly ??? */
2688 temp
= RREG32(RS400_DISP1_REG_CNTL
);
2689 temp
&= ~(RS400_DISP1_START_REQ_LEVEL_MASK
|
2690 RS400_DISP1_STOP_REQ_LEVEL_MASK
);
2691 WREG32(RS400_DISP1_REQ_CNTL1
, (temp
|
2692 (critical_point
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2693 (critical_point
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2694 temp
= RREG32(RS400_DMIF_MEM_CNTL1
);
2695 temp
&= ~(RS400_DISP1_CRITICAL_POINT_START_MASK
|
2696 RS400_DISP1_CRITICAL_POINT_STOP_MASK
);
2697 WREG32(RS400_DMIF_MEM_CNTL1
, (temp
|
2698 (critical_point
<< RS400_DISP1_CRITICAL_POINT_START_SHIFT
) |
2699 (critical_point
<< RS400_DISP1_CRITICAL_POINT_STOP_SHIFT
)));
2703 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2704 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2705 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL
));
2710 stop_req
= mode2
->hdisplay
* pixel_bytes2
/ 16;
2712 if (stop_req
> max_stop_req
)
2713 stop_req
= max_stop_req
;
2716 Find the drain rate of the display buffer.
2718 temp_ff
.full
= rfixed_const((16/pixel_bytes2
));
2719 disp_drain_rate2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2721 grph2_cntl
= RREG32(RADEON_GRPH2_BUFFER_CNTL
);
2722 grph2_cntl
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2723 grph2_cntl
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2724 grph2_cntl
&= ~(RADEON_GRPH_START_REQ_MASK
);
2725 if ((rdev
->family
== CHIP_R350
) &&
2726 (stop_req
> 0x15)) {
2729 grph2_cntl
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2730 grph2_cntl
|= RADEON_GRPH_BUFFER_SIZE
;
2731 grph2_cntl
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2732 RADEON_GRPH_CRITICAL_AT_SOF
|
2733 RADEON_GRPH_STOP_CNTL
);
2735 if ((rdev
->family
== CHIP_RS100
) ||
2736 (rdev
->family
== CHIP_RS200
))
2737 critical_point2
= 0;
2739 temp
= (rdev
->mc
.vram_width
* rdev
->mc
.vram_is_ddr
+ 1)/128;
2740 temp_ff
.full
= rfixed_const(temp
);
2741 temp_ff
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2742 if (sclk_ff
.full
< temp_ff
.full
)
2743 temp_ff
.full
= sclk_ff
.full
;
2745 read_return_rate
.full
= temp_ff
.full
;
2748 temp_ff
.full
= read_return_rate
.full
- disp_drain_rate
.full
;
2749 time_disp1_drop_priority
.full
= rfixed_div(crit_point_ff
, temp_ff
);
2751 time_disp1_drop_priority
.full
= 0;
2753 crit_point_ff
.full
= disp_latency
.full
+ time_disp1_drop_priority
.full
+ disp_latency
.full
;
2754 crit_point_ff
.full
= rfixed_mul(crit_point_ff
, disp_drain_rate2
);
2755 crit_point_ff
.full
+= rfixed_const_half(0);
2757 critical_point2
= rfixed_trunc(crit_point_ff
);
2759 if (rdev
->disp_priority
== 2) {
2760 critical_point2
= 0;
2763 if (max_stop_req
- critical_point2
< 4)
2764 critical_point2
= 0;
2768 if (critical_point2
== 0 && rdev
->family
== CHIP_R300
) {
2769 /* some R300 cards have problem with this set to 0 */
2770 critical_point2
= 0x10;
2773 WREG32(RADEON_GRPH2_BUFFER_CNTL
, ((grph2_cntl
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2774 (critical_point2
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2776 if ((rdev
->family
== CHIP_RS400
) ||
2777 (rdev
->family
== CHIP_RS480
)) {
2779 /* attempt to program RS400 disp2 regs correctly ??? */
2780 temp
= RREG32(RS400_DISP2_REQ_CNTL1
);
2781 temp
&= ~(RS400_DISP2_START_REQ_LEVEL_MASK
|
2782 RS400_DISP2_STOP_REQ_LEVEL_MASK
);
2783 WREG32(RS400_DISP2_REQ_CNTL1
, (temp
|
2784 (critical_point2
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2785 (critical_point2
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2786 temp
= RREG32(RS400_DISP2_REQ_CNTL2
);
2787 temp
&= ~(RS400_DISP2_CRITICAL_POINT_START_MASK
|
2788 RS400_DISP2_CRITICAL_POINT_STOP_MASK
);
2789 WREG32(RS400_DISP2_REQ_CNTL2
, (temp
|
2790 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_START_SHIFT
) |
2791 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_STOP_SHIFT
)));
2793 WREG32(RS400_DISP2_REQ_CNTL1
, 0x105DC1CC);
2794 WREG32(RS400_DISP2_REQ_CNTL2
, 0x2749D000);
2795 WREG32(RS400_DMIF_MEM_CNTL1
, 0x29CA71DC);
2796 WREG32(RS400_DISP1_REQ_CNTL1
, 0x28FBC3AC);
2799 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2800 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL
));
2804 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture
*t
)
2806 DRM_ERROR("pitch %d\n", t
->pitch
);
2807 DRM_ERROR("use_pitch %d\n", t
->use_pitch
);
2808 DRM_ERROR("width %d\n", t
->width
);
2809 DRM_ERROR("width_11 %d\n", t
->width_11
);
2810 DRM_ERROR("height %d\n", t
->height
);
2811 DRM_ERROR("height_11 %d\n", t
->height_11
);
2812 DRM_ERROR("num levels %d\n", t
->num_levels
);
2813 DRM_ERROR("depth %d\n", t
->txdepth
);
2814 DRM_ERROR("bpp %d\n", t
->cpp
);
2815 DRM_ERROR("coordinate type %d\n", t
->tex_coord_type
);
2816 DRM_ERROR("width round to power of 2 %d\n", t
->roundup_w
);
2817 DRM_ERROR("height round to power of 2 %d\n", t
->roundup_h
);
2818 DRM_ERROR("compress format %d\n", t
->compress_format
);
2821 static int r100_cs_track_cube(struct radeon_device
*rdev
,
2822 struct r100_cs_track
*track
, unsigned idx
)
2824 unsigned face
, w
, h
;
2825 struct radeon_bo
*cube_robj
;
2828 for (face
= 0; face
< 5; face
++) {
2829 cube_robj
= track
->textures
[idx
].cube_info
[face
].robj
;
2830 w
= track
->textures
[idx
].cube_info
[face
].width
;
2831 h
= track
->textures
[idx
].cube_info
[face
].height
;
2834 size
*= track
->textures
[idx
].cpp
;
2836 size
+= track
->textures
[idx
].cube_info
[face
].offset
;
2838 if (size
> radeon_bo_size(cube_robj
)) {
2839 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2840 size
, radeon_bo_size(cube_robj
));
2841 r100_cs_track_texture_print(&track
->textures
[idx
]);
2848 static int r100_track_compress_size(int compress_format
, int w
, int h
)
2850 int block_width
, block_height
, block_bytes
;
2851 int wblocks
, hblocks
;
2858 switch (compress_format
) {
2859 case R100_TRACK_COMP_DXT1
:
2864 case R100_TRACK_COMP_DXT35
:
2870 hblocks
= (h
+ block_height
- 1) / block_height
;
2871 wblocks
= (w
+ block_width
- 1) / block_width
;
2872 if (wblocks
< min_wblocks
)
2873 wblocks
= min_wblocks
;
2874 sz
= wblocks
* hblocks
* block_bytes
;
2878 static int r100_cs_track_texture_check(struct radeon_device
*rdev
,
2879 struct r100_cs_track
*track
)
2881 struct radeon_bo
*robj
;
2883 unsigned u
, i
, w
, h
;
2886 for (u
= 0; u
< track
->num_texture
; u
++) {
2887 if (!track
->textures
[u
].enabled
)
2889 robj
= track
->textures
[u
].robj
;
2891 DRM_ERROR("No texture bound to unit %u\n", u
);
2895 for (i
= 0; i
<= track
->textures
[u
].num_levels
; i
++) {
2896 if (track
->textures
[u
].use_pitch
) {
2897 if (rdev
->family
< CHIP_R300
)
2898 w
= (track
->textures
[u
].pitch
/ track
->textures
[u
].cpp
) / (1 << i
);
2900 w
= track
->textures
[u
].pitch
/ (1 << i
);
2902 w
= track
->textures
[u
].width
;
2903 if (rdev
->family
>= CHIP_RV515
)
2904 w
|= track
->textures
[u
].width_11
;
2906 if (track
->textures
[u
].roundup_w
)
2907 w
= roundup_pow_of_two(w
);
2909 h
= track
->textures
[u
].height
;
2910 if (rdev
->family
>= CHIP_RV515
)
2911 h
|= track
->textures
[u
].height_11
;
2913 if (track
->textures
[u
].roundup_h
)
2914 h
= roundup_pow_of_two(h
);
2915 if (track
->textures
[u
].compress_format
) {
2917 size
+= r100_track_compress_size(track
->textures
[u
].compress_format
, w
, h
);
2918 /* compressed textures are block based */
2922 size
*= track
->textures
[u
].cpp
;
2924 switch (track
->textures
[u
].tex_coord_type
) {
2928 size
*= (1 << track
->textures
[u
].txdepth
);
2931 if (track
->separate_cube
) {
2932 ret
= r100_cs_track_cube(rdev
, track
, u
);
2939 DRM_ERROR("Invalid texture coordinate type %u for unit "
2940 "%u\n", track
->textures
[u
].tex_coord_type
, u
);
2943 if (size
> radeon_bo_size(robj
)) {
2944 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2945 "%lu\n", u
, size
, radeon_bo_size(robj
));
2946 r100_cs_track_texture_print(&track
->textures
[u
]);
2953 int r100_cs_track_check(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
2960 for (i
= 0; i
< track
->num_cb
; i
++) {
2961 if (track
->cb
[i
].robj
== NULL
) {
2962 if (!(track
->fastfill
|| track
->color_channel_mask
||
2963 track
->blend_read_enable
)) {
2966 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i
);
2969 size
= track
->cb
[i
].pitch
* track
->cb
[i
].cpp
* track
->maxy
;
2970 size
+= track
->cb
[i
].offset
;
2971 if (size
> radeon_bo_size(track
->cb
[i
].robj
)) {
2972 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2973 "(need %lu have %lu) !\n", i
, size
,
2974 radeon_bo_size(track
->cb
[i
].robj
));
2975 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2976 i
, track
->cb
[i
].pitch
, track
->cb
[i
].cpp
,
2977 track
->cb
[i
].offset
, track
->maxy
);
2981 if (track
->z_enabled
) {
2982 if (track
->zb
.robj
== NULL
) {
2983 DRM_ERROR("[drm] No buffer for z buffer !\n");
2986 size
= track
->zb
.pitch
* track
->zb
.cpp
* track
->maxy
;
2987 size
+= track
->zb
.offset
;
2988 if (size
> radeon_bo_size(track
->zb
.robj
)) {
2989 DRM_ERROR("[drm] Buffer too small for z buffer "
2990 "(need %lu have %lu) !\n", size
,
2991 radeon_bo_size(track
->zb
.robj
));
2992 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2993 track
->zb
.pitch
, track
->zb
.cpp
,
2994 track
->zb
.offset
, track
->maxy
);
2998 prim_walk
= (track
->vap_vf_cntl
>> 4) & 0x3;
2999 nverts
= (track
->vap_vf_cntl
>> 16) & 0xFFFF;
3000 switch (prim_walk
) {
3002 for (i
= 0; i
< track
->num_arrays
; i
++) {
3003 size
= track
->arrays
[i
].esize
* track
->max_indx
* 4;
3004 if (track
->arrays
[i
].robj
== NULL
) {
3005 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3006 "bound\n", prim_walk
, i
);
3009 if (size
> radeon_bo_size(track
->arrays
[i
].robj
)) {
3010 dev_err(rdev
->dev
, "(PW %u) Vertex array %u "
3011 "need %lu dwords have %lu dwords\n",
3012 prim_walk
, i
, size
>> 2,
3013 radeon_bo_size(track
->arrays
[i
].robj
)
3015 DRM_ERROR("Max indices %u\n", track
->max_indx
);
3021 for (i
= 0; i
< track
->num_arrays
; i
++) {
3022 size
= track
->arrays
[i
].esize
* (nverts
- 1) * 4;
3023 if (track
->arrays
[i
].robj
== NULL
) {
3024 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3025 "bound\n", prim_walk
, i
);
3028 if (size
> radeon_bo_size(track
->arrays
[i
].robj
)) {
3029 dev_err(rdev
->dev
, "(PW %u) Vertex array %u "
3030 "need %lu dwords have %lu dwords\n",
3031 prim_walk
, i
, size
>> 2,
3032 radeon_bo_size(track
->arrays
[i
].robj
)
3039 size
= track
->vtx_size
* nverts
;
3040 if (size
!= track
->immd_dwords
) {
3041 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3042 track
->immd_dwords
, size
);
3043 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3044 nverts
, track
->vtx_size
);
3049 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3053 return r100_cs_track_texture_check(rdev
, track
);
3056 void r100_cs_track_clear(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
3060 if (rdev
->family
< CHIP_R300
) {
3062 if (rdev
->family
<= CHIP_RS200
)
3063 track
->num_texture
= 3;
3065 track
->num_texture
= 6;
3067 track
->separate_cube
= 1;
3070 track
->num_texture
= 16;
3072 track
->separate_cube
= 0;
3075 for (i
= 0; i
< track
->num_cb
; i
++) {
3076 track
->cb
[i
].robj
= NULL
;
3077 track
->cb
[i
].pitch
= 8192;
3078 track
->cb
[i
].cpp
= 16;
3079 track
->cb
[i
].offset
= 0;
3081 track
->z_enabled
= true;
3082 track
->zb
.robj
= NULL
;
3083 track
->zb
.pitch
= 8192;
3085 track
->zb
.offset
= 0;
3086 track
->vtx_size
= 0x7F;
3087 track
->immd_dwords
= 0xFFFFFFFFUL
;
3088 track
->num_arrays
= 11;
3089 track
->max_indx
= 0x00FFFFFFUL
;
3090 for (i
= 0; i
< track
->num_arrays
; i
++) {
3091 track
->arrays
[i
].robj
= NULL
;
3092 track
->arrays
[i
].esize
= 0x7F;
3094 for (i
= 0; i
< track
->num_texture
; i
++) {
3095 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
3096 track
->textures
[i
].pitch
= 16536;
3097 track
->textures
[i
].width
= 16536;
3098 track
->textures
[i
].height
= 16536;
3099 track
->textures
[i
].width_11
= 1 << 11;
3100 track
->textures
[i
].height_11
= 1 << 11;
3101 track
->textures
[i
].num_levels
= 12;
3102 if (rdev
->family
<= CHIP_RS200
) {
3103 track
->textures
[i
].tex_coord_type
= 0;
3104 track
->textures
[i
].txdepth
= 0;
3106 track
->textures
[i
].txdepth
= 16;
3107 track
->textures
[i
].tex_coord_type
= 1;
3109 track
->textures
[i
].cpp
= 64;
3110 track
->textures
[i
].robj
= NULL
;
3111 /* CS IB emission code makes sure texture unit are disabled */
3112 track
->textures
[i
].enabled
= false;
3113 track
->textures
[i
].roundup_w
= true;
3114 track
->textures
[i
].roundup_h
= true;
3115 if (track
->separate_cube
)
3116 for (face
= 0; face
< 5; face
++) {
3117 track
->textures
[i
].cube_info
[face
].robj
= NULL
;
3118 track
->textures
[i
].cube_info
[face
].width
= 16536;
3119 track
->textures
[i
].cube_info
[face
].height
= 16536;
3120 track
->textures
[i
].cube_info
[face
].offset
= 0;
3125 int r100_ring_test(struct radeon_device
*rdev
)
3132 r
= radeon_scratch_get(rdev
, &scratch
);
3134 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
3137 WREG32(scratch
, 0xCAFEDEAD);
3138 r
= radeon_ring_lock(rdev
, 2);
3140 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
3141 radeon_scratch_free(rdev
, scratch
);
3144 radeon_ring_write(rdev
, PACKET0(scratch
, 0));
3145 radeon_ring_write(rdev
, 0xDEADBEEF);
3146 radeon_ring_unlock_commit(rdev
);
3147 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3148 tmp
= RREG32(scratch
);
3149 if (tmp
== 0xDEADBEEF) {
3154 if (i
< rdev
->usec_timeout
) {
3155 DRM_INFO("ring test succeeded in %d usecs\n", i
);
3157 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3161 radeon_scratch_free(rdev
, scratch
);
3165 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3167 radeon_ring_write(rdev
, PACKET0(RADEON_CP_IB_BASE
, 1));
3168 radeon_ring_write(rdev
, ib
->gpu_addr
);
3169 radeon_ring_write(rdev
, ib
->length_dw
);
3172 int r100_ib_test(struct radeon_device
*rdev
)
3174 struct radeon_ib
*ib
;
3180 r
= radeon_scratch_get(rdev
, &scratch
);
3182 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
3185 WREG32(scratch
, 0xCAFEDEAD);
3186 r
= radeon_ib_get(rdev
, &ib
);
3190 ib
->ptr
[0] = PACKET0(scratch
, 0);
3191 ib
->ptr
[1] = 0xDEADBEEF;
3192 ib
->ptr
[2] = PACKET2(0);
3193 ib
->ptr
[3] = PACKET2(0);
3194 ib
->ptr
[4] = PACKET2(0);
3195 ib
->ptr
[5] = PACKET2(0);
3196 ib
->ptr
[6] = PACKET2(0);
3197 ib
->ptr
[7] = PACKET2(0);
3199 r
= radeon_ib_schedule(rdev
, ib
);
3201 radeon_scratch_free(rdev
, scratch
);
3202 radeon_ib_free(rdev
, &ib
);
3205 r
= radeon_fence_wait(ib
->fence
, false);
3209 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3210 tmp
= RREG32(scratch
);
3211 if (tmp
== 0xDEADBEEF) {
3216 if (i
< rdev
->usec_timeout
) {
3217 DRM_INFO("ib test succeeded in %u usecs\n", i
);
3219 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3223 radeon_scratch_free(rdev
, scratch
);
3224 radeon_ib_free(rdev
, &ib
);
3228 void r100_ib_fini(struct radeon_device
*rdev
)
3230 radeon_ib_pool_fini(rdev
);
3233 int r100_ib_init(struct radeon_device
*rdev
)
3237 r
= radeon_ib_pool_init(rdev
);
3239 dev_err(rdev
->dev
, "failled initializing IB pool (%d).\n", r
);
3243 r
= r100_ib_test(rdev
);
3245 dev_err(rdev
->dev
, "failled testing IB (%d).\n", r
);
3252 void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
3254 /* Shutdown CP we shouldn't need to do that but better be safe than
3257 rdev
->cp
.ready
= false;
3258 WREG32(R_000740_CP_CSQ_CNTL
, 0);
3260 /* Save few CRTC registers */
3261 save
->GENMO_WT
= RREG8(R_0003C2_GENMO_WT
);
3262 save
->CRTC_EXT_CNTL
= RREG32(R_000054_CRTC_EXT_CNTL
);
3263 save
->CRTC_GEN_CNTL
= RREG32(R_000050_CRTC_GEN_CNTL
);
3264 save
->CUR_OFFSET
= RREG32(R_000260_CUR_OFFSET
);
3265 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3266 save
->CRTC2_GEN_CNTL
= RREG32(R_0003F8_CRTC2_GEN_CNTL
);
3267 save
->CUR2_OFFSET
= RREG32(R_000360_CUR2_OFFSET
);
3270 /* Disable VGA aperture access */
3271 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& save
->GENMO_WT
);
3272 /* Disable cursor, overlay, crtc */
3273 WREG32(R_000260_CUR_OFFSET
, save
->CUR_OFFSET
| S_000260_CUR_LOCK(1));
3274 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
|
3275 S_000054_CRTC_DISPLAY_DIS(1));
3276 WREG32(R_000050_CRTC_GEN_CNTL
,
3277 (C_000050_CRTC_CUR_EN
& save
->CRTC_GEN_CNTL
) |
3278 S_000050_CRTC_DISP_REQ_EN_B(1));
3279 WREG32(R_000420_OV0_SCALE_CNTL
,
3280 C_000420_OV0_OVERLAY_EN
& RREG32(R_000420_OV0_SCALE_CNTL
));
3281 WREG32(R_000260_CUR_OFFSET
, C_000260_CUR_LOCK
& save
->CUR_OFFSET
);
3282 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3283 WREG32(R_000360_CUR2_OFFSET
, save
->CUR2_OFFSET
|
3284 S_000360_CUR2_LOCK(1));
3285 WREG32(R_0003F8_CRTC2_GEN_CNTL
,
3286 (C_0003F8_CRTC2_CUR_EN
& save
->CRTC2_GEN_CNTL
) |
3287 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3288 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3289 WREG32(R_000360_CUR2_OFFSET
,
3290 C_000360_CUR2_LOCK
& save
->CUR2_OFFSET
);
3294 void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
3296 /* Update base address for crtc */
3297 WREG32(R_00023C_DISPLAY_BASE_ADDR
, rdev
->mc
.vram_location
);
3298 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3299 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR
,
3300 rdev
->mc
.vram_location
);
3302 /* Restore CRTC registers */
3303 WREG8(R_0003C2_GENMO_WT
, save
->GENMO_WT
);
3304 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
);
3305 WREG32(R_000050_CRTC_GEN_CNTL
, save
->CRTC_GEN_CNTL
);
3306 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3307 WREG32(R_0003F8_CRTC2_GEN_CNTL
, save
->CRTC2_GEN_CNTL
);
3311 void r100_vga_render_disable(struct radeon_device
*rdev
)
3315 tmp
= RREG8(R_0003C2_GENMO_WT
);
3316 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& tmp
);
3319 static void r100_debugfs(struct radeon_device
*rdev
)
3323 r
= r100_debugfs_mc_info_init(rdev
);
3325 dev_warn(rdev
->dev
, "Failed to create r100_mc debugfs file.\n");
3328 static void r100_mc_program(struct radeon_device
*rdev
)
3330 struct r100_mc_save save
;
3332 /* Stops all mc clients */
3333 r100_mc_stop(rdev
, &save
);
3334 if (rdev
->flags
& RADEON_IS_AGP
) {
3335 WREG32(R_00014C_MC_AGP_LOCATION
,
3336 S_00014C_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
3337 S_00014C_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
3338 WREG32(R_000170_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
3339 if (rdev
->family
> CHIP_RV200
)
3340 WREG32(R_00015C_AGP_BASE_2
,
3341 upper_32_bits(rdev
->mc
.agp_base
) & 0xff);
3343 WREG32(R_00014C_MC_AGP_LOCATION
, 0x0FFFFFFF);
3344 WREG32(R_000170_AGP_BASE
, 0);
3345 if (rdev
->family
> CHIP_RV200
)
3346 WREG32(R_00015C_AGP_BASE_2
, 0);
3348 /* Wait for mc idle */
3349 if (r100_mc_wait_for_idle(rdev
))
3350 dev_warn(rdev
->dev
, "Wait for MC idle timeout.\n");
3351 /* Program MC, should be a 32bits limited address space */
3352 WREG32(R_000148_MC_FB_LOCATION
,
3353 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
3354 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
3355 r100_mc_resume(rdev
, &save
);
3358 void r100_clock_startup(struct radeon_device
*rdev
)
3362 if (radeon_dynclks
!= -1 && radeon_dynclks
)
3363 radeon_legacy_set_clock_gating(rdev
, 1);
3364 /* We need to force on some of the block */
3365 tmp
= RREG32_PLL(R_00000D_SCLK_CNTL
);
3366 tmp
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3367 if ((rdev
->family
== CHIP_RV250
) || (rdev
->family
== CHIP_RV280
))
3368 tmp
|= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3369 WREG32_PLL(R_00000D_SCLK_CNTL
, tmp
);
3372 static int r100_startup(struct radeon_device
*rdev
)
3376 /* set common regs */
3377 r100_set_common_regs(rdev
);
3379 r100_mc_program(rdev
);
3381 r100_clock_startup(rdev
);
3382 /* Initialize GPU configuration (# pipes, ...) */
3383 r100_gpu_init(rdev
);
3384 /* Initialize GART (initialize after TTM so we can allocate
3385 * memory through TTM but finalize after TTM) */
3386 r100_enable_bm(rdev
);
3387 if (rdev
->flags
& RADEON_IS_PCI
) {
3388 r
= r100_pci_gart_enable(rdev
);
3394 rdev
->config
.r100
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
3395 /* 1M ring buffer */
3396 r
= r100_cp_init(rdev
, 1024 * 1024);
3398 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
3401 r
= r100_wb_init(rdev
);
3403 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
3404 r
= r100_ib_init(rdev
);
3406 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
3412 int r100_resume(struct radeon_device
*rdev
)
3414 /* Make sur GART are not working */
3415 if (rdev
->flags
& RADEON_IS_PCI
)
3416 r100_pci_gart_disable(rdev
);
3417 /* Resume clock before doing reset */
3418 r100_clock_startup(rdev
);
3419 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3420 if (radeon_gpu_reset(rdev
)) {
3421 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3422 RREG32(R_000E40_RBBM_STATUS
),
3423 RREG32(R_0007C0_CP_STAT
));
3426 radeon_combios_asic_init(rdev
->ddev
);
3427 /* Resume clock after posting */
3428 r100_clock_startup(rdev
);
3429 /* Initialize surface registers */
3430 radeon_surface_init(rdev
);
3431 return r100_startup(rdev
);
3434 int r100_suspend(struct radeon_device
*rdev
)
3436 r100_cp_disable(rdev
);
3437 r100_wb_disable(rdev
);
3438 r100_irq_disable(rdev
);
3439 if (rdev
->flags
& RADEON_IS_PCI
)
3440 r100_pci_gart_disable(rdev
);
3444 void r100_fini(struct radeon_device
*rdev
)
3449 radeon_gem_fini(rdev
);
3450 if (rdev
->flags
& RADEON_IS_PCI
)
3451 r100_pci_gart_fini(rdev
);
3452 radeon_agp_fini(rdev
);
3453 radeon_irq_kms_fini(rdev
);
3454 radeon_fence_driver_fini(rdev
);
3455 radeon_bo_fini(rdev
);
3456 radeon_atombios_fini(rdev
);
3461 int r100_mc_init(struct radeon_device
*rdev
)
3466 /* Setup GPU memory space */
3467 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
3468 rdev
->mc
.gtt_location
= 0xFFFFFFFFUL
;
3469 if (rdev
->flags
& RADEON_IS_IGP
) {
3470 tmp
= G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM
));
3471 rdev
->mc
.vram_location
= tmp
<< 16;
3473 if (rdev
->flags
& RADEON_IS_AGP
) {
3474 r
= radeon_agp_init(rdev
);
3476 radeon_agp_disable(rdev
);
3478 rdev
->mc
.gtt_location
= rdev
->mc
.agp_base
;
3481 r
= radeon_mc_setup(rdev
);
3487 int r100_init(struct radeon_device
*rdev
)
3491 /* Register debugfs file specific to this group of asics */
3494 r100_vga_render_disable(rdev
);
3495 /* Initialize scratch registers */
3496 radeon_scratch_init(rdev
);
3497 /* Initialize surface registers */
3498 radeon_surface_init(rdev
);
3499 /* TODO: disable VGA need to use VGA request */
3501 if (!radeon_get_bios(rdev
)) {
3502 if (ASIC_IS_AVIVO(rdev
))
3505 if (rdev
->is_atom_bios
) {
3506 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
3509 r
= radeon_combios_init(rdev
);
3513 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3514 if (radeon_gpu_reset(rdev
)) {
3516 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3517 RREG32(R_000E40_RBBM_STATUS
),
3518 RREG32(R_0007C0_CP_STAT
));
3520 /* check if cards are posted or not */
3521 if (radeon_boot_test_post_card(rdev
) == false)
3523 /* Set asic errata */
3525 /* Initialize clocks */
3526 radeon_get_clock_info(rdev
->ddev
);
3527 /* Initialize power management */
3528 radeon_pm_init(rdev
);
3529 /* Get vram informations */
3530 r100_vram_info(rdev
);
3531 /* Initialize memory controller (also test AGP) */
3532 r
= r100_mc_init(rdev
);
3536 r
= radeon_fence_driver_init(rdev
);
3539 r
= radeon_irq_kms_init(rdev
);
3542 /* Memory manager */
3543 r
= radeon_bo_init(rdev
);
3546 if (rdev
->flags
& RADEON_IS_PCI
) {
3547 r
= r100_pci_gart_init(rdev
);
3551 r100_set_safe_registers(rdev
);
3552 rdev
->accel_working
= true;
3553 r
= r100_startup(rdev
);
3555 /* Somethings want wront with the accel init stop accel */
3556 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
3560 radeon_irq_kms_fini(rdev
);
3561 if (rdev
->flags
& RADEON_IS_PCI
)
3562 r100_pci_gart_fini(rdev
);
3563 rdev
->accel_working
= false;