2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
54 MODULE_FIRMWARE(FIRMWARE_R100
);
55 MODULE_FIRMWARE(FIRMWARE_R200
);
56 MODULE_FIRMWARE(FIRMWARE_R300
);
57 MODULE_FIRMWARE(FIRMWARE_R420
);
58 MODULE_FIRMWARE(FIRMWARE_RS690
);
59 MODULE_FIRMWARE(FIRMWARE_RS600
);
60 MODULE_FIRMWARE(FIRMWARE_R520
);
62 #include "r100_track.h"
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
71 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
)
73 /* TODO: can we do somethings here ? */
74 /* It seems hw only cache one entry so we should discard this
75 * entry otherwise if first GPU GART read hit this entry it
76 * could end up in wrong address. */
79 int r100_pci_gart_init(struct radeon_device
*rdev
)
83 if (rdev
->gart
.table
.ram
.ptr
) {
84 WARN(1, "R100 PCI GART already initialized.\n");
87 /* Initialize common gart structure */
88 r
= radeon_gart_init(rdev
);
91 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
92 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
93 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
94 return radeon_gart_table_ram_alloc(rdev
);
97 int r100_pci_gart_enable(struct radeon_device
*rdev
)
101 /* discard memory request outside of configured range */
102 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
103 WREG32(RADEON_AIC_CNTL
, tmp
);
104 /* set address range for PCI address translate */
105 WREG32(RADEON_AIC_LO_ADDR
, rdev
->mc
.gtt_location
);
106 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
107 WREG32(RADEON_AIC_HI_ADDR
, tmp
);
108 /* Enable bus mastering */
109 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
110 WREG32(RADEON_BUS_CNTL
, tmp
);
111 /* set PCI GART page-table base address */
112 WREG32(RADEON_AIC_PT_BASE
, rdev
->gart
.table_addr
);
113 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_PCIGART_TRANSLATE_EN
;
114 WREG32(RADEON_AIC_CNTL
, tmp
);
115 r100_pci_gart_tlb_flush(rdev
);
116 rdev
->gart
.ready
= true;
120 void r100_pci_gart_disable(struct radeon_device
*rdev
)
124 /* discard memory request outside of configured range */
125 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
126 WREG32(RADEON_AIC_CNTL
, tmp
& ~RADEON_PCIGART_TRANSLATE_EN
);
127 WREG32(RADEON_AIC_LO_ADDR
, 0);
128 WREG32(RADEON_AIC_HI_ADDR
, 0);
131 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
133 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
136 rdev
->gart
.table
.ram
.ptr
[i
] = cpu_to_le32(lower_32_bits(addr
));
140 void r100_pci_gart_fini(struct radeon_device
*rdev
)
142 r100_pci_gart_disable(rdev
);
143 radeon_gart_table_ram_free(rdev
);
144 radeon_gart_fini(rdev
);
147 int r100_irq_set(struct radeon_device
*rdev
)
151 if (rdev
->irq
.sw_int
) {
152 tmp
|= RADEON_SW_INT_ENABLE
;
154 if (rdev
->irq
.crtc_vblank_int
[0]) {
155 tmp
|= RADEON_CRTC_VBLANK_MASK
;
157 if (rdev
->irq
.crtc_vblank_int
[1]) {
158 tmp
|= RADEON_CRTC2_VBLANK_MASK
;
160 WREG32(RADEON_GEN_INT_CNTL
, tmp
);
164 void r100_irq_disable(struct radeon_device
*rdev
)
168 WREG32(R_000040_GEN_INT_CNTL
, 0);
169 /* Wait and acknowledge irq */
171 tmp
= RREG32(R_000044_GEN_INT_STATUS
);
172 WREG32(R_000044_GEN_INT_STATUS
, tmp
);
175 static inline uint32_t r100_irq_ack(struct radeon_device
*rdev
)
177 uint32_t irqs
= RREG32(RADEON_GEN_INT_STATUS
);
178 uint32_t irq_mask
= RADEON_SW_INT_TEST
| RADEON_CRTC_VBLANK_STAT
|
179 RADEON_CRTC2_VBLANK_STAT
;
182 WREG32(RADEON_GEN_INT_STATUS
, irqs
);
184 return irqs
& irq_mask
;
187 int r100_irq_process(struct radeon_device
*rdev
)
191 status
= r100_irq_ack(rdev
);
195 if (rdev
->shutdown
) {
200 if (status
& RADEON_SW_INT_TEST
) {
201 radeon_fence_process(rdev
);
203 /* Vertical blank interrupts */
204 if (status
& RADEON_CRTC_VBLANK_STAT
) {
205 drm_handle_vblank(rdev
->ddev
, 0);
207 if (status
& RADEON_CRTC2_VBLANK_STAT
) {
208 drm_handle_vblank(rdev
->ddev
, 1);
210 status
= r100_irq_ack(rdev
);
215 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
218 return RREG32(RADEON_CRTC_CRNT_FRAME
);
220 return RREG32(RADEON_CRTC2_CRNT_FRAME
);
223 void r100_fence_ring_emit(struct radeon_device
*rdev
,
224 struct radeon_fence
*fence
)
226 /* Who ever call radeon_fence_emit should call ring_lock and ask
227 * for enough space (today caller are ib schedule and buffer move) */
228 /* Wait until IDLE & CLEAN */
229 radeon_ring_write(rdev
, PACKET0(0x1720, 0));
230 radeon_ring_write(rdev
, (1 << 16) | (1 << 17));
231 /* Emit fence sequence & fire IRQ */
232 radeon_ring_write(rdev
, PACKET0(rdev
->fence_drv
.scratch_reg
, 0));
233 radeon_ring_write(rdev
, fence
->seq
);
234 radeon_ring_write(rdev
, PACKET0(RADEON_GEN_INT_STATUS
, 0));
235 radeon_ring_write(rdev
, RADEON_SW_INT_FIRE
);
238 int r100_wb_init(struct radeon_device
*rdev
)
242 if (rdev
->wb
.wb_obj
== NULL
) {
243 r
= radeon_object_create(rdev
, NULL
, RADEON_GPU_PAGE_SIZE
,
245 RADEON_GEM_DOMAIN_GTT
,
246 false, &rdev
->wb
.wb_obj
);
248 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r
);
251 r
= radeon_object_pin(rdev
->wb
.wb_obj
,
252 RADEON_GEM_DOMAIN_GTT
,
255 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r
);
258 r
= radeon_object_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
260 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r
);
264 WREG32(R_000774_SCRATCH_ADDR
, rdev
->wb
.gpu_addr
);
265 WREG32(R_00070C_CP_RB_RPTR_ADDR
,
266 S_00070C_RB_RPTR_ADDR((rdev
->wb
.gpu_addr
+ 1024) >> 2));
267 WREG32(R_000770_SCRATCH_UMSK
, 0xff);
271 void r100_wb_disable(struct radeon_device
*rdev
)
273 WREG32(R_000770_SCRATCH_UMSK
, 0);
276 void r100_wb_fini(struct radeon_device
*rdev
)
278 r100_wb_disable(rdev
);
279 if (rdev
->wb
.wb_obj
) {
280 radeon_object_kunmap(rdev
->wb
.wb_obj
);
281 radeon_object_unpin(rdev
->wb
.wb_obj
);
282 radeon_object_unref(&rdev
->wb
.wb_obj
);
284 rdev
->wb
.wb_obj
= NULL
;
288 int r100_copy_blit(struct radeon_device
*rdev
,
292 struct radeon_fence
*fence
)
295 uint32_t stride_bytes
= PAGE_SIZE
;
297 uint32_t stride_pixels
;
302 /* radeon limited to 16k stride */
303 stride_bytes
&= 0x3fff;
304 /* radeon pitch is /64 */
305 pitch
= stride_bytes
/ 64;
306 stride_pixels
= stride_bytes
/ 4;
307 num_loops
= DIV_ROUND_UP(num_pages
, 8191);
309 /* Ask for enough room for blit + flush + fence */
310 ndw
= 64 + (10 * num_loops
);
311 r
= radeon_ring_lock(rdev
, ndw
);
313 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r
, ndw
);
316 while (num_pages
> 0) {
317 cur_pages
= num_pages
;
318 if (cur_pages
> 8191) {
321 num_pages
-= cur_pages
;
323 /* pages are in Y direction - height
324 page width in X direction - width */
325 radeon_ring_write(rdev
, PACKET3(PACKET3_BITBLT_MULTI
, 8));
326 radeon_ring_write(rdev
,
327 RADEON_GMC_SRC_PITCH_OFFSET_CNTL
|
328 RADEON_GMC_DST_PITCH_OFFSET_CNTL
|
329 RADEON_GMC_SRC_CLIPPING
|
330 RADEON_GMC_DST_CLIPPING
|
331 RADEON_GMC_BRUSH_NONE
|
332 (RADEON_COLOR_FORMAT_ARGB8888
<< 8) |
333 RADEON_GMC_SRC_DATATYPE_COLOR
|
335 RADEON_DP_SRC_SOURCE_MEMORY
|
336 RADEON_GMC_CLR_CMP_CNTL_DIS
|
337 RADEON_GMC_WR_MSK_DIS
);
338 radeon_ring_write(rdev
, (pitch
<< 22) | (src_offset
>> 10));
339 radeon_ring_write(rdev
, (pitch
<< 22) | (dst_offset
>> 10));
340 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
341 radeon_ring_write(rdev
, 0);
342 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
343 radeon_ring_write(rdev
, num_pages
);
344 radeon_ring_write(rdev
, num_pages
);
345 radeon_ring_write(rdev
, cur_pages
| (stride_pixels
<< 16));
347 radeon_ring_write(rdev
, PACKET0(RADEON_DSTCACHE_CTLSTAT
, 0));
348 radeon_ring_write(rdev
, RADEON_RB2D_DC_FLUSH_ALL
);
349 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
350 radeon_ring_write(rdev
,
351 RADEON_WAIT_2D_IDLECLEAN
|
352 RADEON_WAIT_HOST_IDLECLEAN
|
353 RADEON_WAIT_DMA_GUI_IDLE
);
355 r
= radeon_fence_emit(rdev
, fence
);
357 radeon_ring_unlock_commit(rdev
);
361 static int r100_cp_wait_for_idle(struct radeon_device
*rdev
)
366 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
367 tmp
= RREG32(R_000E40_RBBM_STATUS
);
368 if (!G_000E40_CP_CMDSTRM_BUSY(tmp
)) {
376 void r100_ring_start(struct radeon_device
*rdev
)
380 r
= radeon_ring_lock(rdev
, 2);
384 radeon_ring_write(rdev
, PACKET0(RADEON_ISYNC_CNTL
, 0));
385 radeon_ring_write(rdev
,
386 RADEON_ISYNC_ANY2D_IDLE3D
|
387 RADEON_ISYNC_ANY3D_IDLE2D
|
388 RADEON_ISYNC_WAIT_IDLEGUI
|
389 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
390 radeon_ring_unlock_commit(rdev
);
394 /* Load the microcode for the CP */
395 static int r100_cp_init_microcode(struct radeon_device
*rdev
)
397 struct platform_device
*pdev
;
398 const char *fw_name
= NULL
;
403 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
406 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
409 if ((rdev
->family
== CHIP_R100
) || (rdev
->family
== CHIP_RV100
) ||
410 (rdev
->family
== CHIP_RV200
) || (rdev
->family
== CHIP_RS100
) ||
411 (rdev
->family
== CHIP_RS200
)) {
412 DRM_INFO("Loading R100 Microcode\n");
413 fw_name
= FIRMWARE_R100
;
414 } else if ((rdev
->family
== CHIP_R200
) ||
415 (rdev
->family
== CHIP_RV250
) ||
416 (rdev
->family
== CHIP_RV280
) ||
417 (rdev
->family
== CHIP_RS300
)) {
418 DRM_INFO("Loading R200 Microcode\n");
419 fw_name
= FIRMWARE_R200
;
420 } else if ((rdev
->family
== CHIP_R300
) ||
421 (rdev
->family
== CHIP_R350
) ||
422 (rdev
->family
== CHIP_RV350
) ||
423 (rdev
->family
== CHIP_RV380
) ||
424 (rdev
->family
== CHIP_RS400
) ||
425 (rdev
->family
== CHIP_RS480
)) {
426 DRM_INFO("Loading R300 Microcode\n");
427 fw_name
= FIRMWARE_R300
;
428 } else if ((rdev
->family
== CHIP_R420
) ||
429 (rdev
->family
== CHIP_R423
) ||
430 (rdev
->family
== CHIP_RV410
)) {
431 DRM_INFO("Loading R400 Microcode\n");
432 fw_name
= FIRMWARE_R420
;
433 } else if ((rdev
->family
== CHIP_RS690
) ||
434 (rdev
->family
== CHIP_RS740
)) {
435 DRM_INFO("Loading RS690/RS740 Microcode\n");
436 fw_name
= FIRMWARE_RS690
;
437 } else if (rdev
->family
== CHIP_RS600
) {
438 DRM_INFO("Loading RS600 Microcode\n");
439 fw_name
= FIRMWARE_RS600
;
440 } else if ((rdev
->family
== CHIP_RV515
) ||
441 (rdev
->family
== CHIP_R520
) ||
442 (rdev
->family
== CHIP_RV530
) ||
443 (rdev
->family
== CHIP_R580
) ||
444 (rdev
->family
== CHIP_RV560
) ||
445 (rdev
->family
== CHIP_RV570
)) {
446 DRM_INFO("Loading R500 Microcode\n");
447 fw_name
= FIRMWARE_R520
;
450 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
451 platform_device_unregister(pdev
);
453 printk(KERN_ERR
"radeon_cp: Failed to load firmware \"%s\"\n",
455 } else if (rdev
->me_fw
->size
% 8) {
457 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
458 rdev
->me_fw
->size
, fw_name
);
460 release_firmware(rdev
->me_fw
);
466 static void r100_cp_load_microcode(struct radeon_device
*rdev
)
468 const __be32
*fw_data
;
471 if (r100_gui_wait_for_idle(rdev
)) {
472 printk(KERN_WARNING
"Failed to wait GUI idle while "
473 "programming pipes. Bad things might happen.\n");
477 size
= rdev
->me_fw
->size
/ 4;
478 fw_data
= (const __be32
*)&rdev
->me_fw
->data
[0];
479 WREG32(RADEON_CP_ME_RAM_ADDR
, 0);
480 for (i
= 0; i
< size
; i
+= 2) {
481 WREG32(RADEON_CP_ME_RAM_DATAH
,
482 be32_to_cpup(&fw_data
[i
]));
483 WREG32(RADEON_CP_ME_RAM_DATAL
,
484 be32_to_cpup(&fw_data
[i
+ 1]));
489 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
)
494 unsigned pre_write_timer
;
495 unsigned pre_write_limit
;
496 unsigned indirect2_start
;
497 unsigned indirect1_start
;
501 if (r100_debugfs_cp_init(rdev
)) {
502 DRM_ERROR("Failed to register debugfs file for CP !\n");
505 tmp
= RREG32(RADEON_CP_CSQ_STAT
);
506 if ((tmp
& (1 << 31))) {
507 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp
);
508 WREG32(RADEON_CP_CSQ_MODE
, 0);
509 WREG32(RADEON_CP_CSQ_CNTL
, 0);
510 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_CP
);
511 tmp
= RREG32(RADEON_RBBM_SOFT_RESET
);
513 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
514 tmp
= RREG32(RADEON_RBBM_SOFT_RESET
);
516 tmp
= RREG32(RADEON_CP_CSQ_STAT
);
517 if ((tmp
& (1 << 31))) {
518 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp
);
521 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp
);
525 r
= r100_cp_init_microcode(rdev
);
527 DRM_ERROR("Failed to load firmware!\n");
532 /* Align ring size */
533 rb_bufsz
= drm_order(ring_size
/ 8);
534 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
535 r100_cp_load_microcode(rdev
);
536 r
= radeon_ring_init(rdev
, ring_size
);
540 /* Each time the cp read 1024 bytes (16 dword/quadword) update
541 * the rptr copy in system ram */
543 /* cp will read 128bytes at a time (4 dwords) */
545 rdev
->cp
.align_mask
= 16 - 1;
546 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
547 pre_write_timer
= 64;
548 /* Force CP_RB_WPTR write if written more than one time before the
552 /* Setup the cp cache like this (cache size is 96 dwords) :
556 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
557 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
558 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
559 * Idea being that most of the gpu cmd will be through indirect1 buffer
560 * so it gets the bigger cache.
562 indirect2_start
= 80;
563 indirect1_start
= 16;
565 WREG32(0x718, pre_write_timer
| (pre_write_limit
<< 28));
566 WREG32(RADEON_CP_RB_CNTL
,
568 RADEON_BUF_SWAP_32BIT
|
570 REG_SET(RADEON_RB_BUFSZ
, rb_bufsz
) |
571 REG_SET(RADEON_RB_BLKSZ
, rb_blksz
) |
572 REG_SET(RADEON_MAX_FETCH
, max_fetch
) |
573 RADEON_RB_NO_UPDATE
);
574 /* Set ring address */
575 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev
->cp
.gpu_addr
);
576 WREG32(RADEON_CP_RB_BASE
, rdev
->cp
.gpu_addr
);
577 /* Force read & write ptr to 0 */
578 tmp
= RREG32(RADEON_CP_RB_CNTL
);
579 WREG32(RADEON_CP_RB_CNTL
, tmp
| RADEON_RB_RPTR_WR_ENA
);
580 WREG32(RADEON_CP_RB_RPTR_WR
, 0);
581 WREG32(RADEON_CP_RB_WPTR
, 0);
582 WREG32(RADEON_CP_RB_CNTL
, tmp
);
584 rdev
->cp
.rptr
= RREG32(RADEON_CP_RB_RPTR
);
585 rdev
->cp
.wptr
= RREG32(RADEON_CP_RB_WPTR
);
586 /* Set cp mode to bus mastering & enable cp*/
587 WREG32(RADEON_CP_CSQ_MODE
,
588 REG_SET(RADEON_INDIRECT2_START
, indirect2_start
) |
589 REG_SET(RADEON_INDIRECT1_START
, indirect1_start
));
591 WREG32(0x744, 0x00004D4D);
592 WREG32(RADEON_CP_CSQ_CNTL
, RADEON_CSQ_PRIBM_INDBM
);
593 radeon_ring_start(rdev
);
594 r
= radeon_ring_test(rdev
);
596 DRM_ERROR("radeon: cp isn't working (%d).\n", r
);
599 rdev
->cp
.ready
= true;
603 void r100_cp_fini(struct radeon_device
*rdev
)
605 if (r100_cp_wait_for_idle(rdev
)) {
606 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
609 r100_cp_disable(rdev
);
610 radeon_ring_fini(rdev
);
611 DRM_INFO("radeon: cp finalized\n");
614 void r100_cp_disable(struct radeon_device
*rdev
)
617 rdev
->cp
.ready
= false;
618 WREG32(RADEON_CP_CSQ_MODE
, 0);
619 WREG32(RADEON_CP_CSQ_CNTL
, 0);
620 if (r100_gui_wait_for_idle(rdev
)) {
621 printk(KERN_WARNING
"Failed to wait GUI idle while "
622 "programming pipes. Bad things might happen.\n");
626 int r100_cp_reset(struct radeon_device
*rdev
)
632 reinit_cp
= rdev
->cp
.ready
;
633 rdev
->cp
.ready
= false;
634 WREG32(RADEON_CP_CSQ_MODE
, 0);
635 WREG32(RADEON_CP_CSQ_CNTL
, 0);
636 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_CP
);
637 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
639 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
640 /* Wait to prevent race in RBBM_STATUS */
642 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
643 tmp
= RREG32(RADEON_RBBM_STATUS
);
644 if (!(tmp
& (1 << 16))) {
645 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
648 return r100_cp_init(rdev
, rdev
->cp
.ring_size
);
654 tmp
= RREG32(RADEON_RBBM_STATUS
);
655 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp
);
659 void r100_cp_commit(struct radeon_device
*rdev
)
661 WREG32(RADEON_CP_RB_WPTR
, rdev
->cp
.wptr
);
662 (void)RREG32(RADEON_CP_RB_WPTR
);
669 int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
670 struct radeon_cs_packet
*pkt
,
671 const unsigned *auth
, unsigned n
,
672 radeon_packet0_check_t check
)
681 /* Check that register fall into register range
682 * determined by the number of entry (n) in the
683 * safe register bitmap.
685 if (pkt
->one_reg_wr
) {
686 if ((reg
>> 7) > n
) {
690 if (((reg
+ (pkt
->count
<< 2)) >> 7) > n
) {
694 for (i
= 0; i
<= pkt
->count
; i
++, idx
++) {
696 m
= 1 << ((reg
>> 2) & 31);
698 r
= check(p
, pkt
, idx
, reg
);
703 if (pkt
->one_reg_wr
) {
704 if (!(auth
[j
] & m
)) {
714 void r100_cs_dump_packet(struct radeon_cs_parser
*p
,
715 struct radeon_cs_packet
*pkt
)
717 volatile uint32_t *ib
;
723 for (i
= 0; i
<= (pkt
->count
+ 1); i
++, idx
++) {
724 DRM_INFO("ib[%d]=0x%08X\n", idx
, ib
[idx
]);
729 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
730 * @parser: parser structure holding parsing context.
731 * @pkt: where to store packet informations
733 * Assume that chunk_ib_index is properly set. Will return -EINVAL
734 * if packet is bigger than remaining ib size. or if packets is unknown.
736 int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
737 struct radeon_cs_packet
*pkt
,
740 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
743 if (idx
>= ib_chunk
->length_dw
) {
744 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
745 idx
, ib_chunk
->length_dw
);
748 header
= radeon_get_ib_value(p
, idx
);
750 pkt
->type
= CP_PACKET_GET_TYPE(header
);
751 pkt
->count
= CP_PACKET_GET_COUNT(header
);
754 pkt
->reg
= CP_PACKET0_GET_REG(header
);
755 pkt
->one_reg_wr
= CP_PACKET0_GET_ONE_REG_WR(header
);
758 pkt
->opcode
= CP_PACKET3_GET_OPCODE(header
);
764 DRM_ERROR("Unknown packet type %d at %d !\n", pkt
->type
, idx
);
767 if ((pkt
->count
+ 1 + pkt
->idx
) >= ib_chunk
->length_dw
) {
768 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
769 pkt
->idx
, pkt
->type
, pkt
->count
, ib_chunk
->length_dw
);
776 * r100_cs_packet_next_vline() - parse userspace VLINE packet
777 * @parser: parser structure holding parsing context.
779 * Userspace sends a special sequence for VLINE waits.
780 * PACKET0 - VLINE_START_END + value
781 * PACKET0 - WAIT_UNTIL +_value
782 * RELOC (P3) - crtc_id in reloc.
784 * This function parses this and relocates the VLINE START END
785 * and WAIT UNTIL packets to the correct crtc.
786 * It also detects a switched off crtc and nulls out the
789 int r100_cs_packet_parse_vline(struct radeon_cs_parser
*p
)
791 struct drm_mode_object
*obj
;
792 struct drm_crtc
*crtc
;
793 struct radeon_crtc
*radeon_crtc
;
794 struct radeon_cs_packet p3reloc
, waitreloc
;
797 uint32_t header
, h_idx
, reg
;
798 volatile uint32_t *ib
;
802 /* parse the wait until */
803 r
= r100_cs_packet_parse(p
, &waitreloc
, p
->idx
);
807 /* check its a wait until and only 1 count */
808 if (waitreloc
.reg
!= RADEON_WAIT_UNTIL
||
809 waitreloc
.count
!= 0) {
810 DRM_ERROR("vline wait had illegal wait until segment\n");
815 if (radeon_get_ib_value(p
, waitreloc
.idx
+ 1) != RADEON_WAIT_CRTC_VLINE
) {
816 DRM_ERROR("vline wait had illegal wait until\n");
821 /* jump over the NOP */
822 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
+ waitreloc
.count
+ 2);
827 p
->idx
+= waitreloc
.count
+ 2;
828 p
->idx
+= p3reloc
.count
+ 2;
830 header
= radeon_get_ib_value(p
, h_idx
);
831 crtc_id
= radeon_get_ib_value(p
, h_idx
+ 5);
832 reg
= CP_PACKET0_GET_REG(header
);
833 mutex_lock(&p
->rdev
->ddev
->mode_config
.mutex
);
834 obj
= drm_mode_object_find(p
->rdev
->ddev
, crtc_id
, DRM_MODE_OBJECT_CRTC
);
836 DRM_ERROR("cannot find crtc %d\n", crtc_id
);
840 crtc
= obj_to_crtc(obj
);
841 radeon_crtc
= to_radeon_crtc(crtc
);
842 crtc_id
= radeon_crtc
->crtc_id
;
844 if (!crtc
->enabled
) {
845 /* if the CRTC isn't enabled - we need to nop out the wait until */
846 ib
[h_idx
+ 2] = PACKET2(0);
847 ib
[h_idx
+ 3] = PACKET2(0);
848 } else if (crtc_id
== 1) {
850 case AVIVO_D1MODE_VLINE_START_END
:
851 header
&= ~R300_CP_PACKET0_REG_MASK
;
852 header
|= AVIVO_D2MODE_VLINE_START_END
>> 2;
854 case RADEON_CRTC_GUI_TRIG_VLINE
:
855 header
&= ~R300_CP_PACKET0_REG_MASK
;
856 header
|= RADEON_CRTC2_GUI_TRIG_VLINE
>> 2;
859 DRM_ERROR("unknown crtc reloc\n");
864 ib
[h_idx
+ 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1
;
867 mutex_unlock(&p
->rdev
->ddev
->mode_config
.mutex
);
872 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
873 * @parser: parser structure holding parsing context.
874 * @data: pointer to relocation data
875 * @offset_start: starting offset
876 * @offset_mask: offset mask (to align start offset on)
877 * @reloc: reloc informations
879 * Check next packet is relocation packet3, do bo validation and compute
880 * GPU offset using the provided start.
882 int r100_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
883 struct radeon_cs_reloc
**cs_reloc
)
885 struct radeon_cs_chunk
*relocs_chunk
;
886 struct radeon_cs_packet p3reloc
;
890 if (p
->chunk_relocs_idx
== -1) {
891 DRM_ERROR("No relocation chunk !\n");
895 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
896 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
);
900 p
->idx
+= p3reloc
.count
+ 2;
901 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
902 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
904 r100_cs_dump_packet(p
, &p3reloc
);
907 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
908 if (idx
>= relocs_chunk
->length_dw
) {
909 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
910 idx
, relocs_chunk
->length_dw
);
911 r100_cs_dump_packet(p
, &p3reloc
);
914 /* FIXME: we assume reloc size is 4 dwords */
915 *cs_reloc
= p
->relocs_ptr
[(idx
/ 4)];
919 static int r100_get_vtx_size(uint32_t vtx_fmt
)
923 /* ordered according to bits in spec */
924 if (vtx_fmt
& RADEON_SE_VTX_FMT_W0
)
926 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPCOLOR
)
928 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPALPHA
)
930 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKCOLOR
)
932 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPSPEC
)
934 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPFOG
)
936 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKSPEC
)
938 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST0
)
940 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST1
)
942 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q1
)
944 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST2
)
946 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q2
)
948 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST3
)
950 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q3
)
952 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q0
)
955 if (vtx_fmt
& (0x7 << 15))
956 vtx_size
+= (vtx_fmt
>> 15) & 0x7;
957 if (vtx_fmt
& RADEON_SE_VTX_FMT_N0
)
959 if (vtx_fmt
& RADEON_SE_VTX_FMT_XY1
)
961 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z1
)
963 if (vtx_fmt
& RADEON_SE_VTX_FMT_W1
)
965 if (vtx_fmt
& RADEON_SE_VTX_FMT_N1
)
967 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z
)
972 static int r100_packet0_check(struct radeon_cs_parser
*p
,
973 struct radeon_cs_packet
*pkt
,
974 unsigned idx
, unsigned reg
)
976 struct radeon_cs_reloc
*reloc
;
977 struct r100_cs_track
*track
;
978 volatile uint32_t *ib
;
986 track
= (struct r100_cs_track
*)p
->track
;
988 idx_value
= radeon_get_ib_value(p
, idx
);
991 case RADEON_CRTC_GUI_TRIG_VLINE
:
992 r
= r100_cs_packet_parse_vline(p
);
994 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
996 r100_cs_dump_packet(p
, pkt
);
1000 /* FIXME: only allow PACKET3 blit? easier to check for out of
1002 case RADEON_DST_PITCH_OFFSET
:
1003 case RADEON_SRC_PITCH_OFFSET
:
1004 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
1008 case RADEON_RB3D_DEPTHOFFSET
:
1009 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1011 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1013 r100_cs_dump_packet(p
, pkt
);
1016 track
->zb
.robj
= reloc
->robj
;
1017 track
->zb
.offset
= idx_value
;
1018 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1020 case RADEON_RB3D_COLOROFFSET
:
1021 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1023 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1025 r100_cs_dump_packet(p
, pkt
);
1028 track
->cb
[0].robj
= reloc
->robj
;
1029 track
->cb
[0].offset
= idx_value
;
1030 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1032 case RADEON_PP_TXOFFSET_0
:
1033 case RADEON_PP_TXOFFSET_1
:
1034 case RADEON_PP_TXOFFSET_2
:
1035 i
= (reg
- RADEON_PP_TXOFFSET_0
) / 24;
1036 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1038 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1040 r100_cs_dump_packet(p
, pkt
);
1043 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1044 track
->textures
[i
].robj
= reloc
->robj
;
1046 case RADEON_PP_CUBIC_OFFSET_T0_0
:
1047 case RADEON_PP_CUBIC_OFFSET_T0_1
:
1048 case RADEON_PP_CUBIC_OFFSET_T0_2
:
1049 case RADEON_PP_CUBIC_OFFSET_T0_3
:
1050 case RADEON_PP_CUBIC_OFFSET_T0_4
:
1051 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T0_0
) / 4;
1052 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1054 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1056 r100_cs_dump_packet(p
, pkt
);
1059 track
->textures
[0].cube_info
[i
].offset
= idx_value
;
1060 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1061 track
->textures
[0].cube_info
[i
].robj
= reloc
->robj
;
1063 case RADEON_PP_CUBIC_OFFSET_T1_0
:
1064 case RADEON_PP_CUBIC_OFFSET_T1_1
:
1065 case RADEON_PP_CUBIC_OFFSET_T1_2
:
1066 case RADEON_PP_CUBIC_OFFSET_T1_3
:
1067 case RADEON_PP_CUBIC_OFFSET_T1_4
:
1068 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T1_0
) / 4;
1069 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1071 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1073 r100_cs_dump_packet(p
, pkt
);
1076 track
->textures
[1].cube_info
[i
].offset
= idx_value
;
1077 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1078 track
->textures
[1].cube_info
[i
].robj
= reloc
->robj
;
1080 case RADEON_PP_CUBIC_OFFSET_T2_0
:
1081 case RADEON_PP_CUBIC_OFFSET_T2_1
:
1082 case RADEON_PP_CUBIC_OFFSET_T2_2
:
1083 case RADEON_PP_CUBIC_OFFSET_T2_3
:
1084 case RADEON_PP_CUBIC_OFFSET_T2_4
:
1085 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T2_0
) / 4;
1086 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1088 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1090 r100_cs_dump_packet(p
, pkt
);
1093 track
->textures
[2].cube_info
[i
].offset
= idx_value
;
1094 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1095 track
->textures
[2].cube_info
[i
].robj
= reloc
->robj
;
1097 case RADEON_RE_WIDTH_HEIGHT
:
1098 track
->maxy
= ((idx_value
>> 16) & 0x7FF);
1100 case RADEON_RB3D_COLORPITCH
:
1101 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1103 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1105 r100_cs_dump_packet(p
, pkt
);
1109 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
1110 tile_flags
|= RADEON_COLOR_TILE_ENABLE
;
1111 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
1112 tile_flags
|= RADEON_COLOR_MICROTILE_ENABLE
;
1114 tmp
= idx_value
& ~(0x7 << 16);
1118 track
->cb
[0].pitch
= idx_value
& RADEON_COLORPITCH_MASK
;
1120 case RADEON_RB3D_DEPTHPITCH
:
1121 track
->zb
.pitch
= idx_value
& RADEON_DEPTHPITCH_MASK
;
1123 case RADEON_RB3D_CNTL
:
1124 switch ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f) {
1130 track
->cb
[0].cpp
= 1;
1135 track
->cb
[0].cpp
= 2;
1138 track
->cb
[0].cpp
= 4;
1141 DRM_ERROR("Invalid color buffer format (%d) !\n",
1142 ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f));
1145 track
->z_enabled
= !!(idx_value
& RADEON_Z_ENABLE
);
1147 case RADEON_RB3D_ZSTENCILCNTL
:
1148 switch (idx_value
& 0xf) {
1164 case RADEON_RB3D_ZPASS_ADDR
:
1165 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1167 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1169 r100_cs_dump_packet(p
, pkt
);
1172 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1174 case RADEON_PP_CNTL
:
1176 uint32_t temp
= idx_value
>> 4;
1177 for (i
= 0; i
< track
->num_texture
; i
++)
1178 track
->textures
[i
].enabled
= !!(temp
& (1 << i
));
1181 case RADEON_SE_VF_CNTL
:
1182 track
->vap_vf_cntl
= idx_value
;
1184 case RADEON_SE_VTX_FMT
:
1185 track
->vtx_size
= r100_get_vtx_size(idx_value
);
1187 case RADEON_PP_TEX_SIZE_0
:
1188 case RADEON_PP_TEX_SIZE_1
:
1189 case RADEON_PP_TEX_SIZE_2
:
1190 i
= (reg
- RADEON_PP_TEX_SIZE_0
) / 8;
1191 track
->textures
[i
].width
= (idx_value
& RADEON_TEX_USIZE_MASK
) + 1;
1192 track
->textures
[i
].height
= ((idx_value
& RADEON_TEX_VSIZE_MASK
) >> RADEON_TEX_VSIZE_SHIFT
) + 1;
1194 case RADEON_PP_TEX_PITCH_0
:
1195 case RADEON_PP_TEX_PITCH_1
:
1196 case RADEON_PP_TEX_PITCH_2
:
1197 i
= (reg
- RADEON_PP_TEX_PITCH_0
) / 8;
1198 track
->textures
[i
].pitch
= idx_value
+ 32;
1200 case RADEON_PP_TXFILTER_0
:
1201 case RADEON_PP_TXFILTER_1
:
1202 case RADEON_PP_TXFILTER_2
:
1203 i
= (reg
- RADEON_PP_TXFILTER_0
) / 24;
1204 track
->textures
[i
].num_levels
= ((idx_value
& RADEON_MAX_MIP_LEVEL_MASK
)
1205 >> RADEON_MAX_MIP_LEVEL_SHIFT
);
1206 tmp
= (idx_value
>> 23) & 0x7;
1207 if (tmp
== 2 || tmp
== 6)
1208 track
->textures
[i
].roundup_w
= false;
1209 tmp
= (idx_value
>> 27) & 0x7;
1210 if (tmp
== 2 || tmp
== 6)
1211 track
->textures
[i
].roundup_h
= false;
1213 case RADEON_PP_TXFORMAT_0
:
1214 case RADEON_PP_TXFORMAT_1
:
1215 case RADEON_PP_TXFORMAT_2
:
1216 i
= (reg
- RADEON_PP_TXFORMAT_0
) / 24;
1217 if (idx_value
& RADEON_TXFORMAT_NON_POWER2
) {
1218 track
->textures
[i
].use_pitch
= 1;
1220 track
->textures
[i
].use_pitch
= 0;
1221 track
->textures
[i
].width
= 1 << ((idx_value
>> RADEON_TXFORMAT_WIDTH_SHIFT
) & RADEON_TXFORMAT_WIDTH_MASK
);
1222 track
->textures
[i
].height
= 1 << ((idx_value
>> RADEON_TXFORMAT_HEIGHT_SHIFT
) & RADEON_TXFORMAT_HEIGHT_MASK
);
1224 if (idx_value
& RADEON_TXFORMAT_CUBIC_MAP_ENABLE
)
1225 track
->textures
[i
].tex_coord_type
= 2;
1226 switch ((idx_value
& RADEON_TXFORMAT_FORMAT_MASK
)) {
1227 case RADEON_TXFORMAT_I8
:
1228 case RADEON_TXFORMAT_RGB332
:
1229 case RADEON_TXFORMAT_Y8
:
1230 track
->textures
[i
].cpp
= 1;
1232 case RADEON_TXFORMAT_AI88
:
1233 case RADEON_TXFORMAT_ARGB1555
:
1234 case RADEON_TXFORMAT_RGB565
:
1235 case RADEON_TXFORMAT_ARGB4444
:
1236 case RADEON_TXFORMAT_VYUY422
:
1237 case RADEON_TXFORMAT_YVYU422
:
1238 case RADEON_TXFORMAT_DXT1
:
1239 case RADEON_TXFORMAT_SHADOW16
:
1240 case RADEON_TXFORMAT_LDUDV655
:
1241 case RADEON_TXFORMAT_DUDV88
:
1242 track
->textures
[i
].cpp
= 2;
1244 case RADEON_TXFORMAT_ARGB8888
:
1245 case RADEON_TXFORMAT_RGBA8888
:
1246 case RADEON_TXFORMAT_DXT23
:
1247 case RADEON_TXFORMAT_DXT45
:
1248 case RADEON_TXFORMAT_SHADOW32
:
1249 case RADEON_TXFORMAT_LDUDUV8888
:
1250 track
->textures
[i
].cpp
= 4;
1253 track
->textures
[i
].cube_info
[4].width
= 1 << ((idx_value
>> 16) & 0xf);
1254 track
->textures
[i
].cube_info
[4].height
= 1 << ((idx_value
>> 20) & 0xf);
1256 case RADEON_PP_CUBIC_FACES_0
:
1257 case RADEON_PP_CUBIC_FACES_1
:
1258 case RADEON_PP_CUBIC_FACES_2
:
1260 i
= (reg
- RADEON_PP_CUBIC_FACES_0
) / 4;
1261 for (face
= 0; face
< 4; face
++) {
1262 track
->textures
[i
].cube_info
[face
].width
= 1 << ((tmp
>> (face
* 8)) & 0xf);
1263 track
->textures
[i
].cube_info
[face
].height
= 1 << ((tmp
>> ((face
* 8) + 4)) & 0xf);
1267 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
1274 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
1275 struct radeon_cs_packet
*pkt
,
1276 struct radeon_object
*robj
)
1281 value
= radeon_get_ib_value(p
, idx
+ 2);
1282 if ((value
+ 1) > radeon_object_size(robj
)) {
1283 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1284 "(need %u have %lu) !\n",
1286 radeon_object_size(robj
));
1292 static int r100_packet3_check(struct radeon_cs_parser
*p
,
1293 struct radeon_cs_packet
*pkt
)
1295 struct radeon_cs_reloc
*reloc
;
1296 struct r100_cs_track
*track
;
1298 volatile uint32_t *ib
;
1303 track
= (struct r100_cs_track
*)p
->track
;
1304 switch (pkt
->opcode
) {
1305 case PACKET3_3D_LOAD_VBPNTR
:
1306 r
= r100_packet3_load_vbpntr(p
, pkt
, idx
);
1310 case PACKET3_INDX_BUFFER
:
1311 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1313 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1314 r100_cs_dump_packet(p
, pkt
);
1317 ib
[idx
+1] = radeon_get_ib_value(p
, idx
+1) + ((u32
)reloc
->lobj
.gpu_offset
);
1318 r
= r100_cs_track_check_pkt3_indx_buffer(p
, pkt
, reloc
->robj
);
1324 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1325 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1327 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1328 r100_cs_dump_packet(p
, pkt
);
1331 ib
[idx
] = radeon_get_ib_value(p
, idx
) + ((u32
)reloc
->lobj
.gpu_offset
);
1332 track
->num_arrays
= 1;
1333 track
->vtx_size
= r100_get_vtx_size(radeon_get_ib_value(p
, idx
+ 2));
1335 track
->arrays
[0].robj
= reloc
->robj
;
1336 track
->arrays
[0].esize
= track
->vtx_size
;
1338 track
->max_indx
= radeon_get_ib_value(p
, idx
+1);
1340 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+3);
1341 track
->immd_dwords
= pkt
->count
- 1;
1342 r
= r100_cs_track_check(p
->rdev
, track
);
1346 case PACKET3_3D_DRAW_IMMD
:
1347 if (((radeon_get_ib_value(p
, idx
+ 1) >> 4) & 0x3) != 3) {
1348 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1351 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1352 track
->immd_dwords
= pkt
->count
- 1;
1353 r
= r100_cs_track_check(p
->rdev
, track
);
1357 /* triggers drawing using in-packet vertex data */
1358 case PACKET3_3D_DRAW_IMMD_2
:
1359 if (((radeon_get_ib_value(p
, idx
) >> 4) & 0x3) != 3) {
1360 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1363 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1364 track
->immd_dwords
= pkt
->count
;
1365 r
= r100_cs_track_check(p
->rdev
, track
);
1369 /* triggers drawing using in-packet vertex data */
1370 case PACKET3_3D_DRAW_VBUF_2
:
1371 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1372 r
= r100_cs_track_check(p
->rdev
, track
);
1376 /* triggers drawing of vertex buffers setup elsewhere */
1377 case PACKET3_3D_DRAW_INDX_2
:
1378 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1379 r
= r100_cs_track_check(p
->rdev
, track
);
1383 /* triggers drawing using indices to vertex buffer */
1384 case PACKET3_3D_DRAW_VBUF
:
1385 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1386 r
= r100_cs_track_check(p
->rdev
, track
);
1390 /* triggers drawing of vertex buffers setup elsewhere */
1391 case PACKET3_3D_DRAW_INDX
:
1392 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1393 r
= r100_cs_track_check(p
->rdev
, track
);
1397 /* triggers drawing using indices to vertex buffer */
1401 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1407 int r100_cs_parse(struct radeon_cs_parser
*p
)
1409 struct radeon_cs_packet pkt
;
1410 struct r100_cs_track
*track
;
1413 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1414 r100_cs_track_clear(p
->rdev
, track
);
1417 r
= r100_cs_packet_parse(p
, &pkt
, p
->idx
);
1421 p
->idx
+= pkt
.count
+ 2;
1424 if (p
->rdev
->family
>= CHIP_R200
)
1425 r
= r100_cs_parse_packet0(p
, &pkt
,
1426 p
->rdev
->config
.r100
.reg_safe_bm
,
1427 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1428 &r200_packet0_check
);
1430 r
= r100_cs_parse_packet0(p
, &pkt
,
1431 p
->rdev
->config
.r100
.reg_safe_bm
,
1432 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1433 &r100_packet0_check
);
1438 r
= r100_packet3_check(p
, &pkt
);
1441 DRM_ERROR("Unknown packet type %d !\n",
1448 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1454 * Global GPU functions
1456 void r100_errata(struct radeon_device
*rdev
)
1458 rdev
->pll_errata
= 0;
1460 if (rdev
->family
== CHIP_RV200
|| rdev
->family
== CHIP_RS200
) {
1461 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DUMMYREADS
;
1464 if (rdev
->family
== CHIP_RV100
||
1465 rdev
->family
== CHIP_RS100
||
1466 rdev
->family
== CHIP_RS200
) {
1467 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DELAY
;
1471 /* Wait for vertical sync on primary CRTC */
1472 void r100_gpu_wait_for_vsync(struct radeon_device
*rdev
)
1474 uint32_t crtc_gen_cntl
, tmp
;
1477 crtc_gen_cntl
= RREG32(RADEON_CRTC_GEN_CNTL
);
1478 if ((crtc_gen_cntl
& RADEON_CRTC_DISP_REQ_EN_B
) ||
1479 !(crtc_gen_cntl
& RADEON_CRTC_EN
)) {
1482 /* Clear the CRTC_VBLANK_SAVE bit */
1483 WREG32(RADEON_CRTC_STATUS
, RADEON_CRTC_VBLANK_SAVE_CLEAR
);
1484 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1485 tmp
= RREG32(RADEON_CRTC_STATUS
);
1486 if (tmp
& RADEON_CRTC_VBLANK_SAVE
) {
1493 /* Wait for vertical sync on secondary CRTC */
1494 void r100_gpu_wait_for_vsync2(struct radeon_device
*rdev
)
1496 uint32_t crtc2_gen_cntl
, tmp
;
1499 crtc2_gen_cntl
= RREG32(RADEON_CRTC2_GEN_CNTL
);
1500 if ((crtc2_gen_cntl
& RADEON_CRTC2_DISP_REQ_EN_B
) ||
1501 !(crtc2_gen_cntl
& RADEON_CRTC2_EN
))
1504 /* Clear the CRTC_VBLANK_SAVE bit */
1505 WREG32(RADEON_CRTC2_STATUS
, RADEON_CRTC2_VBLANK_SAVE_CLEAR
);
1506 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1507 tmp
= RREG32(RADEON_CRTC2_STATUS
);
1508 if (tmp
& RADEON_CRTC2_VBLANK_SAVE
) {
1515 int r100_rbbm_fifo_wait_for_entry(struct radeon_device
*rdev
, unsigned n
)
1520 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1521 tmp
= RREG32(RADEON_RBBM_STATUS
) & RADEON_RBBM_FIFOCNT_MASK
;
1530 int r100_gui_wait_for_idle(struct radeon_device
*rdev
)
1535 if (r100_rbbm_fifo_wait_for_entry(rdev
, 64)) {
1536 printk(KERN_WARNING
"radeon: wait for empty RBBM fifo failed !"
1537 " Bad things might happen.\n");
1539 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1540 tmp
= RREG32(RADEON_RBBM_STATUS
);
1541 if (!(tmp
& (1 << 31))) {
1549 int r100_mc_wait_for_idle(struct radeon_device
*rdev
)
1554 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1555 /* read MC_STATUS */
1556 tmp
= RREG32(0x0150);
1557 if (tmp
& (1 << 2)) {
1565 void r100_gpu_init(struct radeon_device
*rdev
)
1567 /* TODO: anythings to do here ? pipes ? */
1568 r100_hdp_reset(rdev
);
1571 void r100_hdp_reset(struct radeon_device
*rdev
)
1575 tmp
= RREG32(RADEON_HOST_PATH_CNTL
) & RADEON_HDP_APER_CNTL
;
1577 WREG32(RADEON_HOST_PATH_CNTL
, tmp
| RADEON_HDP_SOFT_RESET
| RADEON_HDP_READ_BUFFER_INVALIDATE
);
1578 (void)RREG32(RADEON_HOST_PATH_CNTL
);
1580 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
1581 WREG32(RADEON_HOST_PATH_CNTL
, tmp
);
1582 (void)RREG32(RADEON_HOST_PATH_CNTL
);
1585 int r100_rb2d_reset(struct radeon_device
*rdev
)
1590 WREG32(RADEON_RBBM_SOFT_RESET
, RADEON_SOFT_RESET_E2
);
1591 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
1593 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
1594 /* Wait to prevent race in RBBM_STATUS */
1596 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1597 tmp
= RREG32(RADEON_RBBM_STATUS
);
1598 if (!(tmp
& (1 << 26))) {
1599 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1605 tmp
= RREG32(RADEON_RBBM_STATUS
);
1606 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp
);
1610 int r100_gpu_reset(struct radeon_device
*rdev
)
1614 /* reset order likely matter */
1615 status
= RREG32(RADEON_RBBM_STATUS
);
1617 r100_hdp_reset(rdev
);
1619 if (status
& ((1 << 17) | (1 << 18) | (1 << 27))) {
1620 r100_rb2d_reset(rdev
);
1622 /* TODO: reset 3D engine */
1624 status
= RREG32(RADEON_RBBM_STATUS
);
1625 if (status
& (1 << 16)) {
1626 r100_cp_reset(rdev
);
1628 /* Check if GPU is idle */
1629 status
= RREG32(RADEON_RBBM_STATUS
);
1630 if (status
& (1 << 31)) {
1631 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status
);
1634 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status
);
1642 static void r100_vram_get_type(struct radeon_device
*rdev
)
1646 rdev
->mc
.vram_is_ddr
= false;
1647 if (rdev
->flags
& RADEON_IS_IGP
)
1648 rdev
->mc
.vram_is_ddr
= true;
1649 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG
) & RADEON_MEM_CFG_TYPE_DDR
)
1650 rdev
->mc
.vram_is_ddr
= true;
1651 if ((rdev
->family
== CHIP_RV100
) ||
1652 (rdev
->family
== CHIP_RS100
) ||
1653 (rdev
->family
== CHIP_RS200
)) {
1654 tmp
= RREG32(RADEON_MEM_CNTL
);
1655 if (tmp
& RV100_HALF_MODE
) {
1656 rdev
->mc
.vram_width
= 32;
1658 rdev
->mc
.vram_width
= 64;
1660 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1661 rdev
->mc
.vram_width
/= 4;
1662 rdev
->mc
.vram_is_ddr
= true;
1664 } else if (rdev
->family
<= CHIP_RV280
) {
1665 tmp
= RREG32(RADEON_MEM_CNTL
);
1666 if (tmp
& RADEON_MEM_NUM_CHANNELS_MASK
) {
1667 rdev
->mc
.vram_width
= 128;
1669 rdev
->mc
.vram_width
= 64;
1673 rdev
->mc
.vram_width
= 128;
1677 static u32
r100_get_accessible_vram(struct radeon_device
*rdev
)
1682 aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
1684 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1685 * that is has the 2nd generation multifunction PCI interface
1687 if (rdev
->family
== CHIP_RV280
||
1688 rdev
->family
>= CHIP_RV350
) {
1689 WREG32_P(RADEON_HOST_PATH_CNTL
, RADEON_HDP_APER_CNTL
,
1690 ~RADEON_HDP_APER_CNTL
);
1691 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1692 return aper_size
* 2;
1695 /* Older cards have all sorts of funny issues to deal with. First
1696 * check if it's a multifunction card by reading the PCI config
1697 * header type... Limit those to one aperture size
1699 pci_read_config_byte(rdev
->pdev
, 0xe, &byte
);
1701 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1702 DRM_INFO("Limiting VRAM to one aperture\n");
1706 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1707 * have set it up. We don't write this as it's broken on some ASICs but
1708 * we expect the BIOS to have done the right thing (might be too optimistic...)
1710 if (RREG32(RADEON_HOST_PATH_CNTL
) & RADEON_HDP_APER_CNTL
)
1711 return aper_size
* 2;
1715 void r100_vram_init_sizes(struct radeon_device
*rdev
)
1717 u64 config_aper_size
;
1720 config_aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
1722 if (rdev
->flags
& RADEON_IS_IGP
) {
1724 /* read NB_TOM to get the amount of ram stolen for the GPU */
1725 tom
= RREG32(RADEON_NB_TOM
);
1726 rdev
->mc
.real_vram_size
= (((tom
>> 16) - (tom
& 0xffff) + 1) << 16);
1727 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1728 rdev
->mc
.vram_location
= (tom
& 0xffff) << 16;
1729 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
1730 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
1732 rdev
->mc
.real_vram_size
= RREG32(RADEON_CONFIG_MEMSIZE
);
1733 /* Some production boards of m6 will report 0
1736 if (rdev
->mc
.real_vram_size
== 0) {
1737 rdev
->mc
.real_vram_size
= 8192 * 1024;
1738 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
1740 /* let driver place VRAM */
1741 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
1742 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1743 * Novell bug 204882 + along with lots of ubuntu ones */
1744 if (config_aper_size
> rdev
->mc
.real_vram_size
)
1745 rdev
->mc
.mc_vram_size
= config_aper_size
;
1747 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
1750 /* work out accessible VRAM */
1751 accessible
= r100_get_accessible_vram(rdev
);
1753 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
1754 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
1756 if (accessible
> rdev
->mc
.aper_size
)
1757 accessible
= rdev
->mc
.aper_size
;
1759 if (rdev
->mc
.mc_vram_size
> rdev
->mc
.aper_size
)
1760 rdev
->mc
.mc_vram_size
= rdev
->mc
.aper_size
;
1762 if (rdev
->mc
.real_vram_size
> rdev
->mc
.aper_size
)
1763 rdev
->mc
.real_vram_size
= rdev
->mc
.aper_size
;
1766 void r100_vram_info(struct radeon_device
*rdev
)
1768 r100_vram_get_type(rdev
);
1770 r100_vram_init_sizes(rdev
);
1775 * Indirect registers accessor
1777 void r100_pll_errata_after_index(struct radeon_device
*rdev
)
1779 if (!(rdev
->pll_errata
& CHIP_ERRATA_PLL_DUMMYREADS
)) {
1782 (void)RREG32(RADEON_CLOCK_CNTL_DATA
);
1783 (void)RREG32(RADEON_CRTC_GEN_CNTL
);
1786 static void r100_pll_errata_after_data(struct radeon_device
*rdev
)
1788 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1789 * or the chip could hang on a subsequent access
1791 if (rdev
->pll_errata
& CHIP_ERRATA_PLL_DELAY
) {
1795 /* This function is required to workaround a hardware bug in some (all?)
1796 * revisions of the R300. This workaround should be called after every
1797 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1798 * may not be correct.
1800 if (rdev
->pll_errata
& CHIP_ERRATA_R300_CG
) {
1803 save
= RREG32(RADEON_CLOCK_CNTL_INDEX
);
1804 tmp
= save
& ~(0x3f | RADEON_PLL_WR_EN
);
1805 WREG32(RADEON_CLOCK_CNTL_INDEX
, tmp
);
1806 tmp
= RREG32(RADEON_CLOCK_CNTL_DATA
);
1807 WREG32(RADEON_CLOCK_CNTL_INDEX
, save
);
1811 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
)
1815 WREG8(RADEON_CLOCK_CNTL_INDEX
, reg
& 0x3f);
1816 r100_pll_errata_after_index(rdev
);
1817 data
= RREG32(RADEON_CLOCK_CNTL_DATA
);
1818 r100_pll_errata_after_data(rdev
);
1822 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
1824 WREG8(RADEON_CLOCK_CNTL_INDEX
, ((reg
& 0x3f) | RADEON_PLL_WR_EN
));
1825 r100_pll_errata_after_index(rdev
);
1826 WREG32(RADEON_CLOCK_CNTL_DATA
, v
);
1827 r100_pll_errata_after_data(rdev
);
1830 void r100_set_safe_registers(struct radeon_device
*rdev
)
1832 if (ASIC_IS_RN50(rdev
)) {
1833 rdev
->config
.r100
.reg_safe_bm
= rn50_reg_safe_bm
;
1834 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(rn50_reg_safe_bm
);
1835 } else if (rdev
->family
< CHIP_R200
) {
1836 rdev
->config
.r100
.reg_safe_bm
= r100_reg_safe_bm
;
1837 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(r100_reg_safe_bm
);
1839 r200_set_safe_registers(rdev
);
1846 #if defined(CONFIG_DEBUG_FS)
1847 static int r100_debugfs_rbbm_info(struct seq_file
*m
, void *data
)
1849 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1850 struct drm_device
*dev
= node
->minor
->dev
;
1851 struct radeon_device
*rdev
= dev
->dev_private
;
1852 uint32_t reg
, value
;
1855 seq_printf(m
, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS
));
1856 seq_printf(m
, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1857 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
1858 for (i
= 0; i
< 64; i
++) {
1859 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
| 0x100);
1860 reg
= (RREG32(RADEON_RBBM_CMDFIFO_DATA
) - 1) >> 2;
1861 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
);
1862 value
= RREG32(RADEON_RBBM_CMDFIFO_DATA
);
1863 seq_printf(m
, "[0x%03X] 0x%04X=0x%08X\n", i
, reg
, value
);
1868 static int r100_debugfs_cp_ring_info(struct seq_file
*m
, void *data
)
1870 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1871 struct drm_device
*dev
= node
->minor
->dev
;
1872 struct radeon_device
*rdev
= dev
->dev_private
;
1874 unsigned count
, i
, j
;
1876 radeon_ring_free_size(rdev
);
1877 rdp
= RREG32(RADEON_CP_RB_RPTR
);
1878 wdp
= RREG32(RADEON_CP_RB_WPTR
);
1879 count
= (rdp
+ rdev
->cp
.ring_size
- wdp
) & rdev
->cp
.ptr_mask
;
1880 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
1881 seq_printf(m
, "CP_RB_WPTR 0x%08x\n", wdp
);
1882 seq_printf(m
, "CP_RB_RPTR 0x%08x\n", rdp
);
1883 seq_printf(m
, "%u free dwords in ring\n", rdev
->cp
.ring_free_dw
);
1884 seq_printf(m
, "%u dwords in ring\n", count
);
1885 for (j
= 0; j
<= count
; j
++) {
1886 i
= (rdp
+ j
) & rdev
->cp
.ptr_mask
;
1887 seq_printf(m
, "r[%04d]=0x%08x\n", i
, rdev
->cp
.ring
[i
]);
1893 static int r100_debugfs_cp_csq_fifo(struct seq_file
*m
, void *data
)
1895 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1896 struct drm_device
*dev
= node
->minor
->dev
;
1897 struct radeon_device
*rdev
= dev
->dev_private
;
1898 uint32_t csq_stat
, csq2_stat
, tmp
;
1899 unsigned r_rptr
, r_wptr
, ib1_rptr
, ib1_wptr
, ib2_rptr
, ib2_wptr
;
1902 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
1903 seq_printf(m
, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE
));
1904 csq_stat
= RREG32(RADEON_CP_CSQ_STAT
);
1905 csq2_stat
= RREG32(RADEON_CP_CSQ2_STAT
);
1906 r_rptr
= (csq_stat
>> 0) & 0x3ff;
1907 r_wptr
= (csq_stat
>> 10) & 0x3ff;
1908 ib1_rptr
= (csq_stat
>> 20) & 0x3ff;
1909 ib1_wptr
= (csq2_stat
>> 0) & 0x3ff;
1910 ib2_rptr
= (csq2_stat
>> 10) & 0x3ff;
1911 ib2_wptr
= (csq2_stat
>> 20) & 0x3ff;
1912 seq_printf(m
, "CP_CSQ_STAT 0x%08x\n", csq_stat
);
1913 seq_printf(m
, "CP_CSQ2_STAT 0x%08x\n", csq2_stat
);
1914 seq_printf(m
, "Ring rptr %u\n", r_rptr
);
1915 seq_printf(m
, "Ring wptr %u\n", r_wptr
);
1916 seq_printf(m
, "Indirect1 rptr %u\n", ib1_rptr
);
1917 seq_printf(m
, "Indirect1 wptr %u\n", ib1_wptr
);
1918 seq_printf(m
, "Indirect2 rptr %u\n", ib2_rptr
);
1919 seq_printf(m
, "Indirect2 wptr %u\n", ib2_wptr
);
1920 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1921 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1922 seq_printf(m
, "Ring fifo:\n");
1923 for (i
= 0; i
< 256; i
++) {
1924 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
1925 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
1926 seq_printf(m
, "rfifo[%04d]=0x%08X\n", i
, tmp
);
1928 seq_printf(m
, "Indirect1 fifo:\n");
1929 for (i
= 256; i
<= 512; i
++) {
1930 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
1931 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
1932 seq_printf(m
, "ib1fifo[%04d]=0x%08X\n", i
, tmp
);
1934 seq_printf(m
, "Indirect2 fifo:\n");
1935 for (i
= 640; i
< ib1_wptr
; i
++) {
1936 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
1937 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
1938 seq_printf(m
, "ib2fifo[%04d]=0x%08X\n", i
, tmp
);
1943 static int r100_debugfs_mc_info(struct seq_file
*m
, void *data
)
1945 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1946 struct drm_device
*dev
= node
->minor
->dev
;
1947 struct radeon_device
*rdev
= dev
->dev_private
;
1950 tmp
= RREG32(RADEON_CONFIG_MEMSIZE
);
1951 seq_printf(m
, "CONFIG_MEMSIZE 0x%08x\n", tmp
);
1952 tmp
= RREG32(RADEON_MC_FB_LOCATION
);
1953 seq_printf(m
, "MC_FB_LOCATION 0x%08x\n", tmp
);
1954 tmp
= RREG32(RADEON_BUS_CNTL
);
1955 seq_printf(m
, "BUS_CNTL 0x%08x\n", tmp
);
1956 tmp
= RREG32(RADEON_MC_AGP_LOCATION
);
1957 seq_printf(m
, "MC_AGP_LOCATION 0x%08x\n", tmp
);
1958 tmp
= RREG32(RADEON_AGP_BASE
);
1959 seq_printf(m
, "AGP_BASE 0x%08x\n", tmp
);
1960 tmp
= RREG32(RADEON_HOST_PATH_CNTL
);
1961 seq_printf(m
, "HOST_PATH_CNTL 0x%08x\n", tmp
);
1962 tmp
= RREG32(0x01D0);
1963 seq_printf(m
, "AIC_CTRL 0x%08x\n", tmp
);
1964 tmp
= RREG32(RADEON_AIC_LO_ADDR
);
1965 seq_printf(m
, "AIC_LO_ADDR 0x%08x\n", tmp
);
1966 tmp
= RREG32(RADEON_AIC_HI_ADDR
);
1967 seq_printf(m
, "AIC_HI_ADDR 0x%08x\n", tmp
);
1968 tmp
= RREG32(0x01E4);
1969 seq_printf(m
, "AIC_TLB_ADDR 0x%08x\n", tmp
);
1973 static struct drm_info_list r100_debugfs_rbbm_list
[] = {
1974 {"r100_rbbm_info", r100_debugfs_rbbm_info
, 0, NULL
},
1977 static struct drm_info_list r100_debugfs_cp_list
[] = {
1978 {"r100_cp_ring_info", r100_debugfs_cp_ring_info
, 0, NULL
},
1979 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo
, 0, NULL
},
1982 static struct drm_info_list r100_debugfs_mc_info_list
[] = {
1983 {"r100_mc_info", r100_debugfs_mc_info
, 0, NULL
},
1987 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
)
1989 #if defined(CONFIG_DEBUG_FS)
1990 return radeon_debugfs_add_files(rdev
, r100_debugfs_rbbm_list
, 1);
1996 int r100_debugfs_cp_init(struct radeon_device
*rdev
)
1998 #if defined(CONFIG_DEBUG_FS)
1999 return radeon_debugfs_add_files(rdev
, r100_debugfs_cp_list
, 2);
2005 int r100_debugfs_mc_info_init(struct radeon_device
*rdev
)
2007 #if defined(CONFIG_DEBUG_FS)
2008 return radeon_debugfs_add_files(rdev
, r100_debugfs_mc_info_list
, 1);
2014 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
2015 uint32_t tiling_flags
, uint32_t pitch
,
2016 uint32_t offset
, uint32_t obj_size
)
2018 int surf_index
= reg
* 16;
2021 /* r100/r200 divide by 16 */
2022 if (rdev
->family
< CHIP_R300
)
2027 if (rdev
->family
<= CHIP_RS200
) {
2028 if ((tiling_flags
& (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2029 == (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2030 flags
|= RADEON_SURF_TILE_COLOR_BOTH
;
2031 if (tiling_flags
& RADEON_TILING_MACRO
)
2032 flags
|= RADEON_SURF_TILE_COLOR_MACRO
;
2033 } else if (rdev
->family
<= CHIP_RV280
) {
2034 if (tiling_flags
& (RADEON_TILING_MACRO
))
2035 flags
|= R200_SURF_TILE_COLOR_MACRO
;
2036 if (tiling_flags
& RADEON_TILING_MICRO
)
2037 flags
|= R200_SURF_TILE_COLOR_MICRO
;
2039 if (tiling_flags
& RADEON_TILING_MACRO
)
2040 flags
|= R300_SURF_TILE_MACRO
;
2041 if (tiling_flags
& RADEON_TILING_MICRO
)
2042 flags
|= R300_SURF_TILE_MICRO
;
2045 if (tiling_flags
& RADEON_TILING_SWAP_16BIT
)
2046 flags
|= RADEON_SURF_AP0_SWP_16BPP
| RADEON_SURF_AP1_SWP_16BPP
;
2047 if (tiling_flags
& RADEON_TILING_SWAP_32BIT
)
2048 flags
|= RADEON_SURF_AP0_SWP_32BPP
| RADEON_SURF_AP1_SWP_32BPP
;
2050 DRM_DEBUG("writing surface %d %d %x %x\n", reg
, flags
, offset
, offset
+obj_size
-1);
2051 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, flags
);
2052 WREG32(RADEON_SURFACE0_LOWER_BOUND
+ surf_index
, offset
);
2053 WREG32(RADEON_SURFACE0_UPPER_BOUND
+ surf_index
, offset
+ obj_size
- 1);
2057 void r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
2059 int surf_index
= reg
* 16;
2060 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, 0);
2063 void r100_bandwidth_update(struct radeon_device
*rdev
)
2065 fixed20_12 trcd_ff
, trp_ff
, tras_ff
, trbs_ff
, tcas_ff
;
2066 fixed20_12 sclk_ff
, mclk_ff
, sclk_eff_ff
, sclk_delay_ff
;
2067 fixed20_12 peak_disp_bw
, mem_bw
, pix_clk
, pix_clk2
, temp_ff
, crit_point_ff
;
2068 uint32_t temp
, data
, mem_trcd
, mem_trp
, mem_tras
;
2069 fixed20_12 memtcas_ff
[8] = {
2078 fixed20_12 memtcas_rs480_ff
[8] = {
2088 fixed20_12 memtcas2_ff
[8] = {
2098 fixed20_12 memtrbs
[8] = {
2108 fixed20_12 memtrbs_r4xx
[8] = {
2118 fixed20_12 min_mem_eff
;
2119 fixed20_12 mc_latency_sclk
, mc_latency_mclk
, k1
;
2120 fixed20_12 cur_latency_mclk
, cur_latency_sclk
;
2121 fixed20_12 disp_latency
, disp_latency_overhead
, disp_drain_rate
,
2122 disp_drain_rate2
, read_return_rate
;
2123 fixed20_12 time_disp1_drop_priority
;
2125 int cur_size
= 16; /* in octawords */
2126 int critical_point
= 0, critical_point2
;
2127 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2128 int stop_req
, max_stop_req
;
2129 struct drm_display_mode
*mode1
= NULL
;
2130 struct drm_display_mode
*mode2
= NULL
;
2131 uint32_t pixel_bytes1
= 0;
2132 uint32_t pixel_bytes2
= 0;
2134 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
) {
2135 mode1
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
2136 pixel_bytes1
= rdev
->mode_info
.crtcs
[0]->base
.fb
->bits_per_pixel
/ 8;
2138 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
2139 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
) {
2140 mode2
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
2141 pixel_bytes2
= rdev
->mode_info
.crtcs
[1]->base
.fb
->bits_per_pixel
/ 8;
2145 min_mem_eff
.full
= rfixed_const_8(0);
2147 if ((rdev
->disp_priority
== 2) && ASIC_IS_R300(rdev
)) {
2148 uint32_t mc_init_misc_lat_timer
= RREG32(R300_MC_INIT_MISC_LAT_TIMER
);
2149 mc_init_misc_lat_timer
&= ~(R300_MC_DISP1R_INIT_LAT_MASK
<< R300_MC_DISP1R_INIT_LAT_SHIFT
);
2150 mc_init_misc_lat_timer
&= ~(R300_MC_DISP0R_INIT_LAT_MASK
<< R300_MC_DISP0R_INIT_LAT_SHIFT
);
2151 /* check crtc enables */
2153 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT
);
2155 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT
);
2156 WREG32(R300_MC_INIT_MISC_LAT_TIMER
, mc_init_misc_lat_timer
);
2160 * determine is there is enough bw for current mode
2162 mclk_ff
.full
= rfixed_const(rdev
->clock
.default_mclk
);
2163 temp_ff
.full
= rfixed_const(100);
2164 mclk_ff
.full
= rfixed_div(mclk_ff
, temp_ff
);
2165 sclk_ff
.full
= rfixed_const(rdev
->clock
.default_sclk
);
2166 sclk_ff
.full
= rfixed_div(sclk_ff
, temp_ff
);
2168 temp
= (rdev
->mc
.vram_width
/ 8) * (rdev
->mc
.vram_is_ddr
? 2 : 1);
2169 temp_ff
.full
= rfixed_const(temp
);
2170 mem_bw
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2174 peak_disp_bw
.full
= 0;
2176 temp_ff
.full
= rfixed_const(1000);
2177 pix_clk
.full
= rfixed_const(mode1
->clock
); /* convert to fixed point */
2178 pix_clk
.full
= rfixed_div(pix_clk
, temp_ff
);
2179 temp_ff
.full
= rfixed_const(pixel_bytes1
);
2180 peak_disp_bw
.full
+= rfixed_mul(pix_clk
, temp_ff
);
2183 temp_ff
.full
= rfixed_const(1000);
2184 pix_clk2
.full
= rfixed_const(mode2
->clock
); /* convert to fixed point */
2185 pix_clk2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2186 temp_ff
.full
= rfixed_const(pixel_bytes2
);
2187 peak_disp_bw
.full
+= rfixed_mul(pix_clk2
, temp_ff
);
2190 mem_bw
.full
= rfixed_mul(mem_bw
, min_mem_eff
);
2191 if (peak_disp_bw
.full
>= mem_bw
.full
) {
2192 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2193 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2196 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2197 temp
= RREG32(RADEON_MEM_TIMING_CNTL
);
2198 if ((rdev
->family
== CHIP_RV100
) || (rdev
->flags
& RADEON_IS_IGP
)) { /* RV100, M6, IGPs */
2199 mem_trcd
= ((temp
>> 2) & 0x3) + 1;
2200 mem_trp
= ((temp
& 0x3)) + 1;
2201 mem_tras
= ((temp
& 0x70) >> 4) + 1;
2202 } else if (rdev
->family
== CHIP_R300
||
2203 rdev
->family
== CHIP_R350
) { /* r300, r350 */
2204 mem_trcd
= (temp
& 0x7) + 1;
2205 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2206 mem_tras
= ((temp
>> 11) & 0xf) + 4;
2207 } else if (rdev
->family
== CHIP_RV350
||
2208 rdev
->family
<= CHIP_RV380
) {
2210 mem_trcd
= (temp
& 0x7) + 3;
2211 mem_trp
= ((temp
>> 8) & 0x7) + 3;
2212 mem_tras
= ((temp
>> 11) & 0xf) + 6;
2213 } else if (rdev
->family
== CHIP_R420
||
2214 rdev
->family
== CHIP_R423
||
2215 rdev
->family
== CHIP_RV410
) {
2217 mem_trcd
= (temp
& 0xf) + 3;
2220 mem_trp
= ((temp
>> 8) & 0xf) + 3;
2223 mem_tras
= ((temp
>> 12) & 0x1f) + 6;
2226 } else { /* RV200, R200 */
2227 mem_trcd
= (temp
& 0x7) + 1;
2228 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2229 mem_tras
= ((temp
>> 12) & 0xf) + 4;
2232 trcd_ff
.full
= rfixed_const(mem_trcd
);
2233 trp_ff
.full
= rfixed_const(mem_trp
);
2234 tras_ff
.full
= rfixed_const(mem_tras
);
2236 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2237 temp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2238 data
= (temp
& (7 << 20)) >> 20;
2239 if ((rdev
->family
== CHIP_RV100
) || rdev
->flags
& RADEON_IS_IGP
) {
2240 if (rdev
->family
== CHIP_RS480
) /* don't think rs400 */
2241 tcas_ff
= memtcas_rs480_ff
[data
];
2243 tcas_ff
= memtcas_ff
[data
];
2245 tcas_ff
= memtcas2_ff
[data
];
2247 if (rdev
->family
== CHIP_RS400
||
2248 rdev
->family
== CHIP_RS480
) {
2249 /* extra cas latency stored in bits 23-25 0-4 clocks */
2250 data
= (temp
>> 23) & 0x7;
2252 tcas_ff
.full
+= rfixed_const(data
);
2255 if (ASIC_IS_R300(rdev
) && !(rdev
->flags
& RADEON_IS_IGP
)) {
2256 /* on the R300, Tcas is included in Trbs.
2258 temp
= RREG32(RADEON_MEM_CNTL
);
2259 data
= (R300_MEM_NUM_CHANNELS_MASK
& temp
);
2261 if (R300_MEM_USE_CD_CH_ONLY
& temp
) {
2262 temp
= RREG32(R300_MC_IND_INDEX
);
2263 temp
&= ~R300_MC_IND_ADDR_MASK
;
2264 temp
|= R300_MC_READ_CNTL_CD_mcind
;
2265 WREG32(R300_MC_IND_INDEX
, temp
);
2266 temp
= RREG32(R300_MC_IND_DATA
);
2267 data
= (R300_MEM_RBS_POSITION_C_MASK
& temp
);
2269 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2270 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2273 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2274 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2276 if (rdev
->family
== CHIP_RV410
||
2277 rdev
->family
== CHIP_R420
||
2278 rdev
->family
== CHIP_R423
)
2279 trbs_ff
= memtrbs_r4xx
[data
];
2281 trbs_ff
= memtrbs
[data
];
2282 tcas_ff
.full
+= trbs_ff
.full
;
2285 sclk_eff_ff
.full
= sclk_ff
.full
;
2287 if (rdev
->flags
& RADEON_IS_AGP
) {
2288 fixed20_12 agpmode_ff
;
2289 agpmode_ff
.full
= rfixed_const(radeon_agpmode
);
2290 temp_ff
.full
= rfixed_const_666(16);
2291 sclk_eff_ff
.full
-= rfixed_mul(agpmode_ff
, temp_ff
);
2293 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2295 if (ASIC_IS_R300(rdev
)) {
2296 sclk_delay_ff
.full
= rfixed_const(250);
2298 if ((rdev
->family
== CHIP_RV100
) ||
2299 rdev
->flags
& RADEON_IS_IGP
) {
2300 if (rdev
->mc
.vram_is_ddr
)
2301 sclk_delay_ff
.full
= rfixed_const(41);
2303 sclk_delay_ff
.full
= rfixed_const(33);
2305 if (rdev
->mc
.vram_width
== 128)
2306 sclk_delay_ff
.full
= rfixed_const(57);
2308 sclk_delay_ff
.full
= rfixed_const(41);
2312 mc_latency_sclk
.full
= rfixed_div(sclk_delay_ff
, sclk_eff_ff
);
2314 if (rdev
->mc
.vram_is_ddr
) {
2315 if (rdev
->mc
.vram_width
== 32) {
2316 k1
.full
= rfixed_const(40);
2319 k1
.full
= rfixed_const(20);
2323 k1
.full
= rfixed_const(40);
2327 temp_ff
.full
= rfixed_const(2);
2328 mc_latency_mclk
.full
= rfixed_mul(trcd_ff
, temp_ff
);
2329 temp_ff
.full
= rfixed_const(c
);
2330 mc_latency_mclk
.full
+= rfixed_mul(tcas_ff
, temp_ff
);
2331 temp_ff
.full
= rfixed_const(4);
2332 mc_latency_mclk
.full
+= rfixed_mul(tras_ff
, temp_ff
);
2333 mc_latency_mclk
.full
+= rfixed_mul(trp_ff
, temp_ff
);
2334 mc_latency_mclk
.full
+= k1
.full
;
2336 mc_latency_mclk
.full
= rfixed_div(mc_latency_mclk
, mclk_ff
);
2337 mc_latency_mclk
.full
+= rfixed_div(temp_ff
, sclk_eff_ff
);
2340 HW cursor time assuming worst case of full size colour cursor.
2342 temp_ff
.full
= rfixed_const((2 * (cur_size
- (rdev
->mc
.vram_is_ddr
+ 1))));
2343 temp_ff
.full
+= trcd_ff
.full
;
2344 if (temp_ff
.full
< tras_ff
.full
)
2345 temp_ff
.full
= tras_ff
.full
;
2346 cur_latency_mclk
.full
= rfixed_div(temp_ff
, mclk_ff
);
2348 temp_ff
.full
= rfixed_const(cur_size
);
2349 cur_latency_sclk
.full
= rfixed_div(temp_ff
, sclk_eff_ff
);
2351 Find the total latency for the display data.
2353 disp_latency_overhead
.full
= rfixed_const(8);
2354 disp_latency_overhead
.full
= rfixed_div(disp_latency_overhead
, sclk_ff
);
2355 mc_latency_mclk
.full
+= disp_latency_overhead
.full
+ cur_latency_mclk
.full
;
2356 mc_latency_sclk
.full
+= disp_latency_overhead
.full
+ cur_latency_sclk
.full
;
2358 if (mc_latency_mclk
.full
> mc_latency_sclk
.full
)
2359 disp_latency
.full
= mc_latency_mclk
.full
;
2361 disp_latency
.full
= mc_latency_sclk
.full
;
2363 /* setup Max GRPH_STOP_REQ default value */
2364 if (ASIC_IS_RV100(rdev
))
2365 max_stop_req
= 0x5c;
2367 max_stop_req
= 0x7c;
2371 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2372 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2374 stop_req
= mode1
->hdisplay
* pixel_bytes1
/ 16;
2376 if (stop_req
> max_stop_req
)
2377 stop_req
= max_stop_req
;
2380 Find the drain rate of the display buffer.
2382 temp_ff
.full
= rfixed_const((16/pixel_bytes1
));
2383 disp_drain_rate
.full
= rfixed_div(pix_clk
, temp_ff
);
2386 Find the critical point of the display buffer.
2388 crit_point_ff
.full
= rfixed_mul(disp_drain_rate
, disp_latency
);
2389 crit_point_ff
.full
+= rfixed_const_half(0);
2391 critical_point
= rfixed_trunc(crit_point_ff
);
2393 if (rdev
->disp_priority
== 2) {
2398 The critical point should never be above max_stop_req-4. Setting
2399 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2401 if (max_stop_req
- critical_point
< 4)
2404 if (critical_point
== 0 && mode2
&& rdev
->family
== CHIP_R300
) {
2405 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2406 critical_point
= 0x10;
2409 temp
= RREG32(RADEON_GRPH_BUFFER_CNTL
);
2410 temp
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2411 temp
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2412 temp
&= ~(RADEON_GRPH_START_REQ_MASK
);
2413 if ((rdev
->family
== CHIP_R350
) &&
2414 (stop_req
> 0x15)) {
2417 temp
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2418 temp
|= RADEON_GRPH_BUFFER_SIZE
;
2419 temp
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2420 RADEON_GRPH_CRITICAL_AT_SOF
|
2421 RADEON_GRPH_STOP_CNTL
);
2423 Write the result into the register.
2425 WREG32(RADEON_GRPH_BUFFER_CNTL
, ((temp
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2426 (critical_point
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2429 if ((rdev
->family
== CHIP_RS400
) ||
2430 (rdev
->family
== CHIP_RS480
)) {
2431 /* attempt to program RS400 disp regs correctly ??? */
2432 temp
= RREG32(RS400_DISP1_REG_CNTL
);
2433 temp
&= ~(RS400_DISP1_START_REQ_LEVEL_MASK
|
2434 RS400_DISP1_STOP_REQ_LEVEL_MASK
);
2435 WREG32(RS400_DISP1_REQ_CNTL1
, (temp
|
2436 (critical_point
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2437 (critical_point
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2438 temp
= RREG32(RS400_DMIF_MEM_CNTL1
);
2439 temp
&= ~(RS400_DISP1_CRITICAL_POINT_START_MASK
|
2440 RS400_DISP1_CRITICAL_POINT_STOP_MASK
);
2441 WREG32(RS400_DMIF_MEM_CNTL1
, (temp
|
2442 (critical_point
<< RS400_DISP1_CRITICAL_POINT_START_SHIFT
) |
2443 (critical_point
<< RS400_DISP1_CRITICAL_POINT_STOP_SHIFT
)));
2447 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2448 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2449 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL
));
2454 stop_req
= mode2
->hdisplay
* pixel_bytes2
/ 16;
2456 if (stop_req
> max_stop_req
)
2457 stop_req
= max_stop_req
;
2460 Find the drain rate of the display buffer.
2462 temp_ff
.full
= rfixed_const((16/pixel_bytes2
));
2463 disp_drain_rate2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2465 grph2_cntl
= RREG32(RADEON_GRPH2_BUFFER_CNTL
);
2466 grph2_cntl
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2467 grph2_cntl
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2468 grph2_cntl
&= ~(RADEON_GRPH_START_REQ_MASK
);
2469 if ((rdev
->family
== CHIP_R350
) &&
2470 (stop_req
> 0x15)) {
2473 grph2_cntl
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2474 grph2_cntl
|= RADEON_GRPH_BUFFER_SIZE
;
2475 grph2_cntl
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2476 RADEON_GRPH_CRITICAL_AT_SOF
|
2477 RADEON_GRPH_STOP_CNTL
);
2479 if ((rdev
->family
== CHIP_RS100
) ||
2480 (rdev
->family
== CHIP_RS200
))
2481 critical_point2
= 0;
2483 temp
= (rdev
->mc
.vram_width
* rdev
->mc
.vram_is_ddr
+ 1)/128;
2484 temp_ff
.full
= rfixed_const(temp
);
2485 temp_ff
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2486 if (sclk_ff
.full
< temp_ff
.full
)
2487 temp_ff
.full
= sclk_ff
.full
;
2489 read_return_rate
.full
= temp_ff
.full
;
2492 temp_ff
.full
= read_return_rate
.full
- disp_drain_rate
.full
;
2493 time_disp1_drop_priority
.full
= rfixed_div(crit_point_ff
, temp_ff
);
2495 time_disp1_drop_priority
.full
= 0;
2497 crit_point_ff
.full
= disp_latency
.full
+ time_disp1_drop_priority
.full
+ disp_latency
.full
;
2498 crit_point_ff
.full
= rfixed_mul(crit_point_ff
, disp_drain_rate2
);
2499 crit_point_ff
.full
+= rfixed_const_half(0);
2501 critical_point2
= rfixed_trunc(crit_point_ff
);
2503 if (rdev
->disp_priority
== 2) {
2504 critical_point2
= 0;
2507 if (max_stop_req
- critical_point2
< 4)
2508 critical_point2
= 0;
2512 if (critical_point2
== 0 && rdev
->family
== CHIP_R300
) {
2513 /* some R300 cards have problem with this set to 0 */
2514 critical_point2
= 0x10;
2517 WREG32(RADEON_GRPH2_BUFFER_CNTL
, ((grph2_cntl
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2518 (critical_point2
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2520 if ((rdev
->family
== CHIP_RS400
) ||
2521 (rdev
->family
== CHIP_RS480
)) {
2523 /* attempt to program RS400 disp2 regs correctly ??? */
2524 temp
= RREG32(RS400_DISP2_REQ_CNTL1
);
2525 temp
&= ~(RS400_DISP2_START_REQ_LEVEL_MASK
|
2526 RS400_DISP2_STOP_REQ_LEVEL_MASK
);
2527 WREG32(RS400_DISP2_REQ_CNTL1
, (temp
|
2528 (critical_point2
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2529 (critical_point2
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2530 temp
= RREG32(RS400_DISP2_REQ_CNTL2
);
2531 temp
&= ~(RS400_DISP2_CRITICAL_POINT_START_MASK
|
2532 RS400_DISP2_CRITICAL_POINT_STOP_MASK
);
2533 WREG32(RS400_DISP2_REQ_CNTL2
, (temp
|
2534 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_START_SHIFT
) |
2535 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_STOP_SHIFT
)));
2537 WREG32(RS400_DISP2_REQ_CNTL1
, 0x105DC1CC);
2538 WREG32(RS400_DISP2_REQ_CNTL2
, 0x2749D000);
2539 WREG32(RS400_DMIF_MEM_CNTL1
, 0x29CA71DC);
2540 WREG32(RS400_DISP1_REQ_CNTL1
, 0x28FBC3AC);
2543 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2544 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL
));
2548 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture
*t
)
2550 DRM_ERROR("pitch %d\n", t
->pitch
);
2551 DRM_ERROR("width %d\n", t
->width
);
2552 DRM_ERROR("height %d\n", t
->height
);
2553 DRM_ERROR("num levels %d\n", t
->num_levels
);
2554 DRM_ERROR("depth %d\n", t
->txdepth
);
2555 DRM_ERROR("bpp %d\n", t
->cpp
);
2556 DRM_ERROR("coordinate type %d\n", t
->tex_coord_type
);
2557 DRM_ERROR("width round to power of 2 %d\n", t
->roundup_w
);
2558 DRM_ERROR("height round to power of 2 %d\n", t
->roundup_h
);
2561 static int r100_cs_track_cube(struct radeon_device
*rdev
,
2562 struct r100_cs_track
*track
, unsigned idx
)
2564 unsigned face
, w
, h
;
2565 struct radeon_object
*cube_robj
;
2568 for (face
= 0; face
< 5; face
++) {
2569 cube_robj
= track
->textures
[idx
].cube_info
[face
].robj
;
2570 w
= track
->textures
[idx
].cube_info
[face
].width
;
2571 h
= track
->textures
[idx
].cube_info
[face
].height
;
2574 size
*= track
->textures
[idx
].cpp
;
2576 size
+= track
->textures
[idx
].cube_info
[face
].offset
;
2578 if (size
> radeon_object_size(cube_robj
)) {
2579 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2580 size
, radeon_object_size(cube_robj
));
2581 r100_cs_track_texture_print(&track
->textures
[idx
]);
2588 static int r100_cs_track_texture_check(struct radeon_device
*rdev
,
2589 struct r100_cs_track
*track
)
2591 struct radeon_object
*robj
;
2593 unsigned u
, i
, w
, h
;
2596 for (u
= 0; u
< track
->num_texture
; u
++) {
2597 if (!track
->textures
[u
].enabled
)
2599 robj
= track
->textures
[u
].robj
;
2601 DRM_ERROR("No texture bound to unit %u\n", u
);
2605 for (i
= 0; i
<= track
->textures
[u
].num_levels
; i
++) {
2606 if (track
->textures
[u
].use_pitch
) {
2607 if (rdev
->family
< CHIP_R300
)
2608 w
= (track
->textures
[u
].pitch
/ track
->textures
[u
].cpp
) / (1 << i
);
2610 w
= track
->textures
[u
].pitch
/ (1 << i
);
2612 w
= track
->textures
[u
].width
/ (1 << i
);
2613 if (rdev
->family
>= CHIP_RV515
)
2614 w
|= track
->textures
[u
].width_11
;
2615 if (track
->textures
[u
].roundup_w
)
2616 w
= roundup_pow_of_two(w
);
2618 h
= track
->textures
[u
].height
/ (1 << i
);
2619 if (rdev
->family
>= CHIP_RV515
)
2620 h
|= track
->textures
[u
].height_11
;
2621 if (track
->textures
[u
].roundup_h
)
2622 h
= roundup_pow_of_two(h
);
2625 size
*= track
->textures
[u
].cpp
;
2626 switch (track
->textures
[u
].tex_coord_type
) {
2630 size
*= (1 << track
->textures
[u
].txdepth
);
2633 if (track
->separate_cube
) {
2634 ret
= r100_cs_track_cube(rdev
, track
, u
);
2641 DRM_ERROR("Invalid texture coordinate type %u for unit "
2642 "%u\n", track
->textures
[u
].tex_coord_type
, u
);
2645 if (size
> radeon_object_size(robj
)) {
2646 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2647 "%lu\n", u
, size
, radeon_object_size(robj
));
2648 r100_cs_track_texture_print(&track
->textures
[u
]);
2655 int r100_cs_track_check(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
2662 for (i
= 0; i
< track
->num_cb
; i
++) {
2663 if (track
->cb
[i
].robj
== NULL
) {
2664 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i
);
2667 size
= track
->cb
[i
].pitch
* track
->cb
[i
].cpp
* track
->maxy
;
2668 size
+= track
->cb
[i
].offset
;
2669 if (size
> radeon_object_size(track
->cb
[i
].robj
)) {
2670 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2671 "(need %lu have %lu) !\n", i
, size
,
2672 radeon_object_size(track
->cb
[i
].robj
));
2673 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2674 i
, track
->cb
[i
].pitch
, track
->cb
[i
].cpp
,
2675 track
->cb
[i
].offset
, track
->maxy
);
2679 if (track
->z_enabled
) {
2680 if (track
->zb
.robj
== NULL
) {
2681 DRM_ERROR("[drm] No buffer for z buffer !\n");
2684 size
= track
->zb
.pitch
* track
->zb
.cpp
* track
->maxy
;
2685 size
+= track
->zb
.offset
;
2686 if (size
> radeon_object_size(track
->zb
.robj
)) {
2687 DRM_ERROR("[drm] Buffer too small for z buffer "
2688 "(need %lu have %lu) !\n", size
,
2689 radeon_object_size(track
->zb
.robj
));
2690 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2691 track
->zb
.pitch
, track
->zb
.cpp
,
2692 track
->zb
.offset
, track
->maxy
);
2696 prim_walk
= (track
->vap_vf_cntl
>> 4) & 0x3;
2697 nverts
= (track
->vap_vf_cntl
>> 16) & 0xFFFF;
2698 switch (prim_walk
) {
2700 for (i
= 0; i
< track
->num_arrays
; i
++) {
2701 size
= track
->arrays
[i
].esize
* track
->max_indx
* 4;
2702 if (track
->arrays
[i
].robj
== NULL
) {
2703 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2704 "bound\n", prim_walk
, i
);
2707 if (size
> radeon_object_size(track
->arrays
[i
].robj
)) {
2708 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2709 "have %lu dwords\n", prim_walk
, i
,
2711 radeon_object_size(track
->arrays
[i
].robj
) >> 2);
2712 DRM_ERROR("Max indices %u\n", track
->max_indx
);
2718 for (i
= 0; i
< track
->num_arrays
; i
++) {
2719 size
= track
->arrays
[i
].esize
* (nverts
- 1) * 4;
2720 if (track
->arrays
[i
].robj
== NULL
) {
2721 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2722 "bound\n", prim_walk
, i
);
2725 if (size
> radeon_object_size(track
->arrays
[i
].robj
)) {
2726 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2727 "have %lu dwords\n", prim_walk
, i
, size
>> 2,
2728 radeon_object_size(track
->arrays
[i
].robj
) >> 2);
2734 size
= track
->vtx_size
* nverts
;
2735 if (size
!= track
->immd_dwords
) {
2736 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2737 track
->immd_dwords
, size
);
2738 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2739 nverts
, track
->vtx_size
);
2744 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2748 return r100_cs_track_texture_check(rdev
, track
);
2751 void r100_cs_track_clear(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
2755 if (rdev
->family
< CHIP_R300
) {
2757 if (rdev
->family
<= CHIP_RS200
)
2758 track
->num_texture
= 3;
2760 track
->num_texture
= 6;
2762 track
->separate_cube
= 1;
2765 track
->num_texture
= 16;
2767 track
->separate_cube
= 0;
2770 for (i
= 0; i
< track
->num_cb
; i
++) {
2771 track
->cb
[i
].robj
= NULL
;
2772 track
->cb
[i
].pitch
= 8192;
2773 track
->cb
[i
].cpp
= 16;
2774 track
->cb
[i
].offset
= 0;
2776 track
->z_enabled
= true;
2777 track
->zb
.robj
= NULL
;
2778 track
->zb
.pitch
= 8192;
2780 track
->zb
.offset
= 0;
2781 track
->vtx_size
= 0x7F;
2782 track
->immd_dwords
= 0xFFFFFFFFUL
;
2783 track
->num_arrays
= 11;
2784 track
->max_indx
= 0x00FFFFFFUL
;
2785 for (i
= 0; i
< track
->num_arrays
; i
++) {
2786 track
->arrays
[i
].robj
= NULL
;
2787 track
->arrays
[i
].esize
= 0x7F;
2789 for (i
= 0; i
< track
->num_texture
; i
++) {
2790 track
->textures
[i
].pitch
= 16536;
2791 track
->textures
[i
].width
= 16536;
2792 track
->textures
[i
].height
= 16536;
2793 track
->textures
[i
].width_11
= 1 << 11;
2794 track
->textures
[i
].height_11
= 1 << 11;
2795 track
->textures
[i
].num_levels
= 12;
2796 if (rdev
->family
<= CHIP_RS200
) {
2797 track
->textures
[i
].tex_coord_type
= 0;
2798 track
->textures
[i
].txdepth
= 0;
2800 track
->textures
[i
].txdepth
= 16;
2801 track
->textures
[i
].tex_coord_type
= 1;
2803 track
->textures
[i
].cpp
= 64;
2804 track
->textures
[i
].robj
= NULL
;
2805 /* CS IB emission code makes sure texture unit are disabled */
2806 track
->textures
[i
].enabled
= false;
2807 track
->textures
[i
].roundup_w
= true;
2808 track
->textures
[i
].roundup_h
= true;
2809 if (track
->separate_cube
)
2810 for (face
= 0; face
< 5; face
++) {
2811 track
->textures
[i
].cube_info
[face
].robj
= NULL
;
2812 track
->textures
[i
].cube_info
[face
].width
= 16536;
2813 track
->textures
[i
].cube_info
[face
].height
= 16536;
2814 track
->textures
[i
].cube_info
[face
].offset
= 0;
2819 int r100_ring_test(struct radeon_device
*rdev
)
2826 r
= radeon_scratch_get(rdev
, &scratch
);
2828 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
2831 WREG32(scratch
, 0xCAFEDEAD);
2832 r
= radeon_ring_lock(rdev
, 2);
2834 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2835 radeon_scratch_free(rdev
, scratch
);
2838 radeon_ring_write(rdev
, PACKET0(scratch
, 0));
2839 radeon_ring_write(rdev
, 0xDEADBEEF);
2840 radeon_ring_unlock_commit(rdev
);
2841 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2842 tmp
= RREG32(scratch
);
2843 if (tmp
== 0xDEADBEEF) {
2848 if (i
< rdev
->usec_timeout
) {
2849 DRM_INFO("ring test succeeded in %d usecs\n", i
);
2851 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
2855 radeon_scratch_free(rdev
, scratch
);
2859 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
2861 radeon_ring_write(rdev
, PACKET0(RADEON_CP_IB_BASE
, 1));
2862 radeon_ring_write(rdev
, ib
->gpu_addr
);
2863 radeon_ring_write(rdev
, ib
->length_dw
);
2866 int r100_ib_test(struct radeon_device
*rdev
)
2868 struct radeon_ib
*ib
;
2874 r
= radeon_scratch_get(rdev
, &scratch
);
2876 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
2879 WREG32(scratch
, 0xCAFEDEAD);
2880 r
= radeon_ib_get(rdev
, &ib
);
2884 ib
->ptr
[0] = PACKET0(scratch
, 0);
2885 ib
->ptr
[1] = 0xDEADBEEF;
2886 ib
->ptr
[2] = PACKET2(0);
2887 ib
->ptr
[3] = PACKET2(0);
2888 ib
->ptr
[4] = PACKET2(0);
2889 ib
->ptr
[5] = PACKET2(0);
2890 ib
->ptr
[6] = PACKET2(0);
2891 ib
->ptr
[7] = PACKET2(0);
2893 r
= radeon_ib_schedule(rdev
, ib
);
2895 radeon_scratch_free(rdev
, scratch
);
2896 radeon_ib_free(rdev
, &ib
);
2899 r
= radeon_fence_wait(ib
->fence
, false);
2903 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2904 tmp
= RREG32(scratch
);
2905 if (tmp
== 0xDEADBEEF) {
2910 if (i
< rdev
->usec_timeout
) {
2911 DRM_INFO("ib test succeeded in %u usecs\n", i
);
2913 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2917 radeon_scratch_free(rdev
, scratch
);
2918 radeon_ib_free(rdev
, &ib
);
2922 void r100_ib_fini(struct radeon_device
*rdev
)
2924 radeon_ib_pool_fini(rdev
);
2927 int r100_ib_init(struct radeon_device
*rdev
)
2931 r
= radeon_ib_pool_init(rdev
);
2933 dev_err(rdev
->dev
, "failled initializing IB pool (%d).\n", r
);
2937 r
= r100_ib_test(rdev
);
2939 dev_err(rdev
->dev
, "failled testing IB (%d).\n", r
);
2946 void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
2948 /* Shutdown CP we shouldn't need to do that but better be safe than
2951 rdev
->cp
.ready
= false;
2952 WREG32(R_000740_CP_CSQ_CNTL
, 0);
2954 /* Save few CRTC registers */
2955 save
->GENMO_WT
= RREG8(R_0003C2_GENMO_WT
);
2956 save
->CRTC_EXT_CNTL
= RREG32(R_000054_CRTC_EXT_CNTL
);
2957 save
->CRTC_GEN_CNTL
= RREG32(R_000050_CRTC_GEN_CNTL
);
2958 save
->CUR_OFFSET
= RREG32(R_000260_CUR_OFFSET
);
2959 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
2960 save
->CRTC2_GEN_CNTL
= RREG32(R_0003F8_CRTC2_GEN_CNTL
);
2961 save
->CUR2_OFFSET
= RREG32(R_000360_CUR2_OFFSET
);
2964 /* Disable VGA aperture access */
2965 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& save
->GENMO_WT
);
2966 /* Disable cursor, overlay, crtc */
2967 WREG32(R_000260_CUR_OFFSET
, save
->CUR_OFFSET
| S_000260_CUR_LOCK(1));
2968 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
|
2969 S_000054_CRTC_DISPLAY_DIS(1));
2970 WREG32(R_000050_CRTC_GEN_CNTL
,
2971 (C_000050_CRTC_CUR_EN
& save
->CRTC_GEN_CNTL
) |
2972 S_000050_CRTC_DISP_REQ_EN_B(1));
2973 WREG32(R_000420_OV0_SCALE_CNTL
,
2974 C_000420_OV0_OVERLAY_EN
& RREG32(R_000420_OV0_SCALE_CNTL
));
2975 WREG32(R_000260_CUR_OFFSET
, C_000260_CUR_LOCK
& save
->CUR_OFFSET
);
2976 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
2977 WREG32(R_000360_CUR2_OFFSET
, save
->CUR2_OFFSET
|
2978 S_000360_CUR2_LOCK(1));
2979 WREG32(R_0003F8_CRTC2_GEN_CNTL
,
2980 (C_0003F8_CRTC2_CUR_EN
& save
->CRTC2_GEN_CNTL
) |
2981 S_0003F8_CRTC2_DISPLAY_DIS(1) |
2982 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
2983 WREG32(R_000360_CUR2_OFFSET
,
2984 C_000360_CUR2_LOCK
& save
->CUR2_OFFSET
);
2988 void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
2990 /* Update base address for crtc */
2991 WREG32(R_00023C_DISPLAY_BASE_ADDR
, rdev
->mc
.vram_location
);
2992 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
2993 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR
,
2994 rdev
->mc
.vram_location
);
2996 /* Restore CRTC registers */
2997 WREG8(R_0003C2_GENMO_WT
, save
->GENMO_WT
);
2998 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
);
2999 WREG32(R_000050_CRTC_GEN_CNTL
, save
->CRTC_GEN_CNTL
);
3000 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3001 WREG32(R_0003F8_CRTC2_GEN_CNTL
, save
->CRTC2_GEN_CNTL
);
3005 void r100_vga_render_disable(struct radeon_device
*rdev
)
3009 tmp
= RREG8(R_0003C2_GENMO_WT
);
3010 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& tmp
);
3013 static void r100_debugfs(struct radeon_device
*rdev
)
3017 r
= r100_debugfs_mc_info_init(rdev
);
3019 dev_warn(rdev
->dev
, "Failed to create r100_mc debugfs file.\n");
3022 static void r100_mc_program(struct radeon_device
*rdev
)
3024 struct r100_mc_save save
;
3026 /* Stops all mc clients */
3027 r100_mc_stop(rdev
, &save
);
3028 if (rdev
->flags
& RADEON_IS_AGP
) {
3029 WREG32(R_00014C_MC_AGP_LOCATION
,
3030 S_00014C_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
3031 S_00014C_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
3032 WREG32(R_000170_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
3033 if (rdev
->family
> CHIP_RV200
)
3034 WREG32(R_00015C_AGP_BASE_2
,
3035 upper_32_bits(rdev
->mc
.agp_base
) & 0xff);
3037 WREG32(R_00014C_MC_AGP_LOCATION
, 0x0FFFFFFF);
3038 WREG32(R_000170_AGP_BASE
, 0);
3039 if (rdev
->family
> CHIP_RV200
)
3040 WREG32(R_00015C_AGP_BASE_2
, 0);
3042 /* Wait for mc idle */
3043 if (r100_mc_wait_for_idle(rdev
))
3044 dev_warn(rdev
->dev
, "Wait for MC idle timeout.\n");
3045 /* Program MC, should be a 32bits limited address space */
3046 WREG32(R_000148_MC_FB_LOCATION
,
3047 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
3048 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
3049 r100_mc_resume(rdev
, &save
);
3052 void r100_clock_startup(struct radeon_device
*rdev
)
3056 if (radeon_dynclks
!= -1 && radeon_dynclks
)
3057 radeon_legacy_set_clock_gating(rdev
, 1);
3058 /* We need to force on some of the block */
3059 tmp
= RREG32_PLL(R_00000D_SCLK_CNTL
);
3060 tmp
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3061 if ((rdev
->family
== CHIP_RV250
) || (rdev
->family
== CHIP_RV280
))
3062 tmp
|= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3063 WREG32_PLL(R_00000D_SCLK_CNTL
, tmp
);
3066 static int r100_startup(struct radeon_device
*rdev
)
3070 r100_mc_program(rdev
);
3072 r100_clock_startup(rdev
);
3073 /* Initialize GPU configuration (# pipes, ...) */
3074 r100_gpu_init(rdev
);
3075 /* Initialize GART (initialize after TTM so we can allocate
3076 * memory through TTM but finalize after TTM) */
3077 if (rdev
->flags
& RADEON_IS_PCI
) {
3078 r
= r100_pci_gart_enable(rdev
);
3083 rdev
->irq
.sw_int
= true;
3085 /* 1M ring buffer */
3086 r
= r100_cp_init(rdev
, 1024 * 1024);
3088 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
3091 r
= r100_wb_init(rdev
);
3093 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
3094 r
= r100_ib_init(rdev
);
3096 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
3102 int r100_resume(struct radeon_device
*rdev
)
3104 /* Make sur GART are not working */
3105 if (rdev
->flags
& RADEON_IS_PCI
)
3106 r100_pci_gart_disable(rdev
);
3107 /* Resume clock before doing reset */
3108 r100_clock_startup(rdev
);
3109 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3110 if (radeon_gpu_reset(rdev
)) {
3111 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3112 RREG32(R_000E40_RBBM_STATUS
),
3113 RREG32(R_0007C0_CP_STAT
));
3116 radeon_combios_asic_init(rdev
->ddev
);
3117 /* Resume clock after posting */
3118 r100_clock_startup(rdev
);
3119 return r100_startup(rdev
);
3122 int r100_suspend(struct radeon_device
*rdev
)
3124 r100_cp_disable(rdev
);
3125 r100_wb_disable(rdev
);
3126 r100_irq_disable(rdev
);
3127 if (rdev
->flags
& RADEON_IS_PCI
)
3128 r100_pci_gart_disable(rdev
);
3132 void r100_fini(struct radeon_device
*rdev
)
3138 radeon_gem_fini(rdev
);
3139 if (rdev
->flags
& RADEON_IS_PCI
)
3140 r100_pci_gart_fini(rdev
);
3141 radeon_irq_kms_fini(rdev
);
3142 radeon_fence_driver_fini(rdev
);
3143 radeon_object_fini(rdev
);
3144 radeon_atombios_fini(rdev
);
3149 int r100_mc_init(struct radeon_device
*rdev
)
3154 /* Setup GPU memory space */
3155 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
3156 rdev
->mc
.gtt_location
= 0xFFFFFFFFUL
;
3157 if (rdev
->flags
& RADEON_IS_IGP
) {
3158 tmp
= G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM
));
3159 rdev
->mc
.vram_location
= tmp
<< 16;
3161 if (rdev
->flags
& RADEON_IS_AGP
) {
3162 r
= radeon_agp_init(rdev
);
3164 printk(KERN_WARNING
"[drm] Disabling AGP\n");
3165 rdev
->flags
&= ~RADEON_IS_AGP
;
3166 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
3168 rdev
->mc
.gtt_location
= rdev
->mc
.agp_base
;
3171 r
= radeon_mc_setup(rdev
);
3177 int r100_init(struct radeon_device
*rdev
)
3181 /* Register debugfs file specific to this group of asics */
3184 r100_vga_render_disable(rdev
);
3185 /* Initialize scratch registers */
3186 radeon_scratch_init(rdev
);
3187 /* Initialize surface registers */
3188 radeon_surface_init(rdev
);
3189 /* TODO: disable VGA need to use VGA request */
3191 if (!radeon_get_bios(rdev
)) {
3192 if (ASIC_IS_AVIVO(rdev
))
3195 if (rdev
->is_atom_bios
) {
3196 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
3199 r
= radeon_combios_init(rdev
);
3203 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3204 if (radeon_gpu_reset(rdev
)) {
3206 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3207 RREG32(R_000E40_RBBM_STATUS
),
3208 RREG32(R_0007C0_CP_STAT
));
3210 /* check if cards are posted or not */
3211 if (!radeon_card_posted(rdev
) && rdev
->bios
) {
3212 DRM_INFO("GPU not posted. posting now...\n");
3213 radeon_combios_asic_init(rdev
->ddev
);
3215 /* Set asic errata */
3217 /* Initialize clocks */
3218 radeon_get_clock_info(rdev
->ddev
);
3219 /* Get vram informations */
3220 r100_vram_info(rdev
);
3221 /* Initialize memory controller (also test AGP) */
3222 r
= r100_mc_init(rdev
);
3226 r
= radeon_fence_driver_init(rdev
);
3229 r
= radeon_irq_kms_init(rdev
);
3232 /* Memory manager */
3233 r
= radeon_object_init(rdev
);
3236 if (rdev
->flags
& RADEON_IS_PCI
) {
3237 r
= r100_pci_gart_init(rdev
);
3241 r100_set_safe_registers(rdev
);
3242 rdev
->accel_working
= true;
3243 r
= r100_startup(rdev
);
3245 /* Somethings want wront with the accel init stop accel */
3246 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
3251 if (rdev
->flags
& RADEON_IS_PCI
)
3252 r100_pci_gart_fini(rdev
);
3253 radeon_irq_kms_fini(rdev
);
3254 rdev
->accel_working
= false;