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Merge tag 'jfs-3.12' of git://github.com/kleikamp/linux-shaggy
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "r100d.h"
36 #include "rs100d.h"
37 #include "rv200d.h"
38 #include "rv250d.h"
39 #include "atom.h"
40
41 #include <linux/firmware.h>
42 #include <linux/module.h>
43
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
46
47 /* Firmware Names */
48 #define FIRMWARE_R100 "radeon/R100_cp.bin"
49 #define FIRMWARE_R200 "radeon/R200_cp.bin"
50 #define FIRMWARE_R300 "radeon/R300_cp.bin"
51 #define FIRMWARE_R420 "radeon/R420_cp.bin"
52 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54 #define FIRMWARE_R520 "radeon/R520_cp.bin"
55
56 MODULE_FIRMWARE(FIRMWARE_R100);
57 MODULE_FIRMWARE(FIRMWARE_R200);
58 MODULE_FIRMWARE(FIRMWARE_R300);
59 MODULE_FIRMWARE(FIRMWARE_R420);
60 MODULE_FIRMWARE(FIRMWARE_RS690);
61 MODULE_FIRMWARE(FIRMWARE_RS600);
62 MODULE_FIRMWARE(FIRMWARE_R520);
63
64 #include "r100_track.h"
65
66 /* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
69 */
70
71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
72 {
73 if (crtc == 0) {
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
75 return true;
76 else
77 return false;
78 } else {
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
80 return true;
81 else
82 return false;
83 }
84 }
85
86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
87 {
88 u32 vline1, vline2;
89
90 if (crtc == 0) {
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 } else {
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 }
97 if (vline1 != vline2)
98 return true;
99 else
100 return false;
101 }
102
103 /**
104 * r100_wait_for_vblank - vblank wait asic callback.
105 *
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
108 *
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
110 */
111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
112 {
113 unsigned i = 0;
114
115 if (crtc >= rdev->num_crtc)
116 return;
117
118 if (crtc == 0) {
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
120 return;
121 } else {
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
123 return;
124 }
125
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
128 */
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
132 break;
133 }
134 }
135
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
139 break;
140 }
141 }
142 }
143
144 /**
145 * r100_pre_page_flip - pre-pageflip callback.
146 *
147 * @rdev: radeon_device pointer
148 * @crtc: crtc to prepare for pageflip on
149 *
150 * Pre-pageflip callback (r1xx-r4xx).
151 * Enables the pageflip irq (vblank irq).
152 */
153 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
154 {
155 /* enable the pflip int */
156 radeon_irq_kms_pflip_irq_get(rdev, crtc);
157 }
158
159 /**
160 * r100_post_page_flip - pos-pageflip callback.
161 *
162 * @rdev: radeon_device pointer
163 * @crtc: crtc to cleanup pageflip on
164 *
165 * Post-pageflip callback (r1xx-r4xx).
166 * Disables the pageflip irq (vblank irq).
167 */
168 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
169 {
170 /* disable the pflip int */
171 radeon_irq_kms_pflip_irq_put(rdev, crtc);
172 }
173
174 /**
175 * r100_page_flip - pageflip callback.
176 *
177 * @rdev: radeon_device pointer
178 * @crtc_id: crtc to cleanup pageflip on
179 * @crtc_base: new address of the crtc (GPU MC address)
180 *
181 * Does the actual pageflip (r1xx-r4xx).
182 * During vblank we take the crtc lock and wait for the update_pending
183 * bit to go high, when it does, we release the lock, and allow the
184 * double buffered update to take place.
185 * Returns the current update pending status.
186 */
187 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
188 {
189 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
190 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
191 int i;
192
193 /* Lock the graphics update lock */
194 /* update the scanout addresses */
195 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
196
197 /* Wait for update_pending to go high. */
198 for (i = 0; i < rdev->usec_timeout; i++) {
199 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
200 break;
201 udelay(1);
202 }
203 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
204
205 /* Unlock the lock, so double-buffering can take place inside vblank */
206 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
207 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
208
209 /* Return current update_pending status: */
210 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
211 }
212
213 /**
214 * r100_pm_get_dynpm_state - look up dynpm power state callback.
215 *
216 * @rdev: radeon_device pointer
217 *
218 * Look up the optimal power state based on the
219 * current state of the GPU (r1xx-r5xx).
220 * Used for dynpm only.
221 */
222 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
223 {
224 int i;
225 rdev->pm.dynpm_can_upclock = true;
226 rdev->pm.dynpm_can_downclock = true;
227
228 switch (rdev->pm.dynpm_planned_action) {
229 case DYNPM_ACTION_MINIMUM:
230 rdev->pm.requested_power_state_index = 0;
231 rdev->pm.dynpm_can_downclock = false;
232 break;
233 case DYNPM_ACTION_DOWNCLOCK:
234 if (rdev->pm.current_power_state_index == 0) {
235 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
236 rdev->pm.dynpm_can_downclock = false;
237 } else {
238 if (rdev->pm.active_crtc_count > 1) {
239 for (i = 0; i < rdev->pm.num_power_states; i++) {
240 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
241 continue;
242 else if (i >= rdev->pm.current_power_state_index) {
243 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
244 break;
245 } else {
246 rdev->pm.requested_power_state_index = i;
247 break;
248 }
249 }
250 } else
251 rdev->pm.requested_power_state_index =
252 rdev->pm.current_power_state_index - 1;
253 }
254 /* don't use the power state if crtcs are active and no display flag is set */
255 if ((rdev->pm.active_crtc_count > 0) &&
256 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
257 RADEON_PM_MODE_NO_DISPLAY)) {
258 rdev->pm.requested_power_state_index++;
259 }
260 break;
261 case DYNPM_ACTION_UPCLOCK:
262 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
264 rdev->pm.dynpm_can_upclock = false;
265 } else {
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
269 continue;
270 else if (i <= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
272 break;
273 } else {
274 rdev->pm.requested_power_state_index = i;
275 break;
276 }
277 }
278 } else
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index + 1;
281 }
282 break;
283 case DYNPM_ACTION_DEFAULT:
284 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
285 rdev->pm.dynpm_can_upclock = false;
286 break;
287 case DYNPM_ACTION_NONE:
288 default:
289 DRM_ERROR("Requested mode for not defined action\n");
290 return;
291 }
292 /* only one clock mode per power state */
293 rdev->pm.requested_clock_mode_index = 0;
294
295 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
297 clock_info[rdev->pm.requested_clock_mode_index].sclk,
298 rdev->pm.power_state[rdev->pm.requested_power_state_index].
299 clock_info[rdev->pm.requested_clock_mode_index].mclk,
300 rdev->pm.power_state[rdev->pm.requested_power_state_index].
301 pcie_lanes);
302 }
303
304 /**
305 * r100_pm_init_profile - Initialize power profiles callback.
306 *
307 * @rdev: radeon_device pointer
308 *
309 * Initialize the power states used in profile mode
310 * (r1xx-r3xx).
311 * Used for profile mode only.
312 */
313 void r100_pm_init_profile(struct radeon_device *rdev)
314 {
315 /* default */
316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
320 /* low sh */
321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
325 /* mid sh */
326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
330 /* high sh */
331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
335 /* low mh */
336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
340 /* mid mh */
341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
345 /* high mh */
346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
350 }
351
352 /**
353 * r100_pm_misc - set additional pm hw parameters callback.
354 *
355 * @rdev: radeon_device pointer
356 *
357 * Set non-clock parameters associated with a power state
358 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
359 */
360 void r100_pm_misc(struct radeon_device *rdev)
361 {
362 int requested_index = rdev->pm.requested_power_state_index;
363 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
364 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
365 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
366
367 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
368 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
369 tmp = RREG32(voltage->gpio.reg);
370 if (voltage->active_high)
371 tmp |= voltage->gpio.mask;
372 else
373 tmp &= ~(voltage->gpio.mask);
374 WREG32(voltage->gpio.reg, tmp);
375 if (voltage->delay)
376 udelay(voltage->delay);
377 } else {
378 tmp = RREG32(voltage->gpio.reg);
379 if (voltage->active_high)
380 tmp &= ~voltage->gpio.mask;
381 else
382 tmp |= voltage->gpio.mask;
383 WREG32(voltage->gpio.reg, tmp);
384 if (voltage->delay)
385 udelay(voltage->delay);
386 }
387 }
388
389 sclk_cntl = RREG32_PLL(SCLK_CNTL);
390 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
391 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
392 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
393 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
394 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
395 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
396 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
397 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
398 else
399 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
400 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
401 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
402 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
403 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
404 } else
405 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
406
407 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
408 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
409 if (voltage->delay) {
410 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
411 switch (voltage->delay) {
412 case 33:
413 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
414 break;
415 case 66:
416 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
417 break;
418 case 99:
419 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
420 break;
421 case 132:
422 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
423 break;
424 }
425 } else
426 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
427 } else
428 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
429
430 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
431 sclk_cntl &= ~FORCE_HDP;
432 else
433 sclk_cntl |= FORCE_HDP;
434
435 WREG32_PLL(SCLK_CNTL, sclk_cntl);
436 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
437 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
438
439 /* set pcie lanes */
440 if ((rdev->flags & RADEON_IS_PCIE) &&
441 !(rdev->flags & RADEON_IS_IGP) &&
442 rdev->asic->pm.set_pcie_lanes &&
443 (ps->pcie_lanes !=
444 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
445 radeon_set_pcie_lanes(rdev,
446 ps->pcie_lanes);
447 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
448 }
449 }
450
451 /**
452 * r100_pm_prepare - pre-power state change callback.
453 *
454 * @rdev: radeon_device pointer
455 *
456 * Prepare for a power state change (r1xx-r4xx).
457 */
458 void r100_pm_prepare(struct radeon_device *rdev)
459 {
460 struct drm_device *ddev = rdev->ddev;
461 struct drm_crtc *crtc;
462 struct radeon_crtc *radeon_crtc;
463 u32 tmp;
464
465 /* disable any active CRTCs */
466 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
467 radeon_crtc = to_radeon_crtc(crtc);
468 if (radeon_crtc->enabled) {
469 if (radeon_crtc->crtc_id) {
470 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
471 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
472 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
473 } else {
474 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
475 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
477 }
478 }
479 }
480 }
481
482 /**
483 * r100_pm_finish - post-power state change callback.
484 *
485 * @rdev: radeon_device pointer
486 *
487 * Clean up after a power state change (r1xx-r4xx).
488 */
489 void r100_pm_finish(struct radeon_device *rdev)
490 {
491 struct drm_device *ddev = rdev->ddev;
492 struct drm_crtc *crtc;
493 struct radeon_crtc *radeon_crtc;
494 u32 tmp;
495
496 /* enable any active CRTCs */
497 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
498 radeon_crtc = to_radeon_crtc(crtc);
499 if (radeon_crtc->enabled) {
500 if (radeon_crtc->crtc_id) {
501 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
502 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
503 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
504 } else {
505 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
506 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
507 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
508 }
509 }
510 }
511 }
512
513 /**
514 * r100_gui_idle - gui idle callback.
515 *
516 * @rdev: radeon_device pointer
517 *
518 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
519 * Returns true if idle, false if not.
520 */
521 bool r100_gui_idle(struct radeon_device *rdev)
522 {
523 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
524 return false;
525 else
526 return true;
527 }
528
529 /* hpd for digital panel detect/disconnect */
530 /**
531 * r100_hpd_sense - hpd sense callback.
532 *
533 * @rdev: radeon_device pointer
534 * @hpd: hpd (hotplug detect) pin
535 *
536 * Checks if a digital monitor is connected (r1xx-r4xx).
537 * Returns true if connected, false if not connected.
538 */
539 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
540 {
541 bool connected = false;
542
543 switch (hpd) {
544 case RADEON_HPD_1:
545 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
546 connected = true;
547 break;
548 case RADEON_HPD_2:
549 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
550 connected = true;
551 break;
552 default:
553 break;
554 }
555 return connected;
556 }
557
558 /**
559 * r100_hpd_set_polarity - hpd set polarity callback.
560 *
561 * @rdev: radeon_device pointer
562 * @hpd: hpd (hotplug detect) pin
563 *
564 * Set the polarity of the hpd pin (r1xx-r4xx).
565 */
566 void r100_hpd_set_polarity(struct radeon_device *rdev,
567 enum radeon_hpd_id hpd)
568 {
569 u32 tmp;
570 bool connected = r100_hpd_sense(rdev, hpd);
571
572 switch (hpd) {
573 case RADEON_HPD_1:
574 tmp = RREG32(RADEON_FP_GEN_CNTL);
575 if (connected)
576 tmp &= ~RADEON_FP_DETECT_INT_POL;
577 else
578 tmp |= RADEON_FP_DETECT_INT_POL;
579 WREG32(RADEON_FP_GEN_CNTL, tmp);
580 break;
581 case RADEON_HPD_2:
582 tmp = RREG32(RADEON_FP2_GEN_CNTL);
583 if (connected)
584 tmp &= ~RADEON_FP2_DETECT_INT_POL;
585 else
586 tmp |= RADEON_FP2_DETECT_INT_POL;
587 WREG32(RADEON_FP2_GEN_CNTL, tmp);
588 break;
589 default:
590 break;
591 }
592 }
593
594 /**
595 * r100_hpd_init - hpd setup callback.
596 *
597 * @rdev: radeon_device pointer
598 *
599 * Setup the hpd pins used by the card (r1xx-r4xx).
600 * Set the polarity, and enable the hpd interrupts.
601 */
602 void r100_hpd_init(struct radeon_device *rdev)
603 {
604 struct drm_device *dev = rdev->ddev;
605 struct drm_connector *connector;
606 unsigned enable = 0;
607
608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
610 enable |= 1 << radeon_connector->hpd.hpd;
611 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
612 }
613 radeon_irq_kms_enable_hpd(rdev, enable);
614 }
615
616 /**
617 * r100_hpd_fini - hpd tear down callback.
618 *
619 * @rdev: radeon_device pointer
620 *
621 * Tear down the hpd pins used by the card (r1xx-r4xx).
622 * Disable the hpd interrupts.
623 */
624 void r100_hpd_fini(struct radeon_device *rdev)
625 {
626 struct drm_device *dev = rdev->ddev;
627 struct drm_connector *connector;
628 unsigned disable = 0;
629
630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
631 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
632 disable |= 1 << radeon_connector->hpd.hpd;
633 }
634 radeon_irq_kms_disable_hpd(rdev, disable);
635 }
636
637 /*
638 * PCI GART
639 */
640 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
641 {
642 /* TODO: can we do somethings here ? */
643 /* It seems hw only cache one entry so we should discard this
644 * entry otherwise if first GPU GART read hit this entry it
645 * could end up in wrong address. */
646 }
647
648 int r100_pci_gart_init(struct radeon_device *rdev)
649 {
650 int r;
651
652 if (rdev->gart.ptr) {
653 WARN(1, "R100 PCI GART already initialized\n");
654 return 0;
655 }
656 /* Initialize common gart structure */
657 r = radeon_gart_init(rdev);
658 if (r)
659 return r;
660 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
661 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
662 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
663 return radeon_gart_table_ram_alloc(rdev);
664 }
665
666 int r100_pci_gart_enable(struct radeon_device *rdev)
667 {
668 uint32_t tmp;
669
670 radeon_gart_restore(rdev);
671 /* discard memory request outside of configured range */
672 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
673 WREG32(RADEON_AIC_CNTL, tmp);
674 /* set address range for PCI address translate */
675 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
676 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
677 /* set PCI GART page-table base address */
678 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
680 WREG32(RADEON_AIC_CNTL, tmp);
681 r100_pci_gart_tlb_flush(rdev);
682 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
683 (unsigned)(rdev->mc.gtt_size >> 20),
684 (unsigned long long)rdev->gart.table_addr);
685 rdev->gart.ready = true;
686 return 0;
687 }
688
689 void r100_pci_gart_disable(struct radeon_device *rdev)
690 {
691 uint32_t tmp;
692
693 /* discard memory request outside of configured range */
694 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
695 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
696 WREG32(RADEON_AIC_LO_ADDR, 0);
697 WREG32(RADEON_AIC_HI_ADDR, 0);
698 }
699
700 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
701 {
702 u32 *gtt = rdev->gart.ptr;
703
704 if (i < 0 || i > rdev->gart.num_gpu_pages) {
705 return -EINVAL;
706 }
707 gtt[i] = cpu_to_le32(lower_32_bits(addr));
708 return 0;
709 }
710
711 void r100_pci_gart_fini(struct radeon_device *rdev)
712 {
713 radeon_gart_fini(rdev);
714 r100_pci_gart_disable(rdev);
715 radeon_gart_table_ram_free(rdev);
716 }
717
718 int r100_irq_set(struct radeon_device *rdev)
719 {
720 uint32_t tmp = 0;
721
722 if (!rdev->irq.installed) {
723 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
724 WREG32(R_000040_GEN_INT_CNTL, 0);
725 return -EINVAL;
726 }
727 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
728 tmp |= RADEON_SW_INT_ENABLE;
729 }
730 if (rdev->irq.crtc_vblank_int[0] ||
731 atomic_read(&rdev->irq.pflip[0])) {
732 tmp |= RADEON_CRTC_VBLANK_MASK;
733 }
734 if (rdev->irq.crtc_vblank_int[1] ||
735 atomic_read(&rdev->irq.pflip[1])) {
736 tmp |= RADEON_CRTC2_VBLANK_MASK;
737 }
738 if (rdev->irq.hpd[0]) {
739 tmp |= RADEON_FP_DETECT_MASK;
740 }
741 if (rdev->irq.hpd[1]) {
742 tmp |= RADEON_FP2_DETECT_MASK;
743 }
744 WREG32(RADEON_GEN_INT_CNTL, tmp);
745 return 0;
746 }
747
748 void r100_irq_disable(struct radeon_device *rdev)
749 {
750 u32 tmp;
751
752 WREG32(R_000040_GEN_INT_CNTL, 0);
753 /* Wait and acknowledge irq */
754 mdelay(1);
755 tmp = RREG32(R_000044_GEN_INT_STATUS);
756 WREG32(R_000044_GEN_INT_STATUS, tmp);
757 }
758
759 static uint32_t r100_irq_ack(struct radeon_device *rdev)
760 {
761 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
762 uint32_t irq_mask = RADEON_SW_INT_TEST |
763 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
764 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
765
766 if (irqs) {
767 WREG32(RADEON_GEN_INT_STATUS, irqs);
768 }
769 return irqs & irq_mask;
770 }
771
772 int r100_irq_process(struct radeon_device *rdev)
773 {
774 uint32_t status, msi_rearm;
775 bool queue_hotplug = false;
776
777 status = r100_irq_ack(rdev);
778 if (!status) {
779 return IRQ_NONE;
780 }
781 if (rdev->shutdown) {
782 return IRQ_NONE;
783 }
784 while (status) {
785 /* SW interrupt */
786 if (status & RADEON_SW_INT_TEST) {
787 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
788 }
789 /* Vertical blank interrupts */
790 if (status & RADEON_CRTC_VBLANK_STAT) {
791 if (rdev->irq.crtc_vblank_int[0]) {
792 drm_handle_vblank(rdev->ddev, 0);
793 rdev->pm.vblank_sync = true;
794 wake_up(&rdev->irq.vblank_queue);
795 }
796 if (atomic_read(&rdev->irq.pflip[0]))
797 radeon_crtc_handle_flip(rdev, 0);
798 }
799 if (status & RADEON_CRTC2_VBLANK_STAT) {
800 if (rdev->irq.crtc_vblank_int[1]) {
801 drm_handle_vblank(rdev->ddev, 1);
802 rdev->pm.vblank_sync = true;
803 wake_up(&rdev->irq.vblank_queue);
804 }
805 if (atomic_read(&rdev->irq.pflip[1]))
806 radeon_crtc_handle_flip(rdev, 1);
807 }
808 if (status & RADEON_FP_DETECT_STAT) {
809 queue_hotplug = true;
810 DRM_DEBUG("HPD1\n");
811 }
812 if (status & RADEON_FP2_DETECT_STAT) {
813 queue_hotplug = true;
814 DRM_DEBUG("HPD2\n");
815 }
816 status = r100_irq_ack(rdev);
817 }
818 if (queue_hotplug)
819 schedule_work(&rdev->hotplug_work);
820 if (rdev->msi_enabled) {
821 switch (rdev->family) {
822 case CHIP_RS400:
823 case CHIP_RS480:
824 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
825 WREG32(RADEON_AIC_CNTL, msi_rearm);
826 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
827 break;
828 default:
829 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
830 break;
831 }
832 }
833 return IRQ_HANDLED;
834 }
835
836 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
837 {
838 if (crtc == 0)
839 return RREG32(RADEON_CRTC_CRNT_FRAME);
840 else
841 return RREG32(RADEON_CRTC2_CRNT_FRAME);
842 }
843
844 /* Who ever call radeon_fence_emit should call ring_lock and ask
845 * for enough space (today caller are ib schedule and buffer move) */
846 void r100_fence_ring_emit(struct radeon_device *rdev,
847 struct radeon_fence *fence)
848 {
849 struct radeon_ring *ring = &rdev->ring[fence->ring];
850
851 /* We have to make sure that caches are flushed before
852 * CPU might read something from VRAM. */
853 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
854 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
855 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
856 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
857 /* Wait until IDLE & CLEAN */
858 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
859 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
860 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
862 RADEON_HDP_READ_BUFFER_INVALIDATE);
863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
865 /* Emit fence sequence & fire IRQ */
866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
867 radeon_ring_write(ring, fence->seq);
868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
869 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
870 }
871
872 void r100_semaphore_ring_emit(struct radeon_device *rdev,
873 struct radeon_ring *ring,
874 struct radeon_semaphore *semaphore,
875 bool emit_wait)
876 {
877 /* Unused on older asics, since we don't have semaphores or multiple rings */
878 BUG();
879 }
880
881 int r100_copy_blit(struct radeon_device *rdev,
882 uint64_t src_offset,
883 uint64_t dst_offset,
884 unsigned num_gpu_pages,
885 struct radeon_fence **fence)
886 {
887 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
888 uint32_t cur_pages;
889 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
890 uint32_t pitch;
891 uint32_t stride_pixels;
892 unsigned ndw;
893 int num_loops;
894 int r = 0;
895
896 /* radeon limited to 16k stride */
897 stride_bytes &= 0x3fff;
898 /* radeon pitch is /64 */
899 pitch = stride_bytes / 64;
900 stride_pixels = stride_bytes / 4;
901 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
902
903 /* Ask for enough room for blit + flush + fence */
904 ndw = 64 + (10 * num_loops);
905 r = radeon_ring_lock(rdev, ring, ndw);
906 if (r) {
907 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
908 return -EINVAL;
909 }
910 while (num_gpu_pages > 0) {
911 cur_pages = num_gpu_pages;
912 if (cur_pages > 8191) {
913 cur_pages = 8191;
914 }
915 num_gpu_pages -= cur_pages;
916
917 /* pages are in Y direction - height
918 page width in X direction - width */
919 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
920 radeon_ring_write(ring,
921 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
922 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
923 RADEON_GMC_SRC_CLIPPING |
924 RADEON_GMC_DST_CLIPPING |
925 RADEON_GMC_BRUSH_NONE |
926 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
927 RADEON_GMC_SRC_DATATYPE_COLOR |
928 RADEON_ROP3_S |
929 RADEON_DP_SRC_SOURCE_MEMORY |
930 RADEON_GMC_CLR_CMP_CNTL_DIS |
931 RADEON_GMC_WR_MSK_DIS);
932 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
933 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
934 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
935 radeon_ring_write(ring, 0);
936 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
937 radeon_ring_write(ring, num_gpu_pages);
938 radeon_ring_write(ring, num_gpu_pages);
939 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
940 }
941 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
942 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
943 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
944 radeon_ring_write(ring,
945 RADEON_WAIT_2D_IDLECLEAN |
946 RADEON_WAIT_HOST_IDLECLEAN |
947 RADEON_WAIT_DMA_GUI_IDLE);
948 if (fence) {
949 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
950 }
951 radeon_ring_unlock_commit(rdev, ring);
952 return r;
953 }
954
955 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
956 {
957 unsigned i;
958 u32 tmp;
959
960 for (i = 0; i < rdev->usec_timeout; i++) {
961 tmp = RREG32(R_000E40_RBBM_STATUS);
962 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
963 return 0;
964 }
965 udelay(1);
966 }
967 return -1;
968 }
969
970 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
971 {
972 int r;
973
974 r = radeon_ring_lock(rdev, ring, 2);
975 if (r) {
976 return;
977 }
978 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
979 radeon_ring_write(ring,
980 RADEON_ISYNC_ANY2D_IDLE3D |
981 RADEON_ISYNC_ANY3D_IDLE2D |
982 RADEON_ISYNC_WAIT_IDLEGUI |
983 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
984 radeon_ring_unlock_commit(rdev, ring);
985 }
986
987
988 /* Load the microcode for the CP */
989 static int r100_cp_init_microcode(struct radeon_device *rdev)
990 {
991 const char *fw_name = NULL;
992 int err;
993
994 DRM_DEBUG_KMS("\n");
995
996 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
997 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
998 (rdev->family == CHIP_RS200)) {
999 DRM_INFO("Loading R100 Microcode\n");
1000 fw_name = FIRMWARE_R100;
1001 } else if ((rdev->family == CHIP_R200) ||
1002 (rdev->family == CHIP_RV250) ||
1003 (rdev->family == CHIP_RV280) ||
1004 (rdev->family == CHIP_RS300)) {
1005 DRM_INFO("Loading R200 Microcode\n");
1006 fw_name = FIRMWARE_R200;
1007 } else if ((rdev->family == CHIP_R300) ||
1008 (rdev->family == CHIP_R350) ||
1009 (rdev->family == CHIP_RV350) ||
1010 (rdev->family == CHIP_RV380) ||
1011 (rdev->family == CHIP_RS400) ||
1012 (rdev->family == CHIP_RS480)) {
1013 DRM_INFO("Loading R300 Microcode\n");
1014 fw_name = FIRMWARE_R300;
1015 } else if ((rdev->family == CHIP_R420) ||
1016 (rdev->family == CHIP_R423) ||
1017 (rdev->family == CHIP_RV410)) {
1018 DRM_INFO("Loading R400 Microcode\n");
1019 fw_name = FIRMWARE_R420;
1020 } else if ((rdev->family == CHIP_RS690) ||
1021 (rdev->family == CHIP_RS740)) {
1022 DRM_INFO("Loading RS690/RS740 Microcode\n");
1023 fw_name = FIRMWARE_RS690;
1024 } else if (rdev->family == CHIP_RS600) {
1025 DRM_INFO("Loading RS600 Microcode\n");
1026 fw_name = FIRMWARE_RS600;
1027 } else if ((rdev->family == CHIP_RV515) ||
1028 (rdev->family == CHIP_R520) ||
1029 (rdev->family == CHIP_RV530) ||
1030 (rdev->family == CHIP_R580) ||
1031 (rdev->family == CHIP_RV560) ||
1032 (rdev->family == CHIP_RV570)) {
1033 DRM_INFO("Loading R500 Microcode\n");
1034 fw_name = FIRMWARE_R520;
1035 }
1036
1037 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1038 if (err) {
1039 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1040 fw_name);
1041 } else if (rdev->me_fw->size % 8) {
1042 printk(KERN_ERR
1043 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1044 rdev->me_fw->size, fw_name);
1045 err = -EINVAL;
1046 release_firmware(rdev->me_fw);
1047 rdev->me_fw = NULL;
1048 }
1049 return err;
1050 }
1051
1052 static void r100_cp_load_microcode(struct radeon_device *rdev)
1053 {
1054 const __be32 *fw_data;
1055 int i, size;
1056
1057 if (r100_gui_wait_for_idle(rdev)) {
1058 printk(KERN_WARNING "Failed to wait GUI idle while "
1059 "programming pipes. Bad things might happen.\n");
1060 }
1061
1062 if (rdev->me_fw) {
1063 size = rdev->me_fw->size / 4;
1064 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1065 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1066 for (i = 0; i < size; i += 2) {
1067 WREG32(RADEON_CP_ME_RAM_DATAH,
1068 be32_to_cpup(&fw_data[i]));
1069 WREG32(RADEON_CP_ME_RAM_DATAL,
1070 be32_to_cpup(&fw_data[i + 1]));
1071 }
1072 }
1073 }
1074
1075 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1076 {
1077 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1078 unsigned rb_bufsz;
1079 unsigned rb_blksz;
1080 unsigned max_fetch;
1081 unsigned pre_write_timer;
1082 unsigned pre_write_limit;
1083 unsigned indirect2_start;
1084 unsigned indirect1_start;
1085 uint32_t tmp;
1086 int r;
1087
1088 if (r100_debugfs_cp_init(rdev)) {
1089 DRM_ERROR("Failed to register debugfs file for CP !\n");
1090 }
1091 if (!rdev->me_fw) {
1092 r = r100_cp_init_microcode(rdev);
1093 if (r) {
1094 DRM_ERROR("Failed to load firmware!\n");
1095 return r;
1096 }
1097 }
1098
1099 /* Align ring size */
1100 rb_bufsz = order_base_2(ring_size / 8);
1101 ring_size = (1 << (rb_bufsz + 1)) * 4;
1102 r100_cp_load_microcode(rdev);
1103 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1104 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1105 RADEON_CP_PACKET2);
1106 if (r) {
1107 return r;
1108 }
1109 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1110 * the rptr copy in system ram */
1111 rb_blksz = 9;
1112 /* cp will read 128bytes at a time (4 dwords) */
1113 max_fetch = 1;
1114 ring->align_mask = 16 - 1;
1115 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1116 pre_write_timer = 64;
1117 /* Force CP_RB_WPTR write if written more than one time before the
1118 * delay expire
1119 */
1120 pre_write_limit = 0;
1121 /* Setup the cp cache like this (cache size is 96 dwords) :
1122 * RING 0 to 15
1123 * INDIRECT1 16 to 79
1124 * INDIRECT2 80 to 95
1125 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1126 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1127 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1128 * Idea being that most of the gpu cmd will be through indirect1 buffer
1129 * so it gets the bigger cache.
1130 */
1131 indirect2_start = 80;
1132 indirect1_start = 16;
1133 /* cp setup */
1134 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1135 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1136 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1137 REG_SET(RADEON_MAX_FETCH, max_fetch));
1138 #ifdef __BIG_ENDIAN
1139 tmp |= RADEON_BUF_SWAP_32BIT;
1140 #endif
1141 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1142
1143 /* Set ring address */
1144 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1145 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1146 /* Force read & write ptr to 0 */
1147 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1148 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1149 ring->wptr = 0;
1150 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1151
1152 /* set the wb address whether it's enabled or not */
1153 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1154 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1155 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1156
1157 if (rdev->wb.enabled)
1158 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1159 else {
1160 tmp |= RADEON_RB_NO_UPDATE;
1161 WREG32(R_000770_SCRATCH_UMSK, 0);
1162 }
1163
1164 WREG32(RADEON_CP_RB_CNTL, tmp);
1165 udelay(10);
1166 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1167 /* Set cp mode to bus mastering & enable cp*/
1168 WREG32(RADEON_CP_CSQ_MODE,
1169 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1170 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1171 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1172 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1173 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1174
1175 /* at this point everything should be setup correctly to enable master */
1176 pci_set_master(rdev->pdev);
1177
1178 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1179 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1180 if (r) {
1181 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1182 return r;
1183 }
1184 ring->ready = true;
1185 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1186
1187 if (!ring->rptr_save_reg /* not resuming from suspend */
1188 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1189 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1190 if (r) {
1191 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1192 ring->rptr_save_reg = 0;
1193 }
1194 }
1195 return 0;
1196 }
1197
1198 void r100_cp_fini(struct radeon_device *rdev)
1199 {
1200 if (r100_cp_wait_for_idle(rdev)) {
1201 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1202 }
1203 /* Disable ring */
1204 r100_cp_disable(rdev);
1205 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1206 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1207 DRM_INFO("radeon: cp finalized\n");
1208 }
1209
1210 void r100_cp_disable(struct radeon_device *rdev)
1211 {
1212 /* Disable ring */
1213 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1214 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1215 WREG32(RADEON_CP_CSQ_MODE, 0);
1216 WREG32(RADEON_CP_CSQ_CNTL, 0);
1217 WREG32(R_000770_SCRATCH_UMSK, 0);
1218 if (r100_gui_wait_for_idle(rdev)) {
1219 printk(KERN_WARNING "Failed to wait GUI idle while "
1220 "programming pipes. Bad things might happen.\n");
1221 }
1222 }
1223
1224 /*
1225 * CS functions
1226 */
1227 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1228 struct radeon_cs_packet *pkt,
1229 unsigned idx,
1230 unsigned reg)
1231 {
1232 int r;
1233 u32 tile_flags = 0;
1234 u32 tmp;
1235 struct radeon_cs_reloc *reloc;
1236 u32 value;
1237
1238 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1239 if (r) {
1240 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1241 idx, reg);
1242 radeon_cs_dump_packet(p, pkt);
1243 return r;
1244 }
1245
1246 value = radeon_get_ib_value(p, idx);
1247 tmp = value & 0x003fffff;
1248 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1249
1250 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1251 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1252 tile_flags |= RADEON_DST_TILE_MACRO;
1253 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1254 if (reg == RADEON_SRC_PITCH_OFFSET) {
1255 DRM_ERROR("Cannot src blit from microtiled surface\n");
1256 radeon_cs_dump_packet(p, pkt);
1257 return -EINVAL;
1258 }
1259 tile_flags |= RADEON_DST_TILE_MICRO;
1260 }
1261
1262 tmp |= tile_flags;
1263 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1264 } else
1265 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1266 return 0;
1267 }
1268
1269 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1270 struct radeon_cs_packet *pkt,
1271 int idx)
1272 {
1273 unsigned c, i;
1274 struct radeon_cs_reloc *reloc;
1275 struct r100_cs_track *track;
1276 int r = 0;
1277 volatile uint32_t *ib;
1278 u32 idx_value;
1279
1280 ib = p->ib.ptr;
1281 track = (struct r100_cs_track *)p->track;
1282 c = radeon_get_ib_value(p, idx++) & 0x1F;
1283 if (c > 16) {
1284 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1285 pkt->opcode);
1286 radeon_cs_dump_packet(p, pkt);
1287 return -EINVAL;
1288 }
1289 track->num_arrays = c;
1290 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1291 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1292 if (r) {
1293 DRM_ERROR("No reloc for packet3 %d\n",
1294 pkt->opcode);
1295 radeon_cs_dump_packet(p, pkt);
1296 return r;
1297 }
1298 idx_value = radeon_get_ib_value(p, idx);
1299 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1300
1301 track->arrays[i + 0].esize = idx_value >> 8;
1302 track->arrays[i + 0].robj = reloc->robj;
1303 track->arrays[i + 0].esize &= 0x7F;
1304 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1305 if (r) {
1306 DRM_ERROR("No reloc for packet3 %d\n",
1307 pkt->opcode);
1308 radeon_cs_dump_packet(p, pkt);
1309 return r;
1310 }
1311 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1312 track->arrays[i + 1].robj = reloc->robj;
1313 track->arrays[i + 1].esize = idx_value >> 24;
1314 track->arrays[i + 1].esize &= 0x7F;
1315 }
1316 if (c & 1) {
1317 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1318 if (r) {
1319 DRM_ERROR("No reloc for packet3 %d\n",
1320 pkt->opcode);
1321 radeon_cs_dump_packet(p, pkt);
1322 return r;
1323 }
1324 idx_value = radeon_get_ib_value(p, idx);
1325 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1326 track->arrays[i + 0].robj = reloc->robj;
1327 track->arrays[i + 0].esize = idx_value >> 8;
1328 track->arrays[i + 0].esize &= 0x7F;
1329 }
1330 return r;
1331 }
1332
1333 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1334 struct radeon_cs_packet *pkt,
1335 const unsigned *auth, unsigned n,
1336 radeon_packet0_check_t check)
1337 {
1338 unsigned reg;
1339 unsigned i, j, m;
1340 unsigned idx;
1341 int r;
1342
1343 idx = pkt->idx + 1;
1344 reg = pkt->reg;
1345 /* Check that register fall into register range
1346 * determined by the number of entry (n) in the
1347 * safe register bitmap.
1348 */
1349 if (pkt->one_reg_wr) {
1350 if ((reg >> 7) > n) {
1351 return -EINVAL;
1352 }
1353 } else {
1354 if (((reg + (pkt->count << 2)) >> 7) > n) {
1355 return -EINVAL;
1356 }
1357 }
1358 for (i = 0; i <= pkt->count; i++, idx++) {
1359 j = (reg >> 7);
1360 m = 1 << ((reg >> 2) & 31);
1361 if (auth[j] & m) {
1362 r = check(p, pkt, idx, reg);
1363 if (r) {
1364 return r;
1365 }
1366 }
1367 if (pkt->one_reg_wr) {
1368 if (!(auth[j] & m)) {
1369 break;
1370 }
1371 } else {
1372 reg += 4;
1373 }
1374 }
1375 return 0;
1376 }
1377
1378 /**
1379 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1380 * @parser: parser structure holding parsing context.
1381 *
1382 * Userspace sends a special sequence for VLINE waits.
1383 * PACKET0 - VLINE_START_END + value
1384 * PACKET0 - WAIT_UNTIL +_value
1385 * RELOC (P3) - crtc_id in reloc.
1386 *
1387 * This function parses this and relocates the VLINE START END
1388 * and WAIT UNTIL packets to the correct crtc.
1389 * It also detects a switched off crtc and nulls out the
1390 * wait in that case.
1391 */
1392 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1393 {
1394 struct drm_mode_object *obj;
1395 struct drm_crtc *crtc;
1396 struct radeon_crtc *radeon_crtc;
1397 struct radeon_cs_packet p3reloc, waitreloc;
1398 int crtc_id;
1399 int r;
1400 uint32_t header, h_idx, reg;
1401 volatile uint32_t *ib;
1402
1403 ib = p->ib.ptr;
1404
1405 /* parse the wait until */
1406 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1407 if (r)
1408 return r;
1409
1410 /* check its a wait until and only 1 count */
1411 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1412 waitreloc.count != 0) {
1413 DRM_ERROR("vline wait had illegal wait until segment\n");
1414 return -EINVAL;
1415 }
1416
1417 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1418 DRM_ERROR("vline wait had illegal wait until\n");
1419 return -EINVAL;
1420 }
1421
1422 /* jump over the NOP */
1423 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1424 if (r)
1425 return r;
1426
1427 h_idx = p->idx - 2;
1428 p->idx += waitreloc.count + 2;
1429 p->idx += p3reloc.count + 2;
1430
1431 header = radeon_get_ib_value(p, h_idx);
1432 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1433 reg = R100_CP_PACKET0_GET_REG(header);
1434 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1435 if (!obj) {
1436 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1437 return -EINVAL;
1438 }
1439 crtc = obj_to_crtc(obj);
1440 radeon_crtc = to_radeon_crtc(crtc);
1441 crtc_id = radeon_crtc->crtc_id;
1442
1443 if (!crtc->enabled) {
1444 /* if the CRTC isn't enabled - we need to nop out the wait until */
1445 ib[h_idx + 2] = PACKET2(0);
1446 ib[h_idx + 3] = PACKET2(0);
1447 } else if (crtc_id == 1) {
1448 switch (reg) {
1449 case AVIVO_D1MODE_VLINE_START_END:
1450 header &= ~R300_CP_PACKET0_REG_MASK;
1451 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1452 break;
1453 case RADEON_CRTC_GUI_TRIG_VLINE:
1454 header &= ~R300_CP_PACKET0_REG_MASK;
1455 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1456 break;
1457 default:
1458 DRM_ERROR("unknown crtc reloc\n");
1459 return -EINVAL;
1460 }
1461 ib[h_idx] = header;
1462 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1463 }
1464
1465 return 0;
1466 }
1467
1468 static int r100_get_vtx_size(uint32_t vtx_fmt)
1469 {
1470 int vtx_size;
1471 vtx_size = 2;
1472 /* ordered according to bits in spec */
1473 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1474 vtx_size++;
1475 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1476 vtx_size += 3;
1477 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1478 vtx_size++;
1479 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1480 vtx_size++;
1481 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1482 vtx_size += 3;
1483 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1484 vtx_size++;
1485 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1486 vtx_size++;
1487 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1488 vtx_size += 2;
1489 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1490 vtx_size += 2;
1491 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1492 vtx_size++;
1493 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1494 vtx_size += 2;
1495 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1496 vtx_size++;
1497 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1498 vtx_size += 2;
1499 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1500 vtx_size++;
1501 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1502 vtx_size++;
1503 /* blend weight */
1504 if (vtx_fmt & (0x7 << 15))
1505 vtx_size += (vtx_fmt >> 15) & 0x7;
1506 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1507 vtx_size += 3;
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1509 vtx_size += 2;
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1511 vtx_size++;
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1513 vtx_size++;
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1515 vtx_size++;
1516 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1517 vtx_size++;
1518 return vtx_size;
1519 }
1520
1521 static int r100_packet0_check(struct radeon_cs_parser *p,
1522 struct radeon_cs_packet *pkt,
1523 unsigned idx, unsigned reg)
1524 {
1525 struct radeon_cs_reloc *reloc;
1526 struct r100_cs_track *track;
1527 volatile uint32_t *ib;
1528 uint32_t tmp;
1529 int r;
1530 int i, face;
1531 u32 tile_flags = 0;
1532 u32 idx_value;
1533
1534 ib = p->ib.ptr;
1535 track = (struct r100_cs_track *)p->track;
1536
1537 idx_value = radeon_get_ib_value(p, idx);
1538
1539 switch (reg) {
1540 case RADEON_CRTC_GUI_TRIG_VLINE:
1541 r = r100_cs_packet_parse_vline(p);
1542 if (r) {
1543 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1544 idx, reg);
1545 radeon_cs_dump_packet(p, pkt);
1546 return r;
1547 }
1548 break;
1549 /* FIXME: only allow PACKET3 blit? easier to check for out of
1550 * range access */
1551 case RADEON_DST_PITCH_OFFSET:
1552 case RADEON_SRC_PITCH_OFFSET:
1553 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1554 if (r)
1555 return r;
1556 break;
1557 case RADEON_RB3D_DEPTHOFFSET:
1558 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1559 if (r) {
1560 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1561 idx, reg);
1562 radeon_cs_dump_packet(p, pkt);
1563 return r;
1564 }
1565 track->zb.robj = reloc->robj;
1566 track->zb.offset = idx_value;
1567 track->zb_dirty = true;
1568 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1569 break;
1570 case RADEON_RB3D_COLOROFFSET:
1571 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1572 if (r) {
1573 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1574 idx, reg);
1575 radeon_cs_dump_packet(p, pkt);
1576 return r;
1577 }
1578 track->cb[0].robj = reloc->robj;
1579 track->cb[0].offset = idx_value;
1580 track->cb_dirty = true;
1581 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1582 break;
1583 case RADEON_PP_TXOFFSET_0:
1584 case RADEON_PP_TXOFFSET_1:
1585 case RADEON_PP_TXOFFSET_2:
1586 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1587 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1588 if (r) {
1589 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1590 idx, reg);
1591 radeon_cs_dump_packet(p, pkt);
1592 return r;
1593 }
1594 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1595 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1596 tile_flags |= RADEON_TXO_MACRO_TILE;
1597 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1598 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1599
1600 tmp = idx_value & ~(0x7 << 2);
1601 tmp |= tile_flags;
1602 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1603 } else
1604 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1605 track->textures[i].robj = reloc->robj;
1606 track->tex_dirty = true;
1607 break;
1608 case RADEON_PP_CUBIC_OFFSET_T0_0:
1609 case RADEON_PP_CUBIC_OFFSET_T0_1:
1610 case RADEON_PP_CUBIC_OFFSET_T0_2:
1611 case RADEON_PP_CUBIC_OFFSET_T0_3:
1612 case RADEON_PP_CUBIC_OFFSET_T0_4:
1613 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1614 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1615 if (r) {
1616 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1617 idx, reg);
1618 radeon_cs_dump_packet(p, pkt);
1619 return r;
1620 }
1621 track->textures[0].cube_info[i].offset = idx_value;
1622 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1623 track->textures[0].cube_info[i].robj = reloc->robj;
1624 track->tex_dirty = true;
1625 break;
1626 case RADEON_PP_CUBIC_OFFSET_T1_0:
1627 case RADEON_PP_CUBIC_OFFSET_T1_1:
1628 case RADEON_PP_CUBIC_OFFSET_T1_2:
1629 case RADEON_PP_CUBIC_OFFSET_T1_3:
1630 case RADEON_PP_CUBIC_OFFSET_T1_4:
1631 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1632 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1633 if (r) {
1634 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1635 idx, reg);
1636 radeon_cs_dump_packet(p, pkt);
1637 return r;
1638 }
1639 track->textures[1].cube_info[i].offset = idx_value;
1640 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1641 track->textures[1].cube_info[i].robj = reloc->robj;
1642 track->tex_dirty = true;
1643 break;
1644 case RADEON_PP_CUBIC_OFFSET_T2_0:
1645 case RADEON_PP_CUBIC_OFFSET_T2_1:
1646 case RADEON_PP_CUBIC_OFFSET_T2_2:
1647 case RADEON_PP_CUBIC_OFFSET_T2_3:
1648 case RADEON_PP_CUBIC_OFFSET_T2_4:
1649 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1650 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1651 if (r) {
1652 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1653 idx, reg);
1654 radeon_cs_dump_packet(p, pkt);
1655 return r;
1656 }
1657 track->textures[2].cube_info[i].offset = idx_value;
1658 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1659 track->textures[2].cube_info[i].robj = reloc->robj;
1660 track->tex_dirty = true;
1661 break;
1662 case RADEON_RE_WIDTH_HEIGHT:
1663 track->maxy = ((idx_value >> 16) & 0x7FF);
1664 track->cb_dirty = true;
1665 track->zb_dirty = true;
1666 break;
1667 case RADEON_RB3D_COLORPITCH:
1668 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1669 if (r) {
1670 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1671 idx, reg);
1672 radeon_cs_dump_packet(p, pkt);
1673 return r;
1674 }
1675 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1676 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1677 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1678 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1679 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1680
1681 tmp = idx_value & ~(0x7 << 16);
1682 tmp |= tile_flags;
1683 ib[idx] = tmp;
1684 } else
1685 ib[idx] = idx_value;
1686
1687 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1688 track->cb_dirty = true;
1689 break;
1690 case RADEON_RB3D_DEPTHPITCH:
1691 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1692 track->zb_dirty = true;
1693 break;
1694 case RADEON_RB3D_CNTL:
1695 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1696 case 7:
1697 case 8:
1698 case 9:
1699 case 11:
1700 case 12:
1701 track->cb[0].cpp = 1;
1702 break;
1703 case 3:
1704 case 4:
1705 case 15:
1706 track->cb[0].cpp = 2;
1707 break;
1708 case 6:
1709 track->cb[0].cpp = 4;
1710 break;
1711 default:
1712 DRM_ERROR("Invalid color buffer format (%d) !\n",
1713 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1714 return -EINVAL;
1715 }
1716 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1717 track->cb_dirty = true;
1718 track->zb_dirty = true;
1719 break;
1720 case RADEON_RB3D_ZSTENCILCNTL:
1721 switch (idx_value & 0xf) {
1722 case 0:
1723 track->zb.cpp = 2;
1724 break;
1725 case 2:
1726 case 3:
1727 case 4:
1728 case 5:
1729 case 9:
1730 case 11:
1731 track->zb.cpp = 4;
1732 break;
1733 default:
1734 break;
1735 }
1736 track->zb_dirty = true;
1737 break;
1738 case RADEON_RB3D_ZPASS_ADDR:
1739 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1740 if (r) {
1741 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1742 idx, reg);
1743 radeon_cs_dump_packet(p, pkt);
1744 return r;
1745 }
1746 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1747 break;
1748 case RADEON_PP_CNTL:
1749 {
1750 uint32_t temp = idx_value >> 4;
1751 for (i = 0; i < track->num_texture; i++)
1752 track->textures[i].enabled = !!(temp & (1 << i));
1753 track->tex_dirty = true;
1754 }
1755 break;
1756 case RADEON_SE_VF_CNTL:
1757 track->vap_vf_cntl = idx_value;
1758 break;
1759 case RADEON_SE_VTX_FMT:
1760 track->vtx_size = r100_get_vtx_size(idx_value);
1761 break;
1762 case RADEON_PP_TEX_SIZE_0:
1763 case RADEON_PP_TEX_SIZE_1:
1764 case RADEON_PP_TEX_SIZE_2:
1765 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1766 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1767 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1768 track->tex_dirty = true;
1769 break;
1770 case RADEON_PP_TEX_PITCH_0:
1771 case RADEON_PP_TEX_PITCH_1:
1772 case RADEON_PP_TEX_PITCH_2:
1773 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1774 track->textures[i].pitch = idx_value + 32;
1775 track->tex_dirty = true;
1776 break;
1777 case RADEON_PP_TXFILTER_0:
1778 case RADEON_PP_TXFILTER_1:
1779 case RADEON_PP_TXFILTER_2:
1780 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1781 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1782 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1783 tmp = (idx_value >> 23) & 0x7;
1784 if (tmp == 2 || tmp == 6)
1785 track->textures[i].roundup_w = false;
1786 tmp = (idx_value >> 27) & 0x7;
1787 if (tmp == 2 || tmp == 6)
1788 track->textures[i].roundup_h = false;
1789 track->tex_dirty = true;
1790 break;
1791 case RADEON_PP_TXFORMAT_0:
1792 case RADEON_PP_TXFORMAT_1:
1793 case RADEON_PP_TXFORMAT_2:
1794 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1795 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1796 track->textures[i].use_pitch = 1;
1797 } else {
1798 track->textures[i].use_pitch = 0;
1799 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1800 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1801 }
1802 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1803 track->textures[i].tex_coord_type = 2;
1804 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1805 case RADEON_TXFORMAT_I8:
1806 case RADEON_TXFORMAT_RGB332:
1807 case RADEON_TXFORMAT_Y8:
1808 track->textures[i].cpp = 1;
1809 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1810 break;
1811 case RADEON_TXFORMAT_AI88:
1812 case RADEON_TXFORMAT_ARGB1555:
1813 case RADEON_TXFORMAT_RGB565:
1814 case RADEON_TXFORMAT_ARGB4444:
1815 case RADEON_TXFORMAT_VYUY422:
1816 case RADEON_TXFORMAT_YVYU422:
1817 case RADEON_TXFORMAT_SHADOW16:
1818 case RADEON_TXFORMAT_LDUDV655:
1819 case RADEON_TXFORMAT_DUDV88:
1820 track->textures[i].cpp = 2;
1821 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1822 break;
1823 case RADEON_TXFORMAT_ARGB8888:
1824 case RADEON_TXFORMAT_RGBA8888:
1825 case RADEON_TXFORMAT_SHADOW32:
1826 case RADEON_TXFORMAT_LDUDUV8888:
1827 track->textures[i].cpp = 4;
1828 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1829 break;
1830 case RADEON_TXFORMAT_DXT1:
1831 track->textures[i].cpp = 1;
1832 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1833 break;
1834 case RADEON_TXFORMAT_DXT23:
1835 case RADEON_TXFORMAT_DXT45:
1836 track->textures[i].cpp = 1;
1837 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1838 break;
1839 }
1840 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1841 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1842 track->tex_dirty = true;
1843 break;
1844 case RADEON_PP_CUBIC_FACES_0:
1845 case RADEON_PP_CUBIC_FACES_1:
1846 case RADEON_PP_CUBIC_FACES_2:
1847 tmp = idx_value;
1848 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1849 for (face = 0; face < 4; face++) {
1850 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1851 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1852 }
1853 track->tex_dirty = true;
1854 break;
1855 default:
1856 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1857 reg, idx);
1858 return -EINVAL;
1859 }
1860 return 0;
1861 }
1862
1863 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1864 struct radeon_cs_packet *pkt,
1865 struct radeon_bo *robj)
1866 {
1867 unsigned idx;
1868 u32 value;
1869 idx = pkt->idx + 1;
1870 value = radeon_get_ib_value(p, idx + 2);
1871 if ((value + 1) > radeon_bo_size(robj)) {
1872 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1873 "(need %u have %lu) !\n",
1874 value + 1,
1875 radeon_bo_size(robj));
1876 return -EINVAL;
1877 }
1878 return 0;
1879 }
1880
1881 static int r100_packet3_check(struct radeon_cs_parser *p,
1882 struct radeon_cs_packet *pkt)
1883 {
1884 struct radeon_cs_reloc *reloc;
1885 struct r100_cs_track *track;
1886 unsigned idx;
1887 volatile uint32_t *ib;
1888 int r;
1889
1890 ib = p->ib.ptr;
1891 idx = pkt->idx + 1;
1892 track = (struct r100_cs_track *)p->track;
1893 switch (pkt->opcode) {
1894 case PACKET3_3D_LOAD_VBPNTR:
1895 r = r100_packet3_load_vbpntr(p, pkt, idx);
1896 if (r)
1897 return r;
1898 break;
1899 case PACKET3_INDX_BUFFER:
1900 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1901 if (r) {
1902 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1903 radeon_cs_dump_packet(p, pkt);
1904 return r;
1905 }
1906 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1907 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1908 if (r) {
1909 return r;
1910 }
1911 break;
1912 case 0x23:
1913 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1914 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1915 if (r) {
1916 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1917 radeon_cs_dump_packet(p, pkt);
1918 return r;
1919 }
1920 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1921 track->num_arrays = 1;
1922 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1923
1924 track->arrays[0].robj = reloc->robj;
1925 track->arrays[0].esize = track->vtx_size;
1926
1927 track->max_indx = radeon_get_ib_value(p, idx+1);
1928
1929 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1930 track->immd_dwords = pkt->count - 1;
1931 r = r100_cs_track_check(p->rdev, track);
1932 if (r)
1933 return r;
1934 break;
1935 case PACKET3_3D_DRAW_IMMD:
1936 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1937 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1938 return -EINVAL;
1939 }
1940 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1941 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1942 track->immd_dwords = pkt->count - 1;
1943 r = r100_cs_track_check(p->rdev, track);
1944 if (r)
1945 return r;
1946 break;
1947 /* triggers drawing using in-packet vertex data */
1948 case PACKET3_3D_DRAW_IMMD_2:
1949 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1950 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1951 return -EINVAL;
1952 }
1953 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1954 track->immd_dwords = pkt->count;
1955 r = r100_cs_track_check(p->rdev, track);
1956 if (r)
1957 return r;
1958 break;
1959 /* triggers drawing using in-packet vertex data */
1960 case PACKET3_3D_DRAW_VBUF_2:
1961 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1962 r = r100_cs_track_check(p->rdev, track);
1963 if (r)
1964 return r;
1965 break;
1966 /* triggers drawing of vertex buffers setup elsewhere */
1967 case PACKET3_3D_DRAW_INDX_2:
1968 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1969 r = r100_cs_track_check(p->rdev, track);
1970 if (r)
1971 return r;
1972 break;
1973 /* triggers drawing using indices to vertex buffer */
1974 case PACKET3_3D_DRAW_VBUF:
1975 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1976 r = r100_cs_track_check(p->rdev, track);
1977 if (r)
1978 return r;
1979 break;
1980 /* triggers drawing of vertex buffers setup elsewhere */
1981 case PACKET3_3D_DRAW_INDX:
1982 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1983 r = r100_cs_track_check(p->rdev, track);
1984 if (r)
1985 return r;
1986 break;
1987 /* triggers drawing using indices to vertex buffer */
1988 case PACKET3_3D_CLEAR_HIZ:
1989 case PACKET3_3D_CLEAR_ZMASK:
1990 if (p->rdev->hyperz_filp != p->filp)
1991 return -EINVAL;
1992 break;
1993 case PACKET3_NOP:
1994 break;
1995 default:
1996 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1997 return -EINVAL;
1998 }
1999 return 0;
2000 }
2001
2002 int r100_cs_parse(struct radeon_cs_parser *p)
2003 {
2004 struct radeon_cs_packet pkt;
2005 struct r100_cs_track *track;
2006 int r;
2007
2008 track = kzalloc(sizeof(*track), GFP_KERNEL);
2009 if (!track)
2010 return -ENOMEM;
2011 r100_cs_track_clear(p->rdev, track);
2012 p->track = track;
2013 do {
2014 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2015 if (r) {
2016 return r;
2017 }
2018 p->idx += pkt.count + 2;
2019 switch (pkt.type) {
2020 case RADEON_PACKET_TYPE0:
2021 if (p->rdev->family >= CHIP_R200)
2022 r = r100_cs_parse_packet0(p, &pkt,
2023 p->rdev->config.r100.reg_safe_bm,
2024 p->rdev->config.r100.reg_safe_bm_size,
2025 &r200_packet0_check);
2026 else
2027 r = r100_cs_parse_packet0(p, &pkt,
2028 p->rdev->config.r100.reg_safe_bm,
2029 p->rdev->config.r100.reg_safe_bm_size,
2030 &r100_packet0_check);
2031 break;
2032 case RADEON_PACKET_TYPE2:
2033 break;
2034 case RADEON_PACKET_TYPE3:
2035 r = r100_packet3_check(p, &pkt);
2036 break;
2037 default:
2038 DRM_ERROR("Unknown packet type %d !\n",
2039 pkt.type);
2040 return -EINVAL;
2041 }
2042 if (r)
2043 return r;
2044 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2045 return 0;
2046 }
2047
2048 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2049 {
2050 DRM_ERROR("pitch %d\n", t->pitch);
2051 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2052 DRM_ERROR("width %d\n", t->width);
2053 DRM_ERROR("width_11 %d\n", t->width_11);
2054 DRM_ERROR("height %d\n", t->height);
2055 DRM_ERROR("height_11 %d\n", t->height_11);
2056 DRM_ERROR("num levels %d\n", t->num_levels);
2057 DRM_ERROR("depth %d\n", t->txdepth);
2058 DRM_ERROR("bpp %d\n", t->cpp);
2059 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2060 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2061 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2062 DRM_ERROR("compress format %d\n", t->compress_format);
2063 }
2064
2065 static int r100_track_compress_size(int compress_format, int w, int h)
2066 {
2067 int block_width, block_height, block_bytes;
2068 int wblocks, hblocks;
2069 int min_wblocks;
2070 int sz;
2071
2072 block_width = 4;
2073 block_height = 4;
2074
2075 switch (compress_format) {
2076 case R100_TRACK_COMP_DXT1:
2077 block_bytes = 8;
2078 min_wblocks = 4;
2079 break;
2080 default:
2081 case R100_TRACK_COMP_DXT35:
2082 block_bytes = 16;
2083 min_wblocks = 2;
2084 break;
2085 }
2086
2087 hblocks = (h + block_height - 1) / block_height;
2088 wblocks = (w + block_width - 1) / block_width;
2089 if (wblocks < min_wblocks)
2090 wblocks = min_wblocks;
2091 sz = wblocks * hblocks * block_bytes;
2092 return sz;
2093 }
2094
2095 static int r100_cs_track_cube(struct radeon_device *rdev,
2096 struct r100_cs_track *track, unsigned idx)
2097 {
2098 unsigned face, w, h;
2099 struct radeon_bo *cube_robj;
2100 unsigned long size;
2101 unsigned compress_format = track->textures[idx].compress_format;
2102
2103 for (face = 0; face < 5; face++) {
2104 cube_robj = track->textures[idx].cube_info[face].robj;
2105 w = track->textures[idx].cube_info[face].width;
2106 h = track->textures[idx].cube_info[face].height;
2107
2108 if (compress_format) {
2109 size = r100_track_compress_size(compress_format, w, h);
2110 } else
2111 size = w * h;
2112 size *= track->textures[idx].cpp;
2113
2114 size += track->textures[idx].cube_info[face].offset;
2115
2116 if (size > radeon_bo_size(cube_robj)) {
2117 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2118 size, radeon_bo_size(cube_robj));
2119 r100_cs_track_texture_print(&track->textures[idx]);
2120 return -1;
2121 }
2122 }
2123 return 0;
2124 }
2125
2126 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2127 struct r100_cs_track *track)
2128 {
2129 struct radeon_bo *robj;
2130 unsigned long size;
2131 unsigned u, i, w, h, d;
2132 int ret;
2133
2134 for (u = 0; u < track->num_texture; u++) {
2135 if (!track->textures[u].enabled)
2136 continue;
2137 if (track->textures[u].lookup_disable)
2138 continue;
2139 robj = track->textures[u].robj;
2140 if (robj == NULL) {
2141 DRM_ERROR("No texture bound to unit %u\n", u);
2142 return -EINVAL;
2143 }
2144 size = 0;
2145 for (i = 0; i <= track->textures[u].num_levels; i++) {
2146 if (track->textures[u].use_pitch) {
2147 if (rdev->family < CHIP_R300)
2148 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2149 else
2150 w = track->textures[u].pitch / (1 << i);
2151 } else {
2152 w = track->textures[u].width;
2153 if (rdev->family >= CHIP_RV515)
2154 w |= track->textures[u].width_11;
2155 w = w / (1 << i);
2156 if (track->textures[u].roundup_w)
2157 w = roundup_pow_of_two(w);
2158 }
2159 h = track->textures[u].height;
2160 if (rdev->family >= CHIP_RV515)
2161 h |= track->textures[u].height_11;
2162 h = h / (1 << i);
2163 if (track->textures[u].roundup_h)
2164 h = roundup_pow_of_two(h);
2165 if (track->textures[u].tex_coord_type == 1) {
2166 d = (1 << track->textures[u].txdepth) / (1 << i);
2167 if (!d)
2168 d = 1;
2169 } else {
2170 d = 1;
2171 }
2172 if (track->textures[u].compress_format) {
2173
2174 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2175 /* compressed textures are block based */
2176 } else
2177 size += w * h * d;
2178 }
2179 size *= track->textures[u].cpp;
2180
2181 switch (track->textures[u].tex_coord_type) {
2182 case 0:
2183 case 1:
2184 break;
2185 case 2:
2186 if (track->separate_cube) {
2187 ret = r100_cs_track_cube(rdev, track, u);
2188 if (ret)
2189 return ret;
2190 } else
2191 size *= 6;
2192 break;
2193 default:
2194 DRM_ERROR("Invalid texture coordinate type %u for unit "
2195 "%u\n", track->textures[u].tex_coord_type, u);
2196 return -EINVAL;
2197 }
2198 if (size > radeon_bo_size(robj)) {
2199 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2200 "%lu\n", u, size, radeon_bo_size(robj));
2201 r100_cs_track_texture_print(&track->textures[u]);
2202 return -EINVAL;
2203 }
2204 }
2205 return 0;
2206 }
2207
2208 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2209 {
2210 unsigned i;
2211 unsigned long size;
2212 unsigned prim_walk;
2213 unsigned nverts;
2214 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2215
2216 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2217 !track->blend_read_enable)
2218 num_cb = 0;
2219
2220 for (i = 0; i < num_cb; i++) {
2221 if (track->cb[i].robj == NULL) {
2222 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2223 return -EINVAL;
2224 }
2225 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2226 size += track->cb[i].offset;
2227 if (size > radeon_bo_size(track->cb[i].robj)) {
2228 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2229 "(need %lu have %lu) !\n", i, size,
2230 radeon_bo_size(track->cb[i].robj));
2231 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2232 i, track->cb[i].pitch, track->cb[i].cpp,
2233 track->cb[i].offset, track->maxy);
2234 return -EINVAL;
2235 }
2236 }
2237 track->cb_dirty = false;
2238
2239 if (track->zb_dirty && track->z_enabled) {
2240 if (track->zb.robj == NULL) {
2241 DRM_ERROR("[drm] No buffer for z buffer !\n");
2242 return -EINVAL;
2243 }
2244 size = track->zb.pitch * track->zb.cpp * track->maxy;
2245 size += track->zb.offset;
2246 if (size > radeon_bo_size(track->zb.robj)) {
2247 DRM_ERROR("[drm] Buffer too small for z buffer "
2248 "(need %lu have %lu) !\n", size,
2249 radeon_bo_size(track->zb.robj));
2250 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2251 track->zb.pitch, track->zb.cpp,
2252 track->zb.offset, track->maxy);
2253 return -EINVAL;
2254 }
2255 }
2256 track->zb_dirty = false;
2257
2258 if (track->aa_dirty && track->aaresolve) {
2259 if (track->aa.robj == NULL) {
2260 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2261 return -EINVAL;
2262 }
2263 /* I believe the format comes from colorbuffer0. */
2264 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2265 size += track->aa.offset;
2266 if (size > radeon_bo_size(track->aa.robj)) {
2267 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2268 "(need %lu have %lu) !\n", i, size,
2269 radeon_bo_size(track->aa.robj));
2270 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2271 i, track->aa.pitch, track->cb[0].cpp,
2272 track->aa.offset, track->maxy);
2273 return -EINVAL;
2274 }
2275 }
2276 track->aa_dirty = false;
2277
2278 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2279 if (track->vap_vf_cntl & (1 << 14)) {
2280 nverts = track->vap_alt_nverts;
2281 } else {
2282 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2283 }
2284 switch (prim_walk) {
2285 case 1:
2286 for (i = 0; i < track->num_arrays; i++) {
2287 size = track->arrays[i].esize * track->max_indx * 4;
2288 if (track->arrays[i].robj == NULL) {
2289 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2290 "bound\n", prim_walk, i);
2291 return -EINVAL;
2292 }
2293 if (size > radeon_bo_size(track->arrays[i].robj)) {
2294 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2295 "need %lu dwords have %lu dwords\n",
2296 prim_walk, i, size >> 2,
2297 radeon_bo_size(track->arrays[i].robj)
2298 >> 2);
2299 DRM_ERROR("Max indices %u\n", track->max_indx);
2300 return -EINVAL;
2301 }
2302 }
2303 break;
2304 case 2:
2305 for (i = 0; i < track->num_arrays; i++) {
2306 size = track->arrays[i].esize * (nverts - 1) * 4;
2307 if (track->arrays[i].robj == NULL) {
2308 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2309 "bound\n", prim_walk, i);
2310 return -EINVAL;
2311 }
2312 if (size > radeon_bo_size(track->arrays[i].robj)) {
2313 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2314 "need %lu dwords have %lu dwords\n",
2315 prim_walk, i, size >> 2,
2316 radeon_bo_size(track->arrays[i].robj)
2317 >> 2);
2318 return -EINVAL;
2319 }
2320 }
2321 break;
2322 case 3:
2323 size = track->vtx_size * nverts;
2324 if (size != track->immd_dwords) {
2325 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2326 track->immd_dwords, size);
2327 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2328 nverts, track->vtx_size);
2329 return -EINVAL;
2330 }
2331 break;
2332 default:
2333 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2334 prim_walk);
2335 return -EINVAL;
2336 }
2337
2338 if (track->tex_dirty) {
2339 track->tex_dirty = false;
2340 return r100_cs_track_texture_check(rdev, track);
2341 }
2342 return 0;
2343 }
2344
2345 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2346 {
2347 unsigned i, face;
2348
2349 track->cb_dirty = true;
2350 track->zb_dirty = true;
2351 track->tex_dirty = true;
2352 track->aa_dirty = true;
2353
2354 if (rdev->family < CHIP_R300) {
2355 track->num_cb = 1;
2356 if (rdev->family <= CHIP_RS200)
2357 track->num_texture = 3;
2358 else
2359 track->num_texture = 6;
2360 track->maxy = 2048;
2361 track->separate_cube = 1;
2362 } else {
2363 track->num_cb = 4;
2364 track->num_texture = 16;
2365 track->maxy = 4096;
2366 track->separate_cube = 0;
2367 track->aaresolve = false;
2368 track->aa.robj = NULL;
2369 }
2370
2371 for (i = 0; i < track->num_cb; i++) {
2372 track->cb[i].robj = NULL;
2373 track->cb[i].pitch = 8192;
2374 track->cb[i].cpp = 16;
2375 track->cb[i].offset = 0;
2376 }
2377 track->z_enabled = true;
2378 track->zb.robj = NULL;
2379 track->zb.pitch = 8192;
2380 track->zb.cpp = 4;
2381 track->zb.offset = 0;
2382 track->vtx_size = 0x7F;
2383 track->immd_dwords = 0xFFFFFFFFUL;
2384 track->num_arrays = 11;
2385 track->max_indx = 0x00FFFFFFUL;
2386 for (i = 0; i < track->num_arrays; i++) {
2387 track->arrays[i].robj = NULL;
2388 track->arrays[i].esize = 0x7F;
2389 }
2390 for (i = 0; i < track->num_texture; i++) {
2391 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2392 track->textures[i].pitch = 16536;
2393 track->textures[i].width = 16536;
2394 track->textures[i].height = 16536;
2395 track->textures[i].width_11 = 1 << 11;
2396 track->textures[i].height_11 = 1 << 11;
2397 track->textures[i].num_levels = 12;
2398 if (rdev->family <= CHIP_RS200) {
2399 track->textures[i].tex_coord_type = 0;
2400 track->textures[i].txdepth = 0;
2401 } else {
2402 track->textures[i].txdepth = 16;
2403 track->textures[i].tex_coord_type = 1;
2404 }
2405 track->textures[i].cpp = 64;
2406 track->textures[i].robj = NULL;
2407 /* CS IB emission code makes sure texture unit are disabled */
2408 track->textures[i].enabled = false;
2409 track->textures[i].lookup_disable = false;
2410 track->textures[i].roundup_w = true;
2411 track->textures[i].roundup_h = true;
2412 if (track->separate_cube)
2413 for (face = 0; face < 5; face++) {
2414 track->textures[i].cube_info[face].robj = NULL;
2415 track->textures[i].cube_info[face].width = 16536;
2416 track->textures[i].cube_info[face].height = 16536;
2417 track->textures[i].cube_info[face].offset = 0;
2418 }
2419 }
2420 }
2421
2422 /*
2423 * Global GPU functions
2424 */
2425 static void r100_errata(struct radeon_device *rdev)
2426 {
2427 rdev->pll_errata = 0;
2428
2429 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2430 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2431 }
2432
2433 if (rdev->family == CHIP_RV100 ||
2434 rdev->family == CHIP_RS100 ||
2435 rdev->family == CHIP_RS200) {
2436 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2437 }
2438 }
2439
2440 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2441 {
2442 unsigned i;
2443 uint32_t tmp;
2444
2445 for (i = 0; i < rdev->usec_timeout; i++) {
2446 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2447 if (tmp >= n) {
2448 return 0;
2449 }
2450 DRM_UDELAY(1);
2451 }
2452 return -1;
2453 }
2454
2455 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2456 {
2457 unsigned i;
2458 uint32_t tmp;
2459
2460 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2461 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2462 " Bad things might happen.\n");
2463 }
2464 for (i = 0; i < rdev->usec_timeout; i++) {
2465 tmp = RREG32(RADEON_RBBM_STATUS);
2466 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2467 return 0;
2468 }
2469 DRM_UDELAY(1);
2470 }
2471 return -1;
2472 }
2473
2474 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2475 {
2476 unsigned i;
2477 uint32_t tmp;
2478
2479 for (i = 0; i < rdev->usec_timeout; i++) {
2480 /* read MC_STATUS */
2481 tmp = RREG32(RADEON_MC_STATUS);
2482 if (tmp & RADEON_MC_IDLE) {
2483 return 0;
2484 }
2485 DRM_UDELAY(1);
2486 }
2487 return -1;
2488 }
2489
2490 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2491 {
2492 u32 rbbm_status;
2493
2494 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2495 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2496 radeon_ring_lockup_update(ring);
2497 return false;
2498 }
2499 /* force CP activities */
2500 radeon_ring_force_activity(rdev, ring);
2501 return radeon_ring_test_lockup(rdev, ring);
2502 }
2503
2504 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2505 void r100_enable_bm(struct radeon_device *rdev)
2506 {
2507 uint32_t tmp;
2508 /* Enable bus mastering */
2509 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2510 WREG32(RADEON_BUS_CNTL, tmp);
2511 }
2512
2513 void r100_bm_disable(struct radeon_device *rdev)
2514 {
2515 u32 tmp;
2516
2517 /* disable bus mastering */
2518 tmp = RREG32(R_000030_BUS_CNTL);
2519 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2520 mdelay(1);
2521 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2522 mdelay(1);
2523 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2524 tmp = RREG32(RADEON_BUS_CNTL);
2525 mdelay(1);
2526 pci_clear_master(rdev->pdev);
2527 mdelay(1);
2528 }
2529
2530 int r100_asic_reset(struct radeon_device *rdev)
2531 {
2532 struct r100_mc_save save;
2533 u32 status, tmp;
2534 int ret = 0;
2535
2536 status = RREG32(R_000E40_RBBM_STATUS);
2537 if (!G_000E40_GUI_ACTIVE(status)) {
2538 return 0;
2539 }
2540 r100_mc_stop(rdev, &save);
2541 status = RREG32(R_000E40_RBBM_STATUS);
2542 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2543 /* stop CP */
2544 WREG32(RADEON_CP_CSQ_CNTL, 0);
2545 tmp = RREG32(RADEON_CP_RB_CNTL);
2546 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2547 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2548 WREG32(RADEON_CP_RB_WPTR, 0);
2549 WREG32(RADEON_CP_RB_CNTL, tmp);
2550 /* save PCI state */
2551 pci_save_state(rdev->pdev);
2552 /* disable bus mastering */
2553 r100_bm_disable(rdev);
2554 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2555 S_0000F0_SOFT_RESET_RE(1) |
2556 S_0000F0_SOFT_RESET_PP(1) |
2557 S_0000F0_SOFT_RESET_RB(1));
2558 RREG32(R_0000F0_RBBM_SOFT_RESET);
2559 mdelay(500);
2560 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2561 mdelay(1);
2562 status = RREG32(R_000E40_RBBM_STATUS);
2563 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2564 /* reset CP */
2565 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2566 RREG32(R_0000F0_RBBM_SOFT_RESET);
2567 mdelay(500);
2568 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2569 mdelay(1);
2570 status = RREG32(R_000E40_RBBM_STATUS);
2571 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2572 /* restore PCI & busmastering */
2573 pci_restore_state(rdev->pdev);
2574 r100_enable_bm(rdev);
2575 /* Check if GPU is idle */
2576 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2577 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2578 dev_err(rdev->dev, "failed to reset GPU\n");
2579 ret = -1;
2580 } else
2581 dev_info(rdev->dev, "GPU reset succeed\n");
2582 r100_mc_resume(rdev, &save);
2583 return ret;
2584 }
2585
2586 void r100_set_common_regs(struct radeon_device *rdev)
2587 {
2588 struct drm_device *dev = rdev->ddev;
2589 bool force_dac2 = false;
2590 u32 tmp;
2591
2592 /* set these so they don't interfere with anything */
2593 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2594 WREG32(RADEON_SUBPIC_CNTL, 0);
2595 WREG32(RADEON_VIPH_CONTROL, 0);
2596 WREG32(RADEON_I2C_CNTL_1, 0);
2597 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2598 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2599 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2600
2601 /* always set up dac2 on rn50 and some rv100 as lots
2602 * of servers seem to wire it up to a VGA port but
2603 * don't report it in the bios connector
2604 * table.
2605 */
2606 switch (dev->pdev->device) {
2607 /* RN50 */
2608 case 0x515e:
2609 case 0x5969:
2610 force_dac2 = true;
2611 break;
2612 /* RV100*/
2613 case 0x5159:
2614 case 0x515a:
2615 /* DELL triple head servers */
2616 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2617 ((dev->pdev->subsystem_device == 0x016c) ||
2618 (dev->pdev->subsystem_device == 0x016d) ||
2619 (dev->pdev->subsystem_device == 0x016e) ||
2620 (dev->pdev->subsystem_device == 0x016f) ||
2621 (dev->pdev->subsystem_device == 0x0170) ||
2622 (dev->pdev->subsystem_device == 0x017d) ||
2623 (dev->pdev->subsystem_device == 0x017e) ||
2624 (dev->pdev->subsystem_device == 0x0183) ||
2625 (dev->pdev->subsystem_device == 0x018a) ||
2626 (dev->pdev->subsystem_device == 0x019a)))
2627 force_dac2 = true;
2628 break;
2629 }
2630
2631 if (force_dac2) {
2632 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2633 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2634 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2635
2636 /* For CRT on DAC2, don't turn it on if BIOS didn't
2637 enable it, even it's detected.
2638 */
2639
2640 /* force it to crtc0 */
2641 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2642 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2643 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2644
2645 /* set up the TV DAC */
2646 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2647 RADEON_TV_DAC_STD_MASK |
2648 RADEON_TV_DAC_RDACPD |
2649 RADEON_TV_DAC_GDACPD |
2650 RADEON_TV_DAC_BDACPD |
2651 RADEON_TV_DAC_BGADJ_MASK |
2652 RADEON_TV_DAC_DACADJ_MASK);
2653 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2654 RADEON_TV_DAC_NHOLD |
2655 RADEON_TV_DAC_STD_PS2 |
2656 (0x58 << 16));
2657
2658 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2659 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2660 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2661 }
2662
2663 /* switch PM block to ACPI mode */
2664 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2665 tmp &= ~RADEON_PM_MODE_SEL;
2666 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2667
2668 }
2669
2670 /*
2671 * VRAM info
2672 */
2673 static void r100_vram_get_type(struct radeon_device *rdev)
2674 {
2675 uint32_t tmp;
2676
2677 rdev->mc.vram_is_ddr = false;
2678 if (rdev->flags & RADEON_IS_IGP)
2679 rdev->mc.vram_is_ddr = true;
2680 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2681 rdev->mc.vram_is_ddr = true;
2682 if ((rdev->family == CHIP_RV100) ||
2683 (rdev->family == CHIP_RS100) ||
2684 (rdev->family == CHIP_RS200)) {
2685 tmp = RREG32(RADEON_MEM_CNTL);
2686 if (tmp & RV100_HALF_MODE) {
2687 rdev->mc.vram_width = 32;
2688 } else {
2689 rdev->mc.vram_width = 64;
2690 }
2691 if (rdev->flags & RADEON_SINGLE_CRTC) {
2692 rdev->mc.vram_width /= 4;
2693 rdev->mc.vram_is_ddr = true;
2694 }
2695 } else if (rdev->family <= CHIP_RV280) {
2696 tmp = RREG32(RADEON_MEM_CNTL);
2697 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2698 rdev->mc.vram_width = 128;
2699 } else {
2700 rdev->mc.vram_width = 64;
2701 }
2702 } else {
2703 /* newer IGPs */
2704 rdev->mc.vram_width = 128;
2705 }
2706 }
2707
2708 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2709 {
2710 u32 aper_size;
2711 u8 byte;
2712
2713 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2714
2715 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2716 * that is has the 2nd generation multifunction PCI interface
2717 */
2718 if (rdev->family == CHIP_RV280 ||
2719 rdev->family >= CHIP_RV350) {
2720 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2721 ~RADEON_HDP_APER_CNTL);
2722 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2723 return aper_size * 2;
2724 }
2725
2726 /* Older cards have all sorts of funny issues to deal with. First
2727 * check if it's a multifunction card by reading the PCI config
2728 * header type... Limit those to one aperture size
2729 */
2730 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2731 if (byte & 0x80) {
2732 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2733 DRM_INFO("Limiting VRAM to one aperture\n");
2734 return aper_size;
2735 }
2736
2737 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2738 * have set it up. We don't write this as it's broken on some ASICs but
2739 * we expect the BIOS to have done the right thing (might be too optimistic...)
2740 */
2741 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2742 return aper_size * 2;
2743 return aper_size;
2744 }
2745
2746 void r100_vram_init_sizes(struct radeon_device *rdev)
2747 {
2748 u64 config_aper_size;
2749
2750 /* work out accessible VRAM */
2751 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2752 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2753 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2754 /* FIXME we don't use the second aperture yet when we could use it */
2755 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2756 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2757 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2758 if (rdev->flags & RADEON_IS_IGP) {
2759 uint32_t tom;
2760 /* read NB_TOM to get the amount of ram stolen for the GPU */
2761 tom = RREG32(RADEON_NB_TOM);
2762 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2763 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2764 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2765 } else {
2766 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2767 /* Some production boards of m6 will report 0
2768 * if it's 8 MB
2769 */
2770 if (rdev->mc.real_vram_size == 0) {
2771 rdev->mc.real_vram_size = 8192 * 1024;
2772 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2773 }
2774 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2775 * Novell bug 204882 + along with lots of ubuntu ones
2776 */
2777 if (rdev->mc.aper_size > config_aper_size)
2778 config_aper_size = rdev->mc.aper_size;
2779
2780 if (config_aper_size > rdev->mc.real_vram_size)
2781 rdev->mc.mc_vram_size = config_aper_size;
2782 else
2783 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2784 }
2785 }
2786
2787 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2788 {
2789 uint32_t temp;
2790
2791 temp = RREG32(RADEON_CONFIG_CNTL);
2792 if (state == false) {
2793 temp &= ~RADEON_CFG_VGA_RAM_EN;
2794 temp |= RADEON_CFG_VGA_IO_DIS;
2795 } else {
2796 temp &= ~RADEON_CFG_VGA_IO_DIS;
2797 }
2798 WREG32(RADEON_CONFIG_CNTL, temp);
2799 }
2800
2801 static void r100_mc_init(struct radeon_device *rdev)
2802 {
2803 u64 base;
2804
2805 r100_vram_get_type(rdev);
2806 r100_vram_init_sizes(rdev);
2807 base = rdev->mc.aper_base;
2808 if (rdev->flags & RADEON_IS_IGP)
2809 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2810 radeon_vram_location(rdev, &rdev->mc, base);
2811 rdev->mc.gtt_base_align = 0;
2812 if (!(rdev->flags & RADEON_IS_AGP))
2813 radeon_gtt_location(rdev, &rdev->mc);
2814 radeon_update_bandwidth_info(rdev);
2815 }
2816
2817
2818 /*
2819 * Indirect registers accessor
2820 */
2821 void r100_pll_errata_after_index(struct radeon_device *rdev)
2822 {
2823 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2824 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2825 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2826 }
2827 }
2828
2829 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2830 {
2831 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2832 * or the chip could hang on a subsequent access
2833 */
2834 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2835 mdelay(5);
2836 }
2837
2838 /* This function is required to workaround a hardware bug in some (all?)
2839 * revisions of the R300. This workaround should be called after every
2840 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2841 * may not be correct.
2842 */
2843 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2844 uint32_t save, tmp;
2845
2846 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2847 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2848 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2849 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2850 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2851 }
2852 }
2853
2854 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2855 {
2856 unsigned long flags;
2857 uint32_t data;
2858
2859 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2860 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2861 r100_pll_errata_after_index(rdev);
2862 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2863 r100_pll_errata_after_data(rdev);
2864 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2865 return data;
2866 }
2867
2868 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2869 {
2870 unsigned long flags;
2871
2872 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2873 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2874 r100_pll_errata_after_index(rdev);
2875 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2876 r100_pll_errata_after_data(rdev);
2877 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2878 }
2879
2880 static void r100_set_safe_registers(struct radeon_device *rdev)
2881 {
2882 if (ASIC_IS_RN50(rdev)) {
2883 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2884 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2885 } else if (rdev->family < CHIP_R200) {
2886 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2887 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2888 } else {
2889 r200_set_safe_registers(rdev);
2890 }
2891 }
2892
2893 /*
2894 * Debugfs info
2895 */
2896 #if defined(CONFIG_DEBUG_FS)
2897 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2898 {
2899 struct drm_info_node *node = (struct drm_info_node *) m->private;
2900 struct drm_device *dev = node->minor->dev;
2901 struct radeon_device *rdev = dev->dev_private;
2902 uint32_t reg, value;
2903 unsigned i;
2904
2905 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2906 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2907 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2908 for (i = 0; i < 64; i++) {
2909 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2910 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2911 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2912 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2913 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2914 }
2915 return 0;
2916 }
2917
2918 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2919 {
2920 struct drm_info_node *node = (struct drm_info_node *) m->private;
2921 struct drm_device *dev = node->minor->dev;
2922 struct radeon_device *rdev = dev->dev_private;
2923 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2924 uint32_t rdp, wdp;
2925 unsigned count, i, j;
2926
2927 radeon_ring_free_size(rdev, ring);
2928 rdp = RREG32(RADEON_CP_RB_RPTR);
2929 wdp = RREG32(RADEON_CP_RB_WPTR);
2930 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2931 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2932 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2933 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2934 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2935 seq_printf(m, "%u dwords in ring\n", count);
2936 if (ring->ready) {
2937 for (j = 0; j <= count; j++) {
2938 i = (rdp + j) & ring->ptr_mask;
2939 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2940 }
2941 }
2942 return 0;
2943 }
2944
2945
2946 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2947 {
2948 struct drm_info_node *node = (struct drm_info_node *) m->private;
2949 struct drm_device *dev = node->minor->dev;
2950 struct radeon_device *rdev = dev->dev_private;
2951 uint32_t csq_stat, csq2_stat, tmp;
2952 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2953 unsigned i;
2954
2955 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2956 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2957 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2958 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2959 r_rptr = (csq_stat >> 0) & 0x3ff;
2960 r_wptr = (csq_stat >> 10) & 0x3ff;
2961 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2962 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2963 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2964 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2965 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2966 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2967 seq_printf(m, "Ring rptr %u\n", r_rptr);
2968 seq_printf(m, "Ring wptr %u\n", r_wptr);
2969 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2970 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2971 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2972 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2973 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2974 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2975 seq_printf(m, "Ring fifo:\n");
2976 for (i = 0; i < 256; i++) {
2977 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2978 tmp = RREG32(RADEON_CP_CSQ_DATA);
2979 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2980 }
2981 seq_printf(m, "Indirect1 fifo:\n");
2982 for (i = 256; i <= 512; i++) {
2983 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2984 tmp = RREG32(RADEON_CP_CSQ_DATA);
2985 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2986 }
2987 seq_printf(m, "Indirect2 fifo:\n");
2988 for (i = 640; i < ib1_wptr; i++) {
2989 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2990 tmp = RREG32(RADEON_CP_CSQ_DATA);
2991 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2992 }
2993 return 0;
2994 }
2995
2996 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2997 {
2998 struct drm_info_node *node = (struct drm_info_node *) m->private;
2999 struct drm_device *dev = node->minor->dev;
3000 struct radeon_device *rdev = dev->dev_private;
3001 uint32_t tmp;
3002
3003 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3004 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3005 tmp = RREG32(RADEON_MC_FB_LOCATION);
3006 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3007 tmp = RREG32(RADEON_BUS_CNTL);
3008 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3009 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3010 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3011 tmp = RREG32(RADEON_AGP_BASE);
3012 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3013 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3014 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3015 tmp = RREG32(0x01D0);
3016 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3017 tmp = RREG32(RADEON_AIC_LO_ADDR);
3018 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3019 tmp = RREG32(RADEON_AIC_HI_ADDR);
3020 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3021 tmp = RREG32(0x01E4);
3022 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3023 return 0;
3024 }
3025
3026 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3027 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3028 };
3029
3030 static struct drm_info_list r100_debugfs_cp_list[] = {
3031 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3032 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3033 };
3034
3035 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3036 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3037 };
3038 #endif
3039
3040 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3041 {
3042 #if defined(CONFIG_DEBUG_FS)
3043 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3044 #else
3045 return 0;
3046 #endif
3047 }
3048
3049 int r100_debugfs_cp_init(struct radeon_device *rdev)
3050 {
3051 #if defined(CONFIG_DEBUG_FS)
3052 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3053 #else
3054 return 0;
3055 #endif
3056 }
3057
3058 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3059 {
3060 #if defined(CONFIG_DEBUG_FS)
3061 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3062 #else
3063 return 0;
3064 #endif
3065 }
3066
3067 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3068 uint32_t tiling_flags, uint32_t pitch,
3069 uint32_t offset, uint32_t obj_size)
3070 {
3071 int surf_index = reg * 16;
3072 int flags = 0;
3073
3074 if (rdev->family <= CHIP_RS200) {
3075 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3076 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3077 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3078 if (tiling_flags & RADEON_TILING_MACRO)
3079 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3080 /* setting pitch to 0 disables tiling */
3081 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3082 == 0)
3083 pitch = 0;
3084 } else if (rdev->family <= CHIP_RV280) {
3085 if (tiling_flags & (RADEON_TILING_MACRO))
3086 flags |= R200_SURF_TILE_COLOR_MACRO;
3087 if (tiling_flags & RADEON_TILING_MICRO)
3088 flags |= R200_SURF_TILE_COLOR_MICRO;
3089 } else {
3090 if (tiling_flags & RADEON_TILING_MACRO)
3091 flags |= R300_SURF_TILE_MACRO;
3092 if (tiling_flags & RADEON_TILING_MICRO)
3093 flags |= R300_SURF_TILE_MICRO;
3094 }
3095
3096 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3097 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3098 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3099 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3100
3101 /* r100/r200 divide by 16 */
3102 if (rdev->family < CHIP_R300)
3103 flags |= pitch / 16;
3104 else
3105 flags |= pitch / 8;
3106
3107
3108 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3109 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3110 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3111 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3112 return 0;
3113 }
3114
3115 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3116 {
3117 int surf_index = reg * 16;
3118 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3119 }
3120
3121 void r100_bandwidth_update(struct radeon_device *rdev)
3122 {
3123 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3124 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3125 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3126 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3127 fixed20_12 memtcas_ff[8] = {
3128 dfixed_init(1),
3129 dfixed_init(2),
3130 dfixed_init(3),
3131 dfixed_init(0),
3132 dfixed_init_half(1),
3133 dfixed_init_half(2),
3134 dfixed_init(0),
3135 };
3136 fixed20_12 memtcas_rs480_ff[8] = {
3137 dfixed_init(0),
3138 dfixed_init(1),
3139 dfixed_init(2),
3140 dfixed_init(3),
3141 dfixed_init(0),
3142 dfixed_init_half(1),
3143 dfixed_init_half(2),
3144 dfixed_init_half(3),
3145 };
3146 fixed20_12 memtcas2_ff[8] = {
3147 dfixed_init(0),
3148 dfixed_init(1),
3149 dfixed_init(2),
3150 dfixed_init(3),
3151 dfixed_init(4),
3152 dfixed_init(5),
3153 dfixed_init(6),
3154 dfixed_init(7),
3155 };
3156 fixed20_12 memtrbs[8] = {
3157 dfixed_init(1),
3158 dfixed_init_half(1),
3159 dfixed_init(2),
3160 dfixed_init_half(2),
3161 dfixed_init(3),
3162 dfixed_init_half(3),
3163 dfixed_init(4),
3164 dfixed_init_half(4)
3165 };
3166 fixed20_12 memtrbs_r4xx[8] = {
3167 dfixed_init(4),
3168 dfixed_init(5),
3169 dfixed_init(6),
3170 dfixed_init(7),
3171 dfixed_init(8),
3172 dfixed_init(9),
3173 dfixed_init(10),
3174 dfixed_init(11)
3175 };
3176 fixed20_12 min_mem_eff;
3177 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3178 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3179 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3180 disp_drain_rate2, read_return_rate;
3181 fixed20_12 time_disp1_drop_priority;
3182 int c;
3183 int cur_size = 16; /* in octawords */
3184 int critical_point = 0, critical_point2;
3185 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3186 int stop_req, max_stop_req;
3187 struct drm_display_mode *mode1 = NULL;
3188 struct drm_display_mode *mode2 = NULL;
3189 uint32_t pixel_bytes1 = 0;
3190 uint32_t pixel_bytes2 = 0;
3191
3192 radeon_update_display_priority(rdev);
3193
3194 if (rdev->mode_info.crtcs[0]->base.enabled) {
3195 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3196 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3197 }
3198 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3199 if (rdev->mode_info.crtcs[1]->base.enabled) {
3200 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3201 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3202 }
3203 }
3204
3205 min_mem_eff.full = dfixed_const_8(0);
3206 /* get modes */
3207 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3208 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3209 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3210 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3211 /* check crtc enables */
3212 if (mode2)
3213 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3214 if (mode1)
3215 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3216 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3217 }
3218
3219 /*
3220 * determine is there is enough bw for current mode
3221 */
3222 sclk_ff = rdev->pm.sclk;
3223 mclk_ff = rdev->pm.mclk;
3224
3225 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3226 temp_ff.full = dfixed_const(temp);
3227 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3228
3229 pix_clk.full = 0;
3230 pix_clk2.full = 0;
3231 peak_disp_bw.full = 0;
3232 if (mode1) {
3233 temp_ff.full = dfixed_const(1000);
3234 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3235 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3236 temp_ff.full = dfixed_const(pixel_bytes1);
3237 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3238 }
3239 if (mode2) {
3240 temp_ff.full = dfixed_const(1000);
3241 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3242 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3243 temp_ff.full = dfixed_const(pixel_bytes2);
3244 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3245 }
3246
3247 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3248 if (peak_disp_bw.full >= mem_bw.full) {
3249 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3250 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3251 }
3252
3253 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3254 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3255 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3256 mem_trcd = ((temp >> 2) & 0x3) + 1;
3257 mem_trp = ((temp & 0x3)) + 1;
3258 mem_tras = ((temp & 0x70) >> 4) + 1;
3259 } else if (rdev->family == CHIP_R300 ||
3260 rdev->family == CHIP_R350) { /* r300, r350 */
3261 mem_trcd = (temp & 0x7) + 1;
3262 mem_trp = ((temp >> 8) & 0x7) + 1;
3263 mem_tras = ((temp >> 11) & 0xf) + 4;
3264 } else if (rdev->family == CHIP_RV350 ||
3265 rdev->family <= CHIP_RV380) {
3266 /* rv3x0 */
3267 mem_trcd = (temp & 0x7) + 3;
3268 mem_trp = ((temp >> 8) & 0x7) + 3;
3269 mem_tras = ((temp >> 11) & 0xf) + 6;
3270 } else if (rdev->family == CHIP_R420 ||
3271 rdev->family == CHIP_R423 ||
3272 rdev->family == CHIP_RV410) {
3273 /* r4xx */
3274 mem_trcd = (temp & 0xf) + 3;
3275 if (mem_trcd > 15)
3276 mem_trcd = 15;
3277 mem_trp = ((temp >> 8) & 0xf) + 3;
3278 if (mem_trp > 15)
3279 mem_trp = 15;
3280 mem_tras = ((temp >> 12) & 0x1f) + 6;
3281 if (mem_tras > 31)
3282 mem_tras = 31;
3283 } else { /* RV200, R200 */
3284 mem_trcd = (temp & 0x7) + 1;
3285 mem_trp = ((temp >> 8) & 0x7) + 1;
3286 mem_tras = ((temp >> 12) & 0xf) + 4;
3287 }
3288 /* convert to FF */
3289 trcd_ff.full = dfixed_const(mem_trcd);
3290 trp_ff.full = dfixed_const(mem_trp);
3291 tras_ff.full = dfixed_const(mem_tras);
3292
3293 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3294 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3295 data = (temp & (7 << 20)) >> 20;
3296 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3297 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3298 tcas_ff = memtcas_rs480_ff[data];
3299 else
3300 tcas_ff = memtcas_ff[data];
3301 } else
3302 tcas_ff = memtcas2_ff[data];
3303
3304 if (rdev->family == CHIP_RS400 ||
3305 rdev->family == CHIP_RS480) {
3306 /* extra cas latency stored in bits 23-25 0-4 clocks */
3307 data = (temp >> 23) & 0x7;
3308 if (data < 5)
3309 tcas_ff.full += dfixed_const(data);
3310 }
3311
3312 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3313 /* on the R300, Tcas is included in Trbs.
3314 */
3315 temp = RREG32(RADEON_MEM_CNTL);
3316 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3317 if (data == 1) {
3318 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3319 temp = RREG32(R300_MC_IND_INDEX);
3320 temp &= ~R300_MC_IND_ADDR_MASK;
3321 temp |= R300_MC_READ_CNTL_CD_mcind;
3322 WREG32(R300_MC_IND_INDEX, temp);
3323 temp = RREG32(R300_MC_IND_DATA);
3324 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3325 } else {
3326 temp = RREG32(R300_MC_READ_CNTL_AB);
3327 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3328 }
3329 } else {
3330 temp = RREG32(R300_MC_READ_CNTL_AB);
3331 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3332 }
3333 if (rdev->family == CHIP_RV410 ||
3334 rdev->family == CHIP_R420 ||
3335 rdev->family == CHIP_R423)
3336 trbs_ff = memtrbs_r4xx[data];
3337 else
3338 trbs_ff = memtrbs[data];
3339 tcas_ff.full += trbs_ff.full;
3340 }
3341
3342 sclk_eff_ff.full = sclk_ff.full;
3343
3344 if (rdev->flags & RADEON_IS_AGP) {
3345 fixed20_12 agpmode_ff;
3346 agpmode_ff.full = dfixed_const(radeon_agpmode);
3347 temp_ff.full = dfixed_const_666(16);
3348 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3349 }
3350 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3351
3352 if (ASIC_IS_R300(rdev)) {
3353 sclk_delay_ff.full = dfixed_const(250);
3354 } else {
3355 if ((rdev->family == CHIP_RV100) ||
3356 rdev->flags & RADEON_IS_IGP) {
3357 if (rdev->mc.vram_is_ddr)
3358 sclk_delay_ff.full = dfixed_const(41);
3359 else
3360 sclk_delay_ff.full = dfixed_const(33);
3361 } else {
3362 if (rdev->mc.vram_width == 128)
3363 sclk_delay_ff.full = dfixed_const(57);
3364 else
3365 sclk_delay_ff.full = dfixed_const(41);
3366 }
3367 }
3368
3369 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3370
3371 if (rdev->mc.vram_is_ddr) {
3372 if (rdev->mc.vram_width == 32) {
3373 k1.full = dfixed_const(40);
3374 c = 3;
3375 } else {
3376 k1.full = dfixed_const(20);
3377 c = 1;
3378 }
3379 } else {
3380 k1.full = dfixed_const(40);
3381 c = 3;
3382 }
3383
3384 temp_ff.full = dfixed_const(2);
3385 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3386 temp_ff.full = dfixed_const(c);
3387 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3388 temp_ff.full = dfixed_const(4);
3389 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3390 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3391 mc_latency_mclk.full += k1.full;
3392
3393 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3394 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3395
3396 /*
3397 HW cursor time assuming worst case of full size colour cursor.
3398 */
3399 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3400 temp_ff.full += trcd_ff.full;
3401 if (temp_ff.full < tras_ff.full)
3402 temp_ff.full = tras_ff.full;
3403 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3404
3405 temp_ff.full = dfixed_const(cur_size);
3406 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3407 /*
3408 Find the total latency for the display data.
3409 */
3410 disp_latency_overhead.full = dfixed_const(8);
3411 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3412 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3413 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3414
3415 if (mc_latency_mclk.full > mc_latency_sclk.full)
3416 disp_latency.full = mc_latency_mclk.full;
3417 else
3418 disp_latency.full = mc_latency_sclk.full;
3419
3420 /* setup Max GRPH_STOP_REQ default value */
3421 if (ASIC_IS_RV100(rdev))
3422 max_stop_req = 0x5c;
3423 else
3424 max_stop_req = 0x7c;
3425
3426 if (mode1) {
3427 /* CRTC1
3428 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3429 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3430 */
3431 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3432
3433 if (stop_req > max_stop_req)
3434 stop_req = max_stop_req;
3435
3436 /*
3437 Find the drain rate of the display buffer.
3438 */
3439 temp_ff.full = dfixed_const((16/pixel_bytes1));
3440 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3441
3442 /*
3443 Find the critical point of the display buffer.
3444 */
3445 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3446 crit_point_ff.full += dfixed_const_half(0);
3447
3448 critical_point = dfixed_trunc(crit_point_ff);
3449
3450 if (rdev->disp_priority == 2) {
3451 critical_point = 0;
3452 }
3453
3454 /*
3455 The critical point should never be above max_stop_req-4. Setting
3456 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3457 */
3458 if (max_stop_req - critical_point < 4)
3459 critical_point = 0;
3460
3461 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3462 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3463 critical_point = 0x10;
3464 }
3465
3466 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3467 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3468 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3469 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3470 if ((rdev->family == CHIP_R350) &&
3471 (stop_req > 0x15)) {
3472 stop_req -= 0x10;
3473 }
3474 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3475 temp |= RADEON_GRPH_BUFFER_SIZE;
3476 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3477 RADEON_GRPH_CRITICAL_AT_SOF |
3478 RADEON_GRPH_STOP_CNTL);
3479 /*
3480 Write the result into the register.
3481 */
3482 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3483 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3484
3485 #if 0
3486 if ((rdev->family == CHIP_RS400) ||
3487 (rdev->family == CHIP_RS480)) {
3488 /* attempt to program RS400 disp regs correctly ??? */
3489 temp = RREG32(RS400_DISP1_REG_CNTL);
3490 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3491 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3492 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3493 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3494 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3495 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3496 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3497 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3498 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3499 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3500 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3501 }
3502 #endif
3503
3504 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3505 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3506 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3507 }
3508
3509 if (mode2) {
3510 u32 grph2_cntl;
3511 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3512
3513 if (stop_req > max_stop_req)
3514 stop_req = max_stop_req;
3515
3516 /*
3517 Find the drain rate of the display buffer.
3518 */
3519 temp_ff.full = dfixed_const((16/pixel_bytes2));
3520 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3521
3522 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3523 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3524 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3525 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3526 if ((rdev->family == CHIP_R350) &&
3527 (stop_req > 0x15)) {
3528 stop_req -= 0x10;
3529 }
3530 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3531 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3532 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3533 RADEON_GRPH_CRITICAL_AT_SOF |
3534 RADEON_GRPH_STOP_CNTL);
3535
3536 if ((rdev->family == CHIP_RS100) ||
3537 (rdev->family == CHIP_RS200))
3538 critical_point2 = 0;
3539 else {
3540 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3541 temp_ff.full = dfixed_const(temp);
3542 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3543 if (sclk_ff.full < temp_ff.full)
3544 temp_ff.full = sclk_ff.full;
3545
3546 read_return_rate.full = temp_ff.full;
3547
3548 if (mode1) {
3549 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3550 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3551 } else {
3552 time_disp1_drop_priority.full = 0;
3553 }
3554 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3555 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3556 crit_point_ff.full += dfixed_const_half(0);
3557
3558 critical_point2 = dfixed_trunc(crit_point_ff);
3559
3560 if (rdev->disp_priority == 2) {
3561 critical_point2 = 0;
3562 }
3563
3564 if (max_stop_req - critical_point2 < 4)
3565 critical_point2 = 0;
3566
3567 }
3568
3569 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3570 /* some R300 cards have problem with this set to 0 */
3571 critical_point2 = 0x10;
3572 }
3573
3574 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3575 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3576
3577 if ((rdev->family == CHIP_RS400) ||
3578 (rdev->family == CHIP_RS480)) {
3579 #if 0
3580 /* attempt to program RS400 disp2 regs correctly ??? */
3581 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3582 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3583 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3584 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3585 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3586 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3587 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3588 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3589 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3590 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3591 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3592 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3593 #endif
3594 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3595 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3596 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3597 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3598 }
3599
3600 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3601 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3602 }
3603 }
3604
3605 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3606 {
3607 uint32_t scratch;
3608 uint32_t tmp = 0;
3609 unsigned i;
3610 int r;
3611
3612 r = radeon_scratch_get(rdev, &scratch);
3613 if (r) {
3614 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3615 return r;
3616 }
3617 WREG32(scratch, 0xCAFEDEAD);
3618 r = radeon_ring_lock(rdev, ring, 2);
3619 if (r) {
3620 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3621 radeon_scratch_free(rdev, scratch);
3622 return r;
3623 }
3624 radeon_ring_write(ring, PACKET0(scratch, 0));
3625 radeon_ring_write(ring, 0xDEADBEEF);
3626 radeon_ring_unlock_commit(rdev, ring);
3627 for (i = 0; i < rdev->usec_timeout; i++) {
3628 tmp = RREG32(scratch);
3629 if (tmp == 0xDEADBEEF) {
3630 break;
3631 }
3632 DRM_UDELAY(1);
3633 }
3634 if (i < rdev->usec_timeout) {
3635 DRM_INFO("ring test succeeded in %d usecs\n", i);
3636 } else {
3637 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3638 scratch, tmp);
3639 r = -EINVAL;
3640 }
3641 radeon_scratch_free(rdev, scratch);
3642 return r;
3643 }
3644
3645 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3646 {
3647 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3648
3649 if (ring->rptr_save_reg) {
3650 u32 next_rptr = ring->wptr + 2 + 3;
3651 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3652 radeon_ring_write(ring, next_rptr);
3653 }
3654
3655 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3656 radeon_ring_write(ring, ib->gpu_addr);
3657 radeon_ring_write(ring, ib->length_dw);
3658 }
3659
3660 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3661 {
3662 struct radeon_ib ib;
3663 uint32_t scratch;
3664 uint32_t tmp = 0;
3665 unsigned i;
3666 int r;
3667
3668 r = radeon_scratch_get(rdev, &scratch);
3669 if (r) {
3670 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3671 return r;
3672 }
3673 WREG32(scratch, 0xCAFEDEAD);
3674 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3675 if (r) {
3676 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3677 goto free_scratch;
3678 }
3679 ib.ptr[0] = PACKET0(scratch, 0);
3680 ib.ptr[1] = 0xDEADBEEF;
3681 ib.ptr[2] = PACKET2(0);
3682 ib.ptr[3] = PACKET2(0);
3683 ib.ptr[4] = PACKET2(0);
3684 ib.ptr[5] = PACKET2(0);
3685 ib.ptr[6] = PACKET2(0);
3686 ib.ptr[7] = PACKET2(0);
3687 ib.length_dw = 8;
3688 r = radeon_ib_schedule(rdev, &ib, NULL);
3689 if (r) {
3690 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3691 goto free_ib;
3692 }
3693 r = radeon_fence_wait(ib.fence, false);
3694 if (r) {
3695 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3696 goto free_ib;
3697 }
3698 for (i = 0; i < rdev->usec_timeout; i++) {
3699 tmp = RREG32(scratch);
3700 if (tmp == 0xDEADBEEF) {
3701 break;
3702 }
3703 DRM_UDELAY(1);
3704 }
3705 if (i < rdev->usec_timeout) {
3706 DRM_INFO("ib test succeeded in %u usecs\n", i);
3707 } else {
3708 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3709 scratch, tmp);
3710 r = -EINVAL;
3711 }
3712 free_ib:
3713 radeon_ib_free(rdev, &ib);
3714 free_scratch:
3715 radeon_scratch_free(rdev, scratch);
3716 return r;
3717 }
3718
3719 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3720 {
3721 /* Shutdown CP we shouldn't need to do that but better be safe than
3722 * sorry
3723 */
3724 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3725 WREG32(R_000740_CP_CSQ_CNTL, 0);
3726
3727 /* Save few CRTC registers */
3728 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3729 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3730 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3731 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3732 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3733 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3734 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3735 }
3736
3737 /* Disable VGA aperture access */
3738 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3739 /* Disable cursor, overlay, crtc */
3740 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3741 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3742 S_000054_CRTC_DISPLAY_DIS(1));
3743 WREG32(R_000050_CRTC_GEN_CNTL,
3744 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3745 S_000050_CRTC_DISP_REQ_EN_B(1));
3746 WREG32(R_000420_OV0_SCALE_CNTL,
3747 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3748 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3749 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3750 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3751 S_000360_CUR2_LOCK(1));
3752 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3753 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3754 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3755 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3756 WREG32(R_000360_CUR2_OFFSET,
3757 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3758 }
3759 }
3760
3761 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3762 {
3763 /* Update base address for crtc */
3764 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3765 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3766 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3767 }
3768 /* Restore CRTC registers */
3769 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3770 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3771 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3772 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3773 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3774 }
3775 }
3776
3777 void r100_vga_render_disable(struct radeon_device *rdev)
3778 {
3779 u32 tmp;
3780
3781 tmp = RREG8(R_0003C2_GENMO_WT);
3782 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3783 }
3784
3785 static void r100_debugfs(struct radeon_device *rdev)
3786 {
3787 int r;
3788
3789 r = r100_debugfs_mc_info_init(rdev);
3790 if (r)
3791 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3792 }
3793
3794 static void r100_mc_program(struct radeon_device *rdev)
3795 {
3796 struct r100_mc_save save;
3797
3798 /* Stops all mc clients */
3799 r100_mc_stop(rdev, &save);
3800 if (rdev->flags & RADEON_IS_AGP) {
3801 WREG32(R_00014C_MC_AGP_LOCATION,
3802 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3803 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3804 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3805 if (rdev->family > CHIP_RV200)
3806 WREG32(R_00015C_AGP_BASE_2,
3807 upper_32_bits(rdev->mc.agp_base) & 0xff);
3808 } else {
3809 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3810 WREG32(R_000170_AGP_BASE, 0);
3811 if (rdev->family > CHIP_RV200)
3812 WREG32(R_00015C_AGP_BASE_2, 0);
3813 }
3814 /* Wait for mc idle */
3815 if (r100_mc_wait_for_idle(rdev))
3816 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3817 /* Program MC, should be a 32bits limited address space */
3818 WREG32(R_000148_MC_FB_LOCATION,
3819 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3820 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3821 r100_mc_resume(rdev, &save);
3822 }
3823
3824 static void r100_clock_startup(struct radeon_device *rdev)
3825 {
3826 u32 tmp;
3827
3828 if (radeon_dynclks != -1 && radeon_dynclks)
3829 radeon_legacy_set_clock_gating(rdev, 1);
3830 /* We need to force on some of the block */
3831 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3832 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3833 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3834 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3835 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3836 }
3837
3838 static int r100_startup(struct radeon_device *rdev)
3839 {
3840 int r;
3841
3842 /* set common regs */
3843 r100_set_common_regs(rdev);
3844 /* program mc */
3845 r100_mc_program(rdev);
3846 /* Resume clock */
3847 r100_clock_startup(rdev);
3848 /* Initialize GART (initialize after TTM so we can allocate
3849 * memory through TTM but finalize after TTM) */
3850 r100_enable_bm(rdev);
3851 if (rdev->flags & RADEON_IS_PCI) {
3852 r = r100_pci_gart_enable(rdev);
3853 if (r)
3854 return r;
3855 }
3856
3857 /* allocate wb buffer */
3858 r = radeon_wb_init(rdev);
3859 if (r)
3860 return r;
3861
3862 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3863 if (r) {
3864 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3865 return r;
3866 }
3867
3868 /* Enable IRQ */
3869 if (!rdev->irq.installed) {
3870 r = radeon_irq_kms_init(rdev);
3871 if (r)
3872 return r;
3873 }
3874
3875 r100_irq_set(rdev);
3876 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3877 /* 1M ring buffer */
3878 r = r100_cp_init(rdev, 1024 * 1024);
3879 if (r) {
3880 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3881 return r;
3882 }
3883
3884 r = radeon_ib_pool_init(rdev);
3885 if (r) {
3886 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3887 return r;
3888 }
3889
3890 return 0;
3891 }
3892
3893 int r100_resume(struct radeon_device *rdev)
3894 {
3895 int r;
3896
3897 /* Make sur GART are not working */
3898 if (rdev->flags & RADEON_IS_PCI)
3899 r100_pci_gart_disable(rdev);
3900 /* Resume clock before doing reset */
3901 r100_clock_startup(rdev);
3902 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3903 if (radeon_asic_reset(rdev)) {
3904 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3905 RREG32(R_000E40_RBBM_STATUS),
3906 RREG32(R_0007C0_CP_STAT));
3907 }
3908 /* post */
3909 radeon_combios_asic_init(rdev->ddev);
3910 /* Resume clock after posting */
3911 r100_clock_startup(rdev);
3912 /* Initialize surface registers */
3913 radeon_surface_init(rdev);
3914
3915 rdev->accel_working = true;
3916 r = r100_startup(rdev);
3917 if (r) {
3918 rdev->accel_working = false;
3919 }
3920 return r;
3921 }
3922
3923 int r100_suspend(struct radeon_device *rdev)
3924 {
3925 r100_cp_disable(rdev);
3926 radeon_wb_disable(rdev);
3927 r100_irq_disable(rdev);
3928 if (rdev->flags & RADEON_IS_PCI)
3929 r100_pci_gart_disable(rdev);
3930 return 0;
3931 }
3932
3933 void r100_fini(struct radeon_device *rdev)
3934 {
3935 r100_cp_fini(rdev);
3936 radeon_wb_fini(rdev);
3937 radeon_ib_pool_fini(rdev);
3938 radeon_gem_fini(rdev);
3939 if (rdev->flags & RADEON_IS_PCI)
3940 r100_pci_gart_fini(rdev);
3941 radeon_agp_fini(rdev);
3942 radeon_irq_kms_fini(rdev);
3943 radeon_fence_driver_fini(rdev);
3944 radeon_bo_fini(rdev);
3945 radeon_atombios_fini(rdev);
3946 kfree(rdev->bios);
3947 rdev->bios = NULL;
3948 }
3949
3950 /*
3951 * Due to how kexec works, it can leave the hw fully initialised when it
3952 * boots the new kernel. However doing our init sequence with the CP and
3953 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3954 * do some quick sanity checks and restore sane values to avoid this
3955 * problem.
3956 */
3957 void r100_restore_sanity(struct radeon_device *rdev)
3958 {
3959 u32 tmp;
3960
3961 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3962 if (tmp) {
3963 WREG32(RADEON_CP_CSQ_CNTL, 0);
3964 }
3965 tmp = RREG32(RADEON_CP_RB_CNTL);
3966 if (tmp) {
3967 WREG32(RADEON_CP_RB_CNTL, 0);
3968 }
3969 tmp = RREG32(RADEON_SCRATCH_UMSK);
3970 if (tmp) {
3971 WREG32(RADEON_SCRATCH_UMSK, 0);
3972 }
3973 }
3974
3975 int r100_init(struct radeon_device *rdev)
3976 {
3977 int r;
3978
3979 /* Register debugfs file specific to this group of asics */
3980 r100_debugfs(rdev);
3981 /* Disable VGA */
3982 r100_vga_render_disable(rdev);
3983 /* Initialize scratch registers */
3984 radeon_scratch_init(rdev);
3985 /* Initialize surface registers */
3986 radeon_surface_init(rdev);
3987 /* sanity check some register to avoid hangs like after kexec */
3988 r100_restore_sanity(rdev);
3989 /* TODO: disable VGA need to use VGA request */
3990 /* BIOS*/
3991 if (!radeon_get_bios(rdev)) {
3992 if (ASIC_IS_AVIVO(rdev))
3993 return -EINVAL;
3994 }
3995 if (rdev->is_atom_bios) {
3996 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3997 return -EINVAL;
3998 } else {
3999 r = radeon_combios_init(rdev);
4000 if (r)
4001 return r;
4002 }
4003 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4004 if (radeon_asic_reset(rdev)) {
4005 dev_warn(rdev->dev,
4006 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4007 RREG32(R_000E40_RBBM_STATUS),
4008 RREG32(R_0007C0_CP_STAT));
4009 }
4010 /* check if cards are posted or not */
4011 if (radeon_boot_test_post_card(rdev) == false)
4012 return -EINVAL;
4013 /* Set asic errata */
4014 r100_errata(rdev);
4015 /* Initialize clocks */
4016 radeon_get_clock_info(rdev->ddev);
4017 /* initialize AGP */
4018 if (rdev->flags & RADEON_IS_AGP) {
4019 r = radeon_agp_init(rdev);
4020 if (r) {
4021 radeon_agp_disable(rdev);
4022 }
4023 }
4024 /* initialize VRAM */
4025 r100_mc_init(rdev);
4026 /* Fence driver */
4027 r = radeon_fence_driver_init(rdev);
4028 if (r)
4029 return r;
4030 /* Memory manager */
4031 r = radeon_bo_init(rdev);
4032 if (r)
4033 return r;
4034 if (rdev->flags & RADEON_IS_PCI) {
4035 r = r100_pci_gart_init(rdev);
4036 if (r)
4037 return r;
4038 }
4039 r100_set_safe_registers(rdev);
4040
4041 rdev->accel_working = true;
4042 r = r100_startup(rdev);
4043 if (r) {
4044 /* Somethings want wront with the accel init stop accel */
4045 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4046 r100_cp_fini(rdev);
4047 radeon_wb_fini(rdev);
4048 radeon_ib_pool_fini(rdev);
4049 radeon_irq_kms_fini(rdev);
4050 if (rdev->flags & RADEON_IS_PCI)
4051 r100_pci_gart_fini(rdev);
4052 rdev->accel_working = false;
4053 }
4054 return 0;
4055 }
4056
4057 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4058 bool always_indirect)
4059 {
4060 if (reg < rdev->rmmio_size && !always_indirect)
4061 return readl(((void __iomem *)rdev->rmmio) + reg);
4062 else {
4063 unsigned long flags;
4064 uint32_t ret;
4065
4066 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4067 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4068 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4069 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4070
4071 return ret;
4072 }
4073 }
4074
4075 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4076 bool always_indirect)
4077 {
4078 if (reg < rdev->rmmio_size && !always_indirect)
4079 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4080 else {
4081 unsigned long flags;
4082
4083 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4084 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4085 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4086 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4087 }
4088 }
4089
4090 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4091 {
4092 if (reg < rdev->rio_mem_size)
4093 return ioread32(rdev->rio_mem + reg);
4094 else {
4095 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4096 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4097 }
4098 }
4099
4100 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4101 {
4102 if (reg < rdev->rio_mem_size)
4103 iowrite32(v, rdev->rio_mem + reg);
4104 else {
4105 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4106 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4107 }
4108 }
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