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Merge branch 'topic/hda' into for-linus
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "r100d.h"
35 #include "rs100d.h"
36 #include "rv200d.h"
37 #include "rv250d.h"
38
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
41
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
44
45 /* Firmware Names */
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54 MODULE_FIRMWARE(FIRMWARE_R100);
55 MODULE_FIRMWARE(FIRMWARE_R200);
56 MODULE_FIRMWARE(FIRMWARE_R300);
57 MODULE_FIRMWARE(FIRMWARE_R420);
58 MODULE_FIRMWARE(FIRMWARE_RS690);
59 MODULE_FIRMWARE(FIRMWARE_RS600);
60 MODULE_FIRMWARE(FIRMWARE_R520);
61
62 #include "r100_track.h"
63
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
66 */
67
68 /* hpd for digital panel detect/disconnect */
69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
70 {
71 bool connected = false;
72
73 switch (hpd) {
74 case RADEON_HPD_1:
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
76 connected = true;
77 break;
78 case RADEON_HPD_2:
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86 }
87
88 void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90 {
91 u32 tmp;
92 bool connected = r100_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
97 if (connected)
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
99 else
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
105 if (connected)
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
107 else
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
110 break;
111 default:
112 break;
113 }
114 }
115
116 void r100_hpd_init(struct radeon_device *rdev)
117 {
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 rdev->irq.hpd[0] = true;
126 break;
127 case RADEON_HPD_2:
128 rdev->irq.hpd[1] = true;
129 break;
130 default:
131 break;
132 }
133 }
134 if (rdev->irq.installed)
135 r100_irq_set(rdev);
136 }
137
138 void r100_hpd_fini(struct radeon_device *rdev)
139 {
140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
142
143 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
144 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
145 switch (radeon_connector->hpd.hpd) {
146 case RADEON_HPD_1:
147 rdev->irq.hpd[0] = false;
148 break;
149 case RADEON_HPD_2:
150 rdev->irq.hpd[1] = false;
151 break;
152 default:
153 break;
154 }
155 }
156 }
157
158 /*
159 * PCI GART
160 */
161 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
162 {
163 /* TODO: can we do somethings here ? */
164 /* It seems hw only cache one entry so we should discard this
165 * entry otherwise if first GPU GART read hit this entry it
166 * could end up in wrong address. */
167 }
168
169 int r100_pci_gart_init(struct radeon_device *rdev)
170 {
171 int r;
172
173 if (rdev->gart.table.ram.ptr) {
174 WARN(1, "R100 PCI GART already initialized.\n");
175 return 0;
176 }
177 /* Initialize common gart structure */
178 r = radeon_gart_init(rdev);
179 if (r)
180 return r;
181 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
182 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
183 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
184 return radeon_gart_table_ram_alloc(rdev);
185 }
186
187 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
188 void r100_enable_bm(struct radeon_device *rdev)
189 {
190 uint32_t tmp;
191 /* Enable bus mastering */
192 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
193 WREG32(RADEON_BUS_CNTL, tmp);
194 }
195
196 int r100_pci_gart_enable(struct radeon_device *rdev)
197 {
198 uint32_t tmp;
199
200 /* discard memory request outside of configured range */
201 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
202 WREG32(RADEON_AIC_CNTL, tmp);
203 /* set address range for PCI address translate */
204 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
205 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
206 WREG32(RADEON_AIC_HI_ADDR, tmp);
207 /* set PCI GART page-table base address */
208 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
209 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
210 WREG32(RADEON_AIC_CNTL, tmp);
211 r100_pci_gart_tlb_flush(rdev);
212 rdev->gart.ready = true;
213 return 0;
214 }
215
216 void r100_pci_gart_disable(struct radeon_device *rdev)
217 {
218 uint32_t tmp;
219
220 /* discard memory request outside of configured range */
221 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
222 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
223 WREG32(RADEON_AIC_LO_ADDR, 0);
224 WREG32(RADEON_AIC_HI_ADDR, 0);
225 }
226
227 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
228 {
229 if (i < 0 || i > rdev->gart.num_gpu_pages) {
230 return -EINVAL;
231 }
232 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
233 return 0;
234 }
235
236 void r100_pci_gart_fini(struct radeon_device *rdev)
237 {
238 r100_pci_gart_disable(rdev);
239 radeon_gart_table_ram_free(rdev);
240 radeon_gart_fini(rdev);
241 }
242
243 int r100_irq_set(struct radeon_device *rdev)
244 {
245 uint32_t tmp = 0;
246
247 if (!rdev->irq.installed) {
248 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
249 WREG32(R_000040_GEN_INT_CNTL, 0);
250 return -EINVAL;
251 }
252 if (rdev->irq.sw_int) {
253 tmp |= RADEON_SW_INT_ENABLE;
254 }
255 if (rdev->irq.crtc_vblank_int[0]) {
256 tmp |= RADEON_CRTC_VBLANK_MASK;
257 }
258 if (rdev->irq.crtc_vblank_int[1]) {
259 tmp |= RADEON_CRTC2_VBLANK_MASK;
260 }
261 if (rdev->irq.hpd[0]) {
262 tmp |= RADEON_FP_DETECT_MASK;
263 }
264 if (rdev->irq.hpd[1]) {
265 tmp |= RADEON_FP2_DETECT_MASK;
266 }
267 WREG32(RADEON_GEN_INT_CNTL, tmp);
268 return 0;
269 }
270
271 void r100_irq_disable(struct radeon_device *rdev)
272 {
273 u32 tmp;
274
275 WREG32(R_000040_GEN_INT_CNTL, 0);
276 /* Wait and acknowledge irq */
277 mdelay(1);
278 tmp = RREG32(R_000044_GEN_INT_STATUS);
279 WREG32(R_000044_GEN_INT_STATUS, tmp);
280 }
281
282 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
283 {
284 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
285 uint32_t irq_mask = RADEON_SW_INT_TEST |
286 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
287 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
288
289 if (irqs) {
290 WREG32(RADEON_GEN_INT_STATUS, irqs);
291 }
292 return irqs & irq_mask;
293 }
294
295 int r100_irq_process(struct radeon_device *rdev)
296 {
297 uint32_t status, msi_rearm;
298 bool queue_hotplug = false;
299
300 status = r100_irq_ack(rdev);
301 if (!status) {
302 return IRQ_NONE;
303 }
304 if (rdev->shutdown) {
305 return IRQ_NONE;
306 }
307 while (status) {
308 /* SW interrupt */
309 if (status & RADEON_SW_INT_TEST) {
310 radeon_fence_process(rdev);
311 }
312 /* Vertical blank interrupts */
313 if (status & RADEON_CRTC_VBLANK_STAT) {
314 drm_handle_vblank(rdev->ddev, 0);
315 }
316 if (status & RADEON_CRTC2_VBLANK_STAT) {
317 drm_handle_vblank(rdev->ddev, 1);
318 }
319 if (status & RADEON_FP_DETECT_STAT) {
320 queue_hotplug = true;
321 DRM_DEBUG("HPD1\n");
322 }
323 if (status & RADEON_FP2_DETECT_STAT) {
324 queue_hotplug = true;
325 DRM_DEBUG("HPD2\n");
326 }
327 status = r100_irq_ack(rdev);
328 }
329 if (queue_hotplug)
330 queue_work(rdev->wq, &rdev->hotplug_work);
331 if (rdev->msi_enabled) {
332 switch (rdev->family) {
333 case CHIP_RS400:
334 case CHIP_RS480:
335 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
336 WREG32(RADEON_AIC_CNTL, msi_rearm);
337 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
338 break;
339 default:
340 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
341 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
342 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
343 break;
344 }
345 }
346 return IRQ_HANDLED;
347 }
348
349 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
350 {
351 if (crtc == 0)
352 return RREG32(RADEON_CRTC_CRNT_FRAME);
353 else
354 return RREG32(RADEON_CRTC2_CRNT_FRAME);
355 }
356
357 /* Who ever call radeon_fence_emit should call ring_lock and ask
358 * for enough space (today caller are ib schedule and buffer move) */
359 void r100_fence_ring_emit(struct radeon_device *rdev,
360 struct radeon_fence *fence)
361 {
362 /* We have to make sure that caches are flushed before
363 * CPU might read something from VRAM. */
364 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
365 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
368 /* Wait until IDLE & CLEAN */
369 radeon_ring_write(rdev, PACKET0(0x1720, 0));
370 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
371 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
372 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
373 RADEON_HDP_READ_BUFFER_INVALIDATE);
374 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
375 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
376 /* Emit fence sequence & fire IRQ */
377 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
378 radeon_ring_write(rdev, fence->seq);
379 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
380 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
381 }
382
383 int r100_wb_init(struct radeon_device *rdev)
384 {
385 int r;
386
387 if (rdev->wb.wb_obj == NULL) {
388 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
389 RADEON_GEM_DOMAIN_GTT,
390 &rdev->wb.wb_obj);
391 if (r) {
392 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
393 return r;
394 }
395 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
396 if (unlikely(r != 0))
397 return r;
398 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
399 &rdev->wb.gpu_addr);
400 if (r) {
401 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
402 radeon_bo_unreserve(rdev->wb.wb_obj);
403 return r;
404 }
405 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
406 radeon_bo_unreserve(rdev->wb.wb_obj);
407 if (r) {
408 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
409 return r;
410 }
411 }
412 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
413 WREG32(R_00070C_CP_RB_RPTR_ADDR,
414 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
415 WREG32(R_000770_SCRATCH_UMSK, 0xff);
416 return 0;
417 }
418
419 void r100_wb_disable(struct radeon_device *rdev)
420 {
421 WREG32(R_000770_SCRATCH_UMSK, 0);
422 }
423
424 void r100_wb_fini(struct radeon_device *rdev)
425 {
426 int r;
427
428 r100_wb_disable(rdev);
429 if (rdev->wb.wb_obj) {
430 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
431 if (unlikely(r != 0)) {
432 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
433 return;
434 }
435 radeon_bo_kunmap(rdev->wb.wb_obj);
436 radeon_bo_unpin(rdev->wb.wb_obj);
437 radeon_bo_unreserve(rdev->wb.wb_obj);
438 radeon_bo_unref(&rdev->wb.wb_obj);
439 rdev->wb.wb = NULL;
440 rdev->wb.wb_obj = NULL;
441 }
442 }
443
444 int r100_copy_blit(struct radeon_device *rdev,
445 uint64_t src_offset,
446 uint64_t dst_offset,
447 unsigned num_pages,
448 struct radeon_fence *fence)
449 {
450 uint32_t cur_pages;
451 uint32_t stride_bytes = PAGE_SIZE;
452 uint32_t pitch;
453 uint32_t stride_pixels;
454 unsigned ndw;
455 int num_loops;
456 int r = 0;
457
458 /* radeon limited to 16k stride */
459 stride_bytes &= 0x3fff;
460 /* radeon pitch is /64 */
461 pitch = stride_bytes / 64;
462 stride_pixels = stride_bytes / 4;
463 num_loops = DIV_ROUND_UP(num_pages, 8191);
464
465 /* Ask for enough room for blit + flush + fence */
466 ndw = 64 + (10 * num_loops);
467 r = radeon_ring_lock(rdev, ndw);
468 if (r) {
469 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
470 return -EINVAL;
471 }
472 while (num_pages > 0) {
473 cur_pages = num_pages;
474 if (cur_pages > 8191) {
475 cur_pages = 8191;
476 }
477 num_pages -= cur_pages;
478
479 /* pages are in Y direction - height
480 page width in X direction - width */
481 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
482 radeon_ring_write(rdev,
483 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
484 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
485 RADEON_GMC_SRC_CLIPPING |
486 RADEON_GMC_DST_CLIPPING |
487 RADEON_GMC_BRUSH_NONE |
488 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
489 RADEON_GMC_SRC_DATATYPE_COLOR |
490 RADEON_ROP3_S |
491 RADEON_DP_SRC_SOURCE_MEMORY |
492 RADEON_GMC_CLR_CMP_CNTL_DIS |
493 RADEON_GMC_WR_MSK_DIS);
494 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
495 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
496 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
497 radeon_ring_write(rdev, 0);
498 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
499 radeon_ring_write(rdev, num_pages);
500 radeon_ring_write(rdev, num_pages);
501 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
502 }
503 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
504 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
505 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
506 radeon_ring_write(rdev,
507 RADEON_WAIT_2D_IDLECLEAN |
508 RADEON_WAIT_HOST_IDLECLEAN |
509 RADEON_WAIT_DMA_GUI_IDLE);
510 if (fence) {
511 r = radeon_fence_emit(rdev, fence);
512 }
513 radeon_ring_unlock_commit(rdev);
514 return r;
515 }
516
517 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
518 {
519 unsigned i;
520 u32 tmp;
521
522 for (i = 0; i < rdev->usec_timeout; i++) {
523 tmp = RREG32(R_000E40_RBBM_STATUS);
524 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
525 return 0;
526 }
527 udelay(1);
528 }
529 return -1;
530 }
531
532 void r100_ring_start(struct radeon_device *rdev)
533 {
534 int r;
535
536 r = radeon_ring_lock(rdev, 2);
537 if (r) {
538 return;
539 }
540 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
541 radeon_ring_write(rdev,
542 RADEON_ISYNC_ANY2D_IDLE3D |
543 RADEON_ISYNC_ANY3D_IDLE2D |
544 RADEON_ISYNC_WAIT_IDLEGUI |
545 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
546 radeon_ring_unlock_commit(rdev);
547 }
548
549
550 /* Load the microcode for the CP */
551 static int r100_cp_init_microcode(struct radeon_device *rdev)
552 {
553 struct platform_device *pdev;
554 const char *fw_name = NULL;
555 int err;
556
557 DRM_DEBUG("\n");
558
559 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
560 err = IS_ERR(pdev);
561 if (err) {
562 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
563 return -EINVAL;
564 }
565 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
566 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
567 (rdev->family == CHIP_RS200)) {
568 DRM_INFO("Loading R100 Microcode\n");
569 fw_name = FIRMWARE_R100;
570 } else if ((rdev->family == CHIP_R200) ||
571 (rdev->family == CHIP_RV250) ||
572 (rdev->family == CHIP_RV280) ||
573 (rdev->family == CHIP_RS300)) {
574 DRM_INFO("Loading R200 Microcode\n");
575 fw_name = FIRMWARE_R200;
576 } else if ((rdev->family == CHIP_R300) ||
577 (rdev->family == CHIP_R350) ||
578 (rdev->family == CHIP_RV350) ||
579 (rdev->family == CHIP_RV380) ||
580 (rdev->family == CHIP_RS400) ||
581 (rdev->family == CHIP_RS480)) {
582 DRM_INFO("Loading R300 Microcode\n");
583 fw_name = FIRMWARE_R300;
584 } else if ((rdev->family == CHIP_R420) ||
585 (rdev->family == CHIP_R423) ||
586 (rdev->family == CHIP_RV410)) {
587 DRM_INFO("Loading R400 Microcode\n");
588 fw_name = FIRMWARE_R420;
589 } else if ((rdev->family == CHIP_RS690) ||
590 (rdev->family == CHIP_RS740)) {
591 DRM_INFO("Loading RS690/RS740 Microcode\n");
592 fw_name = FIRMWARE_RS690;
593 } else if (rdev->family == CHIP_RS600) {
594 DRM_INFO("Loading RS600 Microcode\n");
595 fw_name = FIRMWARE_RS600;
596 } else if ((rdev->family == CHIP_RV515) ||
597 (rdev->family == CHIP_R520) ||
598 (rdev->family == CHIP_RV530) ||
599 (rdev->family == CHIP_R580) ||
600 (rdev->family == CHIP_RV560) ||
601 (rdev->family == CHIP_RV570)) {
602 DRM_INFO("Loading R500 Microcode\n");
603 fw_name = FIRMWARE_R520;
604 }
605
606 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
607 platform_device_unregister(pdev);
608 if (err) {
609 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
610 fw_name);
611 } else if (rdev->me_fw->size % 8) {
612 printk(KERN_ERR
613 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
614 rdev->me_fw->size, fw_name);
615 err = -EINVAL;
616 release_firmware(rdev->me_fw);
617 rdev->me_fw = NULL;
618 }
619 return err;
620 }
621
622 static void r100_cp_load_microcode(struct radeon_device *rdev)
623 {
624 const __be32 *fw_data;
625 int i, size;
626
627 if (r100_gui_wait_for_idle(rdev)) {
628 printk(KERN_WARNING "Failed to wait GUI idle while "
629 "programming pipes. Bad things might happen.\n");
630 }
631
632 if (rdev->me_fw) {
633 size = rdev->me_fw->size / 4;
634 fw_data = (const __be32 *)&rdev->me_fw->data[0];
635 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
636 for (i = 0; i < size; i += 2) {
637 WREG32(RADEON_CP_ME_RAM_DATAH,
638 be32_to_cpup(&fw_data[i]));
639 WREG32(RADEON_CP_ME_RAM_DATAL,
640 be32_to_cpup(&fw_data[i + 1]));
641 }
642 }
643 }
644
645 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
646 {
647 unsigned rb_bufsz;
648 unsigned rb_blksz;
649 unsigned max_fetch;
650 unsigned pre_write_timer;
651 unsigned pre_write_limit;
652 unsigned indirect2_start;
653 unsigned indirect1_start;
654 uint32_t tmp;
655 int r;
656
657 if (r100_debugfs_cp_init(rdev)) {
658 DRM_ERROR("Failed to register debugfs file for CP !\n");
659 }
660 /* Reset CP */
661 tmp = RREG32(RADEON_CP_CSQ_STAT);
662 if ((tmp & (1 << 31))) {
663 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
664 WREG32(RADEON_CP_CSQ_MODE, 0);
665 WREG32(RADEON_CP_CSQ_CNTL, 0);
666 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
667 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
668 mdelay(2);
669 WREG32(RADEON_RBBM_SOFT_RESET, 0);
670 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
671 mdelay(2);
672 tmp = RREG32(RADEON_CP_CSQ_STAT);
673 if ((tmp & (1 << 31))) {
674 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
675 }
676 } else {
677 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
678 }
679
680 if (!rdev->me_fw) {
681 r = r100_cp_init_microcode(rdev);
682 if (r) {
683 DRM_ERROR("Failed to load firmware!\n");
684 return r;
685 }
686 }
687
688 /* Align ring size */
689 rb_bufsz = drm_order(ring_size / 8);
690 ring_size = (1 << (rb_bufsz + 1)) * 4;
691 r100_cp_load_microcode(rdev);
692 r = radeon_ring_init(rdev, ring_size);
693 if (r) {
694 return r;
695 }
696 /* Each time the cp read 1024 bytes (16 dword/quadword) update
697 * the rptr copy in system ram */
698 rb_blksz = 9;
699 /* cp will read 128bytes at a time (4 dwords) */
700 max_fetch = 1;
701 rdev->cp.align_mask = 16 - 1;
702 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
703 pre_write_timer = 64;
704 /* Force CP_RB_WPTR write if written more than one time before the
705 * delay expire
706 */
707 pre_write_limit = 0;
708 /* Setup the cp cache like this (cache size is 96 dwords) :
709 * RING 0 to 15
710 * INDIRECT1 16 to 79
711 * INDIRECT2 80 to 95
712 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
713 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
714 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
715 * Idea being that most of the gpu cmd will be through indirect1 buffer
716 * so it gets the bigger cache.
717 */
718 indirect2_start = 80;
719 indirect1_start = 16;
720 /* cp setup */
721 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
722 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
723 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724 REG_SET(RADEON_MAX_FETCH, max_fetch) |
725 RADEON_RB_NO_UPDATE);
726 #ifdef __BIG_ENDIAN
727 tmp |= RADEON_BUF_SWAP_32BIT;
728 #endif
729 WREG32(RADEON_CP_RB_CNTL, tmp);
730
731 /* Set ring address */
732 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
733 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
734 /* Force read & write ptr to 0 */
735 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
736 WREG32(RADEON_CP_RB_RPTR_WR, 0);
737 WREG32(RADEON_CP_RB_WPTR, 0);
738 WREG32(RADEON_CP_RB_CNTL, tmp);
739 udelay(10);
740 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
741 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
742 /* Set cp mode to bus mastering & enable cp*/
743 WREG32(RADEON_CP_CSQ_MODE,
744 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
745 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
746 WREG32(0x718, 0);
747 WREG32(0x744, 0x00004D4D);
748 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
749 radeon_ring_start(rdev);
750 r = radeon_ring_test(rdev);
751 if (r) {
752 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
753 return r;
754 }
755 rdev->cp.ready = true;
756 return 0;
757 }
758
759 void r100_cp_fini(struct radeon_device *rdev)
760 {
761 if (r100_cp_wait_for_idle(rdev)) {
762 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
763 }
764 /* Disable ring */
765 r100_cp_disable(rdev);
766 radeon_ring_fini(rdev);
767 DRM_INFO("radeon: cp finalized\n");
768 }
769
770 void r100_cp_disable(struct radeon_device *rdev)
771 {
772 /* Disable ring */
773 rdev->cp.ready = false;
774 WREG32(RADEON_CP_CSQ_MODE, 0);
775 WREG32(RADEON_CP_CSQ_CNTL, 0);
776 if (r100_gui_wait_for_idle(rdev)) {
777 printk(KERN_WARNING "Failed to wait GUI idle while "
778 "programming pipes. Bad things might happen.\n");
779 }
780 }
781
782 int r100_cp_reset(struct radeon_device *rdev)
783 {
784 uint32_t tmp;
785 bool reinit_cp;
786 int i;
787
788 reinit_cp = rdev->cp.ready;
789 rdev->cp.ready = false;
790 WREG32(RADEON_CP_CSQ_MODE, 0);
791 WREG32(RADEON_CP_CSQ_CNTL, 0);
792 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
793 (void)RREG32(RADEON_RBBM_SOFT_RESET);
794 udelay(200);
795 WREG32(RADEON_RBBM_SOFT_RESET, 0);
796 /* Wait to prevent race in RBBM_STATUS */
797 mdelay(1);
798 for (i = 0; i < rdev->usec_timeout; i++) {
799 tmp = RREG32(RADEON_RBBM_STATUS);
800 if (!(tmp & (1 << 16))) {
801 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
802 tmp);
803 if (reinit_cp) {
804 return r100_cp_init(rdev, rdev->cp.ring_size);
805 }
806 return 0;
807 }
808 DRM_UDELAY(1);
809 }
810 tmp = RREG32(RADEON_RBBM_STATUS);
811 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
812 return -1;
813 }
814
815 void r100_cp_commit(struct radeon_device *rdev)
816 {
817 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
818 (void)RREG32(RADEON_CP_RB_WPTR);
819 }
820
821
822 /*
823 * CS functions
824 */
825 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
826 struct radeon_cs_packet *pkt,
827 const unsigned *auth, unsigned n,
828 radeon_packet0_check_t check)
829 {
830 unsigned reg;
831 unsigned i, j, m;
832 unsigned idx;
833 int r;
834
835 idx = pkt->idx + 1;
836 reg = pkt->reg;
837 /* Check that register fall into register range
838 * determined by the number of entry (n) in the
839 * safe register bitmap.
840 */
841 if (pkt->one_reg_wr) {
842 if ((reg >> 7) > n) {
843 return -EINVAL;
844 }
845 } else {
846 if (((reg + (pkt->count << 2)) >> 7) > n) {
847 return -EINVAL;
848 }
849 }
850 for (i = 0; i <= pkt->count; i++, idx++) {
851 j = (reg >> 7);
852 m = 1 << ((reg >> 2) & 31);
853 if (auth[j] & m) {
854 r = check(p, pkt, idx, reg);
855 if (r) {
856 return r;
857 }
858 }
859 if (pkt->one_reg_wr) {
860 if (!(auth[j] & m)) {
861 break;
862 }
863 } else {
864 reg += 4;
865 }
866 }
867 return 0;
868 }
869
870 void r100_cs_dump_packet(struct radeon_cs_parser *p,
871 struct radeon_cs_packet *pkt)
872 {
873 volatile uint32_t *ib;
874 unsigned i;
875 unsigned idx;
876
877 ib = p->ib->ptr;
878 idx = pkt->idx;
879 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
880 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
881 }
882 }
883
884 /**
885 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
886 * @parser: parser structure holding parsing context.
887 * @pkt: where to store packet informations
888 *
889 * Assume that chunk_ib_index is properly set. Will return -EINVAL
890 * if packet is bigger than remaining ib size. or if packets is unknown.
891 **/
892 int r100_cs_packet_parse(struct radeon_cs_parser *p,
893 struct radeon_cs_packet *pkt,
894 unsigned idx)
895 {
896 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
897 uint32_t header;
898
899 if (idx >= ib_chunk->length_dw) {
900 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
901 idx, ib_chunk->length_dw);
902 return -EINVAL;
903 }
904 header = radeon_get_ib_value(p, idx);
905 pkt->idx = idx;
906 pkt->type = CP_PACKET_GET_TYPE(header);
907 pkt->count = CP_PACKET_GET_COUNT(header);
908 switch (pkt->type) {
909 case PACKET_TYPE0:
910 pkt->reg = CP_PACKET0_GET_REG(header);
911 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
912 break;
913 case PACKET_TYPE3:
914 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
915 break;
916 case PACKET_TYPE2:
917 pkt->count = -1;
918 break;
919 default:
920 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
921 return -EINVAL;
922 }
923 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
924 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
925 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
926 return -EINVAL;
927 }
928 return 0;
929 }
930
931 /**
932 * r100_cs_packet_next_vline() - parse userspace VLINE packet
933 * @parser: parser structure holding parsing context.
934 *
935 * Userspace sends a special sequence for VLINE waits.
936 * PACKET0 - VLINE_START_END + value
937 * PACKET0 - WAIT_UNTIL +_value
938 * RELOC (P3) - crtc_id in reloc.
939 *
940 * This function parses this and relocates the VLINE START END
941 * and WAIT UNTIL packets to the correct crtc.
942 * It also detects a switched off crtc and nulls out the
943 * wait in that case.
944 */
945 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
946 {
947 struct drm_mode_object *obj;
948 struct drm_crtc *crtc;
949 struct radeon_crtc *radeon_crtc;
950 struct radeon_cs_packet p3reloc, waitreloc;
951 int crtc_id;
952 int r;
953 uint32_t header, h_idx, reg;
954 volatile uint32_t *ib;
955
956 ib = p->ib->ptr;
957
958 /* parse the wait until */
959 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
960 if (r)
961 return r;
962
963 /* check its a wait until and only 1 count */
964 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
965 waitreloc.count != 0) {
966 DRM_ERROR("vline wait had illegal wait until segment\n");
967 r = -EINVAL;
968 return r;
969 }
970
971 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
972 DRM_ERROR("vline wait had illegal wait until\n");
973 r = -EINVAL;
974 return r;
975 }
976
977 /* jump over the NOP */
978 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
979 if (r)
980 return r;
981
982 h_idx = p->idx - 2;
983 p->idx += waitreloc.count + 2;
984 p->idx += p3reloc.count + 2;
985
986 header = radeon_get_ib_value(p, h_idx);
987 crtc_id = radeon_get_ib_value(p, h_idx + 5);
988 reg = CP_PACKET0_GET_REG(header);
989 mutex_lock(&p->rdev->ddev->mode_config.mutex);
990 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
991 if (!obj) {
992 DRM_ERROR("cannot find crtc %d\n", crtc_id);
993 r = -EINVAL;
994 goto out;
995 }
996 crtc = obj_to_crtc(obj);
997 radeon_crtc = to_radeon_crtc(crtc);
998 crtc_id = radeon_crtc->crtc_id;
999
1000 if (!crtc->enabled) {
1001 /* if the CRTC isn't enabled - we need to nop out the wait until */
1002 ib[h_idx + 2] = PACKET2(0);
1003 ib[h_idx + 3] = PACKET2(0);
1004 } else if (crtc_id == 1) {
1005 switch (reg) {
1006 case AVIVO_D1MODE_VLINE_START_END:
1007 header &= ~R300_CP_PACKET0_REG_MASK;
1008 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1009 break;
1010 case RADEON_CRTC_GUI_TRIG_VLINE:
1011 header &= ~R300_CP_PACKET0_REG_MASK;
1012 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1013 break;
1014 default:
1015 DRM_ERROR("unknown crtc reloc\n");
1016 r = -EINVAL;
1017 goto out;
1018 }
1019 ib[h_idx] = header;
1020 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1021 }
1022 out:
1023 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1024 return r;
1025 }
1026
1027 /**
1028 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1029 * @parser: parser structure holding parsing context.
1030 * @data: pointer to relocation data
1031 * @offset_start: starting offset
1032 * @offset_mask: offset mask (to align start offset on)
1033 * @reloc: reloc informations
1034 *
1035 * Check next packet is relocation packet3, do bo validation and compute
1036 * GPU offset using the provided start.
1037 **/
1038 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1039 struct radeon_cs_reloc **cs_reloc)
1040 {
1041 struct radeon_cs_chunk *relocs_chunk;
1042 struct radeon_cs_packet p3reloc;
1043 unsigned idx;
1044 int r;
1045
1046 if (p->chunk_relocs_idx == -1) {
1047 DRM_ERROR("No relocation chunk !\n");
1048 return -EINVAL;
1049 }
1050 *cs_reloc = NULL;
1051 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1052 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1053 if (r) {
1054 return r;
1055 }
1056 p->idx += p3reloc.count + 2;
1057 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1058 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1059 p3reloc.idx);
1060 r100_cs_dump_packet(p, &p3reloc);
1061 return -EINVAL;
1062 }
1063 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1064 if (idx >= relocs_chunk->length_dw) {
1065 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1066 idx, relocs_chunk->length_dw);
1067 r100_cs_dump_packet(p, &p3reloc);
1068 return -EINVAL;
1069 }
1070 /* FIXME: we assume reloc size is 4 dwords */
1071 *cs_reloc = p->relocs_ptr[(idx / 4)];
1072 return 0;
1073 }
1074
1075 static int r100_get_vtx_size(uint32_t vtx_fmt)
1076 {
1077 int vtx_size;
1078 vtx_size = 2;
1079 /* ordered according to bits in spec */
1080 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1081 vtx_size++;
1082 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1083 vtx_size += 3;
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1085 vtx_size++;
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1087 vtx_size++;
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1089 vtx_size += 3;
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1091 vtx_size++;
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1093 vtx_size++;
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1095 vtx_size += 2;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1097 vtx_size += 2;
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1099 vtx_size++;
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1101 vtx_size += 2;
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1103 vtx_size++;
1104 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1105 vtx_size += 2;
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1107 vtx_size++;
1108 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1109 vtx_size++;
1110 /* blend weight */
1111 if (vtx_fmt & (0x7 << 15))
1112 vtx_size += (vtx_fmt >> 15) & 0x7;
1113 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1114 vtx_size += 3;
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1116 vtx_size += 2;
1117 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1118 vtx_size++;
1119 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1120 vtx_size++;
1121 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1122 vtx_size++;
1123 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1124 vtx_size++;
1125 return vtx_size;
1126 }
1127
1128 static int r100_packet0_check(struct radeon_cs_parser *p,
1129 struct radeon_cs_packet *pkt,
1130 unsigned idx, unsigned reg)
1131 {
1132 struct radeon_cs_reloc *reloc;
1133 struct r100_cs_track *track;
1134 volatile uint32_t *ib;
1135 uint32_t tmp;
1136 int r;
1137 int i, face;
1138 u32 tile_flags = 0;
1139 u32 idx_value;
1140
1141 ib = p->ib->ptr;
1142 track = (struct r100_cs_track *)p->track;
1143
1144 idx_value = radeon_get_ib_value(p, idx);
1145
1146 switch (reg) {
1147 case RADEON_CRTC_GUI_TRIG_VLINE:
1148 r = r100_cs_packet_parse_vline(p);
1149 if (r) {
1150 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1151 idx, reg);
1152 r100_cs_dump_packet(p, pkt);
1153 return r;
1154 }
1155 break;
1156 /* FIXME: only allow PACKET3 blit? easier to check for out of
1157 * range access */
1158 case RADEON_DST_PITCH_OFFSET:
1159 case RADEON_SRC_PITCH_OFFSET:
1160 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1161 if (r)
1162 return r;
1163 break;
1164 case RADEON_RB3D_DEPTHOFFSET:
1165 r = r100_cs_packet_next_reloc(p, &reloc);
1166 if (r) {
1167 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1168 idx, reg);
1169 r100_cs_dump_packet(p, pkt);
1170 return r;
1171 }
1172 track->zb.robj = reloc->robj;
1173 track->zb.offset = idx_value;
1174 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1175 break;
1176 case RADEON_RB3D_COLOROFFSET:
1177 r = r100_cs_packet_next_reloc(p, &reloc);
1178 if (r) {
1179 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1180 idx, reg);
1181 r100_cs_dump_packet(p, pkt);
1182 return r;
1183 }
1184 track->cb[0].robj = reloc->robj;
1185 track->cb[0].offset = idx_value;
1186 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1187 break;
1188 case RADEON_PP_TXOFFSET_0:
1189 case RADEON_PP_TXOFFSET_1:
1190 case RADEON_PP_TXOFFSET_2:
1191 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1192 r = r100_cs_packet_next_reloc(p, &reloc);
1193 if (r) {
1194 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1195 idx, reg);
1196 r100_cs_dump_packet(p, pkt);
1197 return r;
1198 }
1199 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1200 track->textures[i].robj = reloc->robj;
1201 break;
1202 case RADEON_PP_CUBIC_OFFSET_T0_0:
1203 case RADEON_PP_CUBIC_OFFSET_T0_1:
1204 case RADEON_PP_CUBIC_OFFSET_T0_2:
1205 case RADEON_PP_CUBIC_OFFSET_T0_3:
1206 case RADEON_PP_CUBIC_OFFSET_T0_4:
1207 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1208 r = r100_cs_packet_next_reloc(p, &reloc);
1209 if (r) {
1210 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1211 idx, reg);
1212 r100_cs_dump_packet(p, pkt);
1213 return r;
1214 }
1215 track->textures[0].cube_info[i].offset = idx_value;
1216 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1217 track->textures[0].cube_info[i].robj = reloc->robj;
1218 break;
1219 case RADEON_PP_CUBIC_OFFSET_T1_0:
1220 case RADEON_PP_CUBIC_OFFSET_T1_1:
1221 case RADEON_PP_CUBIC_OFFSET_T1_2:
1222 case RADEON_PP_CUBIC_OFFSET_T1_3:
1223 case RADEON_PP_CUBIC_OFFSET_T1_4:
1224 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1225 r = r100_cs_packet_next_reloc(p, &reloc);
1226 if (r) {
1227 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1228 idx, reg);
1229 r100_cs_dump_packet(p, pkt);
1230 return r;
1231 }
1232 track->textures[1].cube_info[i].offset = idx_value;
1233 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1234 track->textures[1].cube_info[i].robj = reloc->robj;
1235 break;
1236 case RADEON_PP_CUBIC_OFFSET_T2_0:
1237 case RADEON_PP_CUBIC_OFFSET_T2_1:
1238 case RADEON_PP_CUBIC_OFFSET_T2_2:
1239 case RADEON_PP_CUBIC_OFFSET_T2_3:
1240 case RADEON_PP_CUBIC_OFFSET_T2_4:
1241 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1242 r = r100_cs_packet_next_reloc(p, &reloc);
1243 if (r) {
1244 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1245 idx, reg);
1246 r100_cs_dump_packet(p, pkt);
1247 return r;
1248 }
1249 track->textures[2].cube_info[i].offset = idx_value;
1250 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1251 track->textures[2].cube_info[i].robj = reloc->robj;
1252 break;
1253 case RADEON_RE_WIDTH_HEIGHT:
1254 track->maxy = ((idx_value >> 16) & 0x7FF);
1255 break;
1256 case RADEON_RB3D_COLORPITCH:
1257 r = r100_cs_packet_next_reloc(p, &reloc);
1258 if (r) {
1259 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1260 idx, reg);
1261 r100_cs_dump_packet(p, pkt);
1262 return r;
1263 }
1264
1265 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1266 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1267 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1268 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1269
1270 tmp = idx_value & ~(0x7 << 16);
1271 tmp |= tile_flags;
1272 ib[idx] = tmp;
1273
1274 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1275 break;
1276 case RADEON_RB3D_DEPTHPITCH:
1277 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1278 break;
1279 case RADEON_RB3D_CNTL:
1280 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1281 case 7:
1282 case 8:
1283 case 9:
1284 case 11:
1285 case 12:
1286 track->cb[0].cpp = 1;
1287 break;
1288 case 3:
1289 case 4:
1290 case 15:
1291 track->cb[0].cpp = 2;
1292 break;
1293 case 6:
1294 track->cb[0].cpp = 4;
1295 break;
1296 default:
1297 DRM_ERROR("Invalid color buffer format (%d) !\n",
1298 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1299 return -EINVAL;
1300 }
1301 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1302 break;
1303 case RADEON_RB3D_ZSTENCILCNTL:
1304 switch (idx_value & 0xf) {
1305 case 0:
1306 track->zb.cpp = 2;
1307 break;
1308 case 2:
1309 case 3:
1310 case 4:
1311 case 5:
1312 case 9:
1313 case 11:
1314 track->zb.cpp = 4;
1315 break;
1316 default:
1317 break;
1318 }
1319 break;
1320 case RADEON_RB3D_ZPASS_ADDR:
1321 r = r100_cs_packet_next_reloc(p, &reloc);
1322 if (r) {
1323 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1324 idx, reg);
1325 r100_cs_dump_packet(p, pkt);
1326 return r;
1327 }
1328 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1329 break;
1330 case RADEON_PP_CNTL:
1331 {
1332 uint32_t temp = idx_value >> 4;
1333 for (i = 0; i < track->num_texture; i++)
1334 track->textures[i].enabled = !!(temp & (1 << i));
1335 }
1336 break;
1337 case RADEON_SE_VF_CNTL:
1338 track->vap_vf_cntl = idx_value;
1339 break;
1340 case RADEON_SE_VTX_FMT:
1341 track->vtx_size = r100_get_vtx_size(idx_value);
1342 break;
1343 case RADEON_PP_TEX_SIZE_0:
1344 case RADEON_PP_TEX_SIZE_1:
1345 case RADEON_PP_TEX_SIZE_2:
1346 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1347 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1348 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1349 break;
1350 case RADEON_PP_TEX_PITCH_0:
1351 case RADEON_PP_TEX_PITCH_1:
1352 case RADEON_PP_TEX_PITCH_2:
1353 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1354 track->textures[i].pitch = idx_value + 32;
1355 break;
1356 case RADEON_PP_TXFILTER_0:
1357 case RADEON_PP_TXFILTER_1:
1358 case RADEON_PP_TXFILTER_2:
1359 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1360 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1361 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1362 tmp = (idx_value >> 23) & 0x7;
1363 if (tmp == 2 || tmp == 6)
1364 track->textures[i].roundup_w = false;
1365 tmp = (idx_value >> 27) & 0x7;
1366 if (tmp == 2 || tmp == 6)
1367 track->textures[i].roundup_h = false;
1368 break;
1369 case RADEON_PP_TXFORMAT_0:
1370 case RADEON_PP_TXFORMAT_1:
1371 case RADEON_PP_TXFORMAT_2:
1372 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1373 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1374 track->textures[i].use_pitch = 1;
1375 } else {
1376 track->textures[i].use_pitch = 0;
1377 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1378 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1379 }
1380 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1381 track->textures[i].tex_coord_type = 2;
1382 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1383 case RADEON_TXFORMAT_I8:
1384 case RADEON_TXFORMAT_RGB332:
1385 case RADEON_TXFORMAT_Y8:
1386 track->textures[i].cpp = 1;
1387 break;
1388 case RADEON_TXFORMAT_AI88:
1389 case RADEON_TXFORMAT_ARGB1555:
1390 case RADEON_TXFORMAT_RGB565:
1391 case RADEON_TXFORMAT_ARGB4444:
1392 case RADEON_TXFORMAT_VYUY422:
1393 case RADEON_TXFORMAT_YVYU422:
1394 case RADEON_TXFORMAT_SHADOW16:
1395 case RADEON_TXFORMAT_LDUDV655:
1396 case RADEON_TXFORMAT_DUDV88:
1397 track->textures[i].cpp = 2;
1398 break;
1399 case RADEON_TXFORMAT_ARGB8888:
1400 case RADEON_TXFORMAT_RGBA8888:
1401 case RADEON_TXFORMAT_SHADOW32:
1402 case RADEON_TXFORMAT_LDUDUV8888:
1403 track->textures[i].cpp = 4;
1404 break;
1405 case RADEON_TXFORMAT_DXT1:
1406 track->textures[i].cpp = 1;
1407 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1408 break;
1409 case RADEON_TXFORMAT_DXT23:
1410 case RADEON_TXFORMAT_DXT45:
1411 track->textures[i].cpp = 1;
1412 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1413 break;
1414 }
1415 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1416 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1417 break;
1418 case RADEON_PP_CUBIC_FACES_0:
1419 case RADEON_PP_CUBIC_FACES_1:
1420 case RADEON_PP_CUBIC_FACES_2:
1421 tmp = idx_value;
1422 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1423 for (face = 0; face < 4; face++) {
1424 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1425 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1426 }
1427 break;
1428 default:
1429 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1430 reg, idx);
1431 return -EINVAL;
1432 }
1433 return 0;
1434 }
1435
1436 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1437 struct radeon_cs_packet *pkt,
1438 struct radeon_bo *robj)
1439 {
1440 unsigned idx;
1441 u32 value;
1442 idx = pkt->idx + 1;
1443 value = radeon_get_ib_value(p, idx + 2);
1444 if ((value + 1) > radeon_bo_size(robj)) {
1445 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1446 "(need %u have %lu) !\n",
1447 value + 1,
1448 radeon_bo_size(robj));
1449 return -EINVAL;
1450 }
1451 return 0;
1452 }
1453
1454 static int r100_packet3_check(struct radeon_cs_parser *p,
1455 struct radeon_cs_packet *pkt)
1456 {
1457 struct radeon_cs_reloc *reloc;
1458 struct r100_cs_track *track;
1459 unsigned idx;
1460 volatile uint32_t *ib;
1461 int r;
1462
1463 ib = p->ib->ptr;
1464 idx = pkt->idx + 1;
1465 track = (struct r100_cs_track *)p->track;
1466 switch (pkt->opcode) {
1467 case PACKET3_3D_LOAD_VBPNTR:
1468 r = r100_packet3_load_vbpntr(p, pkt, idx);
1469 if (r)
1470 return r;
1471 break;
1472 case PACKET3_INDX_BUFFER:
1473 r = r100_cs_packet_next_reloc(p, &reloc);
1474 if (r) {
1475 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1476 r100_cs_dump_packet(p, pkt);
1477 return r;
1478 }
1479 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1480 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1481 if (r) {
1482 return r;
1483 }
1484 break;
1485 case 0x23:
1486 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1487 r = r100_cs_packet_next_reloc(p, &reloc);
1488 if (r) {
1489 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1490 r100_cs_dump_packet(p, pkt);
1491 return r;
1492 }
1493 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1494 track->num_arrays = 1;
1495 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1496
1497 track->arrays[0].robj = reloc->robj;
1498 track->arrays[0].esize = track->vtx_size;
1499
1500 track->max_indx = radeon_get_ib_value(p, idx+1);
1501
1502 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1503 track->immd_dwords = pkt->count - 1;
1504 r = r100_cs_track_check(p->rdev, track);
1505 if (r)
1506 return r;
1507 break;
1508 case PACKET3_3D_DRAW_IMMD:
1509 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1510 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1511 return -EINVAL;
1512 }
1513 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1514 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1515 track->immd_dwords = pkt->count - 1;
1516 r = r100_cs_track_check(p->rdev, track);
1517 if (r)
1518 return r;
1519 break;
1520 /* triggers drawing using in-packet vertex data */
1521 case PACKET3_3D_DRAW_IMMD_2:
1522 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1523 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1524 return -EINVAL;
1525 }
1526 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1527 track->immd_dwords = pkt->count;
1528 r = r100_cs_track_check(p->rdev, track);
1529 if (r)
1530 return r;
1531 break;
1532 /* triggers drawing using in-packet vertex data */
1533 case PACKET3_3D_DRAW_VBUF_2:
1534 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1535 r = r100_cs_track_check(p->rdev, track);
1536 if (r)
1537 return r;
1538 break;
1539 /* triggers drawing of vertex buffers setup elsewhere */
1540 case PACKET3_3D_DRAW_INDX_2:
1541 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1542 r = r100_cs_track_check(p->rdev, track);
1543 if (r)
1544 return r;
1545 break;
1546 /* triggers drawing using indices to vertex buffer */
1547 case PACKET3_3D_DRAW_VBUF:
1548 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1549 r = r100_cs_track_check(p->rdev, track);
1550 if (r)
1551 return r;
1552 break;
1553 /* triggers drawing of vertex buffers setup elsewhere */
1554 case PACKET3_3D_DRAW_INDX:
1555 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1556 r = r100_cs_track_check(p->rdev, track);
1557 if (r)
1558 return r;
1559 break;
1560 /* triggers drawing using indices to vertex buffer */
1561 case PACKET3_NOP:
1562 break;
1563 default:
1564 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1565 return -EINVAL;
1566 }
1567 return 0;
1568 }
1569
1570 int r100_cs_parse(struct radeon_cs_parser *p)
1571 {
1572 struct radeon_cs_packet pkt;
1573 struct r100_cs_track *track;
1574 int r;
1575
1576 track = kzalloc(sizeof(*track), GFP_KERNEL);
1577 r100_cs_track_clear(p->rdev, track);
1578 p->track = track;
1579 do {
1580 r = r100_cs_packet_parse(p, &pkt, p->idx);
1581 if (r) {
1582 return r;
1583 }
1584 p->idx += pkt.count + 2;
1585 switch (pkt.type) {
1586 case PACKET_TYPE0:
1587 if (p->rdev->family >= CHIP_R200)
1588 r = r100_cs_parse_packet0(p, &pkt,
1589 p->rdev->config.r100.reg_safe_bm,
1590 p->rdev->config.r100.reg_safe_bm_size,
1591 &r200_packet0_check);
1592 else
1593 r = r100_cs_parse_packet0(p, &pkt,
1594 p->rdev->config.r100.reg_safe_bm,
1595 p->rdev->config.r100.reg_safe_bm_size,
1596 &r100_packet0_check);
1597 break;
1598 case PACKET_TYPE2:
1599 break;
1600 case PACKET_TYPE3:
1601 r = r100_packet3_check(p, &pkt);
1602 break;
1603 default:
1604 DRM_ERROR("Unknown packet type %d !\n",
1605 pkt.type);
1606 return -EINVAL;
1607 }
1608 if (r) {
1609 return r;
1610 }
1611 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1612 return 0;
1613 }
1614
1615
1616 /*
1617 * Global GPU functions
1618 */
1619 void r100_errata(struct radeon_device *rdev)
1620 {
1621 rdev->pll_errata = 0;
1622
1623 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1624 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1625 }
1626
1627 if (rdev->family == CHIP_RV100 ||
1628 rdev->family == CHIP_RS100 ||
1629 rdev->family == CHIP_RS200) {
1630 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1631 }
1632 }
1633
1634 /* Wait for vertical sync on primary CRTC */
1635 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1636 {
1637 uint32_t crtc_gen_cntl, tmp;
1638 int i;
1639
1640 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1641 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1642 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1643 return;
1644 }
1645 /* Clear the CRTC_VBLANK_SAVE bit */
1646 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1647 for (i = 0; i < rdev->usec_timeout; i++) {
1648 tmp = RREG32(RADEON_CRTC_STATUS);
1649 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1650 return;
1651 }
1652 DRM_UDELAY(1);
1653 }
1654 }
1655
1656 /* Wait for vertical sync on secondary CRTC */
1657 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1658 {
1659 uint32_t crtc2_gen_cntl, tmp;
1660 int i;
1661
1662 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1663 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1664 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1665 return;
1666
1667 /* Clear the CRTC_VBLANK_SAVE bit */
1668 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1669 for (i = 0; i < rdev->usec_timeout; i++) {
1670 tmp = RREG32(RADEON_CRTC2_STATUS);
1671 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1672 return;
1673 }
1674 DRM_UDELAY(1);
1675 }
1676 }
1677
1678 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1679 {
1680 unsigned i;
1681 uint32_t tmp;
1682
1683 for (i = 0; i < rdev->usec_timeout; i++) {
1684 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1685 if (tmp >= n) {
1686 return 0;
1687 }
1688 DRM_UDELAY(1);
1689 }
1690 return -1;
1691 }
1692
1693 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1694 {
1695 unsigned i;
1696 uint32_t tmp;
1697
1698 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1699 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1700 " Bad things might happen.\n");
1701 }
1702 for (i = 0; i < rdev->usec_timeout; i++) {
1703 tmp = RREG32(RADEON_RBBM_STATUS);
1704 if (!(tmp & (1 << 31))) {
1705 return 0;
1706 }
1707 DRM_UDELAY(1);
1708 }
1709 return -1;
1710 }
1711
1712 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1713 {
1714 unsigned i;
1715 uint32_t tmp;
1716
1717 for (i = 0; i < rdev->usec_timeout; i++) {
1718 /* read MC_STATUS */
1719 tmp = RREG32(0x0150);
1720 if (tmp & (1 << 2)) {
1721 return 0;
1722 }
1723 DRM_UDELAY(1);
1724 }
1725 return -1;
1726 }
1727
1728 void r100_gpu_init(struct radeon_device *rdev)
1729 {
1730 /* TODO: anythings to do here ? pipes ? */
1731 r100_hdp_reset(rdev);
1732 }
1733
1734 void r100_hdp_reset(struct radeon_device *rdev)
1735 {
1736 uint32_t tmp;
1737
1738 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1739 tmp |= (7 << 28);
1740 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1741 (void)RREG32(RADEON_HOST_PATH_CNTL);
1742 udelay(200);
1743 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1744 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1745 (void)RREG32(RADEON_HOST_PATH_CNTL);
1746 }
1747
1748 int r100_rb2d_reset(struct radeon_device *rdev)
1749 {
1750 uint32_t tmp;
1751 int i;
1752
1753 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1754 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1755 udelay(200);
1756 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1757 /* Wait to prevent race in RBBM_STATUS */
1758 mdelay(1);
1759 for (i = 0; i < rdev->usec_timeout; i++) {
1760 tmp = RREG32(RADEON_RBBM_STATUS);
1761 if (!(tmp & (1 << 26))) {
1762 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1763 tmp);
1764 return 0;
1765 }
1766 DRM_UDELAY(1);
1767 }
1768 tmp = RREG32(RADEON_RBBM_STATUS);
1769 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1770 return -1;
1771 }
1772
1773 int r100_gpu_reset(struct radeon_device *rdev)
1774 {
1775 uint32_t status;
1776
1777 /* reset order likely matter */
1778 status = RREG32(RADEON_RBBM_STATUS);
1779 /* reset HDP */
1780 r100_hdp_reset(rdev);
1781 /* reset rb2d */
1782 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1783 r100_rb2d_reset(rdev);
1784 }
1785 /* TODO: reset 3D engine */
1786 /* reset CP */
1787 status = RREG32(RADEON_RBBM_STATUS);
1788 if (status & (1 << 16)) {
1789 r100_cp_reset(rdev);
1790 }
1791 /* Check if GPU is idle */
1792 status = RREG32(RADEON_RBBM_STATUS);
1793 if (status & (1 << 31)) {
1794 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1795 return -1;
1796 }
1797 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1798 return 0;
1799 }
1800
1801 void r100_set_common_regs(struct radeon_device *rdev)
1802 {
1803 /* set these so they don't interfere with anything */
1804 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1805 WREG32(RADEON_SUBPIC_CNTL, 0);
1806 WREG32(RADEON_VIPH_CONTROL, 0);
1807 WREG32(RADEON_I2C_CNTL_1, 0);
1808 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1809 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1810 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1811 }
1812
1813 /*
1814 * VRAM info
1815 */
1816 static void r100_vram_get_type(struct radeon_device *rdev)
1817 {
1818 uint32_t tmp;
1819
1820 rdev->mc.vram_is_ddr = false;
1821 if (rdev->flags & RADEON_IS_IGP)
1822 rdev->mc.vram_is_ddr = true;
1823 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1824 rdev->mc.vram_is_ddr = true;
1825 if ((rdev->family == CHIP_RV100) ||
1826 (rdev->family == CHIP_RS100) ||
1827 (rdev->family == CHIP_RS200)) {
1828 tmp = RREG32(RADEON_MEM_CNTL);
1829 if (tmp & RV100_HALF_MODE) {
1830 rdev->mc.vram_width = 32;
1831 } else {
1832 rdev->mc.vram_width = 64;
1833 }
1834 if (rdev->flags & RADEON_SINGLE_CRTC) {
1835 rdev->mc.vram_width /= 4;
1836 rdev->mc.vram_is_ddr = true;
1837 }
1838 } else if (rdev->family <= CHIP_RV280) {
1839 tmp = RREG32(RADEON_MEM_CNTL);
1840 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1841 rdev->mc.vram_width = 128;
1842 } else {
1843 rdev->mc.vram_width = 64;
1844 }
1845 } else {
1846 /* newer IGPs */
1847 rdev->mc.vram_width = 128;
1848 }
1849 }
1850
1851 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1852 {
1853 u32 aper_size;
1854 u8 byte;
1855
1856 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1857
1858 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1859 * that is has the 2nd generation multifunction PCI interface
1860 */
1861 if (rdev->family == CHIP_RV280 ||
1862 rdev->family >= CHIP_RV350) {
1863 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1864 ~RADEON_HDP_APER_CNTL);
1865 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1866 return aper_size * 2;
1867 }
1868
1869 /* Older cards have all sorts of funny issues to deal with. First
1870 * check if it's a multifunction card by reading the PCI config
1871 * header type... Limit those to one aperture size
1872 */
1873 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1874 if (byte & 0x80) {
1875 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1876 DRM_INFO("Limiting VRAM to one aperture\n");
1877 return aper_size;
1878 }
1879
1880 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1881 * have set it up. We don't write this as it's broken on some ASICs but
1882 * we expect the BIOS to have done the right thing (might be too optimistic...)
1883 */
1884 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1885 return aper_size * 2;
1886 return aper_size;
1887 }
1888
1889 void r100_vram_init_sizes(struct radeon_device *rdev)
1890 {
1891 u64 config_aper_size;
1892 u32 accessible;
1893
1894 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1895
1896 if (rdev->flags & RADEON_IS_IGP) {
1897 uint32_t tom;
1898 /* read NB_TOM to get the amount of ram stolen for the GPU */
1899 tom = RREG32(RADEON_NB_TOM);
1900 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1901 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1902 rdev->mc.vram_location = (tom & 0xffff) << 16;
1903 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1904 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1905 } else {
1906 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1907 /* Some production boards of m6 will report 0
1908 * if it's 8 MB
1909 */
1910 if (rdev->mc.real_vram_size == 0) {
1911 rdev->mc.real_vram_size = 8192 * 1024;
1912 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1913 }
1914 /* let driver place VRAM */
1915 rdev->mc.vram_location = 0xFFFFFFFFUL;
1916 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1917 * Novell bug 204882 + along with lots of ubuntu ones */
1918 if (config_aper_size > rdev->mc.real_vram_size)
1919 rdev->mc.mc_vram_size = config_aper_size;
1920 else
1921 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1922 }
1923
1924 /* work out accessible VRAM */
1925 accessible = r100_get_accessible_vram(rdev);
1926
1927 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1928 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1929
1930 if (accessible > rdev->mc.aper_size)
1931 accessible = rdev->mc.aper_size;
1932
1933 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1934 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1935
1936 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1937 rdev->mc.real_vram_size = rdev->mc.aper_size;
1938 }
1939
1940 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1941 {
1942 uint32_t temp;
1943
1944 temp = RREG32(RADEON_CONFIG_CNTL);
1945 if (state == false) {
1946 temp &= ~(1<<8);
1947 temp |= (1<<9);
1948 } else {
1949 temp &= ~(1<<9);
1950 }
1951 WREG32(RADEON_CONFIG_CNTL, temp);
1952 }
1953
1954 void r100_vram_info(struct radeon_device *rdev)
1955 {
1956 r100_vram_get_type(rdev);
1957
1958 r100_vram_init_sizes(rdev);
1959 }
1960
1961
1962 /*
1963 * Indirect registers accessor
1964 */
1965 void r100_pll_errata_after_index(struct radeon_device *rdev)
1966 {
1967 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1968 return;
1969 }
1970 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1971 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1972 }
1973
1974 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1975 {
1976 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1977 * or the chip could hang on a subsequent access
1978 */
1979 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1980 udelay(5000);
1981 }
1982
1983 /* This function is required to workaround a hardware bug in some (all?)
1984 * revisions of the R300. This workaround should be called after every
1985 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1986 * may not be correct.
1987 */
1988 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1989 uint32_t save, tmp;
1990
1991 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1992 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1993 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1994 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1995 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1996 }
1997 }
1998
1999 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2000 {
2001 uint32_t data;
2002
2003 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2004 r100_pll_errata_after_index(rdev);
2005 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2006 r100_pll_errata_after_data(rdev);
2007 return data;
2008 }
2009
2010 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2011 {
2012 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2013 r100_pll_errata_after_index(rdev);
2014 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2015 r100_pll_errata_after_data(rdev);
2016 }
2017
2018 void r100_set_safe_registers(struct radeon_device *rdev)
2019 {
2020 if (ASIC_IS_RN50(rdev)) {
2021 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2022 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2023 } else if (rdev->family < CHIP_R200) {
2024 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2025 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2026 } else {
2027 r200_set_safe_registers(rdev);
2028 }
2029 }
2030
2031 /*
2032 * Debugfs info
2033 */
2034 #if defined(CONFIG_DEBUG_FS)
2035 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2036 {
2037 struct drm_info_node *node = (struct drm_info_node *) m->private;
2038 struct drm_device *dev = node->minor->dev;
2039 struct radeon_device *rdev = dev->dev_private;
2040 uint32_t reg, value;
2041 unsigned i;
2042
2043 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2044 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2045 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2046 for (i = 0; i < 64; i++) {
2047 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2048 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2049 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2050 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2051 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2052 }
2053 return 0;
2054 }
2055
2056 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2057 {
2058 struct drm_info_node *node = (struct drm_info_node *) m->private;
2059 struct drm_device *dev = node->minor->dev;
2060 struct radeon_device *rdev = dev->dev_private;
2061 uint32_t rdp, wdp;
2062 unsigned count, i, j;
2063
2064 radeon_ring_free_size(rdev);
2065 rdp = RREG32(RADEON_CP_RB_RPTR);
2066 wdp = RREG32(RADEON_CP_RB_WPTR);
2067 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2068 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2069 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2070 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2071 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2072 seq_printf(m, "%u dwords in ring\n", count);
2073 for (j = 0; j <= count; j++) {
2074 i = (rdp + j) & rdev->cp.ptr_mask;
2075 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2076 }
2077 return 0;
2078 }
2079
2080
2081 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2082 {
2083 struct drm_info_node *node = (struct drm_info_node *) m->private;
2084 struct drm_device *dev = node->minor->dev;
2085 struct radeon_device *rdev = dev->dev_private;
2086 uint32_t csq_stat, csq2_stat, tmp;
2087 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2088 unsigned i;
2089
2090 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2091 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2092 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2093 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2094 r_rptr = (csq_stat >> 0) & 0x3ff;
2095 r_wptr = (csq_stat >> 10) & 0x3ff;
2096 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2097 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2098 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2099 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2100 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2101 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2102 seq_printf(m, "Ring rptr %u\n", r_rptr);
2103 seq_printf(m, "Ring wptr %u\n", r_wptr);
2104 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2105 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2106 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2107 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2108 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2109 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2110 seq_printf(m, "Ring fifo:\n");
2111 for (i = 0; i < 256; i++) {
2112 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2113 tmp = RREG32(RADEON_CP_CSQ_DATA);
2114 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2115 }
2116 seq_printf(m, "Indirect1 fifo:\n");
2117 for (i = 256; i <= 512; i++) {
2118 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2119 tmp = RREG32(RADEON_CP_CSQ_DATA);
2120 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2121 }
2122 seq_printf(m, "Indirect2 fifo:\n");
2123 for (i = 640; i < ib1_wptr; i++) {
2124 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2125 tmp = RREG32(RADEON_CP_CSQ_DATA);
2126 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2127 }
2128 return 0;
2129 }
2130
2131 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2132 {
2133 struct drm_info_node *node = (struct drm_info_node *) m->private;
2134 struct drm_device *dev = node->minor->dev;
2135 struct radeon_device *rdev = dev->dev_private;
2136 uint32_t tmp;
2137
2138 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2139 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2140 tmp = RREG32(RADEON_MC_FB_LOCATION);
2141 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2142 tmp = RREG32(RADEON_BUS_CNTL);
2143 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2144 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2145 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2146 tmp = RREG32(RADEON_AGP_BASE);
2147 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2148 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2149 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2150 tmp = RREG32(0x01D0);
2151 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2152 tmp = RREG32(RADEON_AIC_LO_ADDR);
2153 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2154 tmp = RREG32(RADEON_AIC_HI_ADDR);
2155 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2156 tmp = RREG32(0x01E4);
2157 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2158 return 0;
2159 }
2160
2161 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2162 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2163 };
2164
2165 static struct drm_info_list r100_debugfs_cp_list[] = {
2166 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2167 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2168 };
2169
2170 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2171 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2172 };
2173 #endif
2174
2175 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2176 {
2177 #if defined(CONFIG_DEBUG_FS)
2178 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2179 #else
2180 return 0;
2181 #endif
2182 }
2183
2184 int r100_debugfs_cp_init(struct radeon_device *rdev)
2185 {
2186 #if defined(CONFIG_DEBUG_FS)
2187 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2188 #else
2189 return 0;
2190 #endif
2191 }
2192
2193 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2194 {
2195 #if defined(CONFIG_DEBUG_FS)
2196 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2197 #else
2198 return 0;
2199 #endif
2200 }
2201
2202 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2203 uint32_t tiling_flags, uint32_t pitch,
2204 uint32_t offset, uint32_t obj_size)
2205 {
2206 int surf_index = reg * 16;
2207 int flags = 0;
2208
2209 /* r100/r200 divide by 16 */
2210 if (rdev->family < CHIP_R300)
2211 flags = pitch / 16;
2212 else
2213 flags = pitch / 8;
2214
2215 if (rdev->family <= CHIP_RS200) {
2216 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2217 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2218 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2219 if (tiling_flags & RADEON_TILING_MACRO)
2220 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2221 } else if (rdev->family <= CHIP_RV280) {
2222 if (tiling_flags & (RADEON_TILING_MACRO))
2223 flags |= R200_SURF_TILE_COLOR_MACRO;
2224 if (tiling_flags & RADEON_TILING_MICRO)
2225 flags |= R200_SURF_TILE_COLOR_MICRO;
2226 } else {
2227 if (tiling_flags & RADEON_TILING_MACRO)
2228 flags |= R300_SURF_TILE_MACRO;
2229 if (tiling_flags & RADEON_TILING_MICRO)
2230 flags |= R300_SURF_TILE_MICRO;
2231 }
2232
2233 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2234 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2235 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2236 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2237
2238 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2239 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2240 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2241 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2242 return 0;
2243 }
2244
2245 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2246 {
2247 int surf_index = reg * 16;
2248 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2249 }
2250
2251 void r100_bandwidth_update(struct radeon_device *rdev)
2252 {
2253 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2254 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2255 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2256 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2257 fixed20_12 memtcas_ff[8] = {
2258 fixed_init(1),
2259 fixed_init(2),
2260 fixed_init(3),
2261 fixed_init(0),
2262 fixed_init_half(1),
2263 fixed_init_half(2),
2264 fixed_init(0),
2265 };
2266 fixed20_12 memtcas_rs480_ff[8] = {
2267 fixed_init(0),
2268 fixed_init(1),
2269 fixed_init(2),
2270 fixed_init(3),
2271 fixed_init(0),
2272 fixed_init_half(1),
2273 fixed_init_half(2),
2274 fixed_init_half(3),
2275 };
2276 fixed20_12 memtcas2_ff[8] = {
2277 fixed_init(0),
2278 fixed_init(1),
2279 fixed_init(2),
2280 fixed_init(3),
2281 fixed_init(4),
2282 fixed_init(5),
2283 fixed_init(6),
2284 fixed_init(7),
2285 };
2286 fixed20_12 memtrbs[8] = {
2287 fixed_init(1),
2288 fixed_init_half(1),
2289 fixed_init(2),
2290 fixed_init_half(2),
2291 fixed_init(3),
2292 fixed_init_half(3),
2293 fixed_init(4),
2294 fixed_init_half(4)
2295 };
2296 fixed20_12 memtrbs_r4xx[8] = {
2297 fixed_init(4),
2298 fixed_init(5),
2299 fixed_init(6),
2300 fixed_init(7),
2301 fixed_init(8),
2302 fixed_init(9),
2303 fixed_init(10),
2304 fixed_init(11)
2305 };
2306 fixed20_12 min_mem_eff;
2307 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2308 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2309 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2310 disp_drain_rate2, read_return_rate;
2311 fixed20_12 time_disp1_drop_priority;
2312 int c;
2313 int cur_size = 16; /* in octawords */
2314 int critical_point = 0, critical_point2;
2315 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2316 int stop_req, max_stop_req;
2317 struct drm_display_mode *mode1 = NULL;
2318 struct drm_display_mode *mode2 = NULL;
2319 uint32_t pixel_bytes1 = 0;
2320 uint32_t pixel_bytes2 = 0;
2321
2322 if (rdev->mode_info.crtcs[0]->base.enabled) {
2323 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2324 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2325 }
2326 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2327 if (rdev->mode_info.crtcs[1]->base.enabled) {
2328 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2329 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2330 }
2331 }
2332
2333 min_mem_eff.full = rfixed_const_8(0);
2334 /* get modes */
2335 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2336 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2337 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2338 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2339 /* check crtc enables */
2340 if (mode2)
2341 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2342 if (mode1)
2343 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2344 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2345 }
2346
2347 /*
2348 * determine is there is enough bw for current mode
2349 */
2350 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2351 temp_ff.full = rfixed_const(100);
2352 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2353 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2354 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2355
2356 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2357 temp_ff.full = rfixed_const(temp);
2358 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2359
2360 pix_clk.full = 0;
2361 pix_clk2.full = 0;
2362 peak_disp_bw.full = 0;
2363 if (mode1) {
2364 temp_ff.full = rfixed_const(1000);
2365 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2366 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2367 temp_ff.full = rfixed_const(pixel_bytes1);
2368 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2369 }
2370 if (mode2) {
2371 temp_ff.full = rfixed_const(1000);
2372 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2373 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2374 temp_ff.full = rfixed_const(pixel_bytes2);
2375 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2376 }
2377
2378 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2379 if (peak_disp_bw.full >= mem_bw.full) {
2380 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2381 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2382 }
2383
2384 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2385 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2386 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2387 mem_trcd = ((temp >> 2) & 0x3) + 1;
2388 mem_trp = ((temp & 0x3)) + 1;
2389 mem_tras = ((temp & 0x70) >> 4) + 1;
2390 } else if (rdev->family == CHIP_R300 ||
2391 rdev->family == CHIP_R350) { /* r300, r350 */
2392 mem_trcd = (temp & 0x7) + 1;
2393 mem_trp = ((temp >> 8) & 0x7) + 1;
2394 mem_tras = ((temp >> 11) & 0xf) + 4;
2395 } else if (rdev->family == CHIP_RV350 ||
2396 rdev->family <= CHIP_RV380) {
2397 /* rv3x0 */
2398 mem_trcd = (temp & 0x7) + 3;
2399 mem_trp = ((temp >> 8) & 0x7) + 3;
2400 mem_tras = ((temp >> 11) & 0xf) + 6;
2401 } else if (rdev->family == CHIP_R420 ||
2402 rdev->family == CHIP_R423 ||
2403 rdev->family == CHIP_RV410) {
2404 /* r4xx */
2405 mem_trcd = (temp & 0xf) + 3;
2406 if (mem_trcd > 15)
2407 mem_trcd = 15;
2408 mem_trp = ((temp >> 8) & 0xf) + 3;
2409 if (mem_trp > 15)
2410 mem_trp = 15;
2411 mem_tras = ((temp >> 12) & 0x1f) + 6;
2412 if (mem_tras > 31)
2413 mem_tras = 31;
2414 } else { /* RV200, R200 */
2415 mem_trcd = (temp & 0x7) + 1;
2416 mem_trp = ((temp >> 8) & 0x7) + 1;
2417 mem_tras = ((temp >> 12) & 0xf) + 4;
2418 }
2419 /* convert to FF */
2420 trcd_ff.full = rfixed_const(mem_trcd);
2421 trp_ff.full = rfixed_const(mem_trp);
2422 tras_ff.full = rfixed_const(mem_tras);
2423
2424 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2425 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2426 data = (temp & (7 << 20)) >> 20;
2427 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2428 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2429 tcas_ff = memtcas_rs480_ff[data];
2430 else
2431 tcas_ff = memtcas_ff[data];
2432 } else
2433 tcas_ff = memtcas2_ff[data];
2434
2435 if (rdev->family == CHIP_RS400 ||
2436 rdev->family == CHIP_RS480) {
2437 /* extra cas latency stored in bits 23-25 0-4 clocks */
2438 data = (temp >> 23) & 0x7;
2439 if (data < 5)
2440 tcas_ff.full += rfixed_const(data);
2441 }
2442
2443 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2444 /* on the R300, Tcas is included in Trbs.
2445 */
2446 temp = RREG32(RADEON_MEM_CNTL);
2447 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2448 if (data == 1) {
2449 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2450 temp = RREG32(R300_MC_IND_INDEX);
2451 temp &= ~R300_MC_IND_ADDR_MASK;
2452 temp |= R300_MC_READ_CNTL_CD_mcind;
2453 WREG32(R300_MC_IND_INDEX, temp);
2454 temp = RREG32(R300_MC_IND_DATA);
2455 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2456 } else {
2457 temp = RREG32(R300_MC_READ_CNTL_AB);
2458 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2459 }
2460 } else {
2461 temp = RREG32(R300_MC_READ_CNTL_AB);
2462 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2463 }
2464 if (rdev->family == CHIP_RV410 ||
2465 rdev->family == CHIP_R420 ||
2466 rdev->family == CHIP_R423)
2467 trbs_ff = memtrbs_r4xx[data];
2468 else
2469 trbs_ff = memtrbs[data];
2470 tcas_ff.full += trbs_ff.full;
2471 }
2472
2473 sclk_eff_ff.full = sclk_ff.full;
2474
2475 if (rdev->flags & RADEON_IS_AGP) {
2476 fixed20_12 agpmode_ff;
2477 agpmode_ff.full = rfixed_const(radeon_agpmode);
2478 temp_ff.full = rfixed_const_666(16);
2479 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2480 }
2481 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2482
2483 if (ASIC_IS_R300(rdev)) {
2484 sclk_delay_ff.full = rfixed_const(250);
2485 } else {
2486 if ((rdev->family == CHIP_RV100) ||
2487 rdev->flags & RADEON_IS_IGP) {
2488 if (rdev->mc.vram_is_ddr)
2489 sclk_delay_ff.full = rfixed_const(41);
2490 else
2491 sclk_delay_ff.full = rfixed_const(33);
2492 } else {
2493 if (rdev->mc.vram_width == 128)
2494 sclk_delay_ff.full = rfixed_const(57);
2495 else
2496 sclk_delay_ff.full = rfixed_const(41);
2497 }
2498 }
2499
2500 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2501
2502 if (rdev->mc.vram_is_ddr) {
2503 if (rdev->mc.vram_width == 32) {
2504 k1.full = rfixed_const(40);
2505 c = 3;
2506 } else {
2507 k1.full = rfixed_const(20);
2508 c = 1;
2509 }
2510 } else {
2511 k1.full = rfixed_const(40);
2512 c = 3;
2513 }
2514
2515 temp_ff.full = rfixed_const(2);
2516 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2517 temp_ff.full = rfixed_const(c);
2518 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2519 temp_ff.full = rfixed_const(4);
2520 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2521 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2522 mc_latency_mclk.full += k1.full;
2523
2524 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2525 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2526
2527 /*
2528 HW cursor time assuming worst case of full size colour cursor.
2529 */
2530 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2531 temp_ff.full += trcd_ff.full;
2532 if (temp_ff.full < tras_ff.full)
2533 temp_ff.full = tras_ff.full;
2534 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2535
2536 temp_ff.full = rfixed_const(cur_size);
2537 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2538 /*
2539 Find the total latency for the display data.
2540 */
2541 disp_latency_overhead.full = rfixed_const(8);
2542 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2543 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2544 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2545
2546 if (mc_latency_mclk.full > mc_latency_sclk.full)
2547 disp_latency.full = mc_latency_mclk.full;
2548 else
2549 disp_latency.full = mc_latency_sclk.full;
2550
2551 /* setup Max GRPH_STOP_REQ default value */
2552 if (ASIC_IS_RV100(rdev))
2553 max_stop_req = 0x5c;
2554 else
2555 max_stop_req = 0x7c;
2556
2557 if (mode1) {
2558 /* CRTC1
2559 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2560 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2561 */
2562 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2563
2564 if (stop_req > max_stop_req)
2565 stop_req = max_stop_req;
2566
2567 /*
2568 Find the drain rate of the display buffer.
2569 */
2570 temp_ff.full = rfixed_const((16/pixel_bytes1));
2571 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2572
2573 /*
2574 Find the critical point of the display buffer.
2575 */
2576 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2577 crit_point_ff.full += rfixed_const_half(0);
2578
2579 critical_point = rfixed_trunc(crit_point_ff);
2580
2581 if (rdev->disp_priority == 2) {
2582 critical_point = 0;
2583 }
2584
2585 /*
2586 The critical point should never be above max_stop_req-4. Setting
2587 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2588 */
2589 if (max_stop_req - critical_point < 4)
2590 critical_point = 0;
2591
2592 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2593 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2594 critical_point = 0x10;
2595 }
2596
2597 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2598 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2599 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2600 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2601 if ((rdev->family == CHIP_R350) &&
2602 (stop_req > 0x15)) {
2603 stop_req -= 0x10;
2604 }
2605 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2606 temp |= RADEON_GRPH_BUFFER_SIZE;
2607 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2608 RADEON_GRPH_CRITICAL_AT_SOF |
2609 RADEON_GRPH_STOP_CNTL);
2610 /*
2611 Write the result into the register.
2612 */
2613 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2614 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2615
2616 #if 0
2617 if ((rdev->family == CHIP_RS400) ||
2618 (rdev->family == CHIP_RS480)) {
2619 /* attempt to program RS400 disp regs correctly ??? */
2620 temp = RREG32(RS400_DISP1_REG_CNTL);
2621 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2622 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2623 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2624 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2625 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2626 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2627 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2628 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2629 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2630 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2631 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2632 }
2633 #endif
2634
2635 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2636 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2637 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2638 }
2639
2640 if (mode2) {
2641 u32 grph2_cntl;
2642 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2643
2644 if (stop_req > max_stop_req)
2645 stop_req = max_stop_req;
2646
2647 /*
2648 Find the drain rate of the display buffer.
2649 */
2650 temp_ff.full = rfixed_const((16/pixel_bytes2));
2651 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2652
2653 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2654 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2655 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2656 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2657 if ((rdev->family == CHIP_R350) &&
2658 (stop_req > 0x15)) {
2659 stop_req -= 0x10;
2660 }
2661 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2662 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2663 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2664 RADEON_GRPH_CRITICAL_AT_SOF |
2665 RADEON_GRPH_STOP_CNTL);
2666
2667 if ((rdev->family == CHIP_RS100) ||
2668 (rdev->family == CHIP_RS200))
2669 critical_point2 = 0;
2670 else {
2671 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2672 temp_ff.full = rfixed_const(temp);
2673 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2674 if (sclk_ff.full < temp_ff.full)
2675 temp_ff.full = sclk_ff.full;
2676
2677 read_return_rate.full = temp_ff.full;
2678
2679 if (mode1) {
2680 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2681 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2682 } else {
2683 time_disp1_drop_priority.full = 0;
2684 }
2685 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2686 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2687 crit_point_ff.full += rfixed_const_half(0);
2688
2689 critical_point2 = rfixed_trunc(crit_point_ff);
2690
2691 if (rdev->disp_priority == 2) {
2692 critical_point2 = 0;
2693 }
2694
2695 if (max_stop_req - critical_point2 < 4)
2696 critical_point2 = 0;
2697
2698 }
2699
2700 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2701 /* some R300 cards have problem with this set to 0 */
2702 critical_point2 = 0x10;
2703 }
2704
2705 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2706 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2707
2708 if ((rdev->family == CHIP_RS400) ||
2709 (rdev->family == CHIP_RS480)) {
2710 #if 0
2711 /* attempt to program RS400 disp2 regs correctly ??? */
2712 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2713 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2714 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2715 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2716 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2717 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2718 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2719 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2720 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2721 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2722 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2723 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2724 #endif
2725 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2726 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2727 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2728 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2729 }
2730
2731 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2732 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2733 }
2734 }
2735
2736 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2737 {
2738 DRM_ERROR("pitch %d\n", t->pitch);
2739 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2740 DRM_ERROR("width %d\n", t->width);
2741 DRM_ERROR("width_11 %d\n", t->width_11);
2742 DRM_ERROR("height %d\n", t->height);
2743 DRM_ERROR("height_11 %d\n", t->height_11);
2744 DRM_ERROR("num levels %d\n", t->num_levels);
2745 DRM_ERROR("depth %d\n", t->txdepth);
2746 DRM_ERROR("bpp %d\n", t->cpp);
2747 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2748 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2749 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2750 DRM_ERROR("compress format %d\n", t->compress_format);
2751 }
2752
2753 static int r100_cs_track_cube(struct radeon_device *rdev,
2754 struct r100_cs_track *track, unsigned idx)
2755 {
2756 unsigned face, w, h;
2757 struct radeon_bo *cube_robj;
2758 unsigned long size;
2759
2760 for (face = 0; face < 5; face++) {
2761 cube_robj = track->textures[idx].cube_info[face].robj;
2762 w = track->textures[idx].cube_info[face].width;
2763 h = track->textures[idx].cube_info[face].height;
2764
2765 size = w * h;
2766 size *= track->textures[idx].cpp;
2767
2768 size += track->textures[idx].cube_info[face].offset;
2769
2770 if (size > radeon_bo_size(cube_robj)) {
2771 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2772 size, radeon_bo_size(cube_robj));
2773 r100_cs_track_texture_print(&track->textures[idx]);
2774 return -1;
2775 }
2776 }
2777 return 0;
2778 }
2779
2780 static int r100_track_compress_size(int compress_format, int w, int h)
2781 {
2782 int block_width, block_height, block_bytes;
2783 int wblocks, hblocks;
2784 int min_wblocks;
2785 int sz;
2786
2787 block_width = 4;
2788 block_height = 4;
2789
2790 switch (compress_format) {
2791 case R100_TRACK_COMP_DXT1:
2792 block_bytes = 8;
2793 min_wblocks = 4;
2794 break;
2795 default:
2796 case R100_TRACK_COMP_DXT35:
2797 block_bytes = 16;
2798 min_wblocks = 2;
2799 break;
2800 }
2801
2802 hblocks = (h + block_height - 1) / block_height;
2803 wblocks = (w + block_width - 1) / block_width;
2804 if (wblocks < min_wblocks)
2805 wblocks = min_wblocks;
2806 sz = wblocks * hblocks * block_bytes;
2807 return sz;
2808 }
2809
2810 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2811 struct r100_cs_track *track)
2812 {
2813 struct radeon_bo *robj;
2814 unsigned long size;
2815 unsigned u, i, w, h;
2816 int ret;
2817
2818 for (u = 0; u < track->num_texture; u++) {
2819 if (!track->textures[u].enabled)
2820 continue;
2821 robj = track->textures[u].robj;
2822 if (robj == NULL) {
2823 DRM_ERROR("No texture bound to unit %u\n", u);
2824 return -EINVAL;
2825 }
2826 size = 0;
2827 for (i = 0; i <= track->textures[u].num_levels; i++) {
2828 if (track->textures[u].use_pitch) {
2829 if (rdev->family < CHIP_R300)
2830 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2831 else
2832 w = track->textures[u].pitch / (1 << i);
2833 } else {
2834 w = track->textures[u].width;
2835 if (rdev->family >= CHIP_RV515)
2836 w |= track->textures[u].width_11;
2837 w = w / (1 << i);
2838 if (track->textures[u].roundup_w)
2839 w = roundup_pow_of_two(w);
2840 }
2841 h = track->textures[u].height;
2842 if (rdev->family >= CHIP_RV515)
2843 h |= track->textures[u].height_11;
2844 h = h / (1 << i);
2845 if (track->textures[u].roundup_h)
2846 h = roundup_pow_of_two(h);
2847 if (track->textures[u].compress_format) {
2848
2849 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2850 /* compressed textures are block based */
2851 } else
2852 size += w * h;
2853 }
2854 size *= track->textures[u].cpp;
2855
2856 switch (track->textures[u].tex_coord_type) {
2857 case 0:
2858 break;
2859 case 1:
2860 size *= (1 << track->textures[u].txdepth);
2861 break;
2862 case 2:
2863 if (track->separate_cube) {
2864 ret = r100_cs_track_cube(rdev, track, u);
2865 if (ret)
2866 return ret;
2867 } else
2868 size *= 6;
2869 break;
2870 default:
2871 DRM_ERROR("Invalid texture coordinate type %u for unit "
2872 "%u\n", track->textures[u].tex_coord_type, u);
2873 return -EINVAL;
2874 }
2875 if (size > radeon_bo_size(robj)) {
2876 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2877 "%lu\n", u, size, radeon_bo_size(robj));
2878 r100_cs_track_texture_print(&track->textures[u]);
2879 return -EINVAL;
2880 }
2881 }
2882 return 0;
2883 }
2884
2885 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2886 {
2887 unsigned i;
2888 unsigned long size;
2889 unsigned prim_walk;
2890 unsigned nverts;
2891
2892 for (i = 0; i < track->num_cb; i++) {
2893 if (track->cb[i].robj == NULL) {
2894 if (!(track->fastfill || track->color_channel_mask ||
2895 track->blend_read_enable)) {
2896 continue;
2897 }
2898 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2899 return -EINVAL;
2900 }
2901 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2902 size += track->cb[i].offset;
2903 if (size > radeon_bo_size(track->cb[i].robj)) {
2904 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2905 "(need %lu have %lu) !\n", i, size,
2906 radeon_bo_size(track->cb[i].robj));
2907 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2908 i, track->cb[i].pitch, track->cb[i].cpp,
2909 track->cb[i].offset, track->maxy);
2910 return -EINVAL;
2911 }
2912 }
2913 if (track->z_enabled) {
2914 if (track->zb.robj == NULL) {
2915 DRM_ERROR("[drm] No buffer for z buffer !\n");
2916 return -EINVAL;
2917 }
2918 size = track->zb.pitch * track->zb.cpp * track->maxy;
2919 size += track->zb.offset;
2920 if (size > radeon_bo_size(track->zb.robj)) {
2921 DRM_ERROR("[drm] Buffer too small for z buffer "
2922 "(need %lu have %lu) !\n", size,
2923 radeon_bo_size(track->zb.robj));
2924 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2925 track->zb.pitch, track->zb.cpp,
2926 track->zb.offset, track->maxy);
2927 return -EINVAL;
2928 }
2929 }
2930 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2931 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2932 switch (prim_walk) {
2933 case 1:
2934 for (i = 0; i < track->num_arrays; i++) {
2935 size = track->arrays[i].esize * track->max_indx * 4;
2936 if (track->arrays[i].robj == NULL) {
2937 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2938 "bound\n", prim_walk, i);
2939 return -EINVAL;
2940 }
2941 if (size > radeon_bo_size(track->arrays[i].robj)) {
2942 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2943 "need %lu dwords have %lu dwords\n",
2944 prim_walk, i, size >> 2,
2945 radeon_bo_size(track->arrays[i].robj)
2946 >> 2);
2947 DRM_ERROR("Max indices %u\n", track->max_indx);
2948 return -EINVAL;
2949 }
2950 }
2951 break;
2952 case 2:
2953 for (i = 0; i < track->num_arrays; i++) {
2954 size = track->arrays[i].esize * (nverts - 1) * 4;
2955 if (track->arrays[i].robj == NULL) {
2956 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2957 "bound\n", prim_walk, i);
2958 return -EINVAL;
2959 }
2960 if (size > radeon_bo_size(track->arrays[i].robj)) {
2961 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2962 "need %lu dwords have %lu dwords\n",
2963 prim_walk, i, size >> 2,
2964 radeon_bo_size(track->arrays[i].robj)
2965 >> 2);
2966 return -EINVAL;
2967 }
2968 }
2969 break;
2970 case 3:
2971 size = track->vtx_size * nverts;
2972 if (size != track->immd_dwords) {
2973 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2974 track->immd_dwords, size);
2975 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2976 nverts, track->vtx_size);
2977 return -EINVAL;
2978 }
2979 break;
2980 default:
2981 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2982 prim_walk);
2983 return -EINVAL;
2984 }
2985 return r100_cs_track_texture_check(rdev, track);
2986 }
2987
2988 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2989 {
2990 unsigned i, face;
2991
2992 if (rdev->family < CHIP_R300) {
2993 track->num_cb = 1;
2994 if (rdev->family <= CHIP_RS200)
2995 track->num_texture = 3;
2996 else
2997 track->num_texture = 6;
2998 track->maxy = 2048;
2999 track->separate_cube = 1;
3000 } else {
3001 track->num_cb = 4;
3002 track->num_texture = 16;
3003 track->maxy = 4096;
3004 track->separate_cube = 0;
3005 }
3006
3007 for (i = 0; i < track->num_cb; i++) {
3008 track->cb[i].robj = NULL;
3009 track->cb[i].pitch = 8192;
3010 track->cb[i].cpp = 16;
3011 track->cb[i].offset = 0;
3012 }
3013 track->z_enabled = true;
3014 track->zb.robj = NULL;
3015 track->zb.pitch = 8192;
3016 track->zb.cpp = 4;
3017 track->zb.offset = 0;
3018 track->vtx_size = 0x7F;
3019 track->immd_dwords = 0xFFFFFFFFUL;
3020 track->num_arrays = 11;
3021 track->max_indx = 0x00FFFFFFUL;
3022 for (i = 0; i < track->num_arrays; i++) {
3023 track->arrays[i].robj = NULL;
3024 track->arrays[i].esize = 0x7F;
3025 }
3026 for (i = 0; i < track->num_texture; i++) {
3027 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3028 track->textures[i].pitch = 16536;
3029 track->textures[i].width = 16536;
3030 track->textures[i].height = 16536;
3031 track->textures[i].width_11 = 1 << 11;
3032 track->textures[i].height_11 = 1 << 11;
3033 track->textures[i].num_levels = 12;
3034 if (rdev->family <= CHIP_RS200) {
3035 track->textures[i].tex_coord_type = 0;
3036 track->textures[i].txdepth = 0;
3037 } else {
3038 track->textures[i].txdepth = 16;
3039 track->textures[i].tex_coord_type = 1;
3040 }
3041 track->textures[i].cpp = 64;
3042 track->textures[i].robj = NULL;
3043 /* CS IB emission code makes sure texture unit are disabled */
3044 track->textures[i].enabled = false;
3045 track->textures[i].roundup_w = true;
3046 track->textures[i].roundup_h = true;
3047 if (track->separate_cube)
3048 for (face = 0; face < 5; face++) {
3049 track->textures[i].cube_info[face].robj = NULL;
3050 track->textures[i].cube_info[face].width = 16536;
3051 track->textures[i].cube_info[face].height = 16536;
3052 track->textures[i].cube_info[face].offset = 0;
3053 }
3054 }
3055 }
3056
3057 int r100_ring_test(struct radeon_device *rdev)
3058 {
3059 uint32_t scratch;
3060 uint32_t tmp = 0;
3061 unsigned i;
3062 int r;
3063
3064 r = radeon_scratch_get(rdev, &scratch);
3065 if (r) {
3066 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3067 return r;
3068 }
3069 WREG32(scratch, 0xCAFEDEAD);
3070 r = radeon_ring_lock(rdev, 2);
3071 if (r) {
3072 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3073 radeon_scratch_free(rdev, scratch);
3074 return r;
3075 }
3076 radeon_ring_write(rdev, PACKET0(scratch, 0));
3077 radeon_ring_write(rdev, 0xDEADBEEF);
3078 radeon_ring_unlock_commit(rdev);
3079 for (i = 0; i < rdev->usec_timeout; i++) {
3080 tmp = RREG32(scratch);
3081 if (tmp == 0xDEADBEEF) {
3082 break;
3083 }
3084 DRM_UDELAY(1);
3085 }
3086 if (i < rdev->usec_timeout) {
3087 DRM_INFO("ring test succeeded in %d usecs\n", i);
3088 } else {
3089 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3090 scratch, tmp);
3091 r = -EINVAL;
3092 }
3093 radeon_scratch_free(rdev, scratch);
3094 return r;
3095 }
3096
3097 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3098 {
3099 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3100 radeon_ring_write(rdev, ib->gpu_addr);
3101 radeon_ring_write(rdev, ib->length_dw);
3102 }
3103
3104 int r100_ib_test(struct radeon_device *rdev)
3105 {
3106 struct radeon_ib *ib;
3107 uint32_t scratch;
3108 uint32_t tmp = 0;
3109 unsigned i;
3110 int r;
3111
3112 r = radeon_scratch_get(rdev, &scratch);
3113 if (r) {
3114 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3115 return r;
3116 }
3117 WREG32(scratch, 0xCAFEDEAD);
3118 r = radeon_ib_get(rdev, &ib);
3119 if (r) {
3120 return r;
3121 }
3122 ib->ptr[0] = PACKET0(scratch, 0);
3123 ib->ptr[1] = 0xDEADBEEF;
3124 ib->ptr[2] = PACKET2(0);
3125 ib->ptr[3] = PACKET2(0);
3126 ib->ptr[4] = PACKET2(0);
3127 ib->ptr[5] = PACKET2(0);
3128 ib->ptr[6] = PACKET2(0);
3129 ib->ptr[7] = PACKET2(0);
3130 ib->length_dw = 8;
3131 r = radeon_ib_schedule(rdev, ib);
3132 if (r) {
3133 radeon_scratch_free(rdev, scratch);
3134 radeon_ib_free(rdev, &ib);
3135 return r;
3136 }
3137 r = radeon_fence_wait(ib->fence, false);
3138 if (r) {
3139 return r;
3140 }
3141 for (i = 0; i < rdev->usec_timeout; i++) {
3142 tmp = RREG32(scratch);
3143 if (tmp == 0xDEADBEEF) {
3144 break;
3145 }
3146 DRM_UDELAY(1);
3147 }
3148 if (i < rdev->usec_timeout) {
3149 DRM_INFO("ib test succeeded in %u usecs\n", i);
3150 } else {
3151 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3152 scratch, tmp);
3153 r = -EINVAL;
3154 }
3155 radeon_scratch_free(rdev, scratch);
3156 radeon_ib_free(rdev, &ib);
3157 return r;
3158 }
3159
3160 void r100_ib_fini(struct radeon_device *rdev)
3161 {
3162 radeon_ib_pool_fini(rdev);
3163 }
3164
3165 int r100_ib_init(struct radeon_device *rdev)
3166 {
3167 int r;
3168
3169 r = radeon_ib_pool_init(rdev);
3170 if (r) {
3171 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3172 r100_ib_fini(rdev);
3173 return r;
3174 }
3175 r = r100_ib_test(rdev);
3176 if (r) {
3177 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3178 r100_ib_fini(rdev);
3179 return r;
3180 }
3181 return 0;
3182 }
3183
3184 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3185 {
3186 /* Shutdown CP we shouldn't need to do that but better be safe than
3187 * sorry
3188 */
3189 rdev->cp.ready = false;
3190 WREG32(R_000740_CP_CSQ_CNTL, 0);
3191
3192 /* Save few CRTC registers */
3193 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3194 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3195 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3196 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3197 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3198 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3199 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3200 }
3201
3202 /* Disable VGA aperture access */
3203 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3204 /* Disable cursor, overlay, crtc */
3205 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3206 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3207 S_000054_CRTC_DISPLAY_DIS(1));
3208 WREG32(R_000050_CRTC_GEN_CNTL,
3209 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3210 S_000050_CRTC_DISP_REQ_EN_B(1));
3211 WREG32(R_000420_OV0_SCALE_CNTL,
3212 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3213 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3214 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3215 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3216 S_000360_CUR2_LOCK(1));
3217 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3218 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3219 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3220 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3221 WREG32(R_000360_CUR2_OFFSET,
3222 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3223 }
3224 }
3225
3226 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3227 {
3228 /* Update base address for crtc */
3229 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3230 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3231 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3232 rdev->mc.vram_location);
3233 }
3234 /* Restore CRTC registers */
3235 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3236 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3237 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3238 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3239 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3240 }
3241 }
3242
3243 void r100_vga_render_disable(struct radeon_device *rdev)
3244 {
3245 u32 tmp;
3246
3247 tmp = RREG8(R_0003C2_GENMO_WT);
3248 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3249 }
3250
3251 static void r100_debugfs(struct radeon_device *rdev)
3252 {
3253 int r;
3254
3255 r = r100_debugfs_mc_info_init(rdev);
3256 if (r)
3257 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3258 }
3259
3260 static void r100_mc_program(struct radeon_device *rdev)
3261 {
3262 struct r100_mc_save save;
3263
3264 /* Stops all mc clients */
3265 r100_mc_stop(rdev, &save);
3266 if (rdev->flags & RADEON_IS_AGP) {
3267 WREG32(R_00014C_MC_AGP_LOCATION,
3268 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3269 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3270 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3271 if (rdev->family > CHIP_RV200)
3272 WREG32(R_00015C_AGP_BASE_2,
3273 upper_32_bits(rdev->mc.agp_base) & 0xff);
3274 } else {
3275 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3276 WREG32(R_000170_AGP_BASE, 0);
3277 if (rdev->family > CHIP_RV200)
3278 WREG32(R_00015C_AGP_BASE_2, 0);
3279 }
3280 /* Wait for mc idle */
3281 if (r100_mc_wait_for_idle(rdev))
3282 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3283 /* Program MC, should be a 32bits limited address space */
3284 WREG32(R_000148_MC_FB_LOCATION,
3285 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3286 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3287 r100_mc_resume(rdev, &save);
3288 }
3289
3290 void r100_clock_startup(struct radeon_device *rdev)
3291 {
3292 u32 tmp;
3293
3294 if (radeon_dynclks != -1 && radeon_dynclks)
3295 radeon_legacy_set_clock_gating(rdev, 1);
3296 /* We need to force on some of the block */
3297 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3298 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3299 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3300 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3301 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3302 }
3303
3304 static int r100_startup(struct radeon_device *rdev)
3305 {
3306 int r;
3307
3308 /* set common regs */
3309 r100_set_common_regs(rdev);
3310 /* program mc */
3311 r100_mc_program(rdev);
3312 /* Resume clock */
3313 r100_clock_startup(rdev);
3314 /* Initialize GPU configuration (# pipes, ...) */
3315 r100_gpu_init(rdev);
3316 /* Initialize GART (initialize after TTM so we can allocate
3317 * memory through TTM but finalize after TTM) */
3318 r100_enable_bm(rdev);
3319 if (rdev->flags & RADEON_IS_PCI) {
3320 r = r100_pci_gart_enable(rdev);
3321 if (r)
3322 return r;
3323 }
3324 /* Enable IRQ */
3325 r100_irq_set(rdev);
3326 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3327 /* 1M ring buffer */
3328 r = r100_cp_init(rdev, 1024 * 1024);
3329 if (r) {
3330 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3331 return r;
3332 }
3333 r = r100_wb_init(rdev);
3334 if (r)
3335 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3336 r = r100_ib_init(rdev);
3337 if (r) {
3338 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3339 return r;
3340 }
3341 return 0;
3342 }
3343
3344 int r100_resume(struct radeon_device *rdev)
3345 {
3346 /* Make sur GART are not working */
3347 if (rdev->flags & RADEON_IS_PCI)
3348 r100_pci_gart_disable(rdev);
3349 /* Resume clock before doing reset */
3350 r100_clock_startup(rdev);
3351 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3352 if (radeon_gpu_reset(rdev)) {
3353 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3354 RREG32(R_000E40_RBBM_STATUS),
3355 RREG32(R_0007C0_CP_STAT));
3356 }
3357 /* post */
3358 radeon_combios_asic_init(rdev->ddev);
3359 /* Resume clock after posting */
3360 r100_clock_startup(rdev);
3361 /* Initialize surface registers */
3362 radeon_surface_init(rdev);
3363 return r100_startup(rdev);
3364 }
3365
3366 int r100_suspend(struct radeon_device *rdev)
3367 {
3368 r100_cp_disable(rdev);
3369 r100_wb_disable(rdev);
3370 r100_irq_disable(rdev);
3371 if (rdev->flags & RADEON_IS_PCI)
3372 r100_pci_gart_disable(rdev);
3373 return 0;
3374 }
3375
3376 void r100_fini(struct radeon_device *rdev)
3377 {
3378 r100_cp_fini(rdev);
3379 r100_wb_fini(rdev);
3380 r100_ib_fini(rdev);
3381 radeon_gem_fini(rdev);
3382 if (rdev->flags & RADEON_IS_PCI)
3383 r100_pci_gart_fini(rdev);
3384 radeon_agp_fini(rdev);
3385 radeon_irq_kms_fini(rdev);
3386 radeon_fence_driver_fini(rdev);
3387 radeon_bo_fini(rdev);
3388 radeon_atombios_fini(rdev);
3389 kfree(rdev->bios);
3390 rdev->bios = NULL;
3391 }
3392
3393 int r100_mc_init(struct radeon_device *rdev)
3394 {
3395 int r;
3396 u32 tmp;
3397
3398 /* Setup GPU memory space */
3399 rdev->mc.vram_location = 0xFFFFFFFFUL;
3400 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3401 if (rdev->flags & RADEON_IS_IGP) {
3402 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3403 rdev->mc.vram_location = tmp << 16;
3404 }
3405 if (rdev->flags & RADEON_IS_AGP) {
3406 r = radeon_agp_init(rdev);
3407 if (r) {
3408 radeon_agp_disable(rdev);
3409 } else {
3410 rdev->mc.gtt_location = rdev->mc.agp_base;
3411 }
3412 }
3413 r = radeon_mc_setup(rdev);
3414 if (r)
3415 return r;
3416 return 0;
3417 }
3418
3419 int r100_init(struct radeon_device *rdev)
3420 {
3421 int r;
3422
3423 /* Register debugfs file specific to this group of asics */
3424 r100_debugfs(rdev);
3425 /* Disable VGA */
3426 r100_vga_render_disable(rdev);
3427 /* Initialize scratch registers */
3428 radeon_scratch_init(rdev);
3429 /* Initialize surface registers */
3430 radeon_surface_init(rdev);
3431 /* TODO: disable VGA need to use VGA request */
3432 /* BIOS*/
3433 if (!radeon_get_bios(rdev)) {
3434 if (ASIC_IS_AVIVO(rdev))
3435 return -EINVAL;
3436 }
3437 if (rdev->is_atom_bios) {
3438 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3439 return -EINVAL;
3440 } else {
3441 r = radeon_combios_init(rdev);
3442 if (r)
3443 return r;
3444 }
3445 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3446 if (radeon_gpu_reset(rdev)) {
3447 dev_warn(rdev->dev,
3448 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3449 RREG32(R_000E40_RBBM_STATUS),
3450 RREG32(R_0007C0_CP_STAT));
3451 }
3452 /* check if cards are posted or not */
3453 if (radeon_boot_test_post_card(rdev) == false)
3454 return -EINVAL;
3455 /* Set asic errata */
3456 r100_errata(rdev);
3457 /* Initialize clocks */
3458 radeon_get_clock_info(rdev->ddev);
3459 /* Initialize power management */
3460 radeon_pm_init(rdev);
3461 /* Get vram informations */
3462 r100_vram_info(rdev);
3463 /* Initialize memory controller (also test AGP) */
3464 r = r100_mc_init(rdev);
3465 if (r)
3466 return r;
3467 /* Fence driver */
3468 r = radeon_fence_driver_init(rdev);
3469 if (r)
3470 return r;
3471 r = radeon_irq_kms_init(rdev);
3472 if (r)
3473 return r;
3474 /* Memory manager */
3475 r = radeon_bo_init(rdev);
3476 if (r)
3477 return r;
3478 if (rdev->flags & RADEON_IS_PCI) {
3479 r = r100_pci_gart_init(rdev);
3480 if (r)
3481 return r;
3482 }
3483 r100_set_safe_registers(rdev);
3484 rdev->accel_working = true;
3485 r = r100_startup(rdev);
3486 if (r) {
3487 /* Somethings want wront with the accel init stop accel */
3488 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3489 r100_cp_fini(rdev);
3490 r100_wb_fini(rdev);
3491 r100_ib_fini(rdev);
3492 radeon_irq_kms_fini(rdev);
3493 if (rdev->flags & RADEON_IS_PCI)
3494 r100_pci_gart_fini(rdev);
3495 rdev->accel_working = false;
3496 }
3497 return 0;
3498 }
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