2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include <drm/drm_crtc_helper.h>
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
36 #include "radeon_drm.h"
37 #include "r100_track.h"
40 #include "r300_reg_safe.h"
42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
47 * However, scheduling such write to the ring seems harmless, i suspect
48 * the CP read collide with the flush somehow, or maybe the MC, hard to
49 * tell. (Jerome Glisse)
53 * rv370,rv380 PCIE GART
55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
);
57 void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
62 /* Workaround HW bug do flush 2 times */
63 for (i
= 0; i
< 2; i
++) {
64 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
| RADEON_PCIE_TX_GART_INVALIDATE_TLB
);
66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
72 #define R300_PTE_WRITEABLE (1 << 2)
73 #define R300_PTE_READABLE (1 << 3)
75 int rv370_pcie_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
77 void __iomem
*ptr
= rdev
->gart
.ptr
;
79 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
82 addr
= (lower_32_bits(addr
) >> 8) |
83 ((upper_32_bits(addr
) & 0xff) << 24) |
84 R300_PTE_WRITEABLE
| R300_PTE_READABLE
;
85 /* on x86 we want this to be CPU endian, on powerpc
86 * on powerpc without HW swappers, it'll get swapped on way
87 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
88 writel(addr
, ((void __iomem
*)ptr
) + (i
* 4));
92 int rv370_pcie_gart_init(struct radeon_device
*rdev
)
96 if (rdev
->gart
.robj
) {
97 WARN(1, "RV370 PCIE GART already initialized\n");
100 /* Initialize common gart structure */
101 r
= radeon_gart_init(rdev
);
104 r
= rv370_debugfs_pcie_gart_info_init(rdev
);
106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
107 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
108 rdev
->asic
->gart
.tlb_flush
= &rv370_pcie_gart_tlb_flush
;
109 rdev
->asic
->gart
.set_page
= &rv370_pcie_gart_set_page
;
110 return radeon_gart_table_vram_alloc(rdev
);
113 int rv370_pcie_gart_enable(struct radeon_device
*rdev
)
119 if (rdev
->gart
.robj
== NULL
) {
120 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
123 r
= radeon_gart_table_vram_pin(rdev
);
126 radeon_gart_restore(rdev
);
127 /* discard memory request outside of configured range */
128 tmp
= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO
, rdev
->mc
.gtt_start
);
131 tmp
= rdev
->mc
.gtt_end
& ~RADEON_GPU_PAGE_MASK
;
132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO
, tmp
);
133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI
, 0);
134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI
, 0);
135 table_addr
= rdev
->gart
.table_addr
;
136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE
, table_addr
);
137 /* FIXME: setup default page */
138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
, rdev
->mc
.vram_start
);
139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI
, 0);
141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR
, 0);
142 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
143 tmp
|= RADEON_PCIE_TX_GART_EN
;
144 tmp
|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
146 rv370_pcie_gart_tlb_flush(rdev
);
147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
148 (unsigned)(rdev
->mc
.gtt_size
>> 20),
149 (unsigned long long)table_addr
);
150 rdev
->gart
.ready
= true;
154 void rv370_pcie_gart_disable(struct radeon_device
*rdev
)
158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO
, 0);
159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO
, 0);
160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI
, 0);
161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI
, 0);
162 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
163 tmp
|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
& ~RADEON_PCIE_TX_GART_EN
);
165 radeon_gart_table_vram_unpin(rdev
);
168 void rv370_pcie_gart_fini(struct radeon_device
*rdev
)
170 radeon_gart_fini(rdev
);
171 rv370_pcie_gart_disable(rdev
);
172 radeon_gart_table_vram_free(rdev
);
175 void r300_fence_ring_emit(struct radeon_device
*rdev
,
176 struct radeon_fence
*fence
)
178 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
180 /* Who ever call radeon_fence_emit should call ring_lock and ask
181 * for enough space (today caller are ib schedule and buffer move) */
182 /* Write SC register so SC & US assert idle */
183 radeon_ring_write(ring
, PACKET0(R300_RE_SCISSORS_TL
, 0));
184 radeon_ring_write(ring
, 0);
185 radeon_ring_write(ring
, PACKET0(R300_RE_SCISSORS_BR
, 0));
186 radeon_ring_write(ring
, 0);
188 radeon_ring_write(ring
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
189 radeon_ring_write(ring
, R300_RB3D_DC_FLUSH
);
190 radeon_ring_write(ring
, PACKET0(R300_RB3D_ZCACHE_CTLSTAT
, 0));
191 radeon_ring_write(ring
, R300_ZC_FLUSH
);
192 /* Wait until IDLE & CLEAN */
193 radeon_ring_write(ring
, PACKET0(RADEON_WAIT_UNTIL
, 0));
194 radeon_ring_write(ring
, (RADEON_WAIT_3D_IDLECLEAN
|
195 RADEON_WAIT_2D_IDLECLEAN
|
196 RADEON_WAIT_DMA_GUI_IDLE
));
197 radeon_ring_write(ring
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
198 radeon_ring_write(ring
, rdev
->config
.r300
.hdp_cntl
|
199 RADEON_HDP_READ_BUFFER_INVALIDATE
);
200 radeon_ring_write(ring
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
201 radeon_ring_write(ring
, rdev
->config
.r300
.hdp_cntl
);
202 /* Emit fence sequence & fire IRQ */
203 radeon_ring_write(ring
, PACKET0(rdev
->fence_drv
[fence
->ring
].scratch_reg
, 0));
204 radeon_ring_write(ring
, fence
->seq
);
205 radeon_ring_write(ring
, PACKET0(RADEON_GEN_INT_STATUS
, 0));
206 radeon_ring_write(ring
, RADEON_SW_INT_FIRE
);
209 void r300_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
211 unsigned gb_tile_config
;
214 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
215 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
);
216 switch(rdev
->num_gb_pipes
) {
218 gb_tile_config
|= R300_PIPE_COUNT_R300
;
221 gb_tile_config
|= R300_PIPE_COUNT_R420_3P
;
224 gb_tile_config
|= R300_PIPE_COUNT_R420
;
228 gb_tile_config
|= R300_PIPE_COUNT_RV350
;
232 r
= radeon_ring_lock(rdev
, ring
, 64);
236 radeon_ring_write(ring
, PACKET0(RADEON_ISYNC_CNTL
, 0));
237 radeon_ring_write(ring
,
238 RADEON_ISYNC_ANY2D_IDLE3D
|
239 RADEON_ISYNC_ANY3D_IDLE2D
|
240 RADEON_ISYNC_WAIT_IDLEGUI
|
241 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
242 radeon_ring_write(ring
, PACKET0(R300_GB_TILE_CONFIG
, 0));
243 radeon_ring_write(ring
, gb_tile_config
);
244 radeon_ring_write(ring
, PACKET0(RADEON_WAIT_UNTIL
, 0));
245 radeon_ring_write(ring
,
246 RADEON_WAIT_2D_IDLECLEAN
|
247 RADEON_WAIT_3D_IDLECLEAN
);
248 radeon_ring_write(ring
, PACKET0(R300_DST_PIPE_CONFIG
, 0));
249 radeon_ring_write(ring
, R300_PIPE_AUTO_CONFIG
);
250 radeon_ring_write(ring
, PACKET0(R300_GB_SELECT
, 0));
251 radeon_ring_write(ring
, 0);
252 radeon_ring_write(ring
, PACKET0(R300_GB_ENABLE
, 0));
253 radeon_ring_write(ring
, 0);
254 radeon_ring_write(ring
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
255 radeon_ring_write(ring
, R300_RB3D_DC_FLUSH
| R300_RB3D_DC_FREE
);
256 radeon_ring_write(ring
, PACKET0(R300_RB3D_ZCACHE_CTLSTAT
, 0));
257 radeon_ring_write(ring
, R300_ZC_FLUSH
| R300_ZC_FREE
);
258 radeon_ring_write(ring
, PACKET0(RADEON_WAIT_UNTIL
, 0));
259 radeon_ring_write(ring
,
260 RADEON_WAIT_2D_IDLECLEAN
|
261 RADEON_WAIT_3D_IDLECLEAN
);
262 radeon_ring_write(ring
, PACKET0(R300_GB_AA_CONFIG
, 0));
263 radeon_ring_write(ring
, 0);
264 radeon_ring_write(ring
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
265 radeon_ring_write(ring
, R300_RB3D_DC_FLUSH
| R300_RB3D_DC_FREE
);
266 radeon_ring_write(ring
, PACKET0(R300_RB3D_ZCACHE_CTLSTAT
, 0));
267 radeon_ring_write(ring
, R300_ZC_FLUSH
| R300_ZC_FREE
);
268 radeon_ring_write(ring
, PACKET0(R300_GB_MSPOS0
, 0));
269 radeon_ring_write(ring
,
270 ((6 << R300_MS_X0_SHIFT
) |
271 (6 << R300_MS_Y0_SHIFT
) |
272 (6 << R300_MS_X1_SHIFT
) |
273 (6 << R300_MS_Y1_SHIFT
) |
274 (6 << R300_MS_X2_SHIFT
) |
275 (6 << R300_MS_Y2_SHIFT
) |
276 (6 << R300_MSBD0_Y_SHIFT
) |
277 (6 << R300_MSBD0_X_SHIFT
)));
278 radeon_ring_write(ring
, PACKET0(R300_GB_MSPOS1
, 0));
279 radeon_ring_write(ring
,
280 ((6 << R300_MS_X3_SHIFT
) |
281 (6 << R300_MS_Y3_SHIFT
) |
282 (6 << R300_MS_X4_SHIFT
) |
283 (6 << R300_MS_Y4_SHIFT
) |
284 (6 << R300_MS_X5_SHIFT
) |
285 (6 << R300_MS_Y5_SHIFT
) |
286 (6 << R300_MSBD1_SHIFT
)));
287 radeon_ring_write(ring
, PACKET0(R300_GA_ENHANCE
, 0));
288 radeon_ring_write(ring
, R300_GA_DEADLOCK_CNTL
| R300_GA_FASTSYNC_CNTL
);
289 radeon_ring_write(ring
, PACKET0(R300_GA_POLY_MODE
, 0));
290 radeon_ring_write(ring
,
291 R300_FRONT_PTYPE_TRIANGE
| R300_BACK_PTYPE_TRIANGE
);
292 radeon_ring_write(ring
, PACKET0(R300_GA_ROUND_MODE
, 0));
293 radeon_ring_write(ring
,
294 R300_GEOMETRY_ROUND_NEAREST
|
295 R300_COLOR_ROUND_NEAREST
);
296 radeon_ring_unlock_commit(rdev
, ring
);
299 void r300_errata(struct radeon_device
*rdev
)
301 rdev
->pll_errata
= 0;
303 if (rdev
->family
== CHIP_R300
&&
304 (RREG32(RADEON_CONFIG_CNTL
) & RADEON_CFG_ATI_REV_ID_MASK
) == RADEON_CFG_ATI_REV_A11
) {
305 rdev
->pll_errata
|= CHIP_ERRATA_R300_CG
;
309 int r300_mc_wait_for_idle(struct radeon_device
*rdev
)
314 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
316 tmp
= RREG32(RADEON_MC_STATUS
);
317 if (tmp
& R300_MC_IDLE
) {
325 void r300_gpu_init(struct radeon_device
*rdev
)
327 uint32_t gb_tile_config
, tmp
;
329 if ((rdev
->family
== CHIP_R300
&& rdev
->pdev
->device
!= 0x4144) ||
330 (rdev
->family
== CHIP_R350
&& rdev
->pdev
->device
!= 0x4148)) {
332 rdev
->num_gb_pipes
= 2;
334 /* rv350,rv370,rv380,r300 AD, r350 AH */
335 rdev
->num_gb_pipes
= 1;
337 rdev
->num_z_pipes
= 1;
338 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
);
339 switch (rdev
->num_gb_pipes
) {
341 gb_tile_config
|= R300_PIPE_COUNT_R300
;
344 gb_tile_config
|= R300_PIPE_COUNT_R420_3P
;
347 gb_tile_config
|= R300_PIPE_COUNT_R420
;
351 gb_tile_config
|= R300_PIPE_COUNT_RV350
;
354 WREG32(R300_GB_TILE_CONFIG
, gb_tile_config
);
356 if (r100_gui_wait_for_idle(rdev
)) {
357 printk(KERN_WARNING
"Failed to wait GUI idle while "
358 "programming pipes. Bad things might happen.\n");
361 tmp
= RREG32(R300_DST_PIPE_CONFIG
);
362 WREG32(R300_DST_PIPE_CONFIG
, tmp
| R300_PIPE_AUTO_CONFIG
);
364 WREG32(R300_RB2D_DSTCACHE_MODE
,
365 R300_DC_AUTOFLUSH_ENABLE
|
366 R300_DC_DC_DISABLE_IGNORE_PE
);
368 if (r100_gui_wait_for_idle(rdev
)) {
369 printk(KERN_WARNING
"Failed to wait GUI idle while "
370 "programming pipes. Bad things might happen.\n");
372 if (r300_mc_wait_for_idle(rdev
)) {
373 printk(KERN_WARNING
"Failed to wait MC idle while "
374 "programming pipes. Bad things might happen.\n");
376 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
377 rdev
->num_gb_pipes
, rdev
->num_z_pipes
);
380 bool r300_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
385 rbbm_status
= RREG32(R_000E40_RBBM_STATUS
);
386 if (!G_000E40_GUI_ACTIVE(rbbm_status
)) {
387 r100_gpu_lockup_update(&rdev
->config
.r300
.lockup
, ring
);
390 /* force CP activities */
391 r
= radeon_ring_lock(rdev
, ring
, 2);
394 radeon_ring_write(ring
, 0x80000000);
395 radeon_ring_write(ring
, 0x80000000);
396 radeon_ring_unlock_commit(rdev
, ring
);
398 ring
->rptr
= RREG32(RADEON_CP_RB_RPTR
);
399 return r100_gpu_cp_is_lockup(rdev
, &rdev
->config
.r300
.lockup
, ring
);
402 int r300_asic_reset(struct radeon_device
*rdev
)
404 struct r100_mc_save save
;
408 status
= RREG32(R_000E40_RBBM_STATUS
);
409 if (!G_000E40_GUI_ACTIVE(status
)) {
412 r100_mc_stop(rdev
, &save
);
413 status
= RREG32(R_000E40_RBBM_STATUS
);
414 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
416 WREG32(RADEON_CP_CSQ_CNTL
, 0);
417 tmp
= RREG32(RADEON_CP_RB_CNTL
);
418 WREG32(RADEON_CP_RB_CNTL
, tmp
| RADEON_RB_RPTR_WR_ENA
);
419 WREG32(RADEON_CP_RB_RPTR_WR
, 0);
420 WREG32(RADEON_CP_RB_WPTR
, 0);
421 WREG32(RADEON_CP_RB_CNTL
, tmp
);
423 pci_save_state(rdev
->pdev
);
424 /* disable bus mastering */
425 r100_bm_disable(rdev
);
426 WREG32(R_0000F0_RBBM_SOFT_RESET
, S_0000F0_SOFT_RESET_VAP(1) |
427 S_0000F0_SOFT_RESET_GA(1));
428 RREG32(R_0000F0_RBBM_SOFT_RESET
);
430 WREG32(R_0000F0_RBBM_SOFT_RESET
, 0);
432 status
= RREG32(R_000E40_RBBM_STATUS
);
433 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
434 /* resetting the CP seems to be problematic sometimes it end up
435 * hard locking the computer, but it's necessary for successful
436 * reset more test & playing is needed on R3XX/R4XX to find a
437 * reliable (if any solution)
439 WREG32(R_0000F0_RBBM_SOFT_RESET
, S_0000F0_SOFT_RESET_CP(1));
440 RREG32(R_0000F0_RBBM_SOFT_RESET
);
442 WREG32(R_0000F0_RBBM_SOFT_RESET
, 0);
444 status
= RREG32(R_000E40_RBBM_STATUS
);
445 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
446 /* restore PCI & busmastering */
447 pci_restore_state(rdev
->pdev
);
448 r100_enable_bm(rdev
);
449 /* Check if GPU is idle */
450 if (G_000E40_GA_BUSY(status
) || G_000E40_VAP_BUSY(status
)) {
451 dev_err(rdev
->dev
, "failed to reset GPU\n");
452 rdev
->gpu_lockup
= true;
455 dev_info(rdev
->dev
, "GPU reset succeed\n");
456 r100_mc_resume(rdev
, &save
);
461 * r300,r350,rv350,rv380 VRAM info
463 void r300_mc_init(struct radeon_device
*rdev
)
468 /* DDR for all card after R300 & IGP */
469 rdev
->mc
.vram_is_ddr
= true;
470 tmp
= RREG32(RADEON_MEM_CNTL
);
471 tmp
&= R300_MEM_NUM_CHANNELS_MASK
;
473 case 0: rdev
->mc
.vram_width
= 64; break;
474 case 1: rdev
->mc
.vram_width
= 128; break;
475 case 2: rdev
->mc
.vram_width
= 256; break;
476 default: rdev
->mc
.vram_width
= 128; break;
478 r100_vram_init_sizes(rdev
);
479 base
= rdev
->mc
.aper_base
;
480 if (rdev
->flags
& RADEON_IS_IGP
)
481 base
= (RREG32(RADEON_NB_TOM
) & 0xffff) << 16;
482 radeon_vram_location(rdev
, &rdev
->mc
, base
);
483 rdev
->mc
.gtt_base_align
= 0;
484 if (!(rdev
->flags
& RADEON_IS_AGP
))
485 radeon_gtt_location(rdev
, &rdev
->mc
);
486 radeon_update_bandwidth_info(rdev
);
489 void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
491 uint32_t link_width_cntl
, mask
;
493 if (rdev
->flags
& RADEON_IS_IGP
)
496 if (!(rdev
->flags
& RADEON_IS_PCIE
))
499 /* FIXME wait for idle */
503 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
506 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
509 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
512 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
515 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
518 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
522 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
526 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
528 if ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) ==
529 (mask
<< RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
))
532 link_width_cntl
&= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK
|
533 RADEON_PCIE_LC_RECONFIG_NOW
|
534 RADEON_PCIE_LC_RECONFIG_LATER
|
535 RADEON_PCIE_LC_SHORT_RECONFIG_EN
);
536 link_width_cntl
|= mask
;
537 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
538 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, (link_width_cntl
|
539 RADEON_PCIE_LC_RECONFIG_NOW
));
541 /* wait for lane set to complete */
542 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
543 while (link_width_cntl
== 0xffffffff)
544 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
548 int rv370_get_pcie_lanes(struct radeon_device
*rdev
)
552 if (rdev
->flags
& RADEON_IS_IGP
)
555 if (!(rdev
->flags
& RADEON_IS_PCIE
))
558 /* FIXME wait for idle */
560 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
562 switch ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
) {
563 case RADEON_PCIE_LC_LINK_WIDTH_X0
:
565 case RADEON_PCIE_LC_LINK_WIDTH_X1
:
567 case RADEON_PCIE_LC_LINK_WIDTH_X2
:
569 case RADEON_PCIE_LC_LINK_WIDTH_X4
:
571 case RADEON_PCIE_LC_LINK_WIDTH_X8
:
573 case RADEON_PCIE_LC_LINK_WIDTH_X16
:
579 #if defined(CONFIG_DEBUG_FS)
580 static int rv370_debugfs_pcie_gart_info(struct seq_file
*m
, void *data
)
582 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
583 struct drm_device
*dev
= node
->minor
->dev
;
584 struct radeon_device
*rdev
= dev
->dev_private
;
587 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
588 seq_printf(m
, "PCIE_TX_GART_CNTL 0x%08x\n", tmp
);
589 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_BASE
);
590 seq_printf(m
, "PCIE_TX_GART_BASE 0x%08x\n", tmp
);
591 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO
);
592 seq_printf(m
, "PCIE_TX_GART_START_LO 0x%08x\n", tmp
);
593 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI
);
594 seq_printf(m
, "PCIE_TX_GART_START_HI 0x%08x\n", tmp
);
595 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO
);
596 seq_printf(m
, "PCIE_TX_GART_END_LO 0x%08x\n", tmp
);
597 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI
);
598 seq_printf(m
, "PCIE_TX_GART_END_HI 0x%08x\n", tmp
);
599 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR
);
600 seq_printf(m
, "PCIE_TX_GART_ERROR 0x%08x\n", tmp
);
604 static struct drm_info_list rv370_pcie_gart_info_list
[] = {
605 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info
, 0, NULL
},
609 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
)
611 #if defined(CONFIG_DEBUG_FS)
612 return radeon_debugfs_add_files(rdev
, rv370_pcie_gart_info_list
, 1);
618 static int r300_packet0_check(struct radeon_cs_parser
*p
,
619 struct radeon_cs_packet
*pkt
,
620 unsigned idx
, unsigned reg
)
622 struct radeon_cs_reloc
*reloc
;
623 struct r100_cs_track
*track
;
624 volatile uint32_t *ib
;
625 uint32_t tmp
, tile_flags
= 0;
631 track
= (struct r100_cs_track
*)p
->track
;
632 idx_value
= radeon_get_ib_value(p
, idx
);
635 case AVIVO_D1MODE_VLINE_START_END
:
636 case RADEON_CRTC_GUI_TRIG_VLINE
:
637 r
= r100_cs_packet_parse_vline(p
);
639 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
641 r100_cs_dump_packet(p
, pkt
);
645 case RADEON_DST_PITCH_OFFSET
:
646 case RADEON_SRC_PITCH_OFFSET
:
647 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
651 case R300_RB3D_COLOROFFSET0
:
652 case R300_RB3D_COLOROFFSET1
:
653 case R300_RB3D_COLOROFFSET2
:
654 case R300_RB3D_COLOROFFSET3
:
655 i
= (reg
- R300_RB3D_COLOROFFSET0
) >> 2;
656 r
= r100_cs_packet_next_reloc(p
, &reloc
);
658 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
660 r100_cs_dump_packet(p
, pkt
);
663 track
->cb
[i
].robj
= reloc
->robj
;
664 track
->cb
[i
].offset
= idx_value
;
665 track
->cb_dirty
= true;
666 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
668 case R300_ZB_DEPTHOFFSET
:
669 r
= r100_cs_packet_next_reloc(p
, &reloc
);
671 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
673 r100_cs_dump_packet(p
, pkt
);
676 track
->zb
.robj
= reloc
->robj
;
677 track
->zb
.offset
= idx_value
;
678 track
->zb_dirty
= true;
679 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
681 case R300_TX_OFFSET_0
:
682 case R300_TX_OFFSET_0
+4:
683 case R300_TX_OFFSET_0
+8:
684 case R300_TX_OFFSET_0
+12:
685 case R300_TX_OFFSET_0
+16:
686 case R300_TX_OFFSET_0
+20:
687 case R300_TX_OFFSET_0
+24:
688 case R300_TX_OFFSET_0
+28:
689 case R300_TX_OFFSET_0
+32:
690 case R300_TX_OFFSET_0
+36:
691 case R300_TX_OFFSET_0
+40:
692 case R300_TX_OFFSET_0
+44:
693 case R300_TX_OFFSET_0
+48:
694 case R300_TX_OFFSET_0
+52:
695 case R300_TX_OFFSET_0
+56:
696 case R300_TX_OFFSET_0
+60:
697 i
= (reg
- R300_TX_OFFSET_0
) >> 2;
698 r
= r100_cs_packet_next_reloc(p
, &reloc
);
700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
702 r100_cs_dump_packet(p
, pkt
);
706 if (p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
) {
707 ib
[idx
] = (idx_value
& 31) | /* keep the 1st 5 bits */
708 ((idx_value
& ~31) + (u32
)reloc
->lobj
.gpu_offset
);
710 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
711 tile_flags
|= R300_TXO_MACRO_TILE
;
712 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
713 tile_flags
|= R300_TXO_MICRO_TILE
;
714 else if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
715 tile_flags
|= R300_TXO_MICRO_TILE_SQUARE
;
717 tmp
= idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
721 track
->textures
[i
].robj
= reloc
->robj
;
722 track
->tex_dirty
= true;
724 /* Tracked registers */
727 track
->vap_vf_cntl
= idx_value
;
731 track
->vtx_size
= idx_value
& 0x7F;
734 /* VAP_VF_MAX_VTX_INDX */
735 track
->max_indx
= idx_value
& 0x00FFFFFFUL
;
738 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
739 if (p
->rdev
->family
< CHIP_RV515
)
741 track
->vap_alt_nverts
= idx_value
& 0xFFFFFF;
745 track
->maxy
= ((idx_value
>> 13) & 0x1FFF) + 1;
746 if (p
->rdev
->family
< CHIP_RV515
) {
749 track
->cb_dirty
= true;
750 track
->zb_dirty
= true;
754 if ((idx_value
& (1 << 10)) && /* CMASK_ENABLE */
755 p
->rdev
->cmask_filp
!= p
->filp
) {
756 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
759 track
->num_cb
= ((idx_value
>> 5) & 0x3) + 1;
760 track
->cb_dirty
= true;
766 /* RB3D_COLORPITCH0 */
767 /* RB3D_COLORPITCH1 */
768 /* RB3D_COLORPITCH2 */
769 /* RB3D_COLORPITCH3 */
770 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
771 r
= r100_cs_packet_next_reloc(p
, &reloc
);
773 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
775 r100_cs_dump_packet(p
, pkt
);
779 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
780 tile_flags
|= R300_COLOR_TILE_ENABLE
;
781 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
782 tile_flags
|= R300_COLOR_MICROTILE_ENABLE
;
783 else if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
784 tile_flags
|= R300_COLOR_MICROTILE_SQUARE_ENABLE
;
786 tmp
= idx_value
& ~(0x7 << 16);
790 i
= (reg
- 0x4E38) >> 2;
791 track
->cb
[i
].pitch
= idx_value
& 0x3FFE;
792 switch (((idx_value
>> 21) & 0xF)) {
796 track
->cb
[i
].cpp
= 1;
802 track
->cb
[i
].cpp
= 2;
805 if (p
->rdev
->family
< CHIP_RV515
) {
806 DRM_ERROR("Invalid color buffer format (%d)!\n",
807 ((idx_value
>> 21) & 0xF));
812 track
->cb
[i
].cpp
= 4;
815 track
->cb
[i
].cpp
= 8;
818 track
->cb
[i
].cpp
= 16;
821 DRM_ERROR("Invalid color buffer format (%d) !\n",
822 ((idx_value
>> 21) & 0xF));
825 track
->cb_dirty
= true;
830 track
->z_enabled
= true;
832 track
->z_enabled
= false;
834 track
->zb_dirty
= true;
838 switch ((idx_value
& 0xF)) {
847 DRM_ERROR("Invalid z buffer format (%d) !\n",
851 track
->zb_dirty
= true;
855 if (!(p
->cs_flags
& RADEON_CS_KEEP_TILING_FLAGS
)) {
856 r
= r100_cs_packet_next_reloc(p
, &reloc
);
858 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
860 r100_cs_dump_packet(p
, pkt
);
864 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
865 tile_flags
|= R300_DEPTHMACROTILE_ENABLE
;
866 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
867 tile_flags
|= R300_DEPTHMICROTILE_TILED
;
868 else if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO_SQUARE
)
869 tile_flags
|= R300_DEPTHMICROTILE_TILED_SQUARE
;
871 tmp
= idx_value
& ~(0x7 << 16);
875 track
->zb
.pitch
= idx_value
& 0x3FFC;
876 track
->zb_dirty
= true;
880 for (i
= 0; i
< 16; i
++) {
883 enabled
= !!(idx_value
& (1 << i
));
884 track
->textures
[i
].enabled
= enabled
;
886 track
->tex_dirty
= true;
904 /* TX_FORMAT1_[0-15] */
905 i
= (reg
- 0x44C0) >> 2;
906 tmp
= (idx_value
>> 25) & 0x3;
907 track
->textures
[i
].tex_coord_type
= tmp
;
908 switch ((idx_value
& 0x1F)) {
909 case R300_TX_FORMAT_X8
:
910 case R300_TX_FORMAT_Y4X4
:
911 case R300_TX_FORMAT_Z3Y3X2
:
912 track
->textures
[i
].cpp
= 1;
913 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
915 case R300_TX_FORMAT_X16
:
916 case R300_TX_FORMAT_FL_I16
:
917 case R300_TX_FORMAT_Y8X8
:
918 case R300_TX_FORMAT_Z5Y6X5
:
919 case R300_TX_FORMAT_Z6Y5X5
:
920 case R300_TX_FORMAT_W4Z4Y4X4
:
921 case R300_TX_FORMAT_W1Z5Y5X5
:
922 case R300_TX_FORMAT_D3DMFT_CxV8U8
:
923 case R300_TX_FORMAT_B8G8_B8G8
:
924 case R300_TX_FORMAT_G8R8_G8B8
:
925 track
->textures
[i
].cpp
= 2;
926 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
928 case R300_TX_FORMAT_Y16X16
:
929 case R300_TX_FORMAT_FL_I16A16
:
930 case R300_TX_FORMAT_Z11Y11X10
:
931 case R300_TX_FORMAT_Z10Y11X11
:
932 case R300_TX_FORMAT_W8Z8Y8X8
:
933 case R300_TX_FORMAT_W2Z10Y10X10
:
935 case R300_TX_FORMAT_FL_I32
:
937 track
->textures
[i
].cpp
= 4;
938 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
940 case R300_TX_FORMAT_W16Z16Y16X16
:
941 case R300_TX_FORMAT_FL_R16G16B16A16
:
942 case R300_TX_FORMAT_FL_I32A32
:
943 track
->textures
[i
].cpp
= 8;
944 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
946 case R300_TX_FORMAT_FL_R32G32B32A32
:
947 track
->textures
[i
].cpp
= 16;
948 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
950 case R300_TX_FORMAT_DXT1
:
951 track
->textures
[i
].cpp
= 1;
952 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT1
;
954 case R300_TX_FORMAT_ATI2N
:
955 if (p
->rdev
->family
< CHIP_R420
) {
956 DRM_ERROR("Invalid texture format %u\n",
960 /* The same rules apply as for DXT3/5. */
962 case R300_TX_FORMAT_DXT3
:
963 case R300_TX_FORMAT_DXT5
:
964 track
->textures
[i
].cpp
= 1;
965 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT35
;
968 DRM_ERROR("Invalid texture format %u\n",
972 track
->tex_dirty
= true;
990 /* TX_FILTER0_[0-15] */
991 i
= (reg
- 0x4400) >> 2;
992 tmp
= idx_value
& 0x7;
993 if (tmp
== 2 || tmp
== 4 || tmp
== 6) {
994 track
->textures
[i
].roundup_w
= false;
996 tmp
= (idx_value
>> 3) & 0x7;
997 if (tmp
== 2 || tmp
== 4 || tmp
== 6) {
998 track
->textures
[i
].roundup_h
= false;
1000 track
->tex_dirty
= true;
1018 /* TX_FORMAT2_[0-15] */
1019 i
= (reg
- 0x4500) >> 2;
1020 tmp
= idx_value
& 0x3FFF;
1021 track
->textures
[i
].pitch
= tmp
+ 1;
1022 if (p
->rdev
->family
>= CHIP_RV515
) {
1023 tmp
= ((idx_value
>> 15) & 1) << 11;
1024 track
->textures
[i
].width_11
= tmp
;
1025 tmp
= ((idx_value
>> 16) & 1) << 11;
1026 track
->textures
[i
].height_11
= tmp
;
1029 if (idx_value
& (1 << 14)) {
1030 /* The same rules apply as for DXT1. */
1031 track
->textures
[i
].compress_format
=
1032 R100_TRACK_COMP_DXT1
;
1034 } else if (idx_value
& (1 << 14)) {
1035 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1038 track
->tex_dirty
= true;
1056 /* TX_FORMAT0_[0-15] */
1057 i
= (reg
- 0x4480) >> 2;
1058 tmp
= idx_value
& 0x7FF;
1059 track
->textures
[i
].width
= tmp
+ 1;
1060 tmp
= (idx_value
>> 11) & 0x7FF;
1061 track
->textures
[i
].height
= tmp
+ 1;
1062 tmp
= (idx_value
>> 26) & 0xF;
1063 track
->textures
[i
].num_levels
= tmp
;
1064 tmp
= idx_value
& (1 << 31);
1065 track
->textures
[i
].use_pitch
= !!tmp
;
1066 tmp
= (idx_value
>> 22) & 0xF;
1067 track
->textures
[i
].txdepth
= tmp
;
1068 track
->tex_dirty
= true;
1070 case R300_ZB_ZPASS_ADDR
:
1071 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1073 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1075 r100_cs_dump_packet(p
, pkt
);
1078 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1081 /* RB3D_COLOR_CHANNEL_MASK */
1082 track
->color_channel_mask
= idx_value
;
1083 track
->cb_dirty
= true;
1087 /* r300c emits this register - we need to disable hyperz for it
1088 * without complaining */
1089 if (p
->rdev
->hyperz_filp
!= p
->filp
) {
1090 if (idx_value
& 0x1)
1091 ib
[idx
] = idx_value
& ~1;
1096 track
->zb_cb_clear
= !!(idx_value
& (1 << 5));
1097 track
->cb_dirty
= true;
1098 track
->zb_dirty
= true;
1099 if (p
->rdev
->hyperz_filp
!= p
->filp
) {
1100 if (idx_value
& (R300_HIZ_ENABLE
|
1101 R300_RD_COMP_ENABLE
|
1102 R300_WR_COMP_ENABLE
|
1103 R300_FAST_FILL_ENABLE
))
1108 /* RB3D_BLENDCNTL */
1109 track
->blend_read_enable
= !!(idx_value
& (1 << 2));
1110 track
->cb_dirty
= true;
1112 case R300_RB3D_AARESOLVE_OFFSET
:
1113 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1115 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1117 r100_cs_dump_packet(p
, pkt
);
1120 track
->aa
.robj
= reloc
->robj
;
1121 track
->aa
.offset
= idx_value
;
1122 track
->aa_dirty
= true;
1123 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1125 case R300_RB3D_AARESOLVE_PITCH
:
1126 track
->aa
.pitch
= idx_value
& 0x3FFE;
1127 track
->aa_dirty
= true;
1129 case R300_RB3D_AARESOLVE_CTL
:
1130 track
->aaresolve
= idx_value
& 0x1;
1131 track
->aa_dirty
= true;
1133 case 0x4f30: /* ZB_MASK_OFFSET */
1134 case 0x4f34: /* ZB_ZMASK_PITCH */
1135 case 0x4f44: /* ZB_HIZ_OFFSET */
1136 case 0x4f54: /* ZB_HIZ_PITCH */
1137 if (idx_value
&& (p
->rdev
->hyperz_filp
!= p
->filp
))
1141 if (idx_value
&& (p
->rdev
->hyperz_filp
!= p
->filp
))
1143 /* GB_Z_PEQ_CONFIG */
1144 if (p
->rdev
->family
>= CHIP_RV350
)
1149 /* valid register only on RV530 */
1150 if (p
->rdev
->family
== CHIP_RV530
)
1152 /* fallthrough do not move */
1158 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1159 reg
, idx
, idx_value
);
1163 static int r300_packet3_check(struct radeon_cs_parser
*p
,
1164 struct radeon_cs_packet
*pkt
)
1166 struct radeon_cs_reloc
*reloc
;
1167 struct r100_cs_track
*track
;
1168 volatile uint32_t *ib
;
1174 track
= (struct r100_cs_track
*)p
->track
;
1175 switch(pkt
->opcode
) {
1176 case PACKET3_3D_LOAD_VBPNTR
:
1177 r
= r100_packet3_load_vbpntr(p
, pkt
, idx
);
1181 case PACKET3_INDX_BUFFER
:
1182 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1184 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1185 r100_cs_dump_packet(p
, pkt
);
1188 ib
[idx
+1] = radeon_get_ib_value(p
, idx
+ 1) + ((u32
)reloc
->lobj
.gpu_offset
);
1189 r
= r100_cs_track_check_pkt3_indx_buffer(p
, pkt
, reloc
->robj
);
1195 case PACKET3_3D_DRAW_IMMD
:
1196 /* Number of dwords is vtx_size * (num_vertices - 1)
1197 * PRIM_WALK must be equal to 3 vertex data in embedded
1199 if (((radeon_get_ib_value(p
, idx
+ 1) >> 4) & 0x3) != 3) {
1200 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1203 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1204 track
->immd_dwords
= pkt
->count
- 1;
1205 r
= r100_cs_track_check(p
->rdev
, track
);
1210 case PACKET3_3D_DRAW_IMMD_2
:
1211 /* Number of dwords is vtx_size * (num_vertices - 1)
1212 * PRIM_WALK must be equal to 3 vertex data in embedded
1214 if (((radeon_get_ib_value(p
, idx
) >> 4) & 0x3) != 3) {
1215 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1218 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1219 track
->immd_dwords
= pkt
->count
;
1220 r
= r100_cs_track_check(p
->rdev
, track
);
1225 case PACKET3_3D_DRAW_VBUF
:
1226 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1227 r
= r100_cs_track_check(p
->rdev
, track
);
1232 case PACKET3_3D_DRAW_VBUF_2
:
1233 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1234 r
= r100_cs_track_check(p
->rdev
, track
);
1239 case PACKET3_3D_DRAW_INDX
:
1240 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1241 r
= r100_cs_track_check(p
->rdev
, track
);
1246 case PACKET3_3D_DRAW_INDX_2
:
1247 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1248 r
= r100_cs_track_check(p
->rdev
, track
);
1253 case PACKET3_3D_CLEAR_HIZ
:
1254 case PACKET3_3D_CLEAR_ZMASK
:
1255 if (p
->rdev
->hyperz_filp
!= p
->filp
)
1258 case PACKET3_3D_CLEAR_CMASK
:
1259 if (p
->rdev
->cmask_filp
!= p
->filp
)
1265 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1271 int r300_cs_parse(struct radeon_cs_parser
*p
)
1273 struct radeon_cs_packet pkt
;
1274 struct r100_cs_track
*track
;
1277 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1280 r100_cs_track_clear(p
->rdev
, track
);
1283 r
= r100_cs_packet_parse(p
, &pkt
, p
->idx
);
1287 p
->idx
+= pkt
.count
+ 2;
1290 r
= r100_cs_parse_packet0(p
, &pkt
,
1291 p
->rdev
->config
.r300
.reg_safe_bm
,
1292 p
->rdev
->config
.r300
.reg_safe_bm_size
,
1293 &r300_packet0_check
);
1298 r
= r300_packet3_check(p
, &pkt
);
1301 DRM_ERROR("Unknown packet type %d !\n", pkt
.type
);
1307 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1311 void r300_set_reg_safe(struct radeon_device
*rdev
)
1313 rdev
->config
.r300
.reg_safe_bm
= r300_reg_safe_bm
;
1314 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(r300_reg_safe_bm
);
1317 void r300_mc_program(struct radeon_device
*rdev
)
1319 struct r100_mc_save save
;
1322 r
= r100_debugfs_mc_info_init(rdev
);
1324 dev_err(rdev
->dev
, "Failed to create r100_mc debugfs file.\n");
1327 /* Stops all mc clients */
1328 r100_mc_stop(rdev
, &save
);
1329 if (rdev
->flags
& RADEON_IS_AGP
) {
1330 WREG32(R_00014C_MC_AGP_LOCATION
,
1331 S_00014C_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
1332 S_00014C_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
1333 WREG32(R_000170_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
1334 WREG32(R_00015C_AGP_BASE_2
,
1335 upper_32_bits(rdev
->mc
.agp_base
) & 0xff);
1337 WREG32(R_00014C_MC_AGP_LOCATION
, 0x0FFFFFFF);
1338 WREG32(R_000170_AGP_BASE
, 0);
1339 WREG32(R_00015C_AGP_BASE_2
, 0);
1341 /* Wait for mc idle */
1342 if (r300_mc_wait_for_idle(rdev
))
1343 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1344 /* Program MC, should be a 32bits limited address space */
1345 WREG32(R_000148_MC_FB_LOCATION
,
1346 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
1347 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
1348 r100_mc_resume(rdev
, &save
);
1351 void r300_clock_startup(struct radeon_device
*rdev
)
1355 if (radeon_dynclks
!= -1 && radeon_dynclks
)
1356 radeon_legacy_set_clock_gating(rdev
, 1);
1357 /* We need to force on some of the block */
1358 tmp
= RREG32_PLL(R_00000D_SCLK_CNTL
);
1359 tmp
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1360 if ((rdev
->family
== CHIP_RV350
) || (rdev
->family
== CHIP_RV380
))
1361 tmp
|= S_00000D_FORCE_VAP(1);
1362 WREG32_PLL(R_00000D_SCLK_CNTL
, tmp
);
1365 static int r300_startup(struct radeon_device
*rdev
)
1369 /* set common regs */
1370 r100_set_common_regs(rdev
);
1372 r300_mc_program(rdev
);
1374 r300_clock_startup(rdev
);
1375 /* Initialize GPU configuration (# pipes, ...) */
1376 r300_gpu_init(rdev
);
1377 /* Initialize GART (initialize after TTM so we can allocate
1378 * memory through TTM but finalize after TTM) */
1379 if (rdev
->flags
& RADEON_IS_PCIE
) {
1380 r
= rv370_pcie_gart_enable(rdev
);
1385 if (rdev
->family
== CHIP_R300
||
1386 rdev
->family
== CHIP_R350
||
1387 rdev
->family
== CHIP_RV350
)
1388 r100_enable_bm(rdev
);
1390 if (rdev
->flags
& RADEON_IS_PCI
) {
1391 r
= r100_pci_gart_enable(rdev
);
1396 /* allocate wb buffer */
1397 r
= radeon_wb_init(rdev
);
1401 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
1403 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
1409 rdev
->config
.r300
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
1410 /* 1M ring buffer */
1411 r
= r100_cp_init(rdev
, 1024 * 1024);
1413 dev_err(rdev
->dev
, "failed initializing CP (%d).\n", r
);
1417 r
= radeon_ib_pool_start(rdev
);
1421 r
= radeon_ib_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
]);
1423 dev_err(rdev
->dev
, "failed testing IB (%d).\n", r
);
1424 rdev
->accel_working
= false;
1431 int r300_resume(struct radeon_device
*rdev
)
1433 /* Make sur GART are not working */
1434 if (rdev
->flags
& RADEON_IS_PCIE
)
1435 rv370_pcie_gart_disable(rdev
);
1436 if (rdev
->flags
& RADEON_IS_PCI
)
1437 r100_pci_gart_disable(rdev
);
1438 /* Resume clock before doing reset */
1439 r300_clock_startup(rdev
);
1440 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1441 if (radeon_asic_reset(rdev
)) {
1442 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1443 RREG32(R_000E40_RBBM_STATUS
),
1444 RREG32(R_0007C0_CP_STAT
));
1447 radeon_combios_asic_init(rdev
->ddev
);
1448 /* Resume clock after posting */
1449 r300_clock_startup(rdev
);
1450 /* Initialize surface registers */
1451 radeon_surface_init(rdev
);
1453 rdev
->accel_working
= true;
1454 return r300_startup(rdev
);
1457 int r300_suspend(struct radeon_device
*rdev
)
1459 radeon_ib_pool_suspend(rdev
);
1460 r100_cp_disable(rdev
);
1461 radeon_wb_disable(rdev
);
1462 r100_irq_disable(rdev
);
1463 if (rdev
->flags
& RADEON_IS_PCIE
)
1464 rv370_pcie_gart_disable(rdev
);
1465 if (rdev
->flags
& RADEON_IS_PCI
)
1466 r100_pci_gart_disable(rdev
);
1470 void r300_fini(struct radeon_device
*rdev
)
1473 radeon_wb_fini(rdev
);
1475 radeon_gem_fini(rdev
);
1476 if (rdev
->flags
& RADEON_IS_PCIE
)
1477 rv370_pcie_gart_fini(rdev
);
1478 if (rdev
->flags
& RADEON_IS_PCI
)
1479 r100_pci_gart_fini(rdev
);
1480 radeon_agp_fini(rdev
);
1481 radeon_irq_kms_fini(rdev
);
1482 radeon_fence_driver_fini(rdev
);
1483 radeon_bo_fini(rdev
);
1484 radeon_atombios_fini(rdev
);
1489 int r300_init(struct radeon_device
*rdev
)
1494 r100_vga_render_disable(rdev
);
1495 /* Initialize scratch registers */
1496 radeon_scratch_init(rdev
);
1497 /* Initialize surface registers */
1498 radeon_surface_init(rdev
);
1499 /* TODO: disable VGA need to use VGA request */
1500 /* restore some register to sane defaults */
1501 r100_restore_sanity(rdev
);
1503 if (!radeon_get_bios(rdev
)) {
1504 if (ASIC_IS_AVIVO(rdev
))
1507 if (rdev
->is_atom_bios
) {
1508 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
1511 r
= radeon_combios_init(rdev
);
1515 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1516 if (radeon_asic_reset(rdev
)) {
1518 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1519 RREG32(R_000E40_RBBM_STATUS
),
1520 RREG32(R_0007C0_CP_STAT
));
1522 /* check if cards are posted or not */
1523 if (radeon_boot_test_post_card(rdev
) == false)
1525 /* Set asic errata */
1527 /* Initialize clocks */
1528 radeon_get_clock_info(rdev
->ddev
);
1529 /* initialize AGP */
1530 if (rdev
->flags
& RADEON_IS_AGP
) {
1531 r
= radeon_agp_init(rdev
);
1533 radeon_agp_disable(rdev
);
1536 /* initialize memory controller */
1539 r
= radeon_fence_driver_init(rdev
);
1542 r
= radeon_irq_kms_init(rdev
);
1545 /* Memory manager */
1546 r
= radeon_bo_init(rdev
);
1549 if (rdev
->flags
& RADEON_IS_PCIE
) {
1550 r
= rv370_pcie_gart_init(rdev
);
1554 if (rdev
->flags
& RADEON_IS_PCI
) {
1555 r
= r100_pci_gart_init(rdev
);
1559 r300_set_reg_safe(rdev
);
1561 r
= radeon_ib_pool_init(rdev
);
1562 rdev
->accel_working
= true;
1564 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
1565 rdev
->accel_working
= false;
1568 r
= r300_startup(rdev
);
1570 /* Somethings want wront with the accel init stop accel */
1571 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
1573 radeon_wb_fini(rdev
);
1575 radeon_irq_kms_fini(rdev
);
1576 if (rdev
->flags
& RADEON_IS_PCIE
)
1577 rv370_pcie_gart_fini(rdev
);
1578 if (rdev
->flags
& RADEON_IS_PCI
)
1579 r100_pci_gart_fini(rdev
);
1580 radeon_agp_fini(rdev
);
1581 rdev
->accel_working
= false;