drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "radeon_reg.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "atom.h"
  35 #include "r100d.h"
  36 #include "r420d.h"
  37 #include "r420_reg_safe.h"
  38
  39 static void r420_set_reg_safe(struct radeon_device *rdev)
  40 {
  41         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  42         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
  43 }
  44
  45 void r420_pipes_init(struct radeon_device *rdev)
  46 {
  47         unsigned tmp;
  48         unsigned gb_pipe_select;
  49         unsigned num_pipes;
  50
  51         /* GA_ENHANCE workaround TCL deadlock issue */
  52         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  53                (1 << 2) | (1 << 3));
  54         /* add idle wait as per freedesktop.org bug 24041 */
  55         if (r100_gui_wait_for_idle(rdev)) {
  56                 printk(KERN_WARNING "Failed to wait GUI idle while "
  57                        "programming pipes. Bad things might happen.\n");
  58         }
  59         /* get max number of pipes */
  60         gb_pipe_select = RREG32(0x402C);
  61         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  62         rdev->num_gb_pipes = num_pipes;
  63         tmp = 0;
  64         switch (num_pipes) {
  65         default:
  66                 /* force to 1 pipe */
  67                 num_pipes = 1;
  68         case 1:
  69                 tmp = (0 << 1);
  70                 break;
  71         case 2:
  72                 tmp = (3 << 1);
  73                 break;
  74         case 3:
  75                 tmp = (6 << 1);
  76                 break;
  77         case 4:
  78                 tmp = (7 << 1);
  79                 break;
  80         }
  81         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
  82         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  83         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
  84         WREG32(R300_GB_TILE_CONFIG, tmp);
  85         if (r100_gui_wait_for_idle(rdev)) {
  86                 printk(KERN_WARNING "Failed to wait GUI idle while "
  87                        "programming pipes. Bad things might happen.\n");
  88         }
  89
  90         tmp = RREG32(R300_DST_PIPE_CONFIG);
  91         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
  92
  93         WREG32(R300_RB2D_DSTCACHE_MODE,
  94                RREG32(R300_RB2D_DSTCACHE_MODE) |
  95                R300_DC_AUTOFLUSH_ENABLE |
  96                R300_DC_DC_DISABLE_IGNORE_PE);
  97
  98         if (r100_gui_wait_for_idle(rdev)) {
  99                 printk(KERN_WARNING "Failed to wait GUI idle while "
 100                        "programming pipes. Bad things might happen.\n");
 101         }
 102
 103         if (rdev->family == CHIP_RV530) {
 104                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 105                 if ((tmp & 3) == 3)
 106                         rdev->num_z_pipes = 2;
 107                 else
 108                         rdev->num_z_pipes = 1;
 109         } else
 110                 rdev->num_z_pipes = 1;
 111
 112         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 113                  rdev->num_gb_pipes, rdev->num_z_pipes);
 114 }
 115
 116 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 117 {
 118         u32 r;
 119
 120         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 121         r = RREG32(R_0001FC_MC_IND_DATA);
 122         return r;
 123 }
 124
 125 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 126 {
 127         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 128                 S_0001F8_MC_IND_WR_EN(1));
 129         WREG32(R_0001FC_MC_IND_DATA, v);
 130 }
 131
 132 static void r420_debugfs(struct radeon_device *rdev)
 133 {
 134         if (r100_debugfs_rbbm_init(rdev)) {
 135                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 136         }
 137         if (r420_debugfs_pipes_info_init(rdev)) {
 138                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 139         }
 140 }
 141
 142 static void r420_clock_resume(struct radeon_device *rdev)
 143 {
 144         u32 sclk_cntl;
 145
 146         if (radeon_dynclks != -1 && radeon_dynclks)
 147                 radeon_atom_set_clock_gating(rdev, 1);
 148         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 149         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 150         if (rdev->family == CHIP_R420)
 151                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 152         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 153 }
 154
 155 static void r420_cp_errata_init(struct radeon_device *rdev)
 156 {
 157         /* RV410 and R420 can lock up if CP DMA to host memory happens
 158          * while the 2D engine is busy.
 159          *
 160          * The proper workaround is to queue a RESYNC at the beginning
 161          * of the CP init, apparently.
 162          */
 163         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 164         radeon_ring_lock(rdev, 8);
 165         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 166         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 167         radeon_ring_write(rdev, 0xDEADBEEF);
 168         radeon_ring_unlock_commit(rdev);
 169 }
 170
 171 static void r420_cp_errata_fini(struct radeon_device *rdev)
 172 {
 173         /* Catch the RESYNC we dispatched all the way back,
 174          * at the very beginning of the CP init.
 175          */
 176         radeon_ring_lock(rdev, 8);
 177         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 178         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 179         radeon_ring_unlock_commit(rdev);
 180         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 181 }
 182
 183 static int r420_startup(struct radeon_device *rdev)
 184 {
 185         int r;
 186
 187         /* set common regs */
 188         r100_set_common_regs(rdev);
 189         /* program mc */
 190         r300_mc_program(rdev);
 191         /* Resume clock */
 192         r420_clock_resume(rdev);
 193         /* Initialize GART (initialize after TTM so we can allocate
 194          * memory through TTM but finalize after TTM) */
 195         if (rdev->flags & RADEON_IS_PCIE) {
 196                 r = rv370_pcie_gart_enable(rdev);
 197                 if (r)
 198                         return r;
 199         }
 200         if (rdev->flags & RADEON_IS_PCI) {
 201                 r = r100_pci_gart_enable(rdev);
 202                 if (r)
 203                         return r;
 204         }
 205         r420_pipes_init(rdev);
 206         /* Enable IRQ */
 207         r100_irq_set(rdev);
 208         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 209         /* 1M ring buffer */
 210         r = r100_cp_init(rdev, 1024 * 1024);
 211         if (r) {
 212                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 213                 return r;
 214         }
 215         r420_cp_errata_init(rdev);
 216         r = r100_wb_init(rdev);
 217         if (r) {
 218                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 219         }
 220         r = r100_ib_init(rdev);
 221         if (r) {
 222                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 223                 return r;
 224         }
 225         return 0;
 226 }
 227
 228 int r420_resume(struct radeon_device *rdev)
 229 {
 230         /* Make sur GART are not working */
 231         if (rdev->flags & RADEON_IS_PCIE)
 232                 rv370_pcie_gart_disable(rdev);
 233         if (rdev->flags & RADEON_IS_PCI)
 234                 r100_pci_gart_disable(rdev);
 235         /* Resume clock before doing reset */
 236         r420_clock_resume(rdev);
 237         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 238         if (radeon_gpu_reset(rdev)) {
 239                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 240                         RREG32(R_000E40_RBBM_STATUS),
 241                         RREG32(R_0007C0_CP_STAT));
 242         }
 243         /* check if cards are posted or not */
 244         if (rdev->is_atom_bios) {
 245                 atom_asic_init(rdev->mode_info.atom_context);
 246         } else {
 247                 radeon_combios_asic_init(rdev->ddev);
 248         }
 249         /* Resume clock after posting */
 250         r420_clock_resume(rdev);
 251         /* Initialize surface registers */
 252         radeon_surface_init(rdev);
 253         return r420_startup(rdev);
 254 }
 255
 256 int r420_suspend(struct radeon_device *rdev)
 257 {
 258         r420_cp_errata_fini(rdev);
 259         r100_cp_disable(rdev);
 260         r100_wb_disable(rdev);
 261         r100_irq_disable(rdev);
 262         if (rdev->flags & RADEON_IS_PCIE)
 263                 rv370_pcie_gart_disable(rdev);
 264         if (rdev->flags & RADEON_IS_PCI)
 265                 r100_pci_gart_disable(rdev);
 266         return 0;
 267 }
 268
 269 void r420_fini(struct radeon_device *rdev)
 270 {
 271         radeon_pm_fini(rdev);
 272         r100_cp_fini(rdev);
 273         r100_wb_fini(rdev);
 274         r100_ib_fini(rdev);
 275         radeon_gem_fini(rdev);
 276         if (rdev->flags & RADEON_IS_PCIE)
 277                 rv370_pcie_gart_fini(rdev);
 278         if (rdev->flags & RADEON_IS_PCI)
 279                 r100_pci_gart_fini(rdev);
 280         radeon_agp_fini(rdev);
 281         radeon_irq_kms_fini(rdev);
 282         radeon_fence_driver_fini(rdev);
 283         radeon_bo_fini(rdev);
 284         if (rdev->is_atom_bios) {
 285                 radeon_atombios_fini(rdev);
 286         } else {
 287                 radeon_combios_fini(rdev);
 288         }
 289         kfree(rdev->bios);
 290         rdev->bios = NULL;
 291 }
 292
 293 int r420_init(struct radeon_device *rdev)
 294 {
 295         int r;
 296
 297         /* Initialize scratch registers */
 298         radeon_scratch_init(rdev);
 299         /* Initialize surface registers */
 300         radeon_surface_init(rdev);
 301         /* TODO: disable VGA need to use VGA request */
 302         /* BIOS*/
 303         if (!radeon_get_bios(rdev)) {
 304                 if (ASIC_IS_AVIVO(rdev))
 305                         return -EINVAL;
 306         }
 307         if (rdev->is_atom_bios) {
 308                 r = radeon_atombios_init(rdev);
 309                 if (r) {
 310                         return r;
 311                 }
 312         } else {
 313                 r = radeon_combios_init(rdev);
 314                 if (r) {
 315                         return r;
 316                 }
 317         }
 318         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 319         if (radeon_gpu_reset(rdev)) {
 320                 dev_warn(rdev->dev,
 321                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 322                         RREG32(R_000E40_RBBM_STATUS),
 323                         RREG32(R_0007C0_CP_STAT));
 324         }
 325         /* check if cards are posted or not */
 326         if (radeon_boot_test_post_card(rdev) == false)
 327                 return -EINVAL;
 328
 329         /* Initialize clocks */
 330         radeon_get_clock_info(rdev->ddev);
 331         /* Initialize power management */
 332         radeon_pm_init(rdev);
 333         /* initialize AGP */
 334         if (rdev->flags & RADEON_IS_AGP) {
 335                 r = radeon_agp_init(rdev);
 336                 if (r) {
 337                         radeon_agp_disable(rdev);
 338                 }
 339         }
 340         /* initialize memory controller */
 341         r300_mc_init(rdev);
 342         r420_debugfs(rdev);
 343         /* Fence driver */
 344         r = radeon_fence_driver_init(rdev);
 345         if (r) {
 346                 return r;
 347         }
 348         r = radeon_irq_kms_init(rdev);
 349         if (r) {
 350                 return r;
 351         }
 352         /* Memory manager */
 353         r = radeon_bo_init(rdev);
 354         if (r) {
 355                 return r;
 356         }
 357         if (rdev->family == CHIP_R420)
 358                 r100_enable_bm(rdev);
 359
 360         if (rdev->flags & RADEON_IS_PCIE) {
 361                 r = rv370_pcie_gart_init(rdev);
 362                 if (r)
 363                         return r;
 364         }
 365         if (rdev->flags & RADEON_IS_PCI) {
 366                 r = r100_pci_gart_init(rdev);
 367                 if (r)
 368                         return r;
 369         }
 370         r420_set_reg_safe(rdev);
 371         rdev->accel_working = true;
 372         r = r420_startup(rdev);
 373         if (r) {
 374                 /* Somethings want wront with the accel init stop accel */
 375                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 376                 r100_cp_fini(rdev);
 377                 r100_wb_fini(rdev);
 378                 r100_ib_fini(rdev);
 379                 radeon_irq_kms_fini(rdev);
 380                 if (rdev->flags & RADEON_IS_PCIE)
 381                         rv370_pcie_gart_fini(rdev);
 382                 if (rdev->flags & RADEON_IS_PCI)
 383                         r100_pci_gart_fini(rdev);
 384                 radeon_agp_fini(rdev);
 385                 rdev->accel_working = false;
 386         }
 387         return 0;
 388 }
 389
 390 /*
 391  * Debugfs info
 392  */
 393 #if defined(CONFIG_DEBUG_FS)
 394 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 395 {
 396         struct drm_info_node *node = (struct drm_info_node *) m->private;
 397         struct drm_device *dev = node->minor->dev;
 398         struct radeon_device *rdev = dev->dev_private;
 399         uint32_t tmp;
 400
 401         tmp = RREG32(R400_GB_PIPE_SELECT);
 402         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 403         tmp = RREG32(R300_GB_TILE_CONFIG);
 404         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 405         tmp = RREG32(R300_DST_PIPE_CONFIG);
 406         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 407         return 0;
 408 }
 409
 410 static struct drm_info_list r420_pipes_info_list[] = {
 411         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 412 };
 413 #endif
 414
 415 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 416 {
 417 #if defined(CONFIG_DEBUG_FS)
 418         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 419 #else
 420         return 0;
 421 #endif
 422 }