drivers/gpu/drm/radeon/r520.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "radeon_share.h"
  32
  33 /* r520,rv530,rv560,rv570,r580 depends on : */
  34 void r100_hdp_reset(struct radeon_device *rdev);
  35 int rv370_pcie_gart_enable(struct radeon_device *rdev);
  36 void rv370_pcie_gart_disable(struct radeon_device *rdev);
  37 void r420_pipes_init(struct radeon_device *rdev);
  38 void rs600_mc_disable_clients(struct radeon_device *rdev);
  39 void rs600_disable_vga(struct radeon_device *rdev);
  40 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  41 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  42
  43 /* This files gather functions specifics to:
  44  * r520,rv530,rv560,rv570,r580
  45  *
  46  * Some of these functions might be used by newer ASICs.
  47  */
  48 void r520_gpu_init(struct radeon_device *rdev);
  49 int r520_mc_wait_for_idle(struct radeon_device *rdev);
  50
  51
  52 /*
  53  * MC
  54  */
  55 int r520_mc_init(struct radeon_device *rdev)
  56 {
  57         uint32_t tmp;
  58         int r;
  59
  60         if (r100_debugfs_rbbm_init(rdev)) {
  61                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  62         }
  63         if (rv515_debugfs_pipes_info_init(rdev)) {
  64                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  65         }
  66         if (rv515_debugfs_ga_info_init(rdev)) {
  67                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  68         }
  69
  70         r520_gpu_init(rdev);
  71         rv370_pcie_gart_disable(rdev);
  72
  73         /* Setup GPU memory space */
  74         rdev->mc.vram_location = 0xFFFFFFFFUL;
  75         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  76         if (rdev->flags & RADEON_IS_AGP) {
  77                 r = radeon_agp_init(rdev);
  78                 if (r) {
  79                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  80                         rdev->flags &= ~RADEON_IS_AGP;
  81                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  82                 } else {
  83                         rdev->mc.gtt_location = rdev->mc.agp_base;
  84                 }
  85         }
  86         r = radeon_mc_setup(rdev);
  87         if (r) {
  88                 return r;
  89         }
  90
  91         /* Program GPU memory space */
  92         rs600_mc_disable_clients(rdev);
  93         if (r520_mc_wait_for_idle(rdev)) {
  94                 printk(KERN_WARNING "Failed to wait MC idle while "
  95                        "programming pipes. Bad things might happen.\n");
  96         }
  97         /* Write VRAM size in case we are limiting it */
  98         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  99         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 100         tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
 101         tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
 102         WREG32_MC(R520_MC_FB_LOCATION, tmp);
 103         WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 104         WREG32(0x310, rdev->mc.vram_location);
 105         if (rdev->flags & RADEON_IS_AGP) {
 106                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 107                 tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16);
 108                 tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16);
 109                 WREG32_MC(R520_MC_AGP_LOCATION, tmp);
 110                 WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base);
 111                 WREG32_MC(R520_MC_AGP_BASE_2, 0);
 112         } else {
 113                 WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
 114                 WREG32_MC(R520_MC_AGP_BASE, 0);
 115                 WREG32_MC(R520_MC_AGP_BASE_2, 0);
 116         }
 117         return 0;
 118 }
 119
 120 void r520_mc_fini(struct radeon_device *rdev)
 121 {
 122         rv370_pcie_gart_disable(rdev);
 123         radeon_gart_table_vram_free(rdev);
 124         radeon_gart_fini(rdev);
 125 }
 126
 127
 128 /*
 129  * Global GPU functions
 130  */
 131 void r520_errata(struct radeon_device *rdev)
 132 {
 133         rdev->pll_errata = 0;
 134 }
 135
 136 int r520_mc_wait_for_idle(struct radeon_device *rdev)
 137 {
 138         unsigned i;
 139         uint32_t tmp;
 140
 141         for (i = 0; i < rdev->usec_timeout; i++) {
 142                 /* read MC_STATUS */
 143                 tmp = RREG32_MC(R520_MC_STATUS);
 144                 if (tmp & R520_MC_STATUS_IDLE) {
 145                         return 0;
 146                 }
 147                 DRM_UDELAY(1);
 148         }
 149         return -1;
 150 }
 151
 152 void r520_gpu_init(struct radeon_device *rdev)
 153 {
 154         unsigned pipe_select_current, gb_pipe_select, tmp;
 155
 156         r100_hdp_reset(rdev);
 157         rs600_disable_vga(rdev);
 158         /*
 159          * DST_PIPE_CONFIG              0x170C
 160          * GB_TILE_CONFIG               0x4018
 161          * GB_FIFO_SIZE                 0x4024
 162          * GB_PIPE_SELECT               0x402C
 163          * GB_PIPE_SELECT2              0x4124
 164          *      Z_PIPE_SHIFT                    0
 165          *      Z_PIPE_MASK                     0x000000003
 166          * GB_FIFO_SIZE2                0x4128
 167          *      SC_SFIFO_SIZE_SHIFT             0
 168          *      SC_SFIFO_SIZE_MASK              0x000000003
 169          *      SC_MFIFO_SIZE_SHIFT             2
 170          *      SC_MFIFO_SIZE_MASK              0x00000000C
 171          *      FG_SFIFO_SIZE_SHIFT             4
 172          *      FG_SFIFO_SIZE_MASK              0x000000030
 173          *      ZB_MFIFO_SIZE_SHIFT             6
 174          *      ZB_MFIFO_SIZE_MASK              0x0000000C0
 175          * GA_ENHANCE                   0x4274
 176          * SU_REG_DEST                  0x42C8
 177          */
 178         /* workaround for RV530 */
 179         if (rdev->family == CHIP_RV530) {
 180                 WREG32(0x4128, 0xFF);
 181         }
 182         r420_pipes_init(rdev);
 183         gb_pipe_select = RREG32(0x402C);
 184         tmp = RREG32(0x170C);
 185         pipe_select_current = (tmp >> 2) & 3;
 186         tmp = (1 << pipe_select_current) |
 187               (((gb_pipe_select >> 8) & 0xF) << 4);
 188         WREG32_PLL(0x000D, tmp);
 189         if (r520_mc_wait_for_idle(rdev)) {
 190                 printk(KERN_WARNING "Failed to wait MC idle while "
 191                        "programming pipes. Bad things might happen.\n");
 192         }
 193 }
 194
 195
 196 /*
 197  * VRAM info
 198  */
 199 static void r520_vram_get_type(struct radeon_device *rdev)
 200 {
 201         uint32_t tmp;
 202
 203         rdev->mc.vram_width = 128;
 204         rdev->mc.vram_is_ddr = true;
 205         tmp = RREG32_MC(R520_MC_CNTL0);
 206         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
 207         case 0:
 208                 rdev->mc.vram_width = 32;
 209                 break;
 210         case 1:
 211                 rdev->mc.vram_width = 64;
 212                 break;
 213         case 2:
 214                 rdev->mc.vram_width = 128;
 215                 break;
 216         case 3:
 217                 rdev->mc.vram_width = 256;
 218                 break;
 219         default:
 220                 rdev->mc.vram_width = 128;
 221                 break;
 222         }
 223         if (tmp & R520_MC_CHANNEL_SIZE)
 224                 rdev->mc.vram_width *= 2;
 225 }
 226
 227 void r520_vram_info(struct radeon_device *rdev)
 228 {
 229         fixed20_12 a;
 230
 231         r520_vram_get_type(rdev);
 232
 233         r100_vram_init_sizes(rdev);
 234         /* FIXME: we should enforce default clock in case GPU is not in
 235          * default setup
 236          */
 237         a.full = rfixed_const(100);
 238         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 239         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 240 }
 241
 242 void r520_bandwidth_update(struct radeon_device *rdev)
 243 {
 244         rv515_bandwidth_avivo_update(rdev);
 245 }