2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include <linux/module.h>
34 #include "radeon_drm.h"
36 #include "radeon_asic.h"
37 #include "radeon_mode.h"
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define RLC_UCODE_SIZE 768
45 #define R700_PFP_UCODE_SIZE 848
46 #define R700_PM4_UCODE_SIZE 1360
47 #define R700_RLC_UCODE_SIZE 1024
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define CAYMAN_RLC_UCODE_SIZE 1024
52 #define ARUBA_RLC_UCODE_SIZE 1536
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
97 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
);
99 /* r600,rv610,rv630,rv620,rv635,rv670 */
100 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
101 void r600_gpu_init(struct radeon_device
*rdev
);
102 void r600_fini(struct radeon_device
*rdev
);
103 void r600_irq_disable(struct radeon_device
*rdev
);
104 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
);
106 /* get temperature in millidegrees */
107 int rv6xx_get_temp(struct radeon_device
*rdev
)
109 u32 temp
= (RREG32(CG_THERMAL_STATUS
) & ASIC_T_MASK
) >>
111 int actual_temp
= temp
& 0xff;
116 return actual_temp
* 1000;
119 void r600_pm_get_dynpm_state(struct radeon_device
*rdev
)
123 rdev
->pm
.dynpm_can_upclock
= true;
124 rdev
->pm
.dynpm_can_downclock
= true;
126 /* power state array is low to high, default is first */
127 if ((rdev
->flags
& RADEON_IS_IGP
) || (rdev
->family
== CHIP_R600
)) {
128 int min_power_state_index
= 0;
130 if (rdev
->pm
.num_power_states
> 2)
131 min_power_state_index
= 1;
133 switch (rdev
->pm
.dynpm_planned_action
) {
134 case DYNPM_ACTION_MINIMUM
:
135 rdev
->pm
.requested_power_state_index
= min_power_state_index
;
136 rdev
->pm
.requested_clock_mode_index
= 0;
137 rdev
->pm
.dynpm_can_downclock
= false;
139 case DYNPM_ACTION_DOWNCLOCK
:
140 if (rdev
->pm
.current_power_state_index
== min_power_state_index
) {
141 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
142 rdev
->pm
.dynpm_can_downclock
= false;
144 if (rdev
->pm
.active_crtc_count
> 1) {
145 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
146 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
148 else if (i
>= rdev
->pm
.current_power_state_index
) {
149 rdev
->pm
.requested_power_state_index
=
150 rdev
->pm
.current_power_state_index
;
153 rdev
->pm
.requested_power_state_index
= i
;
158 if (rdev
->pm
.current_power_state_index
== 0)
159 rdev
->pm
.requested_power_state_index
=
160 rdev
->pm
.num_power_states
- 1;
162 rdev
->pm
.requested_power_state_index
=
163 rdev
->pm
.current_power_state_index
- 1;
166 rdev
->pm
.requested_clock_mode_index
= 0;
167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev
->pm
.active_crtc_count
> 0) &&
169 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
170 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
171 RADEON_PM_MODE_NO_DISPLAY
)) {
172 rdev
->pm
.requested_power_state_index
++;
175 case DYNPM_ACTION_UPCLOCK
:
176 if (rdev
->pm
.current_power_state_index
== (rdev
->pm
.num_power_states
- 1)) {
177 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
178 rdev
->pm
.dynpm_can_upclock
= false;
180 if (rdev
->pm
.active_crtc_count
> 1) {
181 for (i
= (rdev
->pm
.num_power_states
- 1); i
>= 0; i
--) {
182 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
184 else if (i
<= rdev
->pm
.current_power_state_index
) {
185 rdev
->pm
.requested_power_state_index
=
186 rdev
->pm
.current_power_state_index
;
189 rdev
->pm
.requested_power_state_index
= i
;
194 rdev
->pm
.requested_power_state_index
=
195 rdev
->pm
.current_power_state_index
+ 1;
197 rdev
->pm
.requested_clock_mode_index
= 0;
199 case DYNPM_ACTION_DEFAULT
:
200 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
201 rdev
->pm
.requested_clock_mode_index
= 0;
202 rdev
->pm
.dynpm_can_upclock
= false;
204 case DYNPM_ACTION_NONE
:
206 DRM_ERROR("Requested mode for not defined action\n");
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev
->pm
.active_crtc_count
> 1) {
214 rdev
->pm
.requested_power_state_index
= -1;
215 /* start at 1 as we don't want the default mode */
216 for (i
= 1; i
< rdev
->pm
.num_power_states
; i
++) {
217 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
219 else if ((rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_PERFORMANCE
) ||
220 (rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_BATTERY
)) {
221 rdev
->pm
.requested_power_state_index
= i
;
225 /* if nothing selected, grab the default state. */
226 if (rdev
->pm
.requested_power_state_index
== -1)
227 rdev
->pm
.requested_power_state_index
= 0;
229 rdev
->pm
.requested_power_state_index
= 1;
231 switch (rdev
->pm
.dynpm_planned_action
) {
232 case DYNPM_ACTION_MINIMUM
:
233 rdev
->pm
.requested_clock_mode_index
= 0;
234 rdev
->pm
.dynpm_can_downclock
= false;
236 case DYNPM_ACTION_DOWNCLOCK
:
237 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
238 if (rdev
->pm
.current_clock_mode_index
== 0) {
239 rdev
->pm
.requested_clock_mode_index
= 0;
240 rdev
->pm
.dynpm_can_downclock
= false;
242 rdev
->pm
.requested_clock_mode_index
=
243 rdev
->pm
.current_clock_mode_index
- 1;
245 rdev
->pm
.requested_clock_mode_index
= 0;
246 rdev
->pm
.dynpm_can_downclock
= false;
248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev
->pm
.active_crtc_count
> 0) &&
250 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
251 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
252 RADEON_PM_MODE_NO_DISPLAY
)) {
253 rdev
->pm
.requested_clock_mode_index
++;
256 case DYNPM_ACTION_UPCLOCK
:
257 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
258 if (rdev
->pm
.current_clock_mode_index
==
259 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1)) {
260 rdev
->pm
.requested_clock_mode_index
= rdev
->pm
.current_clock_mode_index
;
261 rdev
->pm
.dynpm_can_upclock
= false;
263 rdev
->pm
.requested_clock_mode_index
=
264 rdev
->pm
.current_clock_mode_index
+ 1;
266 rdev
->pm
.requested_clock_mode_index
=
267 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1;
268 rdev
->pm
.dynpm_can_upclock
= false;
271 case DYNPM_ACTION_DEFAULT
:
272 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
273 rdev
->pm
.requested_clock_mode_index
= 0;
274 rdev
->pm
.dynpm_can_upclock
= false;
276 case DYNPM_ACTION_NONE
:
278 DRM_ERROR("Requested mode for not defined action\n");
283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
284 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
285 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
,
286 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
287 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
,
288 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
292 void rs780_pm_init_profile(struct radeon_device
*rdev
)
294 if (rdev
->pm
.num_power_states
== 2) {
296 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
297 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
298 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
299 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
301 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 0;
302 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 0;
303 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
304 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
306 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 0;
307 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 0;
308 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
309 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
311 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 0;
312 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
313 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
314 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
316 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 0;
317 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
318 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
319 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
321 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 0;
322 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
323 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
324 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
326 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 0;
327 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 1;
328 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
329 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
330 } else if (rdev
->pm
.num_power_states
== 3) {
332 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
333 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
334 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
335 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
337 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
338 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
339 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
340 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
342 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
343 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
344 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
345 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
347 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
348 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 2;
349 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
350 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
352 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 1;
353 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 1;
354 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
355 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
357 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 1;
358 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 1;
359 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
360 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
362 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 1;
363 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
364 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
365 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
368 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
369 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
370 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
371 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
373 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 2;
374 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 2;
375 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
376 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
378 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 2;
379 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 2;
380 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
381 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
383 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 2;
384 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 3;
385 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
386 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
388 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
389 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
390 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
391 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
393 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
394 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
395 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
396 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
398 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
399 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 3;
400 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
401 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
405 void r600_pm_init_profile(struct radeon_device
*rdev
)
409 if (rdev
->family
== CHIP_R600
) {
412 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
413 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
414 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
415 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
417 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
418 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
419 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
420 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
422 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
423 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
424 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
425 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
427 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
428 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
429 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
430 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
432 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
433 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
434 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
435 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
437 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
438 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
439 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
440 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
442 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
443 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
444 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
445 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
447 if (rdev
->pm
.num_power_states
< 4) {
449 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
450 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
451 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
452 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
454 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
455 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
456 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
457 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
459 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
460 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
461 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
462 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
464 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
465 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
466 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
467 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
469 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
470 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 2;
471 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
472 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
474 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
475 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 2;
476 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
477 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
479 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
480 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
481 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
482 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
485 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
486 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
487 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
488 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
490 if (rdev
->flags
& RADEON_IS_MOBILITY
)
491 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
493 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
494 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= idx
;
495 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= idx
;
496 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
497 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
499 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= idx
;
500 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= idx
;
501 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
502 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
504 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
505 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= idx
;
506 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= idx
;
507 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
508 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
510 if (rdev
->flags
& RADEON_IS_MOBILITY
)
511 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
513 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
514 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= idx
;
515 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= idx
;
516 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
517 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
519 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= idx
;
520 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= idx
;
521 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
522 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
524 idx
= radeon_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
525 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= idx
;
526 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= idx
;
527 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
528 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
533 void r600_pm_misc(struct radeon_device
*rdev
)
535 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
536 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
537 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
538 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
540 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage
->voltage
== 0xff01)
544 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
545 radeon_atom_set_voltage(rdev
, voltage
->voltage
, SET_VOLTAGE_TYPE_ASIC_VDDC
);
546 rdev
->pm
.current_vddc
= voltage
->voltage
;
547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage
->voltage
);
552 bool r600_gui_idle(struct radeon_device
*rdev
)
554 if (RREG32(GRBM_STATUS
) & GUI_ACTIVE
)
560 /* hpd for digital panel detect/disconnect */
561 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
563 bool connected
= false;
565 if (ASIC_IS_DCE3(rdev
)) {
568 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
572 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
576 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
580 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
585 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
589 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
616 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
617 enum radeon_hpd_id hpd
)
620 bool connected
= r600_hpd_sense(rdev
, hpd
);
622 if (ASIC_IS_DCE3(rdev
)) {
625 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
627 tmp
&= ~DC_HPDx_INT_POLARITY
;
629 tmp
|= DC_HPDx_INT_POLARITY
;
630 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
633 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
635 tmp
&= ~DC_HPDx_INT_POLARITY
;
637 tmp
|= DC_HPDx_INT_POLARITY
;
638 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
641 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
643 tmp
&= ~DC_HPDx_INT_POLARITY
;
645 tmp
|= DC_HPDx_INT_POLARITY
;
646 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
649 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
651 tmp
&= ~DC_HPDx_INT_POLARITY
;
653 tmp
|= DC_HPDx_INT_POLARITY
;
654 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
657 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
659 tmp
&= ~DC_HPDx_INT_POLARITY
;
661 tmp
|= DC_HPDx_INT_POLARITY
;
662 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
666 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
668 tmp
&= ~DC_HPDx_INT_POLARITY
;
670 tmp
|= DC_HPDx_INT_POLARITY
;
671 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
679 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
681 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
683 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
687 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
689 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
691 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
695 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
697 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
699 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
708 void r600_hpd_init(struct radeon_device
*rdev
)
710 struct drm_device
*dev
= rdev
->ddev
;
711 struct drm_connector
*connector
;
714 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
715 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
717 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
718 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
719 /* don't try to enable hpd on eDP or LVDS avoid breaking the
720 * aux dp channel on imac and help (but not completely fix)
721 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
725 if (ASIC_IS_DCE3(rdev
)) {
726 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
727 if (ASIC_IS_DCE32(rdev
))
730 switch (radeon_connector
->hpd
.hpd
) {
732 WREG32(DC_HPD1_CONTROL
, tmp
);
735 WREG32(DC_HPD2_CONTROL
, tmp
);
738 WREG32(DC_HPD3_CONTROL
, tmp
);
741 WREG32(DC_HPD4_CONTROL
, tmp
);
745 WREG32(DC_HPD5_CONTROL
, tmp
);
748 WREG32(DC_HPD6_CONTROL
, tmp
);
754 switch (radeon_connector
->hpd
.hpd
) {
756 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
759 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
762 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
768 enable
|= 1 << radeon_connector
->hpd
.hpd
;
769 radeon_hpd_set_polarity(rdev
, radeon_connector
->hpd
.hpd
);
771 radeon_irq_kms_enable_hpd(rdev
, enable
);
774 void r600_hpd_fini(struct radeon_device
*rdev
)
776 struct drm_device
*dev
= rdev
->ddev
;
777 struct drm_connector
*connector
;
778 unsigned disable
= 0;
780 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
781 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
782 if (ASIC_IS_DCE3(rdev
)) {
783 switch (radeon_connector
->hpd
.hpd
) {
785 WREG32(DC_HPD1_CONTROL
, 0);
788 WREG32(DC_HPD2_CONTROL
, 0);
791 WREG32(DC_HPD3_CONTROL
, 0);
794 WREG32(DC_HPD4_CONTROL
, 0);
798 WREG32(DC_HPD5_CONTROL
, 0);
801 WREG32(DC_HPD6_CONTROL
, 0);
807 switch (radeon_connector
->hpd
.hpd
) {
809 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, 0);
812 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, 0);
815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, 0);
821 disable
|= 1 << radeon_connector
->hpd
.hpd
;
823 radeon_irq_kms_disable_hpd(rdev
, disable
);
829 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
834 /* flush hdp cache so updates hit vram */
835 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
836 !(rdev
->flags
& RADEON_IS_AGP
)) {
837 void __iomem
*ptr
= (void *)rdev
->gart
.ptr
;
840 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
841 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
842 * This seems to cause problems on some AGP cards. Just use the old
845 WREG32(HDP_DEBUG1
, 0);
846 tmp
= readl((void __iomem
*)ptr
);
848 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
850 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR
, rdev
->mc
.gtt_start
>> 12);
851 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (rdev
->mc
.gtt_end
- 1) >> 12);
852 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
853 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
855 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
856 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
858 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
868 int r600_pcie_gart_init(struct radeon_device
*rdev
)
872 if (rdev
->gart
.robj
) {
873 WARN(1, "R600 PCIE GART already initialized\n");
876 /* Initialize common gart structure */
877 r
= radeon_gart_init(rdev
);
880 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
881 return radeon_gart_table_vram_alloc(rdev
);
884 int r600_pcie_gart_enable(struct radeon_device
*rdev
)
889 if (rdev
->gart
.robj
== NULL
) {
890 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
893 r
= radeon_gart_table_vram_pin(rdev
);
896 radeon_gart_restore(rdev
);
899 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
900 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
901 EFFECTIVE_L2_QUEUE_SIZE(7));
902 WREG32(VM_L2_CNTL2
, 0);
903 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
904 /* Setup TLB control */
905 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
906 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
907 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
908 ENABLE_WAIT_L2_QUERY
;
909 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
910 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
911 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
912 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
913 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
914 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
915 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
916 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
917 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
918 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
919 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
920 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
921 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
922 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
923 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
924 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
925 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
926 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
927 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
928 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
929 (u32
)(rdev
->dummy_page
.addr
>> 12));
930 for (i
= 1; i
< 7; i
++)
931 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
933 r600_pcie_gart_tlb_flush(rdev
);
934 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
935 (unsigned)(rdev
->mc
.gtt_size
>> 20),
936 (unsigned long long)rdev
->gart
.table_addr
);
937 rdev
->gart
.ready
= true;
941 void r600_pcie_gart_disable(struct radeon_device
*rdev
)
946 /* Disable all tables */
947 for (i
= 0; i
< 7; i
++)
948 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
950 /* Disable L2 cache */
951 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
952 EFFECTIVE_L2_QUEUE_SIZE(7));
953 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup L1 TLB control */
955 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
956 ENABLE_WAIT_L2_QUERY
;
957 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
958 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
959 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
960 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
961 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
962 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
963 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
964 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
965 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
);
966 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
);
967 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
968 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
969 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
);
970 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
971 radeon_gart_table_vram_unpin(rdev
);
974 void r600_pcie_gart_fini(struct radeon_device
*rdev
)
976 radeon_gart_fini(rdev
);
977 r600_pcie_gart_disable(rdev
);
978 radeon_gart_table_vram_free(rdev
);
981 void r600_agp_enable(struct radeon_device
*rdev
)
987 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
988 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
989 EFFECTIVE_L2_QUEUE_SIZE(7));
990 WREG32(VM_L2_CNTL2
, 0);
991 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
992 /* Setup TLB control */
993 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
994 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
996 ENABLE_WAIT_L2_QUERY
;
997 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
998 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
999 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
1000 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
1001 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
1002 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
1003 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
1004 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
1005 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
1009 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1010 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1011 for (i
= 0; i
< 7; i
++)
1012 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
1015 int r600_mc_wait_for_idle(struct radeon_device
*rdev
)
1020 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1021 /* read MC_STATUS */
1022 tmp
= RREG32(R_000E50_SRBM_STATUS
) & 0x3F00;
1030 static void r600_mc_program(struct radeon_device
*rdev
)
1032 struct rv515_mc_save save
;
1036 /* Initialize HDP */
1037 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1038 WREG32((0x2c14 + j
), 0x00000000);
1039 WREG32((0x2c18 + j
), 0x00000000);
1040 WREG32((0x2c1c + j
), 0x00000000);
1041 WREG32((0x2c20 + j
), 0x00000000);
1042 WREG32((0x2c24 + j
), 0x00000000);
1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1046 rv515_mc_stop(rdev
, &save
);
1047 if (r600_mc_wait_for_idle(rdev
)) {
1048 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1050 /* Lockout access through VGA aperture (doesn't exist before R600) */
1051 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1052 /* Update configuration */
1053 if (rdev
->flags
& RADEON_IS_AGP
) {
1054 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1055 /* VRAM before AGP */
1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1057 rdev
->mc
.vram_start
>> 12);
1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1059 rdev
->mc
.gtt_end
>> 12);
1061 /* VRAM after AGP */
1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1063 rdev
->mc
.gtt_start
>> 12);
1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1065 rdev
->mc
.vram_end
>> 12);
1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
>> 12);
1069 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
>> 12);
1071 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, rdev
->vram_scratch
.gpu_addr
>> 12);
1072 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1073 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1074 WREG32(MC_VM_FB_LOCATION
, tmp
);
1075 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1076 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
1077 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1078 if (rdev
->flags
& RADEON_IS_AGP
) {
1079 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 22);
1080 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 22);
1081 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1083 WREG32(MC_VM_AGP_BASE
, 0);
1084 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1085 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1087 if (r600_mc_wait_for_idle(rdev
)) {
1088 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1090 rv515_mc_resume(rdev
, &save
);
1091 /* we need to own VRAM, so turn off the VGA renderer here
1092 * to stop it overwriting our objects */
1093 rv515_vga_render_disable(rdev
);
1097 * r600_vram_gtt_location - try to find VRAM & GTT location
1098 * @rdev: radeon device structure holding all necessary informations
1099 * @mc: memory controller structure holding memory informations
1101 * Function will place try to place VRAM at same place as in CPU (PCI)
1102 * address space as some GPU seems to have issue when we reprogram at
1103 * different address space.
1105 * If there is not enough space to fit the unvisible VRAM after the
1106 * aperture then we limit the VRAM size to the aperture.
1108 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109 * them to be in one from GPU point of view so that we can program GPU to
1110 * catch access outside them (weird GPU policy see ??).
1112 * This function will never fails, worst case are limiting VRAM or GTT.
1114 * Note: GTT start, end, size should be initialized before calling this
1115 * function on AGP platform.
1117 static void r600_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
1119 u64 size_bf
, size_af
;
1121 if (mc
->mc_vram_size
> 0xE0000000) {
1122 /* leave room for at least 512M GTT */
1123 dev_warn(rdev
->dev
, "limiting VRAM\n");
1124 mc
->real_vram_size
= 0xE0000000;
1125 mc
->mc_vram_size
= 0xE0000000;
1127 if (rdev
->flags
& RADEON_IS_AGP
) {
1128 size_bf
= mc
->gtt_start
;
1129 size_af
= 0xFFFFFFFF - mc
->gtt_end
;
1130 if (size_bf
> size_af
) {
1131 if (mc
->mc_vram_size
> size_bf
) {
1132 dev_warn(rdev
->dev
, "limiting VRAM\n");
1133 mc
->real_vram_size
= size_bf
;
1134 mc
->mc_vram_size
= size_bf
;
1136 mc
->vram_start
= mc
->gtt_start
- mc
->mc_vram_size
;
1138 if (mc
->mc_vram_size
> size_af
) {
1139 dev_warn(rdev
->dev
, "limiting VRAM\n");
1140 mc
->real_vram_size
= size_af
;
1141 mc
->mc_vram_size
= size_af
;
1143 mc
->vram_start
= mc
->gtt_end
+ 1;
1145 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
1146 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147 mc
->mc_vram_size
>> 20, mc
->vram_start
,
1148 mc
->vram_end
, mc
->real_vram_size
>> 20);
1151 if (rdev
->flags
& RADEON_IS_IGP
) {
1152 base
= RREG32(MC_VM_FB_LOCATION
) & 0xFFFF;
1155 radeon_vram_location(rdev
, &rdev
->mc
, base
);
1156 rdev
->mc
.gtt_base_align
= 0;
1157 radeon_gtt_location(rdev
, mc
);
1161 int r600_mc_init(struct radeon_device
*rdev
)
1164 int chansize
, numchan
;
1166 /* Get VRAM informations */
1167 rdev
->mc
.vram_is_ddr
= true;
1168 tmp
= RREG32(RAMCFG
);
1169 if (tmp
& CHANSIZE_OVERRIDE
) {
1171 } else if (tmp
& CHANSIZE_MASK
) {
1176 tmp
= RREG32(CHMAP
);
1177 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1192 rdev
->mc
.vram_width
= numchan
* chansize
;
1193 /* Could aper size report 0 ? */
1194 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
1195 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
1196 /* Setup GPU memory space */
1197 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
1198 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
1199 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1200 r600_vram_gtt_location(rdev
, &rdev
->mc
);
1202 if (rdev
->flags
& RADEON_IS_IGP
) {
1203 rs690_pm_info(rdev
);
1204 rdev
->mc
.igp_sideport_enabled
= radeon_atombios_sideport_present(rdev
);
1206 radeon_update_bandwidth_info(rdev
);
1210 int r600_vram_scratch_init(struct radeon_device
*rdev
)
1214 if (rdev
->vram_scratch
.robj
== NULL
) {
1215 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
,
1216 PAGE_SIZE
, true, RADEON_GEM_DOMAIN_VRAM
,
1217 NULL
, &rdev
->vram_scratch
.robj
);
1223 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
1224 if (unlikely(r
!= 0))
1226 r
= radeon_bo_pin(rdev
->vram_scratch
.robj
,
1227 RADEON_GEM_DOMAIN_VRAM
, &rdev
->vram_scratch
.gpu_addr
);
1229 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1232 r
= radeon_bo_kmap(rdev
->vram_scratch
.robj
,
1233 (void **)&rdev
->vram_scratch
.ptr
);
1235 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
1236 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1241 void r600_vram_scratch_fini(struct radeon_device
*rdev
)
1245 if (rdev
->vram_scratch
.robj
== NULL
) {
1248 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
1249 if (likely(r
== 0)) {
1250 radeon_bo_kunmap(rdev
->vram_scratch
.robj
);
1251 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
1252 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
1254 radeon_bo_unref(&rdev
->vram_scratch
.robj
);
1257 /* We doesn't check that the GPU really needs a reset we simply do the
1258 * reset, it's up to the caller to determine if the GPU needs one. We
1259 * might add an helper function to check that.
1261 int r600_gpu_soft_reset(struct radeon_device
*rdev
)
1263 struct rv515_mc_save save
;
1264 u32 grbm_busy_mask
= S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1265 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1266 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1267 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1268 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1269 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1270 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1271 S_008010_GUI_ACTIVE(1);
1272 u32 grbm2_busy_mask
= S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1273 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1274 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1275 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1276 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1277 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1278 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1279 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1282 if (!(RREG32(GRBM_STATUS
) & GUI_ACTIVE
))
1285 dev_info(rdev
->dev
, "GPU softreset \n");
1286 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
1287 RREG32(R_008010_GRBM_STATUS
));
1288 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
1289 RREG32(R_008014_GRBM_STATUS2
));
1290 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
1291 RREG32(R_000E50_SRBM_STATUS
));
1292 rv515_mc_stop(rdev
, &save
);
1293 if (r600_mc_wait_for_idle(rdev
)) {
1294 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1296 /* Disable CP parsing/prefetching */
1297 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1298 /* Check if any of the rendering block is busy and reset it */
1299 if ((RREG32(R_008010_GRBM_STATUS
) & grbm_busy_mask
) ||
1300 (RREG32(R_008014_GRBM_STATUS2
) & grbm2_busy_mask
)) {
1301 tmp
= S_008020_SOFT_RESET_CR(1) |
1302 S_008020_SOFT_RESET_DB(1) |
1303 S_008020_SOFT_RESET_CB(1) |
1304 S_008020_SOFT_RESET_PA(1) |
1305 S_008020_SOFT_RESET_SC(1) |
1306 S_008020_SOFT_RESET_SMX(1) |
1307 S_008020_SOFT_RESET_SPI(1) |
1308 S_008020_SOFT_RESET_SX(1) |
1309 S_008020_SOFT_RESET_SH(1) |
1310 S_008020_SOFT_RESET_TC(1) |
1311 S_008020_SOFT_RESET_TA(1) |
1312 S_008020_SOFT_RESET_VC(1) |
1313 S_008020_SOFT_RESET_VGT(1);
1314 dev_info(rdev
->dev
, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1315 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1316 RREG32(R_008020_GRBM_SOFT_RESET
);
1318 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
1320 /* Reset CP (we always reset CP) */
1321 tmp
= S_008020_SOFT_RESET_CP(1);
1322 dev_info(rdev
->dev
, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1323 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1324 RREG32(R_008020_GRBM_SOFT_RESET
);
1326 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
1327 /* Wait a little for things to settle down */
1329 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
1330 RREG32(R_008010_GRBM_STATUS
));
1331 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
1332 RREG32(R_008014_GRBM_STATUS2
));
1333 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
1334 RREG32(R_000E50_SRBM_STATUS
));
1335 rv515_mc_resume(rdev
, &save
);
1339 bool r600_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
1345 srbm_status
= RREG32(R_000E50_SRBM_STATUS
);
1346 grbm_status
= RREG32(R_008010_GRBM_STATUS
);
1347 grbm_status2
= RREG32(R_008014_GRBM_STATUS2
);
1348 if (!G_008010_GUI_ACTIVE(grbm_status
)) {
1349 radeon_ring_lockup_update(ring
);
1352 /* force CP activities */
1353 radeon_ring_force_activity(rdev
, ring
);
1354 return radeon_ring_test_lockup(rdev
, ring
);
1357 int r600_asic_reset(struct radeon_device
*rdev
)
1359 return r600_gpu_soft_reset(rdev
);
1362 u32
r6xx_remap_render_backend(struct radeon_device
*rdev
,
1363 u32 tiling_pipe_num
,
1365 u32 total_max_rb_num
,
1366 u32 disabled_rb_mask
)
1368 u32 rendering_pipe_num
, rb_num_width
, req_rb_num
;
1369 u32 pipe_rb_ratio
, pipe_rb_remain
;
1370 u32 data
= 0, mask
= 1 << (max_rb_num
- 1);
1373 /* mask out the RBs that don't exist on that asic */
1374 disabled_rb_mask
|= (0xff << max_rb_num
) & 0xff;
1376 rendering_pipe_num
= 1 << tiling_pipe_num
;
1377 req_rb_num
= total_max_rb_num
- r600_count_pipe_bits(disabled_rb_mask
);
1378 BUG_ON(rendering_pipe_num
< req_rb_num
);
1380 pipe_rb_ratio
= rendering_pipe_num
/ req_rb_num
;
1381 pipe_rb_remain
= rendering_pipe_num
- pipe_rb_ratio
* req_rb_num
;
1383 if (rdev
->family
<= CHIP_RV740
) {
1391 for (i
= 0; i
< max_rb_num
; i
++) {
1392 if (!(mask
& disabled_rb_mask
)) {
1393 for (j
= 0; j
< pipe_rb_ratio
; j
++) {
1394 data
<<= rb_num_width
;
1395 data
|= max_rb_num
- i
- 1;
1397 if (pipe_rb_remain
) {
1398 data
<<= rb_num_width
;
1399 data
|= max_rb_num
- i
- 1;
1409 int r600_count_pipe_bits(uint32_t val
)
1413 for (i
= 0; i
< 32; i
++) {
1420 void r600_gpu_init(struct radeon_device
*rdev
)
1424 u32 cc_rb_backend_disable
;
1425 u32 cc_gc_shader_pipe_config
;
1429 u32 sq_gpr_resource_mgmt_1
= 0;
1430 u32 sq_gpr_resource_mgmt_2
= 0;
1431 u32 sq_thread_resource_mgmt
= 0;
1432 u32 sq_stack_resource_mgmt_1
= 0;
1433 u32 sq_stack_resource_mgmt_2
= 0;
1434 u32 disabled_rb_mask
;
1436 rdev
->config
.r600
.tiling_group_size
= 256;
1437 switch (rdev
->family
) {
1439 rdev
->config
.r600
.max_pipes
= 4;
1440 rdev
->config
.r600
.max_tile_pipes
= 8;
1441 rdev
->config
.r600
.max_simds
= 4;
1442 rdev
->config
.r600
.max_backends
= 4;
1443 rdev
->config
.r600
.max_gprs
= 256;
1444 rdev
->config
.r600
.max_threads
= 192;
1445 rdev
->config
.r600
.max_stack_entries
= 256;
1446 rdev
->config
.r600
.max_hw_contexts
= 8;
1447 rdev
->config
.r600
.max_gs_threads
= 16;
1448 rdev
->config
.r600
.sx_max_export_size
= 128;
1449 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1450 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1451 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1455 rdev
->config
.r600
.max_pipes
= 2;
1456 rdev
->config
.r600
.max_tile_pipes
= 2;
1457 rdev
->config
.r600
.max_simds
= 3;
1458 rdev
->config
.r600
.max_backends
= 1;
1459 rdev
->config
.r600
.max_gprs
= 128;
1460 rdev
->config
.r600
.max_threads
= 192;
1461 rdev
->config
.r600
.max_stack_entries
= 128;
1462 rdev
->config
.r600
.max_hw_contexts
= 8;
1463 rdev
->config
.r600
.max_gs_threads
= 4;
1464 rdev
->config
.r600
.sx_max_export_size
= 128;
1465 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1466 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1467 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1473 rdev
->config
.r600
.max_pipes
= 1;
1474 rdev
->config
.r600
.max_tile_pipes
= 1;
1475 rdev
->config
.r600
.max_simds
= 2;
1476 rdev
->config
.r600
.max_backends
= 1;
1477 rdev
->config
.r600
.max_gprs
= 128;
1478 rdev
->config
.r600
.max_threads
= 192;
1479 rdev
->config
.r600
.max_stack_entries
= 128;
1480 rdev
->config
.r600
.max_hw_contexts
= 4;
1481 rdev
->config
.r600
.max_gs_threads
= 4;
1482 rdev
->config
.r600
.sx_max_export_size
= 128;
1483 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1484 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1485 rdev
->config
.r600
.sq_num_cf_insts
= 1;
1488 rdev
->config
.r600
.max_pipes
= 4;
1489 rdev
->config
.r600
.max_tile_pipes
= 4;
1490 rdev
->config
.r600
.max_simds
= 4;
1491 rdev
->config
.r600
.max_backends
= 4;
1492 rdev
->config
.r600
.max_gprs
= 192;
1493 rdev
->config
.r600
.max_threads
= 192;
1494 rdev
->config
.r600
.max_stack_entries
= 256;
1495 rdev
->config
.r600
.max_hw_contexts
= 8;
1496 rdev
->config
.r600
.max_gs_threads
= 16;
1497 rdev
->config
.r600
.sx_max_export_size
= 128;
1498 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1499 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1500 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1506 /* Initialize HDP */
1507 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1508 WREG32((0x2c14 + j
), 0x00000000);
1509 WREG32((0x2c18 + j
), 0x00000000);
1510 WREG32((0x2c1c + j
), 0x00000000);
1511 WREG32((0x2c20 + j
), 0x00000000);
1512 WREG32((0x2c24 + j
), 0x00000000);
1515 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1519 ramcfg
= RREG32(RAMCFG
);
1520 switch (rdev
->config
.r600
.max_tile_pipes
) {
1522 tiling_config
|= PIPE_TILING(0);
1525 tiling_config
|= PIPE_TILING(1);
1528 tiling_config
|= PIPE_TILING(2);
1531 tiling_config
|= PIPE_TILING(3);
1536 rdev
->config
.r600
.tiling_npipes
= rdev
->config
.r600
.max_tile_pipes
;
1537 rdev
->config
.r600
.tiling_nbanks
= 4 << ((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1538 tiling_config
|= BANK_TILING((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1539 tiling_config
|= GROUP_SIZE((ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1541 tmp
= (ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
1543 tiling_config
|= ROW_TILING(3);
1544 tiling_config
|= SAMPLE_SPLIT(3);
1546 tiling_config
|= ROW_TILING(tmp
);
1547 tiling_config
|= SAMPLE_SPLIT(tmp
);
1549 tiling_config
|= BANK_SWAPS(1);
1551 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
1552 tmp
= R6XX_MAX_BACKENDS
-
1553 r600_count_pipe_bits((cc_rb_backend_disable
>> 16) & R6XX_MAX_BACKENDS_MASK
);
1554 if (tmp
< rdev
->config
.r600
.max_backends
) {
1555 rdev
->config
.r600
.max_backends
= tmp
;
1558 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0x00ffff00;
1559 tmp
= R6XX_MAX_PIPES
-
1560 r600_count_pipe_bits((cc_gc_shader_pipe_config
>> 8) & R6XX_MAX_PIPES_MASK
);
1561 if (tmp
< rdev
->config
.r600
.max_pipes
) {
1562 rdev
->config
.r600
.max_pipes
= tmp
;
1564 tmp
= R6XX_MAX_SIMDS
-
1565 r600_count_pipe_bits((cc_gc_shader_pipe_config
>> 16) & R6XX_MAX_SIMDS_MASK
);
1566 if (tmp
< rdev
->config
.r600
.max_simds
) {
1567 rdev
->config
.r600
.max_simds
= tmp
;
1570 disabled_rb_mask
= (RREG32(CC_RB_BACKEND_DISABLE
) >> 16) & R6XX_MAX_BACKENDS_MASK
;
1571 tmp
= (tiling_config
& PIPE_TILING__MASK
) >> PIPE_TILING__SHIFT
;
1572 tmp
= r6xx_remap_render_backend(rdev
, tmp
, rdev
->config
.r600
.max_backends
,
1573 R6XX_MAX_BACKENDS
, disabled_rb_mask
);
1574 tiling_config
|= tmp
<< 16;
1575 rdev
->config
.r600
.backend_map
= tmp
;
1577 rdev
->config
.r600
.tile_config
= tiling_config
;
1578 WREG32(GB_TILING_CONFIG
, tiling_config
);
1579 WREG32(DCP_TILING_CONFIG
, tiling_config
& 0xffff);
1580 WREG32(HDP_TILING_CONFIG
, tiling_config
& 0xffff);
1582 tmp
= R6XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
1583 WREG32(VGT_OUT_DEALLOC_CNTL
, (tmp
* 4) & DEALLOC_DIST_MASK
);
1584 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((tmp
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
1586 /* Setup some CP states */
1587 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1588 WREG32(CP_MEQ_THRESHOLDS
, (MEQ_END(0x40) | ROQ_END(0x40)));
1590 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
| SYNC_GRADIENT
|
1591 SYNC_WALKER
| SYNC_ALIGNER
));
1592 /* Setup various GPU states */
1593 if (rdev
->family
== CHIP_RV670
)
1594 WREG32(ARB_GDEC_RD_CNTL
, 0x00000021);
1596 tmp
= RREG32(SX_DEBUG_1
);
1597 tmp
|= SMX_EVENT_RELEASE
;
1598 if ((rdev
->family
> CHIP_R600
))
1599 tmp
|= ENABLE_NEW_SMX_ADDRESS
;
1600 WREG32(SX_DEBUG_1
, tmp
);
1602 if (((rdev
->family
) == CHIP_R600
) ||
1603 ((rdev
->family
) == CHIP_RV630
) ||
1604 ((rdev
->family
) == CHIP_RV610
) ||
1605 ((rdev
->family
) == CHIP_RV620
) ||
1606 ((rdev
->family
) == CHIP_RS780
) ||
1607 ((rdev
->family
) == CHIP_RS880
)) {
1608 WREG32(DB_DEBUG
, PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
1610 WREG32(DB_DEBUG
, 0);
1612 WREG32(DB_WATERMARKS
, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1613 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1615 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1616 WREG32(VGT_NUM_INSTANCES
, 0);
1618 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
1619 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(0));
1621 tmp
= RREG32(SQ_MS_FIFO_SIZES
);
1622 if (((rdev
->family
) == CHIP_RV610
) ||
1623 ((rdev
->family
) == CHIP_RV620
) ||
1624 ((rdev
->family
) == CHIP_RS780
) ||
1625 ((rdev
->family
) == CHIP_RS880
)) {
1626 tmp
= (CACHE_FIFO_SIZE(0xa) |
1627 FETCH_FIFO_HIWATER(0xa) |
1628 DONE_FIFO_HIWATER(0xe0) |
1629 ALU_UPDATE_FIFO_HIWATER(0x8));
1630 } else if (((rdev
->family
) == CHIP_R600
) ||
1631 ((rdev
->family
) == CHIP_RV630
)) {
1632 tmp
&= ~DONE_FIFO_HIWATER(0xff);
1633 tmp
|= DONE_FIFO_HIWATER(0x4);
1635 WREG32(SQ_MS_FIFO_SIZES
, tmp
);
1637 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1638 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1640 sq_config
= RREG32(SQ_CONFIG
);
1641 sq_config
&= ~(PS_PRIO(3) |
1645 sq_config
|= (DX9_CONSTS
|
1652 if ((rdev
->family
) == CHIP_R600
) {
1653 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(124) |
1655 NUM_CLAUSE_TEMP_GPRS(4));
1656 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(0) |
1658 sq_thread_resource_mgmt
= (NUM_PS_THREADS(136) |
1659 NUM_VS_THREADS(48) |
1662 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(128) |
1663 NUM_VS_STACK_ENTRIES(128));
1664 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(0) |
1665 NUM_ES_STACK_ENTRIES(0));
1666 } else if (((rdev
->family
) == CHIP_RV610
) ||
1667 ((rdev
->family
) == CHIP_RV620
) ||
1668 ((rdev
->family
) == CHIP_RS780
) ||
1669 ((rdev
->family
) == CHIP_RS880
)) {
1670 /* no vertex cache */
1671 sq_config
&= ~VC_ENABLE
;
1673 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1675 NUM_CLAUSE_TEMP_GPRS(2));
1676 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1678 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1679 NUM_VS_THREADS(78) |
1681 NUM_ES_THREADS(31));
1682 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1683 NUM_VS_STACK_ENTRIES(40));
1684 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1685 NUM_ES_STACK_ENTRIES(16));
1686 } else if (((rdev
->family
) == CHIP_RV630
) ||
1687 ((rdev
->family
) == CHIP_RV635
)) {
1688 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1690 NUM_CLAUSE_TEMP_GPRS(2));
1691 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(18) |
1693 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1694 NUM_VS_THREADS(78) |
1696 NUM_ES_THREADS(31));
1697 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1698 NUM_VS_STACK_ENTRIES(40));
1699 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1700 NUM_ES_STACK_ENTRIES(16));
1701 } else if ((rdev
->family
) == CHIP_RV670
) {
1702 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1704 NUM_CLAUSE_TEMP_GPRS(2));
1705 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1707 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1708 NUM_VS_THREADS(78) |
1710 NUM_ES_THREADS(31));
1711 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(64) |
1712 NUM_VS_STACK_ENTRIES(64));
1713 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(64) |
1714 NUM_ES_STACK_ENTRIES(64));
1717 WREG32(SQ_CONFIG
, sq_config
);
1718 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1719 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1720 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1721 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1722 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1724 if (((rdev
->family
) == CHIP_RV610
) ||
1725 ((rdev
->family
) == CHIP_RV620
) ||
1726 ((rdev
->family
) == CHIP_RS780
) ||
1727 ((rdev
->family
) == CHIP_RS880
)) {
1728 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(TC_ONLY
));
1730 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
));
1733 /* More default values. 2D/3D driver should adjust as needed */
1734 WREG32(PA_SC_AA_SAMPLE_LOCS_2S
, (S0_X(0xc) | S0_Y(0x4) |
1735 S1_X(0x4) | S1_Y(0xc)));
1736 WREG32(PA_SC_AA_SAMPLE_LOCS_4S
, (S0_X(0xe) | S0_Y(0xe) |
1737 S1_X(0x2) | S1_Y(0x2) |
1738 S2_X(0xa) | S2_Y(0x6) |
1739 S3_X(0x6) | S3_Y(0xa)));
1740 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (S0_X(0xe) | S0_Y(0xb) |
1741 S1_X(0x4) | S1_Y(0xc) |
1742 S2_X(0x1) | S2_Y(0x6) |
1743 S3_X(0xa) | S3_Y(0xe)));
1744 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (S4_X(0x6) | S4_Y(0x1) |
1745 S5_X(0x0) | S5_Y(0x0) |
1746 S6_X(0xb) | S6_Y(0x4) |
1747 S7_X(0x7) | S7_Y(0x8)));
1749 WREG32(VGT_STRMOUT_EN
, 0);
1750 tmp
= rdev
->config
.r600
.max_pipes
* 16;
1751 switch (rdev
->family
) {
1767 WREG32(VGT_ES_PER_GS
, 128);
1768 WREG32(VGT_GS_PER_ES
, tmp
);
1769 WREG32(VGT_GS_PER_VS
, 2);
1770 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1772 /* more default values. 2D/3D driver should adjust as needed */
1773 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1774 WREG32(VGT_STRMOUT_EN
, 0);
1776 WREG32(PA_SC_MODE_CNTL
, 0);
1777 WREG32(PA_SC_AA_CONFIG
, 0);
1778 WREG32(PA_SC_LINE_STIPPLE
, 0);
1779 WREG32(SPI_INPUT_Z
, 0);
1780 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
1781 WREG32(CB_COLOR7_FRAG
, 0);
1783 /* Clear render buffer base addresses */
1784 WREG32(CB_COLOR0_BASE
, 0);
1785 WREG32(CB_COLOR1_BASE
, 0);
1786 WREG32(CB_COLOR2_BASE
, 0);
1787 WREG32(CB_COLOR3_BASE
, 0);
1788 WREG32(CB_COLOR4_BASE
, 0);
1789 WREG32(CB_COLOR5_BASE
, 0);
1790 WREG32(CB_COLOR6_BASE
, 0);
1791 WREG32(CB_COLOR7_BASE
, 0);
1792 WREG32(CB_COLOR7_FRAG
, 0);
1794 switch (rdev
->family
) {
1799 tmp
= TC_L2_SIZE(8);
1803 tmp
= TC_L2_SIZE(4);
1806 tmp
= TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT
;
1809 tmp
= TC_L2_SIZE(0);
1812 WREG32(TC_CNTL
, tmp
);
1814 tmp
= RREG32(HDP_HOST_PATH_CNTL
);
1815 WREG32(HDP_HOST_PATH_CNTL
, tmp
);
1817 tmp
= RREG32(ARB_POP
);
1818 tmp
|= ENABLE_TC128
;
1819 WREG32(ARB_POP
, tmp
);
1821 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1822 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
1824 WREG32(PA_SC_ENHANCE
, FORCE_EOV_MAX_CLK_CNT(4095));
1825 WREG32(VC_ENHANCE
, 0);
1830 * Indirect registers accessor
1832 u32
r600_pciep_rreg(struct radeon_device
*rdev
, u32 reg
)
1836 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1837 (void)RREG32(PCIE_PORT_INDEX
);
1838 r
= RREG32(PCIE_PORT_DATA
);
1842 void r600_pciep_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
1844 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1845 (void)RREG32(PCIE_PORT_INDEX
);
1846 WREG32(PCIE_PORT_DATA
, (v
));
1847 (void)RREG32(PCIE_PORT_DATA
);
1853 void r600_cp_stop(struct radeon_device
*rdev
)
1855 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
1856 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1857 WREG32(SCRATCH_UMSK
, 0);
1860 int r600_init_microcode(struct radeon_device
*rdev
)
1862 struct platform_device
*pdev
;
1863 const char *chip_name
;
1864 const char *rlc_chip_name
;
1865 size_t pfp_req_size
, me_req_size
, rlc_req_size
;
1871 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
1874 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
1878 switch (rdev
->family
) {
1881 rlc_chip_name
= "R600";
1884 chip_name
= "RV610";
1885 rlc_chip_name
= "R600";
1888 chip_name
= "RV630";
1889 rlc_chip_name
= "R600";
1892 chip_name
= "RV620";
1893 rlc_chip_name
= "R600";
1896 chip_name
= "RV635";
1897 rlc_chip_name
= "R600";
1900 chip_name
= "RV670";
1901 rlc_chip_name
= "R600";
1905 chip_name
= "RS780";
1906 rlc_chip_name
= "R600";
1909 chip_name
= "RV770";
1910 rlc_chip_name
= "R700";
1914 chip_name
= "RV730";
1915 rlc_chip_name
= "R700";
1918 chip_name
= "RV710";
1919 rlc_chip_name
= "R700";
1922 chip_name
= "CEDAR";
1923 rlc_chip_name
= "CEDAR";
1926 chip_name
= "REDWOOD";
1927 rlc_chip_name
= "REDWOOD";
1930 chip_name
= "JUNIPER";
1931 rlc_chip_name
= "JUNIPER";
1935 chip_name
= "CYPRESS";
1936 rlc_chip_name
= "CYPRESS";
1940 rlc_chip_name
= "SUMO";
1944 rlc_chip_name
= "SUMO";
1947 chip_name
= "SUMO2";
1948 rlc_chip_name
= "SUMO";
1953 if (rdev
->family
>= CHIP_CEDAR
) {
1954 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
1955 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
1956 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
1957 } else if (rdev
->family
>= CHIP_RV770
) {
1958 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
1959 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
1960 rlc_req_size
= R700_RLC_UCODE_SIZE
* 4;
1962 pfp_req_size
= PFP_UCODE_SIZE
* 4;
1963 me_req_size
= PM4_UCODE_SIZE
* 12;
1964 rlc_req_size
= RLC_UCODE_SIZE
* 4;
1967 DRM_INFO("Loading %s Microcode\n", chip_name
);
1969 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
1970 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, &pdev
->dev
);
1973 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
1975 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1976 rdev
->pfp_fw
->size
, fw_name
);
1981 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
1982 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
1985 if (rdev
->me_fw
->size
!= me_req_size
) {
1987 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1988 rdev
->me_fw
->size
, fw_name
);
1992 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
1993 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, &pdev
->dev
);
1996 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
1998 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1999 rdev
->rlc_fw
->size
, fw_name
);
2004 platform_device_unregister(pdev
);
2009 "r600_cp: Failed to load firmware \"%s\"\n",
2011 release_firmware(rdev
->pfp_fw
);
2012 rdev
->pfp_fw
= NULL
;
2013 release_firmware(rdev
->me_fw
);
2015 release_firmware(rdev
->rlc_fw
);
2016 rdev
->rlc_fw
= NULL
;
2021 static int r600_cp_load_microcode(struct radeon_device
*rdev
)
2023 const __be32
*fw_data
;
2026 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
2035 RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
2038 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2039 RREG32(GRBM_SOFT_RESET
);
2041 WREG32(GRBM_SOFT_RESET
, 0);
2043 WREG32(CP_ME_RAM_WADDR
, 0);
2045 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
2046 WREG32(CP_ME_RAM_WADDR
, 0);
2047 for (i
= 0; i
< PM4_UCODE_SIZE
* 3; i
++)
2048 WREG32(CP_ME_RAM_DATA
,
2049 be32_to_cpup(fw_data
++));
2051 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
2052 WREG32(CP_PFP_UCODE_ADDR
, 0);
2053 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
2054 WREG32(CP_PFP_UCODE_DATA
,
2055 be32_to_cpup(fw_data
++));
2057 WREG32(CP_PFP_UCODE_ADDR
, 0);
2058 WREG32(CP_ME_RAM_WADDR
, 0);
2059 WREG32(CP_ME_RAM_RADDR
, 0);
2063 int r600_cp_start(struct radeon_device
*rdev
)
2065 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2069 r
= radeon_ring_lock(rdev
, ring
, 7);
2071 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2074 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
2075 radeon_ring_write(ring
, 0x1);
2076 if (rdev
->family
>= CHIP_RV770
) {
2077 radeon_ring_write(ring
, 0x0);
2078 radeon_ring_write(ring
, rdev
->config
.rv770
.max_hw_contexts
- 1);
2080 radeon_ring_write(ring
, 0x3);
2081 radeon_ring_write(ring
, rdev
->config
.r600
.max_hw_contexts
- 1);
2083 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2084 radeon_ring_write(ring
, 0);
2085 radeon_ring_write(ring
, 0);
2086 radeon_ring_unlock_commit(rdev
, ring
);
2089 WREG32(R_0086D8_CP_ME_CNTL
, cp_me
);
2093 int r600_cp_resume(struct radeon_device
*rdev
)
2095 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2101 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2102 RREG32(GRBM_SOFT_RESET
);
2104 WREG32(GRBM_SOFT_RESET
, 0);
2106 /* Set ring buffer size */
2107 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
2108 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2110 tmp
|= BUF_SWAP_32BIT
;
2112 WREG32(CP_RB_CNTL
, tmp
);
2113 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
2115 /* Set the write pointer delay */
2116 WREG32(CP_RB_WPTR_DELAY
, 0);
2118 /* Initialize the ring buffer's read and write pointers */
2119 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2120 WREG32(CP_RB_RPTR_WR
, 0);
2122 WREG32(CP_RB_WPTR
, ring
->wptr
);
2124 /* set the wb address whether it's enabled or not */
2125 WREG32(CP_RB_RPTR_ADDR
,
2126 ((rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC));
2127 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
2128 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
2130 if (rdev
->wb
.enabled
)
2131 WREG32(SCRATCH_UMSK
, 0xff);
2133 tmp
|= RB_NO_UPDATE
;
2134 WREG32(SCRATCH_UMSK
, 0);
2138 WREG32(CP_RB_CNTL
, tmp
);
2140 WREG32(CP_RB_BASE
, ring
->gpu_addr
>> 8);
2141 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
2143 ring
->rptr
= RREG32(CP_RB_RPTR
);
2145 r600_cp_start(rdev
);
2147 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, ring
);
2149 ring
->ready
= false;
2155 void r600_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ring_size
)
2160 /* Align ring size */
2161 rb_bufsz
= drm_order(ring_size
/ 8);
2162 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
2163 ring
->ring_size
= ring_size
;
2164 ring
->align_mask
= 16 - 1;
2166 r
= radeon_scratch_get(rdev
, &ring
->rptr_save_reg
);
2168 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r
);
2169 ring
->rptr_save_reg
= 0;
2173 void r600_cp_fini(struct radeon_device
*rdev
)
2175 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2177 radeon_ring_fini(rdev
, ring
);
2178 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
2183 * GPU scratch registers helpers function.
2185 void r600_scratch_init(struct radeon_device
*rdev
)
2189 rdev
->scratch
.num_reg
= 7;
2190 rdev
->scratch
.reg_base
= SCRATCH_REG0
;
2191 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
2192 rdev
->scratch
.free
[i
] = true;
2193 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
2197 int r600_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2204 r
= radeon_scratch_get(rdev
, &scratch
);
2206 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
2209 WREG32(scratch
, 0xCAFEDEAD);
2210 r
= radeon_ring_lock(rdev
, ring
, 3);
2212 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring
->idx
, r
);
2213 radeon_scratch_free(rdev
, scratch
);
2216 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2217 radeon_ring_write(ring
, ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2218 radeon_ring_write(ring
, 0xDEADBEEF);
2219 radeon_ring_unlock_commit(rdev
, ring
);
2220 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2221 tmp
= RREG32(scratch
);
2222 if (tmp
== 0xDEADBEEF)
2226 if (i
< rdev
->usec_timeout
) {
2227 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
2229 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2230 ring
->idx
, scratch
, tmp
);
2233 radeon_scratch_free(rdev
, scratch
);
2237 void r600_fence_ring_emit(struct radeon_device
*rdev
,
2238 struct radeon_fence
*fence
)
2240 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
2242 if (rdev
->wb
.use_event
) {
2243 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
2244 /* flush read cache over gart */
2245 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
2246 radeon_ring_write(ring
, PACKET3_TC_ACTION_ENA
|
2247 PACKET3_VC_ACTION_ENA
|
2248 PACKET3_SH_ACTION_ENA
);
2249 radeon_ring_write(ring
, 0xFFFFFFFF);
2250 radeon_ring_write(ring
, 0);
2251 radeon_ring_write(ring
, 10); /* poll interval */
2252 /* EVENT_WRITE_EOP - flush caches, send int */
2253 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2254 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS
) | EVENT_INDEX(5));
2255 radeon_ring_write(ring
, addr
& 0xffffffff);
2256 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2257 radeon_ring_write(ring
, fence
->seq
);
2258 radeon_ring_write(ring
, 0);
2260 /* flush read cache over gart */
2261 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
2262 radeon_ring_write(ring
, PACKET3_TC_ACTION_ENA
|
2263 PACKET3_VC_ACTION_ENA
|
2264 PACKET3_SH_ACTION_ENA
);
2265 radeon_ring_write(ring
, 0xFFFFFFFF);
2266 radeon_ring_write(ring
, 0);
2267 radeon_ring_write(ring
, 10); /* poll interval */
2268 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2269 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0));
2270 /* wait for 3D idle clean */
2271 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2272 radeon_ring_write(ring
, (WAIT_UNTIL
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2273 radeon_ring_write(ring
, WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
2274 /* Emit fence sequence & fire IRQ */
2275 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2276 radeon_ring_write(ring
, ((rdev
->fence_drv
[fence
->ring
].scratch_reg
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2277 radeon_ring_write(ring
, fence
->seq
);
2278 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2279 radeon_ring_write(ring
, PACKET0(CP_INT_STATUS
, 0));
2280 radeon_ring_write(ring
, RB_INT_STAT
);
2284 void r600_semaphore_ring_emit(struct radeon_device
*rdev
,
2285 struct radeon_ring
*ring
,
2286 struct radeon_semaphore
*semaphore
,
2289 uint64_t addr
= semaphore
->gpu_addr
;
2290 unsigned sel
= emit_wait
? PACKET3_SEM_SEL_WAIT
: PACKET3_SEM_SEL_SIGNAL
;
2292 if (rdev
->family
< CHIP_CAYMAN
)
2293 sel
|= PACKET3_SEM_WAIT_ON_SIGNAL
;
2295 radeon_ring_write(ring
, PACKET3(PACKET3_MEM_SEMAPHORE
, 1));
2296 radeon_ring_write(ring
, addr
& 0xffffffff);
2297 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | sel
);
2300 int r600_copy_blit(struct radeon_device
*rdev
,
2301 uint64_t src_offset
,
2302 uint64_t dst_offset
,
2303 unsigned num_gpu_pages
,
2304 struct radeon_fence
**fence
)
2306 struct radeon_semaphore
*sem
= NULL
;
2307 struct radeon_sa_bo
*vb
= NULL
;
2310 r
= r600_blit_prepare_copy(rdev
, num_gpu_pages
, fence
, &vb
, &sem
);
2314 r600_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_gpu_pages
, vb
);
2315 r600_blit_done_copy(rdev
, fence
, vb
, sem
);
2319 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
2320 uint32_t tiling_flags
, uint32_t pitch
,
2321 uint32_t offset
, uint32_t obj_size
)
2323 /* FIXME: implement */
2327 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
2329 /* FIXME: implement */
2332 int r600_startup(struct radeon_device
*rdev
)
2334 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2337 /* enable pcie gen2 link */
2338 r600_pcie_gen2_enable(rdev
);
2340 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
2341 r
= r600_init_microcode(rdev
);
2343 DRM_ERROR("Failed to load firmware!\n");
2348 r
= r600_vram_scratch_init(rdev
);
2352 r600_mc_program(rdev
);
2353 if (rdev
->flags
& RADEON_IS_AGP
) {
2354 r600_agp_enable(rdev
);
2356 r
= r600_pcie_gart_enable(rdev
);
2360 r600_gpu_init(rdev
);
2361 r
= r600_blit_init(rdev
);
2363 r600_blit_fini(rdev
);
2364 rdev
->asic
->copy
.copy
= NULL
;
2365 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
2368 /* allocate wb buffer */
2369 r
= radeon_wb_init(rdev
);
2373 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
2375 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
2380 r
= r600_irq_init(rdev
);
2382 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
2383 radeon_irq_kms_fini(rdev
);
2388 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
2389 R600_CP_RB_RPTR
, R600_CP_RB_WPTR
,
2390 0, 0xfffff, RADEON_CP_PACKET2
);
2394 r
= r600_cp_load_microcode(rdev
);
2397 r
= r600_cp_resume(rdev
);
2401 r
= radeon_ib_pool_init(rdev
);
2403 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
2407 r
= r600_audio_init(rdev
);
2409 DRM_ERROR("radeon: audio init failed\n");
2416 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
)
2420 temp
= RREG32(CONFIG_CNTL
);
2421 if (state
== false) {
2427 WREG32(CONFIG_CNTL
, temp
);
2430 int r600_resume(struct radeon_device
*rdev
)
2434 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2435 * posting will perform necessary task to bring back GPU into good
2439 atom_asic_init(rdev
->mode_info
.atom_context
);
2441 rdev
->accel_working
= true;
2442 r
= r600_startup(rdev
);
2444 DRM_ERROR("r600 startup failed on resume\n");
2445 rdev
->accel_working
= false;
2452 int r600_suspend(struct radeon_device
*rdev
)
2454 r600_audio_fini(rdev
);
2456 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
2457 r600_irq_suspend(rdev
);
2458 radeon_wb_disable(rdev
);
2459 r600_pcie_gart_disable(rdev
);
2464 /* Plan is to move initialization in that function and use
2465 * helper function so that radeon_device_init pretty much
2466 * do nothing more than calling asic specific function. This
2467 * should also allow to remove a bunch of callback function
2470 int r600_init(struct radeon_device
*rdev
)
2474 if (r600_debugfs_mc_info_init(rdev
)) {
2475 DRM_ERROR("Failed to register debugfs file for mc !\n");
2478 if (!radeon_get_bios(rdev
)) {
2479 if (ASIC_IS_AVIVO(rdev
))
2482 /* Must be an ATOMBIOS */
2483 if (!rdev
->is_atom_bios
) {
2484 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
2487 r
= radeon_atombios_init(rdev
);
2490 /* Post card if necessary */
2491 if (!radeon_card_posted(rdev
)) {
2493 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2496 DRM_INFO("GPU not posted. posting now...\n");
2497 atom_asic_init(rdev
->mode_info
.atom_context
);
2499 /* Initialize scratch registers */
2500 r600_scratch_init(rdev
);
2501 /* Initialize surface registers */
2502 radeon_surface_init(rdev
);
2503 /* Initialize clocks */
2504 radeon_get_clock_info(rdev
->ddev
);
2506 r
= radeon_fence_driver_init(rdev
);
2509 if (rdev
->flags
& RADEON_IS_AGP
) {
2510 r
= radeon_agp_init(rdev
);
2512 radeon_agp_disable(rdev
);
2514 r
= r600_mc_init(rdev
);
2517 /* Memory manager */
2518 r
= radeon_bo_init(rdev
);
2522 r
= radeon_irq_kms_init(rdev
);
2526 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ring_obj
= NULL
;
2527 r600_ring_init(rdev
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
], 1024 * 1024);
2529 rdev
->ih
.ring_obj
= NULL
;
2530 r600_ih_ring_init(rdev
, 64 * 1024);
2532 r
= r600_pcie_gart_init(rdev
);
2536 rdev
->accel_working
= true;
2537 r
= r600_startup(rdev
);
2539 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
2541 r600_irq_fini(rdev
);
2542 radeon_wb_fini(rdev
);
2543 radeon_ib_pool_fini(rdev
);
2544 radeon_irq_kms_fini(rdev
);
2545 r600_pcie_gart_fini(rdev
);
2546 rdev
->accel_working
= false;
2552 void r600_fini(struct radeon_device
*rdev
)
2554 r600_audio_fini(rdev
);
2555 r600_blit_fini(rdev
);
2557 r600_irq_fini(rdev
);
2558 radeon_wb_fini(rdev
);
2559 radeon_ib_pool_fini(rdev
);
2560 radeon_irq_kms_fini(rdev
);
2561 r600_pcie_gart_fini(rdev
);
2562 r600_vram_scratch_fini(rdev
);
2563 radeon_agp_fini(rdev
);
2564 radeon_gem_fini(rdev
);
2565 radeon_fence_driver_fini(rdev
);
2566 radeon_bo_fini(rdev
);
2567 radeon_atombios_fini(rdev
);
2576 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
2578 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
2580 if (ring
->rptr_save_reg
) {
2581 uint32_t next_rptr
= ring
->wptr
+ 3 + 4;
2582 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2583 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
2584 PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2585 radeon_ring_write(ring
, next_rptr
);
2588 radeon_ring_write(ring
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
2589 radeon_ring_write(ring
,
2593 (ib
->gpu_addr
& 0xFFFFFFFC));
2594 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
2595 radeon_ring_write(ring
, ib
->length_dw
);
2598 int r600_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2600 struct radeon_ib ib
;
2606 r
= radeon_scratch_get(rdev
, &scratch
);
2608 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
2611 WREG32(scratch
, 0xCAFEDEAD);
2612 r
= radeon_ib_get(rdev
, ring
->idx
, &ib
, 256);
2614 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
2617 ib
.ptr
[0] = PACKET3(PACKET3_SET_CONFIG_REG
, 1);
2618 ib
.ptr
[1] = ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2619 ib
.ptr
[2] = 0xDEADBEEF;
2621 r
= radeon_ib_schedule(rdev
, &ib
, NULL
);
2623 radeon_scratch_free(rdev
, scratch
);
2624 radeon_ib_free(rdev
, &ib
);
2625 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
2628 r
= radeon_fence_wait(ib
.fence
, false);
2630 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
2633 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2634 tmp
= RREG32(scratch
);
2635 if (tmp
== 0xDEADBEEF)
2639 if (i
< rdev
->usec_timeout
) {
2640 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib
.fence
->ring
, i
);
2642 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2646 radeon_scratch_free(rdev
, scratch
);
2647 radeon_ib_free(rdev
, &ib
);
2654 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2655 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2656 * writing to the ring and the GPU consuming, the GPU writes to the ring
2657 * and host consumes. As the host irq handler processes interrupts, it
2658 * increments the rptr. When the rptr catches up with the wptr, all the
2659 * current interrupts have been processed.
2662 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
2666 /* Align ring size */
2667 rb_bufsz
= drm_order(ring_size
/ 4);
2668 ring_size
= (1 << rb_bufsz
) * 4;
2669 rdev
->ih
.ring_size
= ring_size
;
2670 rdev
->ih
.ptr_mask
= rdev
->ih
.ring_size
- 1;
2674 int r600_ih_ring_alloc(struct radeon_device
*rdev
)
2678 /* Allocate ring buffer */
2679 if (rdev
->ih
.ring_obj
== NULL
) {
2680 r
= radeon_bo_create(rdev
, rdev
->ih
.ring_size
,
2682 RADEON_GEM_DOMAIN_GTT
,
2683 NULL
, &rdev
->ih
.ring_obj
);
2685 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r
);
2688 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2689 if (unlikely(r
!= 0))
2691 r
= radeon_bo_pin(rdev
->ih
.ring_obj
,
2692 RADEON_GEM_DOMAIN_GTT
,
2693 &rdev
->ih
.gpu_addr
);
2695 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2696 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r
);
2699 r
= radeon_bo_kmap(rdev
->ih
.ring_obj
,
2700 (void **)&rdev
->ih
.ring
);
2701 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2703 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r
);
2710 void r600_ih_ring_fini(struct radeon_device
*rdev
)
2713 if (rdev
->ih
.ring_obj
) {
2714 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2715 if (likely(r
== 0)) {
2716 radeon_bo_kunmap(rdev
->ih
.ring_obj
);
2717 radeon_bo_unpin(rdev
->ih
.ring_obj
);
2718 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2720 radeon_bo_unref(&rdev
->ih
.ring_obj
);
2721 rdev
->ih
.ring
= NULL
;
2722 rdev
->ih
.ring_obj
= NULL
;
2726 void r600_rlc_stop(struct radeon_device
*rdev
)
2729 if ((rdev
->family
>= CHIP_RV770
) &&
2730 (rdev
->family
<= CHIP_RV740
)) {
2731 /* r7xx asics need to soft reset RLC before halting */
2732 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_RLC
);
2733 RREG32(SRBM_SOFT_RESET
);
2735 WREG32(SRBM_SOFT_RESET
, 0);
2736 RREG32(SRBM_SOFT_RESET
);
2739 WREG32(RLC_CNTL
, 0);
2742 static void r600_rlc_start(struct radeon_device
*rdev
)
2744 WREG32(RLC_CNTL
, RLC_ENABLE
);
2747 static int r600_rlc_init(struct radeon_device
*rdev
)
2750 const __be32
*fw_data
;
2755 r600_rlc_stop(rdev
);
2757 WREG32(RLC_HB_CNTL
, 0);
2759 if (rdev
->family
== CHIP_ARUBA
) {
2760 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE
, rdev
->rlc
.save_restore_gpu_addr
>> 8);
2761 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE
, rdev
->rlc
.clear_state_gpu_addr
>> 8);
2763 if (rdev
->family
<= CHIP_CAYMAN
) {
2764 WREG32(RLC_HB_BASE
, 0);
2765 WREG32(RLC_HB_RPTR
, 0);
2766 WREG32(RLC_HB_WPTR
, 0);
2768 if (rdev
->family
<= CHIP_CAICOS
) {
2769 WREG32(RLC_HB_WPTR_LSB_ADDR
, 0);
2770 WREG32(RLC_HB_WPTR_MSB_ADDR
, 0);
2772 WREG32(RLC_MC_CNTL
, 0);
2773 WREG32(RLC_UCODE_CNTL
, 0);
2775 fw_data
= (const __be32
*)rdev
->rlc_fw
->data
;
2776 if (rdev
->family
>= CHIP_ARUBA
) {
2777 for (i
= 0; i
< ARUBA_RLC_UCODE_SIZE
; i
++) {
2778 WREG32(RLC_UCODE_ADDR
, i
);
2779 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2781 } else if (rdev
->family
>= CHIP_CAYMAN
) {
2782 for (i
= 0; i
< CAYMAN_RLC_UCODE_SIZE
; i
++) {
2783 WREG32(RLC_UCODE_ADDR
, i
);
2784 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2786 } else if (rdev
->family
>= CHIP_CEDAR
) {
2787 for (i
= 0; i
< EVERGREEN_RLC_UCODE_SIZE
; i
++) {
2788 WREG32(RLC_UCODE_ADDR
, i
);
2789 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2791 } else if (rdev
->family
>= CHIP_RV770
) {
2792 for (i
= 0; i
< R700_RLC_UCODE_SIZE
; i
++) {
2793 WREG32(RLC_UCODE_ADDR
, i
);
2794 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2797 for (i
= 0; i
< RLC_UCODE_SIZE
; i
++) {
2798 WREG32(RLC_UCODE_ADDR
, i
);
2799 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2802 WREG32(RLC_UCODE_ADDR
, 0);
2804 r600_rlc_start(rdev
);
2809 static void r600_enable_interrupts(struct radeon_device
*rdev
)
2811 u32 ih_cntl
= RREG32(IH_CNTL
);
2812 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2814 ih_cntl
|= ENABLE_INTR
;
2815 ih_rb_cntl
|= IH_RB_ENABLE
;
2816 WREG32(IH_CNTL
, ih_cntl
);
2817 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2818 rdev
->ih
.enabled
= true;
2821 void r600_disable_interrupts(struct radeon_device
*rdev
)
2823 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2824 u32 ih_cntl
= RREG32(IH_CNTL
);
2826 ih_rb_cntl
&= ~IH_RB_ENABLE
;
2827 ih_cntl
&= ~ENABLE_INTR
;
2828 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2829 WREG32(IH_CNTL
, ih_cntl
);
2830 /* set rptr, wptr to 0 */
2831 WREG32(IH_RB_RPTR
, 0);
2832 WREG32(IH_RB_WPTR
, 0);
2833 rdev
->ih
.enabled
= false;
2837 static void r600_disable_interrupt_state(struct radeon_device
*rdev
)
2841 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2842 WREG32(GRBM_INT_CNTL
, 0);
2843 WREG32(DxMODE_INT_MASK
, 0);
2844 WREG32(D1GRPH_INTERRUPT_CONTROL
, 0);
2845 WREG32(D2GRPH_INTERRUPT_CONTROL
, 0);
2846 if (ASIC_IS_DCE3(rdev
)) {
2847 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL
, 0);
2848 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL
, 0);
2849 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2850 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2851 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2852 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2853 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2854 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2855 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2856 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2857 if (ASIC_IS_DCE32(rdev
)) {
2858 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2859 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2860 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2861 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2862 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
2863 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, tmp
);
2864 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
2865 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, tmp
);
2867 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
2868 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
2869 tmp
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
2870 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
2873 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2874 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2875 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2876 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
2877 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2878 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
2879 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2880 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
2881 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
2882 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
2883 tmp
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
2884 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
2888 int r600_irq_init(struct radeon_device
*rdev
)
2892 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
2895 ret
= r600_ih_ring_alloc(rdev
);
2900 r600_disable_interrupts(rdev
);
2903 ret
= r600_rlc_init(rdev
);
2905 r600_ih_ring_fini(rdev
);
2909 /* setup interrupt control */
2910 /* set dummy read address to ring address */
2911 WREG32(INTERRUPT_CNTL2
, rdev
->ih
.gpu_addr
>> 8);
2912 interrupt_cntl
= RREG32(INTERRUPT_CNTL
);
2913 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2914 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2916 interrupt_cntl
&= ~IH_DUMMY_RD_OVERRIDE
;
2917 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2918 interrupt_cntl
&= ~IH_REQ_NONSNOOP_EN
;
2919 WREG32(INTERRUPT_CNTL
, interrupt_cntl
);
2921 WREG32(IH_RB_BASE
, rdev
->ih
.gpu_addr
>> 8);
2922 rb_bufsz
= drm_order(rdev
->ih
.ring_size
/ 4);
2924 ih_rb_cntl
= (IH_WPTR_OVERFLOW_ENABLE
|
2925 IH_WPTR_OVERFLOW_CLEAR
|
2928 if (rdev
->wb
.enabled
)
2929 ih_rb_cntl
|= IH_WPTR_WRITEBACK_ENABLE
;
2931 /* set the writeback address whether it's enabled or not */
2932 WREG32(IH_RB_WPTR_ADDR_LO
, (rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFFFFFFFC);
2933 WREG32(IH_RB_WPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFF);
2935 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2937 /* set rptr, wptr to 0 */
2938 WREG32(IH_RB_RPTR
, 0);
2939 WREG32(IH_RB_WPTR
, 0);
2941 /* Default settings for IH_CNTL (disabled at first) */
2942 ih_cntl
= MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2943 /* RPTR_REARM only works if msi's are enabled */
2944 if (rdev
->msi_enabled
)
2945 ih_cntl
|= RPTR_REARM
;
2946 WREG32(IH_CNTL
, ih_cntl
);
2948 /* force the active interrupt state to all disabled */
2949 if (rdev
->family
>= CHIP_CEDAR
)
2950 evergreen_disable_interrupt_state(rdev
);
2952 r600_disable_interrupt_state(rdev
);
2954 /* at this point everything should be setup correctly to enable master */
2955 pci_set_master(rdev
->pdev
);
2958 r600_enable_interrupts(rdev
);
2963 void r600_irq_suspend(struct radeon_device
*rdev
)
2965 r600_irq_disable(rdev
);
2966 r600_rlc_stop(rdev
);
2969 void r600_irq_fini(struct radeon_device
*rdev
)
2971 r600_irq_suspend(rdev
);
2972 r600_ih_ring_fini(rdev
);
2975 int r600_irq_set(struct radeon_device
*rdev
)
2977 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
2979 u32 hpd1
, hpd2
, hpd3
, hpd4
= 0, hpd5
= 0, hpd6
= 0;
2980 u32 grbm_int_cntl
= 0;
2982 u32 d1grph
= 0, d2grph
= 0;
2984 if (!rdev
->irq
.installed
) {
2985 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2988 /* don't enable anything if the ih is disabled */
2989 if (!rdev
->ih
.enabled
) {
2990 r600_disable_interrupts(rdev
);
2991 /* force the active interrupt state to all disabled */
2992 r600_disable_interrupt_state(rdev
);
2996 if (ASIC_IS_DCE3(rdev
)) {
2997 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2998 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
2999 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3000 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3001 if (ASIC_IS_DCE32(rdev
)) {
3002 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3003 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3004 hdmi0
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
3005 hdmi1
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
) & ~AFMT_AZ_FORMAT_WTRIG_MASK
;
3007 hdmi0
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3008 hdmi1
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3011 hpd1
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3012 hpd2
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3013 hpd3
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3014 hdmi0
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3015 hdmi1
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
) & ~HDMI0_AZ_FORMAT_WTRIG_MASK
;
3018 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
3019 DRM_DEBUG("r600_irq_set: sw int\n");
3020 cp_int_cntl
|= RB_INT_ENABLE
;
3021 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
3023 if (rdev
->irq
.crtc_vblank_int
[0] ||
3024 atomic_read(&rdev
->irq
.pflip
[0])) {
3025 DRM_DEBUG("r600_irq_set: vblank 0\n");
3026 mode_int
|= D1MODE_VBLANK_INT_MASK
;
3028 if (rdev
->irq
.crtc_vblank_int
[1] ||
3029 atomic_read(&rdev
->irq
.pflip
[1])) {
3030 DRM_DEBUG("r600_irq_set: vblank 1\n");
3031 mode_int
|= D2MODE_VBLANK_INT_MASK
;
3033 if (rdev
->irq
.hpd
[0]) {
3034 DRM_DEBUG("r600_irq_set: hpd 1\n");
3035 hpd1
|= DC_HPDx_INT_EN
;
3037 if (rdev
->irq
.hpd
[1]) {
3038 DRM_DEBUG("r600_irq_set: hpd 2\n");
3039 hpd2
|= DC_HPDx_INT_EN
;
3041 if (rdev
->irq
.hpd
[2]) {
3042 DRM_DEBUG("r600_irq_set: hpd 3\n");
3043 hpd3
|= DC_HPDx_INT_EN
;
3045 if (rdev
->irq
.hpd
[3]) {
3046 DRM_DEBUG("r600_irq_set: hpd 4\n");
3047 hpd4
|= DC_HPDx_INT_EN
;
3049 if (rdev
->irq
.hpd
[4]) {
3050 DRM_DEBUG("r600_irq_set: hpd 5\n");
3051 hpd5
|= DC_HPDx_INT_EN
;
3053 if (rdev
->irq
.hpd
[5]) {
3054 DRM_DEBUG("r600_irq_set: hpd 6\n");
3055 hpd6
|= DC_HPDx_INT_EN
;
3057 if (rdev
->irq
.afmt
[0]) {
3058 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3059 hdmi0
|= HDMI0_AZ_FORMAT_WTRIG_MASK
;
3061 if (rdev
->irq
.afmt
[1]) {
3062 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3063 hdmi1
|= HDMI0_AZ_FORMAT_WTRIG_MASK
;
3065 if (rdev
->irq
.gui_idle
) {
3066 DRM_DEBUG("gui idle\n");
3067 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
3070 WREG32(CP_INT_CNTL
, cp_int_cntl
);
3071 WREG32(DxMODE_INT_MASK
, mode_int
);
3072 WREG32(D1GRPH_INTERRUPT_CONTROL
, d1grph
);
3073 WREG32(D2GRPH_INTERRUPT_CONTROL
, d2grph
);
3074 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
3075 if (ASIC_IS_DCE3(rdev
)) {
3076 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
3077 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
3078 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
3079 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
3080 if (ASIC_IS_DCE32(rdev
)) {
3081 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
3082 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
3083 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, hdmi0
);
3084 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, hdmi1
);
3086 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, hdmi0
);
3087 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, hdmi1
);
3090 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
3091 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
3092 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, hpd3
);
3093 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, hdmi0
);
3094 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, hdmi1
);
3100 static void r600_irq_ack(struct radeon_device
*rdev
)
3104 if (ASIC_IS_DCE3(rdev
)) {
3105 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DCE3_DISP_INTERRUPT_STATUS
);
3106 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE
);
3107 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2
);
3108 if (ASIC_IS_DCE32(rdev
)) {
3109 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(AFMT_STATUS
+ DCE3_HDMI_OFFSET0
);
3110 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(AFMT_STATUS
+ DCE3_HDMI_OFFSET1
);
3112 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(HDMI0_STATUS
);
3113 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(DCE3_HDMI1_STATUS
);
3116 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
3117 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
3118 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= 0;
3119 rdev
->irq
.stat_regs
.r600
.hdmi0_status
= RREG32(HDMI0_STATUS
);
3120 rdev
->irq
.stat_regs
.r600
.hdmi1_status
= RREG32(HDMI1_STATUS
);
3122 rdev
->irq
.stat_regs
.r600
.d1grph_int
= RREG32(D1GRPH_INTERRUPT_STATUS
);
3123 rdev
->irq
.stat_regs
.r600
.d2grph_int
= RREG32(D2GRPH_INTERRUPT_STATUS
);
3125 if (rdev
->irq
.stat_regs
.r600
.d1grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
3126 WREG32(D1GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
3127 if (rdev
->irq
.stat_regs
.r600
.d2grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
3128 WREG32(D2GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
3129 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
3130 WREG32(D1MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
3131 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
)
3132 WREG32(D1MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
3133 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
)
3134 WREG32(D2MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
3135 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
)
3136 WREG32(D2MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
3137 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
3138 if (ASIC_IS_DCE3(rdev
)) {
3139 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
3140 tmp
|= DC_HPDx_INT_ACK
;
3141 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
3143 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
3144 tmp
|= DC_HPDx_INT_ACK
;
3145 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
3148 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
3149 if (ASIC_IS_DCE3(rdev
)) {
3150 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
3151 tmp
|= DC_HPDx_INT_ACK
;
3152 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
3154 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
3155 tmp
|= DC_HPDx_INT_ACK
;
3156 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
3159 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
3160 if (ASIC_IS_DCE3(rdev
)) {
3161 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
3162 tmp
|= DC_HPDx_INT_ACK
;
3163 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
3165 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
3166 tmp
|= DC_HPDx_INT_ACK
;
3167 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
3170 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
3171 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
3172 tmp
|= DC_HPDx_INT_ACK
;
3173 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
3175 if (ASIC_IS_DCE32(rdev
)) {
3176 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
3177 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3178 tmp
|= DC_HPDx_INT_ACK
;
3179 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
3181 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
3182 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3183 tmp
|= DC_HPDx_INT_ACK
;
3184 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
3186 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& AFMT_AZ_FORMAT_WTRIG
) {
3187 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
);
3188 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3189 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET0
, tmp
);
3191 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& AFMT_AZ_FORMAT_WTRIG
) {
3192 tmp
= RREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
);
3193 tmp
|= AFMT_AZ_FORMAT_WTRIG_ACK
;
3194 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ DCE3_HDMI_OFFSET1
, tmp
);
3197 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& HDMI0_AZ_FORMAT_WTRIG
) {
3198 tmp
= RREG32(HDMI0_AUDIO_PACKET_CONTROL
);
3199 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
3200 WREG32(HDMI0_AUDIO_PACKET_CONTROL
, tmp
);
3202 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& HDMI0_AZ_FORMAT_WTRIG
) {
3203 if (ASIC_IS_DCE3(rdev
)) {
3204 tmp
= RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
);
3205 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
3206 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
3208 tmp
= RREG32(HDMI1_AUDIO_PACKET_CONTROL
);
3209 tmp
|= HDMI0_AZ_FORMAT_WTRIG_ACK
;
3210 WREG32(HDMI1_AUDIO_PACKET_CONTROL
, tmp
);
3216 void r600_irq_disable(struct radeon_device
*rdev
)
3218 r600_disable_interrupts(rdev
);
3219 /* Wait and acknowledge irq */
3222 r600_disable_interrupt_state(rdev
);
3225 static u32
r600_get_ih_wptr(struct radeon_device
*rdev
)
3229 if (rdev
->wb
.enabled
)
3230 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
3232 wptr
= RREG32(IH_RB_WPTR
);
3234 if (wptr
& RB_OVERFLOW
) {
3235 /* When a ring buffer overflow happen start parsing interrupt
3236 * from the last not overwritten vector (wptr + 16). Hopefully
3237 * this should allow us to catchup.
3239 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3240 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
3241 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
3242 tmp
= RREG32(IH_RB_CNTL
);
3243 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
3244 WREG32(IH_RB_CNTL
, tmp
);
3246 return (wptr
& rdev
->ih
.ptr_mask
);
3250 * Each IV ring entry is 128 bits:
3251 * [7:0] - interrupt source id
3253 * [59:32] - interrupt source data
3254 * [127:60] - reserved
3256 * The basic interrupt vector entries
3257 * are decoded as follows:
3258 * src_id src_data description
3263 * 19 0 FP Hot plug detection A
3264 * 19 1 FP Hot plug detection B
3265 * 19 2 DAC A auto-detection
3266 * 19 3 DAC B auto-detection
3272 * 181 - EOP Interrupt
3275 * Note, these are based on r600 and may need to be
3276 * adjusted or added to on newer asics
3279 int r600_irq_process(struct radeon_device
*rdev
)
3283 u32 src_id
, src_data
;
3285 bool queue_hotplug
= false;
3286 bool queue_hdmi
= false;
3288 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
3291 /* No MSIs, need a dummy read to flush PCI DMAs */
3292 if (!rdev
->msi_enabled
)
3295 wptr
= r600_get_ih_wptr(rdev
);
3298 /* is somebody else already processing irqs? */
3299 if (atomic_xchg(&rdev
->ih
.lock
, 1))
3302 rptr
= rdev
->ih
.rptr
;
3303 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
3305 /* Order reading of wptr vs. reading of IH ring data */
3308 /* display interrupts */
3311 while (rptr
!= wptr
) {
3312 /* wptr/rptr are in bytes! */
3313 ring_index
= rptr
/ 4;
3314 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
3315 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
3318 case 1: /* D1 vblank/vline */
3320 case 0: /* D1 vblank */
3321 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
3322 if (rdev
->irq
.crtc_vblank_int
[0]) {
3323 drm_handle_vblank(rdev
->ddev
, 0);
3324 rdev
->pm
.vblank_sync
= true;
3325 wake_up(&rdev
->irq
.vblank_queue
);
3327 if (atomic_read(&rdev
->irq
.pflip
[0]))
3328 radeon_crtc_handle_flip(rdev
, 0);
3329 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
3330 DRM_DEBUG("IH: D1 vblank\n");
3333 case 1: /* D1 vline */
3334 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
3335 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
3336 DRM_DEBUG("IH: D1 vline\n");
3340 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3344 case 5: /* D2 vblank/vline */
3346 case 0: /* D2 vblank */
3347 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
) {
3348 if (rdev
->irq
.crtc_vblank_int
[1]) {
3349 drm_handle_vblank(rdev
->ddev
, 1);
3350 rdev
->pm
.vblank_sync
= true;
3351 wake_up(&rdev
->irq
.vblank_queue
);
3353 if (atomic_read(&rdev
->irq
.pflip
[1]))
3354 radeon_crtc_handle_flip(rdev
, 1);
3355 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VBLANK_INTERRUPT
;
3356 DRM_DEBUG("IH: D2 vblank\n");
3359 case 1: /* D1 vline */
3360 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
) {
3361 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VLINE_INTERRUPT
;
3362 DRM_DEBUG("IH: D2 vline\n");
3366 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3370 case 19: /* HPD/DAC hotplug */
3373 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
3374 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD1_INTERRUPT
;
3375 queue_hotplug
= true;
3376 DRM_DEBUG("IH: HPD1\n");
3380 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
3381 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD2_INTERRUPT
;
3382 queue_hotplug
= true;
3383 DRM_DEBUG("IH: HPD2\n");
3387 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
3388 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD3_INTERRUPT
;
3389 queue_hotplug
= true;
3390 DRM_DEBUG("IH: HPD3\n");
3394 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
3395 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD4_INTERRUPT
;
3396 queue_hotplug
= true;
3397 DRM_DEBUG("IH: HPD4\n");
3401 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
3402 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD5_INTERRUPT
;
3403 queue_hotplug
= true;
3404 DRM_DEBUG("IH: HPD5\n");
3408 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
3409 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD6_INTERRUPT
;
3410 queue_hotplug
= true;
3411 DRM_DEBUG("IH: HPD6\n");
3415 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3422 if (rdev
->irq
.stat_regs
.r600
.hdmi0_status
& HDMI0_AZ_FORMAT_WTRIG
) {
3423 rdev
->irq
.stat_regs
.r600
.hdmi0_status
&= ~HDMI0_AZ_FORMAT_WTRIG
;
3425 DRM_DEBUG("IH: HDMI0\n");
3429 if (rdev
->irq
.stat_regs
.r600
.hdmi1_status
& HDMI0_AZ_FORMAT_WTRIG
) {
3430 rdev
->irq
.stat_regs
.r600
.hdmi1_status
&= ~HDMI0_AZ_FORMAT_WTRIG
;
3432 DRM_DEBUG("IH: HDMI1\n");
3436 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3440 case 176: /* CP_INT in ring buffer */
3441 case 177: /* CP_INT in IB1 */
3442 case 178: /* CP_INT in IB2 */
3443 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
3444 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3446 case 181: /* CP EOP event */
3447 DRM_DEBUG("IH: CP EOP\n");
3448 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3450 case 233: /* GUI IDLE */
3451 DRM_DEBUG("IH: GUI idle\n");
3452 wake_up(&rdev
->irq
.idle_queue
);
3455 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3459 /* wptr/rptr are in bytes! */
3461 rptr
&= rdev
->ih
.ptr_mask
;
3464 schedule_work(&rdev
->hotplug_work
);
3466 schedule_work(&rdev
->audio_work
);
3467 rdev
->ih
.rptr
= rptr
;
3468 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3469 atomic_set(&rdev
->ih
.lock
, 0);
3471 /* make sure wptr hasn't changed while processing */
3472 wptr
= r600_get_ih_wptr(rdev
);
3482 #if defined(CONFIG_DEBUG_FS)
3484 static int r600_debugfs_mc_info(struct seq_file
*m
, void *data
)
3486 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3487 struct drm_device
*dev
= node
->minor
->dev
;
3488 struct radeon_device
*rdev
= dev
->dev_private
;
3490 DREG32_SYS(m
, rdev
, R_000E50_SRBM_STATUS
);
3491 DREG32_SYS(m
, rdev
, VM_L2_STATUS
);
3495 static struct drm_info_list r600_mc_info_list
[] = {
3496 {"r600_mc_info", r600_debugfs_mc_info
, 0, NULL
},
3500 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
)
3502 #if defined(CONFIG_DEBUG_FS)
3503 return radeon_debugfs_add_files(rdev
, r600_mc_info_list
, ARRAY_SIZE(r600_mc_info_list
));
3510 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3511 * rdev: radeon device structure
3512 * bo: buffer object struct which userspace is waiting for idle
3514 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3515 * through ring buffer, this leads to corruption in rendering, see
3516 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3517 * directly perform HDP flush by writing register through MMIO.
3519 void r600_ioctl_wait_idle(struct radeon_device
*rdev
, struct radeon_bo
*bo
)
3521 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3522 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3523 * This seems to cause problems on some AGP cards. Just use the old
3526 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
3527 rdev
->vram_scratch
.ptr
&& !(rdev
->flags
& RADEON_IS_AGP
)) {
3528 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
3531 WREG32(HDP_DEBUG1
, 0);
3532 tmp
= readl((void __iomem
*)ptr
);
3534 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
3537 void r600_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
3539 u32 link_width_cntl
, mask
, target_reg
;
3541 if (rdev
->flags
& RADEON_IS_IGP
)
3544 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3547 /* x2 cards have a special sequence */
3548 if (ASIC_IS_X2(rdev
))
3551 /* FIXME wait for idle */
3555 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
3558 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
3561 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
3564 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
3567 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
3570 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
3574 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
3578 link_width_cntl
= RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
3580 if ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) ==
3581 (mask
<< RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
))
3584 if (link_width_cntl
& R600_PCIE_LC_UPCONFIGURE_DIS
)
3587 link_width_cntl
&= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK
|
3588 RADEON_PCIE_LC_RECONFIG_NOW
|
3589 R600_PCIE_LC_RENEGOTIATE_EN
|
3590 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
);
3591 link_width_cntl
|= mask
;
3593 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3595 /* some northbridges can renegotiate the link rather than requiring
3596 * a complete re-config.
3597 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3599 if (link_width_cntl
& R600_PCIE_LC_RENEGOTIATION_SUPPORT
)
3600 link_width_cntl
|= R600_PCIE_LC_RENEGOTIATE_EN
| R600_PCIE_LC_UPCONFIGURE_SUPPORT
;
3602 link_width_cntl
|= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
;
3604 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, (link_width_cntl
|
3605 RADEON_PCIE_LC_RECONFIG_NOW
));
3607 if (rdev
->family
>= CHIP_RV770
)
3608 target_reg
= R700_TARGET_AND_CURRENT_PROFILE_INDEX
;
3610 target_reg
= R600_TARGET_AND_CURRENT_PROFILE_INDEX
;
3612 /* wait for lane set to complete */
3613 link_width_cntl
= RREG32(target_reg
);
3614 while (link_width_cntl
== 0xffffffff)
3615 link_width_cntl
= RREG32(target_reg
);
3619 int r600_get_pcie_lanes(struct radeon_device
*rdev
)
3621 u32 link_width_cntl
;
3623 if (rdev
->flags
& RADEON_IS_IGP
)
3626 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3629 /* x2 cards have a special sequence */
3630 if (ASIC_IS_X2(rdev
))
3633 /* FIXME wait for idle */
3635 link_width_cntl
= RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
3637 switch ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
) {
3638 case RADEON_PCIE_LC_LINK_WIDTH_X0
:
3640 case RADEON_PCIE_LC_LINK_WIDTH_X1
:
3642 case RADEON_PCIE_LC_LINK_WIDTH_X2
:
3644 case RADEON_PCIE_LC_LINK_WIDTH_X4
:
3646 case RADEON_PCIE_LC_LINK_WIDTH_X8
:
3648 case RADEON_PCIE_LC_LINK_WIDTH_X16
:
3654 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
)
3656 u32 link_width_cntl
, lanes
, speed_cntl
, training_cntl
, tmp
;
3659 if (radeon_pcie_gen2
== 0)
3662 if (rdev
->flags
& RADEON_IS_IGP
)
3665 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3668 /* x2 cards have a special sequence */
3669 if (ASIC_IS_X2(rdev
))
3672 /* only RV6xx+ chips are supported */
3673 if (rdev
->family
<= CHIP_R600
)
3676 /* 55 nm r6xx asics */
3677 if ((rdev
->family
== CHIP_RV670
) ||
3678 (rdev
->family
== CHIP_RV620
) ||
3679 (rdev
->family
== CHIP_RV635
)) {
3680 /* advertise upconfig capability */
3681 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3682 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3683 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3684 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3685 if (link_width_cntl
& LC_RENEGOTIATION_SUPPORT
) {
3686 lanes
= (link_width_cntl
& LC_LINK_WIDTH_RD_MASK
) >> LC_LINK_WIDTH_RD_SHIFT
;
3687 link_width_cntl
&= ~(LC_LINK_WIDTH_MASK
|
3688 LC_RECONFIG_ARC_MISSING_ESCAPE
);
3689 link_width_cntl
|= lanes
| LC_RECONFIG_NOW
| LC_RENEGOTIATE_EN
;
3690 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3692 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3693 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3697 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3698 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) &&
3699 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3701 /* 55 nm r6xx asics */
3702 if ((rdev
->family
== CHIP_RV670
) ||
3703 (rdev
->family
== CHIP_RV620
) ||
3704 (rdev
->family
== CHIP_RV635
)) {
3705 WREG32(MM_CFGREGS_CNTL
, 0x8);
3706 link_cntl2
= RREG32(0x4088);
3707 WREG32(MM_CFGREGS_CNTL
, 0);
3708 /* not supported yet */
3709 if (link_cntl2
& SELECTABLE_DEEMPHASIS
)
3713 speed_cntl
&= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
;
3714 speed_cntl
|= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT
);
3715 speed_cntl
&= ~LC_VOLTAGE_TIMER_SEL_MASK
;
3716 speed_cntl
&= ~LC_FORCE_DIS_HW_SPEED_CHANGE
;
3717 speed_cntl
|= LC_FORCE_EN_HW_SPEED_CHANGE
;
3718 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3720 tmp
= RREG32(0x541c);
3721 WREG32(0x541c, tmp
| 0x8);
3722 WREG32(MM_CFGREGS_CNTL
, MM_WR_TO_CFG_EN
);
3723 link_cntl2
= RREG16(0x4088);
3724 link_cntl2
&= ~TARGET_LINK_SPEED_MASK
;
3726 WREG16(0x4088, link_cntl2
);
3727 WREG32(MM_CFGREGS_CNTL
, 0);
3729 if ((rdev
->family
== CHIP_RV670
) ||
3730 (rdev
->family
== CHIP_RV620
) ||
3731 (rdev
->family
== CHIP_RV635
)) {
3732 training_cntl
= RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL
);
3733 training_cntl
&= ~LC_POINT_7_PLUS_EN
;
3734 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL
, training_cntl
);
3736 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3737 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3738 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3741 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3742 speed_cntl
|= LC_GEN2_EN_STRAP
;
3743 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3746 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3747 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3749 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3751 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3752 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);