2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
33 #include "radeon_drm.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
53 MODULE_FIRMWARE("radeon/R600_me.bin");
54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV610_me.bin");
56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV630_me.bin");
58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV620_me.bin");
60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV635_me.bin");
62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV670_me.bin");
64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65 MODULE_FIRMWARE("radeon/RS780_me.bin");
66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV770_me.bin");
68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69 MODULE_FIRMWARE("radeon/RV730_me.bin");
70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
86 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
87 MODULE_FIRMWARE("radeon/PALM_me.bin");
88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
90 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
);
92 /* r600,rv610,rv630,rv620,rv635,rv670 */
93 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
94 void r600_gpu_init(struct radeon_device
*rdev
);
95 void r600_fini(struct radeon_device
*rdev
);
96 void r600_irq_disable(struct radeon_device
*rdev
);
97 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
);
99 /* get temperature in millidegrees */
100 int rv6xx_get_temp(struct radeon_device
*rdev
)
102 u32 temp
= (RREG32(CG_THERMAL_STATUS
) & ASIC_T_MASK
) >>
104 int actual_temp
= temp
& 0xff;
109 return actual_temp
* 1000;
112 void r600_pm_get_dynpm_state(struct radeon_device
*rdev
)
116 rdev
->pm
.dynpm_can_upclock
= true;
117 rdev
->pm
.dynpm_can_downclock
= true;
119 /* power state array is low to high, default is first */
120 if ((rdev
->flags
& RADEON_IS_IGP
) || (rdev
->family
== CHIP_R600
)) {
121 int min_power_state_index
= 0;
123 if (rdev
->pm
.num_power_states
> 2)
124 min_power_state_index
= 1;
126 switch (rdev
->pm
.dynpm_planned_action
) {
127 case DYNPM_ACTION_MINIMUM
:
128 rdev
->pm
.requested_power_state_index
= min_power_state_index
;
129 rdev
->pm
.requested_clock_mode_index
= 0;
130 rdev
->pm
.dynpm_can_downclock
= false;
132 case DYNPM_ACTION_DOWNCLOCK
:
133 if (rdev
->pm
.current_power_state_index
== min_power_state_index
) {
134 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
135 rdev
->pm
.dynpm_can_downclock
= false;
137 if (rdev
->pm
.active_crtc_count
> 1) {
138 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
139 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
141 else if (i
>= rdev
->pm
.current_power_state_index
) {
142 rdev
->pm
.requested_power_state_index
=
143 rdev
->pm
.current_power_state_index
;
146 rdev
->pm
.requested_power_state_index
= i
;
151 if (rdev
->pm
.current_power_state_index
== 0)
152 rdev
->pm
.requested_power_state_index
=
153 rdev
->pm
.num_power_states
- 1;
155 rdev
->pm
.requested_power_state_index
=
156 rdev
->pm
.current_power_state_index
- 1;
159 rdev
->pm
.requested_clock_mode_index
= 0;
160 /* don't use the power state if crtcs are active and no display flag is set */
161 if ((rdev
->pm
.active_crtc_count
> 0) &&
162 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
163 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
164 RADEON_PM_MODE_NO_DISPLAY
)) {
165 rdev
->pm
.requested_power_state_index
++;
168 case DYNPM_ACTION_UPCLOCK
:
169 if (rdev
->pm
.current_power_state_index
== (rdev
->pm
.num_power_states
- 1)) {
170 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
171 rdev
->pm
.dynpm_can_upclock
= false;
173 if (rdev
->pm
.active_crtc_count
> 1) {
174 for (i
= (rdev
->pm
.num_power_states
- 1); i
>= 0; i
--) {
175 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
177 else if (i
<= rdev
->pm
.current_power_state_index
) {
178 rdev
->pm
.requested_power_state_index
=
179 rdev
->pm
.current_power_state_index
;
182 rdev
->pm
.requested_power_state_index
= i
;
187 rdev
->pm
.requested_power_state_index
=
188 rdev
->pm
.current_power_state_index
+ 1;
190 rdev
->pm
.requested_clock_mode_index
= 0;
192 case DYNPM_ACTION_DEFAULT
:
193 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
194 rdev
->pm
.requested_clock_mode_index
= 0;
195 rdev
->pm
.dynpm_can_upclock
= false;
197 case DYNPM_ACTION_NONE
:
199 DRM_ERROR("Requested mode for not defined action\n");
203 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
204 /* for now just select the first power state and switch between clock modes */
205 /* power state array is low to high, default is first (0) */
206 if (rdev
->pm
.active_crtc_count
> 1) {
207 rdev
->pm
.requested_power_state_index
= -1;
208 /* start at 1 as we don't want the default mode */
209 for (i
= 1; i
< rdev
->pm
.num_power_states
; i
++) {
210 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
212 else if ((rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_PERFORMANCE
) ||
213 (rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_BATTERY
)) {
214 rdev
->pm
.requested_power_state_index
= i
;
218 /* if nothing selected, grab the default state. */
219 if (rdev
->pm
.requested_power_state_index
== -1)
220 rdev
->pm
.requested_power_state_index
= 0;
222 rdev
->pm
.requested_power_state_index
= 1;
224 switch (rdev
->pm
.dynpm_planned_action
) {
225 case DYNPM_ACTION_MINIMUM
:
226 rdev
->pm
.requested_clock_mode_index
= 0;
227 rdev
->pm
.dynpm_can_downclock
= false;
229 case DYNPM_ACTION_DOWNCLOCK
:
230 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
231 if (rdev
->pm
.current_clock_mode_index
== 0) {
232 rdev
->pm
.requested_clock_mode_index
= 0;
233 rdev
->pm
.dynpm_can_downclock
= false;
235 rdev
->pm
.requested_clock_mode_index
=
236 rdev
->pm
.current_clock_mode_index
- 1;
238 rdev
->pm
.requested_clock_mode_index
= 0;
239 rdev
->pm
.dynpm_can_downclock
= false;
241 /* don't use the power state if crtcs are active and no display flag is set */
242 if ((rdev
->pm
.active_crtc_count
> 0) &&
243 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
244 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
245 RADEON_PM_MODE_NO_DISPLAY
)) {
246 rdev
->pm
.requested_clock_mode_index
++;
249 case DYNPM_ACTION_UPCLOCK
:
250 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
251 if (rdev
->pm
.current_clock_mode_index
==
252 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1)) {
253 rdev
->pm
.requested_clock_mode_index
= rdev
->pm
.current_clock_mode_index
;
254 rdev
->pm
.dynpm_can_upclock
= false;
256 rdev
->pm
.requested_clock_mode_index
=
257 rdev
->pm
.current_clock_mode_index
+ 1;
259 rdev
->pm
.requested_clock_mode_index
=
260 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1;
261 rdev
->pm
.dynpm_can_upclock
= false;
264 case DYNPM_ACTION_DEFAULT
:
265 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
266 rdev
->pm
.requested_clock_mode_index
= 0;
267 rdev
->pm
.dynpm_can_upclock
= false;
269 case DYNPM_ACTION_NONE
:
271 DRM_ERROR("Requested mode for not defined action\n");
276 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
277 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
278 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
,
279 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
280 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
,
281 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
285 static int r600_pm_get_type_index(struct radeon_device
*rdev
,
286 enum radeon_pm_state_type ps_type
,
290 int found_instance
= -1;
292 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
293 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
295 if (found_instance
== instance
)
299 /* return default if no match */
300 return rdev
->pm
.default_power_state_index
;
303 void rs780_pm_init_profile(struct radeon_device
*rdev
)
305 if (rdev
->pm
.num_power_states
== 2) {
307 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
308 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
309 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
310 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
312 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 0;
313 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 0;
314 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
315 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
317 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 0;
318 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 0;
319 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
320 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
322 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 0;
323 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
324 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
325 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
327 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 0;
328 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
329 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
330 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
332 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 0;
333 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
334 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
335 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
337 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 0;
338 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 1;
339 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
340 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
341 } else if (rdev
->pm
.num_power_states
== 3) {
343 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
344 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
345 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
346 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
348 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
349 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
350 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
351 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
353 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
354 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
355 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
356 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
358 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
359 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 2;
360 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
361 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
363 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 1;
364 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 1;
365 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
366 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
368 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 1;
369 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 1;
370 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
371 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
373 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 1;
374 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
375 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
376 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
379 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
380 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
381 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
382 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
384 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 2;
385 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 2;
386 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
387 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
389 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 2;
390 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 2;
391 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
392 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
394 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 2;
395 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 3;
396 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
397 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
399 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
400 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
401 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
402 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
404 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
405 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
406 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
407 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
409 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
410 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 3;
411 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
412 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
416 void r600_pm_init_profile(struct radeon_device
*rdev
)
418 if (rdev
->family
== CHIP_R600
) {
421 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
422 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
423 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
424 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
426 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
427 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
428 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
429 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
431 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
432 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
433 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
434 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
436 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
437 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
438 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
439 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
441 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
442 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
443 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
444 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
446 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
447 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
448 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
449 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
451 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
452 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
453 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
454 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
456 if (rdev
->pm
.num_power_states
< 4) {
458 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
459 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
460 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
461 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
463 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
464 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
465 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
466 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
468 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
469 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
470 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
471 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
473 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
474 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
475 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
476 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
478 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
479 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 2;
480 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
481 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
483 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
484 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 2;
485 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
486 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
488 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
489 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
490 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
491 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
494 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
495 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
496 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
497 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
499 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
500 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
=
501 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
502 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
=
503 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
504 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
505 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
507 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
=
508 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
509 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
=
510 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
511 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
512 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
515 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
516 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
=
517 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
518 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
=
519 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
520 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
521 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
523 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
=
524 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
525 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
=
526 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
527 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
528 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
531 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
=
532 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
533 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
=
534 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
535 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
536 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
538 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
539 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
=
540 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
541 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
=
542 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
543 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
544 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
546 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
=
547 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
548 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
=
549 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
550 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
551 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
554 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
555 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
=
556 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
557 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
=
558 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
559 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
560 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
562 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
=
563 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
564 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
=
565 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
566 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
567 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
570 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
=
571 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
572 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
=
573 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
574 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
575 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
580 void r600_pm_misc(struct radeon_device
*rdev
)
582 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
583 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
584 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
585 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
587 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
588 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
589 radeon_atom_set_voltage(rdev
, voltage
->voltage
);
590 rdev
->pm
.current_vddc
= voltage
->voltage
;
591 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage
->voltage
);
596 bool r600_gui_idle(struct radeon_device
*rdev
)
598 if (RREG32(GRBM_STATUS
) & GUI_ACTIVE
)
604 /* hpd for digital panel detect/disconnect */
605 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
607 bool connected
= false;
609 if (ASIC_IS_DCE3(rdev
)) {
612 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
616 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
620 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
624 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
629 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
633 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
642 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
646 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
650 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
660 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
661 enum radeon_hpd_id hpd
)
664 bool connected
= r600_hpd_sense(rdev
, hpd
);
666 if (ASIC_IS_DCE3(rdev
)) {
669 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
671 tmp
&= ~DC_HPDx_INT_POLARITY
;
673 tmp
|= DC_HPDx_INT_POLARITY
;
674 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
677 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
679 tmp
&= ~DC_HPDx_INT_POLARITY
;
681 tmp
|= DC_HPDx_INT_POLARITY
;
682 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
685 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
687 tmp
&= ~DC_HPDx_INT_POLARITY
;
689 tmp
|= DC_HPDx_INT_POLARITY
;
690 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
693 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
695 tmp
&= ~DC_HPDx_INT_POLARITY
;
697 tmp
|= DC_HPDx_INT_POLARITY
;
698 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
701 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
703 tmp
&= ~DC_HPDx_INT_POLARITY
;
705 tmp
|= DC_HPDx_INT_POLARITY
;
706 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
710 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
712 tmp
&= ~DC_HPDx_INT_POLARITY
;
714 tmp
|= DC_HPDx_INT_POLARITY
;
715 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
723 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
725 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
727 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
728 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
731 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
733 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
735 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
736 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
739 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
741 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
743 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
744 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
752 void r600_hpd_init(struct radeon_device
*rdev
)
754 struct drm_device
*dev
= rdev
->ddev
;
755 struct drm_connector
*connector
;
757 if (ASIC_IS_DCE3(rdev
)) {
758 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
759 if (ASIC_IS_DCE32(rdev
))
762 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
763 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
764 switch (radeon_connector
->hpd
.hpd
) {
766 WREG32(DC_HPD1_CONTROL
, tmp
);
767 rdev
->irq
.hpd
[0] = true;
770 WREG32(DC_HPD2_CONTROL
, tmp
);
771 rdev
->irq
.hpd
[1] = true;
774 WREG32(DC_HPD3_CONTROL
, tmp
);
775 rdev
->irq
.hpd
[2] = true;
778 WREG32(DC_HPD4_CONTROL
, tmp
);
779 rdev
->irq
.hpd
[3] = true;
783 WREG32(DC_HPD5_CONTROL
, tmp
);
784 rdev
->irq
.hpd
[4] = true;
787 WREG32(DC_HPD6_CONTROL
, tmp
);
788 rdev
->irq
.hpd
[5] = true;
795 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
796 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
797 switch (radeon_connector
->hpd
.hpd
) {
799 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
800 rdev
->irq
.hpd
[0] = true;
803 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
804 rdev
->irq
.hpd
[1] = true;
807 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
808 rdev
->irq
.hpd
[2] = true;
815 if (rdev
->irq
.installed
)
819 void r600_hpd_fini(struct radeon_device
*rdev
)
821 struct drm_device
*dev
= rdev
->ddev
;
822 struct drm_connector
*connector
;
824 if (ASIC_IS_DCE3(rdev
)) {
825 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
826 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
827 switch (radeon_connector
->hpd
.hpd
) {
829 WREG32(DC_HPD1_CONTROL
, 0);
830 rdev
->irq
.hpd
[0] = false;
833 WREG32(DC_HPD2_CONTROL
, 0);
834 rdev
->irq
.hpd
[1] = false;
837 WREG32(DC_HPD3_CONTROL
, 0);
838 rdev
->irq
.hpd
[2] = false;
841 WREG32(DC_HPD4_CONTROL
, 0);
842 rdev
->irq
.hpd
[3] = false;
846 WREG32(DC_HPD5_CONTROL
, 0);
847 rdev
->irq
.hpd
[4] = false;
850 WREG32(DC_HPD6_CONTROL
, 0);
851 rdev
->irq
.hpd
[5] = false;
858 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
859 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
860 switch (radeon_connector
->hpd
.hpd
) {
862 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, 0);
863 rdev
->irq
.hpd
[0] = false;
866 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, 0);
867 rdev
->irq
.hpd
[1] = false;
870 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, 0);
871 rdev
->irq
.hpd
[2] = false;
883 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
888 /* flush hdp cache so updates hit vram */
889 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
890 !(rdev
->flags
& RADEON_IS_AGP
)) {
891 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
894 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
895 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
896 * This seems to cause problems on some AGP cards. Just use the old
899 WREG32(HDP_DEBUG1
, 0);
900 tmp
= readl((void __iomem
*)ptr
);
902 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
904 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR
, rdev
->mc
.gtt_start
>> 12);
905 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (rdev
->mc
.gtt_end
- 1) >> 12);
906 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
907 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
909 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
910 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
912 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
922 int r600_pcie_gart_init(struct radeon_device
*rdev
)
926 if (rdev
->gart
.table
.vram
.robj
) {
927 WARN(1, "R600 PCIE GART already initialized\n");
930 /* Initialize common gart structure */
931 r
= radeon_gart_init(rdev
);
934 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
935 return radeon_gart_table_vram_alloc(rdev
);
938 int r600_pcie_gart_enable(struct radeon_device
*rdev
)
943 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
944 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
947 r
= radeon_gart_table_vram_pin(rdev
);
950 radeon_gart_restore(rdev
);
953 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
954 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
955 EFFECTIVE_L2_QUEUE_SIZE(7));
956 WREG32(VM_L2_CNTL2
, 0);
957 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
958 /* Setup TLB control */
959 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
960 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
961 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
962 ENABLE_WAIT_L2_QUERY
;
963 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
964 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
965 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
966 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
967 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
968 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
969 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
970 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
971 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
972 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
973 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
974 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
975 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
976 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
977 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
978 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
979 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
980 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
981 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
982 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
983 (u32
)(rdev
->dummy_page
.addr
>> 12));
984 for (i
= 1; i
< 7; i
++)
985 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
987 r600_pcie_gart_tlb_flush(rdev
);
988 rdev
->gart
.ready
= true;
992 void r600_pcie_gart_disable(struct radeon_device
*rdev
)
997 /* Disable all tables */
998 for (i
= 0; i
< 7; i
++)
999 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
1001 /* Disable L2 cache */
1002 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
1003 EFFECTIVE_L2_QUEUE_SIZE(7));
1004 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1005 /* Setup L1 TLB control */
1006 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1007 ENABLE_WAIT_L2_QUERY
;
1008 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
1009 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
1010 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
1011 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
1012 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
1013 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
1014 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
1015 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
1016 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
);
1018 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
1020 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
);
1021 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
1022 if (rdev
->gart
.table
.vram
.robj
) {
1023 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
1024 if (likely(r
== 0)) {
1025 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
1026 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
1027 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
1032 void r600_pcie_gart_fini(struct radeon_device
*rdev
)
1034 radeon_gart_fini(rdev
);
1035 r600_pcie_gart_disable(rdev
);
1036 radeon_gart_table_vram_free(rdev
);
1039 void r600_agp_enable(struct radeon_device
*rdev
)
1044 /* Setup L2 cache */
1045 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1046 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1047 EFFECTIVE_L2_QUEUE_SIZE(7));
1048 WREG32(VM_L2_CNTL2
, 0);
1049 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1050 /* Setup TLB control */
1051 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1052 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1053 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1054 ENABLE_WAIT_L2_QUERY
;
1055 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
1056 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
1057 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
1058 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
1059 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
1060 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
1061 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
1062 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
1063 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
1064 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
1065 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
1066 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
1067 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1068 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1069 for (i
= 0; i
< 7; i
++)
1070 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
1073 int r600_mc_wait_for_idle(struct radeon_device
*rdev
)
1078 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1079 /* read MC_STATUS */
1080 tmp
= RREG32(R_000E50_SRBM_STATUS
) & 0x3F00;
1088 static void r600_mc_program(struct radeon_device
*rdev
)
1090 struct rv515_mc_save save
;
1094 /* Initialize HDP */
1095 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1096 WREG32((0x2c14 + j
), 0x00000000);
1097 WREG32((0x2c18 + j
), 0x00000000);
1098 WREG32((0x2c1c + j
), 0x00000000);
1099 WREG32((0x2c20 + j
), 0x00000000);
1100 WREG32((0x2c24 + j
), 0x00000000);
1102 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1104 rv515_mc_stop(rdev
, &save
);
1105 if (r600_mc_wait_for_idle(rdev
)) {
1106 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1108 /* Lockout access through VGA aperture (doesn't exist before R600) */
1109 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1110 /* Update configuration */
1111 if (rdev
->flags
& RADEON_IS_AGP
) {
1112 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1113 /* VRAM before AGP */
1114 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1115 rdev
->mc
.vram_start
>> 12);
1116 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1117 rdev
->mc
.gtt_end
>> 12);
1119 /* VRAM after AGP */
1120 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1121 rdev
->mc
.gtt_start
>> 12);
1122 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1123 rdev
->mc
.vram_end
>> 12);
1126 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
>> 12);
1127 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
>> 12);
1129 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
1130 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1131 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1132 WREG32(MC_VM_FB_LOCATION
, tmp
);
1133 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1134 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
1135 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1136 if (rdev
->flags
& RADEON_IS_AGP
) {
1137 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 22);
1138 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 22);
1139 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1141 WREG32(MC_VM_AGP_BASE
, 0);
1142 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1143 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1145 if (r600_mc_wait_for_idle(rdev
)) {
1146 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1148 rv515_mc_resume(rdev
, &save
);
1149 /* we need to own VRAM, so turn off the VGA renderer here
1150 * to stop it overwriting our objects */
1151 rv515_vga_render_disable(rdev
);
1155 * r600_vram_gtt_location - try to find VRAM & GTT location
1156 * @rdev: radeon device structure holding all necessary informations
1157 * @mc: memory controller structure holding memory informations
1159 * Function will place try to place VRAM at same place as in CPU (PCI)
1160 * address space as some GPU seems to have issue when we reprogram at
1161 * different address space.
1163 * If there is not enough space to fit the unvisible VRAM after the
1164 * aperture then we limit the VRAM size to the aperture.
1166 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1167 * them to be in one from GPU point of view so that we can program GPU to
1168 * catch access outside them (weird GPU policy see ??).
1170 * This function will never fails, worst case are limiting VRAM or GTT.
1172 * Note: GTT start, end, size should be initialized before calling this
1173 * function on AGP platform.
1175 static void r600_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
1177 u64 size_bf
, size_af
;
1179 if (mc
->mc_vram_size
> 0xE0000000) {
1180 /* leave room for at least 512M GTT */
1181 dev_warn(rdev
->dev
, "limiting VRAM\n");
1182 mc
->real_vram_size
= 0xE0000000;
1183 mc
->mc_vram_size
= 0xE0000000;
1185 if (rdev
->flags
& RADEON_IS_AGP
) {
1186 size_bf
= mc
->gtt_start
;
1187 size_af
= 0xFFFFFFFF - mc
->gtt_end
+ 1;
1188 if (size_bf
> size_af
) {
1189 if (mc
->mc_vram_size
> size_bf
) {
1190 dev_warn(rdev
->dev
, "limiting VRAM\n");
1191 mc
->real_vram_size
= size_bf
;
1192 mc
->mc_vram_size
= size_bf
;
1194 mc
->vram_start
= mc
->gtt_start
- mc
->mc_vram_size
;
1196 if (mc
->mc_vram_size
> size_af
) {
1197 dev_warn(rdev
->dev
, "limiting VRAM\n");
1198 mc
->real_vram_size
= size_af
;
1199 mc
->mc_vram_size
= size_af
;
1201 mc
->vram_start
= mc
->gtt_end
;
1203 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
1204 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1205 mc
->mc_vram_size
>> 20, mc
->vram_start
,
1206 mc
->vram_end
, mc
->real_vram_size
>> 20);
1209 if (rdev
->flags
& RADEON_IS_IGP
) {
1210 base
= RREG32(MC_VM_FB_LOCATION
) & 0xFFFF;
1213 radeon_vram_location(rdev
, &rdev
->mc
, base
);
1214 rdev
->mc
.gtt_base_align
= 0;
1215 radeon_gtt_location(rdev
, mc
);
1219 int r600_mc_init(struct radeon_device
*rdev
)
1222 int chansize
, numchan
;
1224 /* Get VRAM informations */
1225 rdev
->mc
.vram_is_ddr
= true;
1226 tmp
= RREG32(RAMCFG
);
1227 if (tmp
& CHANSIZE_OVERRIDE
) {
1229 } else if (tmp
& CHANSIZE_MASK
) {
1234 tmp
= RREG32(CHMAP
);
1235 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1250 rdev
->mc
.vram_width
= numchan
* chansize
;
1251 /* Could aper size report 0 ? */
1252 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
1253 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
1254 /* Setup GPU memory space */
1255 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
1256 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
1257 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1258 rdev
->mc
.active_vram_size
= rdev
->mc
.visible_vram_size
;
1259 r600_vram_gtt_location(rdev
, &rdev
->mc
);
1261 if (rdev
->flags
& RADEON_IS_IGP
) {
1262 rs690_pm_info(rdev
);
1263 rdev
->mc
.igp_sideport_enabled
= radeon_atombios_sideport_present(rdev
);
1265 radeon_update_bandwidth_info(rdev
);
1269 /* We doesn't check that the GPU really needs a reset we simply do the
1270 * reset, it's up to the caller to determine if the GPU needs one. We
1271 * might add an helper function to check that.
1273 int r600_gpu_soft_reset(struct radeon_device
*rdev
)
1275 struct rv515_mc_save save
;
1276 u32 grbm_busy_mask
= S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1277 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1278 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1279 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1280 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1281 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1282 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1283 S_008010_GUI_ACTIVE(1);
1284 u32 grbm2_busy_mask
= S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1285 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1286 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1287 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1288 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1289 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1290 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1291 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1294 if (!(RREG32(GRBM_STATUS
) & GUI_ACTIVE
))
1297 dev_info(rdev
->dev
, "GPU softreset \n");
1298 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
1299 RREG32(R_008010_GRBM_STATUS
));
1300 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
1301 RREG32(R_008014_GRBM_STATUS2
));
1302 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
1303 RREG32(R_000E50_SRBM_STATUS
));
1304 rv515_mc_stop(rdev
, &save
);
1305 if (r600_mc_wait_for_idle(rdev
)) {
1306 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1308 /* Disable CP parsing/prefetching */
1309 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1310 /* Check if any of the rendering block is busy and reset it */
1311 if ((RREG32(R_008010_GRBM_STATUS
) & grbm_busy_mask
) ||
1312 (RREG32(R_008014_GRBM_STATUS2
) & grbm2_busy_mask
)) {
1313 tmp
= S_008020_SOFT_RESET_CR(1) |
1314 S_008020_SOFT_RESET_DB(1) |
1315 S_008020_SOFT_RESET_CB(1) |
1316 S_008020_SOFT_RESET_PA(1) |
1317 S_008020_SOFT_RESET_SC(1) |
1318 S_008020_SOFT_RESET_SMX(1) |
1319 S_008020_SOFT_RESET_SPI(1) |
1320 S_008020_SOFT_RESET_SX(1) |
1321 S_008020_SOFT_RESET_SH(1) |
1322 S_008020_SOFT_RESET_TC(1) |
1323 S_008020_SOFT_RESET_TA(1) |
1324 S_008020_SOFT_RESET_VC(1) |
1325 S_008020_SOFT_RESET_VGT(1);
1326 dev_info(rdev
->dev
, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1327 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1328 RREG32(R_008020_GRBM_SOFT_RESET
);
1330 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
1332 /* Reset CP (we always reset CP) */
1333 tmp
= S_008020_SOFT_RESET_CP(1);
1334 dev_info(rdev
->dev
, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1335 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1336 RREG32(R_008020_GRBM_SOFT_RESET
);
1338 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
1339 /* Wait a little for things to settle down */
1341 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
1342 RREG32(R_008010_GRBM_STATUS
));
1343 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
1344 RREG32(R_008014_GRBM_STATUS2
));
1345 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
1346 RREG32(R_000E50_SRBM_STATUS
));
1347 rv515_mc_resume(rdev
, &save
);
1351 bool r600_gpu_is_lockup(struct radeon_device
*rdev
)
1356 struct r100_gpu_lockup
*lockup
;
1359 if (rdev
->family
>= CHIP_RV770
)
1360 lockup
= &rdev
->config
.rv770
.lockup
;
1362 lockup
= &rdev
->config
.r600
.lockup
;
1364 srbm_status
= RREG32(R_000E50_SRBM_STATUS
);
1365 grbm_status
= RREG32(R_008010_GRBM_STATUS
);
1366 grbm_status2
= RREG32(R_008014_GRBM_STATUS2
);
1367 if (!G_008010_GUI_ACTIVE(grbm_status
)) {
1368 r100_gpu_lockup_update(lockup
, &rdev
->cp
);
1371 /* force CP activities */
1372 r
= radeon_ring_lock(rdev
, 2);
1375 radeon_ring_write(rdev
, 0x80000000);
1376 radeon_ring_write(rdev
, 0x80000000);
1377 radeon_ring_unlock_commit(rdev
);
1379 rdev
->cp
.rptr
= RREG32(R600_CP_RB_RPTR
);
1380 return r100_gpu_cp_is_lockup(rdev
, lockup
, &rdev
->cp
);
1383 int r600_asic_reset(struct radeon_device
*rdev
)
1385 return r600_gpu_soft_reset(rdev
);
1388 static u32
r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
1390 u32 backend_disable_mask
)
1392 u32 backend_map
= 0;
1393 u32 enabled_backends_mask
;
1394 u32 enabled_backends_count
;
1396 u32 swizzle_pipe
[R6XX_MAX_PIPES
];
1400 if (num_tile_pipes
> R6XX_MAX_PIPES
)
1401 num_tile_pipes
= R6XX_MAX_PIPES
;
1402 if (num_tile_pipes
< 1)
1404 if (num_backends
> R6XX_MAX_BACKENDS
)
1405 num_backends
= R6XX_MAX_BACKENDS
;
1406 if (num_backends
< 1)
1409 enabled_backends_mask
= 0;
1410 enabled_backends_count
= 0;
1411 for (i
= 0; i
< R6XX_MAX_BACKENDS
; ++i
) {
1412 if (((backend_disable_mask
>> i
) & 1) == 0) {
1413 enabled_backends_mask
|= (1 << i
);
1414 ++enabled_backends_count
;
1416 if (enabled_backends_count
== num_backends
)
1420 if (enabled_backends_count
== 0) {
1421 enabled_backends_mask
= 1;
1422 enabled_backends_count
= 1;
1425 if (enabled_backends_count
!= num_backends
)
1426 num_backends
= enabled_backends_count
;
1428 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R6XX_MAX_PIPES
);
1429 switch (num_tile_pipes
) {
1431 swizzle_pipe
[0] = 0;
1434 swizzle_pipe
[0] = 0;
1435 swizzle_pipe
[1] = 1;
1438 swizzle_pipe
[0] = 0;
1439 swizzle_pipe
[1] = 1;
1440 swizzle_pipe
[2] = 2;
1443 swizzle_pipe
[0] = 0;
1444 swizzle_pipe
[1] = 1;
1445 swizzle_pipe
[2] = 2;
1446 swizzle_pipe
[3] = 3;
1449 swizzle_pipe
[0] = 0;
1450 swizzle_pipe
[1] = 1;
1451 swizzle_pipe
[2] = 2;
1452 swizzle_pipe
[3] = 3;
1453 swizzle_pipe
[4] = 4;
1456 swizzle_pipe
[0] = 0;
1457 swizzle_pipe
[1] = 2;
1458 swizzle_pipe
[2] = 4;
1459 swizzle_pipe
[3] = 5;
1460 swizzle_pipe
[4] = 1;
1461 swizzle_pipe
[5] = 3;
1464 swizzle_pipe
[0] = 0;
1465 swizzle_pipe
[1] = 2;
1466 swizzle_pipe
[2] = 4;
1467 swizzle_pipe
[3] = 6;
1468 swizzle_pipe
[4] = 1;
1469 swizzle_pipe
[5] = 3;
1470 swizzle_pipe
[6] = 5;
1473 swizzle_pipe
[0] = 0;
1474 swizzle_pipe
[1] = 2;
1475 swizzle_pipe
[2] = 4;
1476 swizzle_pipe
[3] = 6;
1477 swizzle_pipe
[4] = 1;
1478 swizzle_pipe
[5] = 3;
1479 swizzle_pipe
[6] = 5;
1480 swizzle_pipe
[7] = 7;
1485 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
1486 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
1487 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
1489 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
1491 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
1497 int r600_count_pipe_bits(uint32_t val
)
1501 for (i
= 0; i
< 32; i
++) {
1508 void r600_gpu_init(struct radeon_device
*rdev
)
1513 u32 cc_rb_backend_disable
;
1514 u32 cc_gc_shader_pipe_config
;
1518 u32 sq_gpr_resource_mgmt_1
= 0;
1519 u32 sq_gpr_resource_mgmt_2
= 0;
1520 u32 sq_thread_resource_mgmt
= 0;
1521 u32 sq_stack_resource_mgmt_1
= 0;
1522 u32 sq_stack_resource_mgmt_2
= 0;
1524 /* FIXME: implement */
1525 switch (rdev
->family
) {
1527 rdev
->config
.r600
.max_pipes
= 4;
1528 rdev
->config
.r600
.max_tile_pipes
= 8;
1529 rdev
->config
.r600
.max_simds
= 4;
1530 rdev
->config
.r600
.max_backends
= 4;
1531 rdev
->config
.r600
.max_gprs
= 256;
1532 rdev
->config
.r600
.max_threads
= 192;
1533 rdev
->config
.r600
.max_stack_entries
= 256;
1534 rdev
->config
.r600
.max_hw_contexts
= 8;
1535 rdev
->config
.r600
.max_gs_threads
= 16;
1536 rdev
->config
.r600
.sx_max_export_size
= 128;
1537 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1538 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1539 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1543 rdev
->config
.r600
.max_pipes
= 2;
1544 rdev
->config
.r600
.max_tile_pipes
= 2;
1545 rdev
->config
.r600
.max_simds
= 3;
1546 rdev
->config
.r600
.max_backends
= 1;
1547 rdev
->config
.r600
.max_gprs
= 128;
1548 rdev
->config
.r600
.max_threads
= 192;
1549 rdev
->config
.r600
.max_stack_entries
= 128;
1550 rdev
->config
.r600
.max_hw_contexts
= 8;
1551 rdev
->config
.r600
.max_gs_threads
= 4;
1552 rdev
->config
.r600
.sx_max_export_size
= 128;
1553 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1554 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1555 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1561 rdev
->config
.r600
.max_pipes
= 1;
1562 rdev
->config
.r600
.max_tile_pipes
= 1;
1563 rdev
->config
.r600
.max_simds
= 2;
1564 rdev
->config
.r600
.max_backends
= 1;
1565 rdev
->config
.r600
.max_gprs
= 128;
1566 rdev
->config
.r600
.max_threads
= 192;
1567 rdev
->config
.r600
.max_stack_entries
= 128;
1568 rdev
->config
.r600
.max_hw_contexts
= 4;
1569 rdev
->config
.r600
.max_gs_threads
= 4;
1570 rdev
->config
.r600
.sx_max_export_size
= 128;
1571 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1572 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1573 rdev
->config
.r600
.sq_num_cf_insts
= 1;
1576 rdev
->config
.r600
.max_pipes
= 4;
1577 rdev
->config
.r600
.max_tile_pipes
= 4;
1578 rdev
->config
.r600
.max_simds
= 4;
1579 rdev
->config
.r600
.max_backends
= 4;
1580 rdev
->config
.r600
.max_gprs
= 192;
1581 rdev
->config
.r600
.max_threads
= 192;
1582 rdev
->config
.r600
.max_stack_entries
= 256;
1583 rdev
->config
.r600
.max_hw_contexts
= 8;
1584 rdev
->config
.r600
.max_gs_threads
= 16;
1585 rdev
->config
.r600
.sx_max_export_size
= 128;
1586 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1587 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1588 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1594 /* Initialize HDP */
1595 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1596 WREG32((0x2c14 + j
), 0x00000000);
1597 WREG32((0x2c18 + j
), 0x00000000);
1598 WREG32((0x2c1c + j
), 0x00000000);
1599 WREG32((0x2c20 + j
), 0x00000000);
1600 WREG32((0x2c24 + j
), 0x00000000);
1603 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1607 ramcfg
= RREG32(RAMCFG
);
1608 switch (rdev
->config
.r600
.max_tile_pipes
) {
1610 tiling_config
|= PIPE_TILING(0);
1613 tiling_config
|= PIPE_TILING(1);
1616 tiling_config
|= PIPE_TILING(2);
1619 tiling_config
|= PIPE_TILING(3);
1624 rdev
->config
.r600
.tiling_npipes
= rdev
->config
.r600
.max_tile_pipes
;
1625 rdev
->config
.r600
.tiling_nbanks
= 4 << ((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1626 tiling_config
|= BANK_TILING((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1627 tiling_config
|= GROUP_SIZE((ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1628 if ((ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
)
1629 rdev
->config
.r600
.tiling_group_size
= 512;
1631 rdev
->config
.r600
.tiling_group_size
= 256;
1632 tmp
= (ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
1634 tiling_config
|= ROW_TILING(3);
1635 tiling_config
|= SAMPLE_SPLIT(3);
1637 tiling_config
|= ROW_TILING(tmp
);
1638 tiling_config
|= SAMPLE_SPLIT(tmp
);
1640 tiling_config
|= BANK_SWAPS(1);
1642 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
1643 cc_rb_backend_disable
|=
1644 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK
<< rdev
->config
.r600
.max_backends
) & R6XX_MAX_BACKENDS_MASK
);
1646 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
1647 cc_gc_shader_pipe_config
|=
1648 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK
<< rdev
->config
.r600
.max_pipes
) & R6XX_MAX_PIPES_MASK
);
1649 cc_gc_shader_pipe_config
|=
1650 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK
<< rdev
->config
.r600
.max_simds
) & R6XX_MAX_SIMDS_MASK
);
1652 backend_map
= r600_get_tile_pipe_to_backend_map(rdev
->config
.r600
.max_tile_pipes
,
1653 (R6XX_MAX_BACKENDS
-
1654 r600_count_pipe_bits((cc_rb_backend_disable
&
1655 R6XX_MAX_BACKENDS_MASK
) >> 16)),
1656 (cc_rb_backend_disable
>> 16));
1657 rdev
->config
.r600
.tile_config
= tiling_config
;
1658 tiling_config
|= BACKEND_MAP(backend_map
);
1659 WREG32(GB_TILING_CONFIG
, tiling_config
);
1660 WREG32(DCP_TILING_CONFIG
, tiling_config
& 0xffff);
1661 WREG32(HDP_TILING_CONFIG
, tiling_config
& 0xffff);
1664 WREG32(CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1665 WREG32(CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1666 WREG32(GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1668 tmp
= R6XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
1669 WREG32(VGT_OUT_DEALLOC_CNTL
, (tmp
* 4) & DEALLOC_DIST_MASK
);
1670 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((tmp
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
1672 /* Setup some CP states */
1673 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1674 WREG32(CP_MEQ_THRESHOLDS
, (MEQ_END(0x40) | ROQ_END(0x40)));
1676 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
| SYNC_GRADIENT
|
1677 SYNC_WALKER
| SYNC_ALIGNER
));
1678 /* Setup various GPU states */
1679 if (rdev
->family
== CHIP_RV670
)
1680 WREG32(ARB_GDEC_RD_CNTL
, 0x00000021);
1682 tmp
= RREG32(SX_DEBUG_1
);
1683 tmp
|= SMX_EVENT_RELEASE
;
1684 if ((rdev
->family
> CHIP_R600
))
1685 tmp
|= ENABLE_NEW_SMX_ADDRESS
;
1686 WREG32(SX_DEBUG_1
, tmp
);
1688 if (((rdev
->family
) == CHIP_R600
) ||
1689 ((rdev
->family
) == CHIP_RV630
) ||
1690 ((rdev
->family
) == CHIP_RV610
) ||
1691 ((rdev
->family
) == CHIP_RV620
) ||
1692 ((rdev
->family
) == CHIP_RS780
) ||
1693 ((rdev
->family
) == CHIP_RS880
)) {
1694 WREG32(DB_DEBUG
, PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
1696 WREG32(DB_DEBUG
, 0);
1698 WREG32(DB_WATERMARKS
, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1699 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1701 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1702 WREG32(VGT_NUM_INSTANCES
, 0);
1704 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
1705 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(0));
1707 tmp
= RREG32(SQ_MS_FIFO_SIZES
);
1708 if (((rdev
->family
) == CHIP_RV610
) ||
1709 ((rdev
->family
) == CHIP_RV620
) ||
1710 ((rdev
->family
) == CHIP_RS780
) ||
1711 ((rdev
->family
) == CHIP_RS880
)) {
1712 tmp
= (CACHE_FIFO_SIZE(0xa) |
1713 FETCH_FIFO_HIWATER(0xa) |
1714 DONE_FIFO_HIWATER(0xe0) |
1715 ALU_UPDATE_FIFO_HIWATER(0x8));
1716 } else if (((rdev
->family
) == CHIP_R600
) ||
1717 ((rdev
->family
) == CHIP_RV630
)) {
1718 tmp
&= ~DONE_FIFO_HIWATER(0xff);
1719 tmp
|= DONE_FIFO_HIWATER(0x4);
1721 WREG32(SQ_MS_FIFO_SIZES
, tmp
);
1723 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1724 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1726 sq_config
= RREG32(SQ_CONFIG
);
1727 sq_config
&= ~(PS_PRIO(3) |
1731 sq_config
|= (DX9_CONSTS
|
1738 if ((rdev
->family
) == CHIP_R600
) {
1739 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(124) |
1741 NUM_CLAUSE_TEMP_GPRS(4));
1742 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(0) |
1744 sq_thread_resource_mgmt
= (NUM_PS_THREADS(136) |
1745 NUM_VS_THREADS(48) |
1748 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(128) |
1749 NUM_VS_STACK_ENTRIES(128));
1750 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(0) |
1751 NUM_ES_STACK_ENTRIES(0));
1752 } else if (((rdev
->family
) == CHIP_RV610
) ||
1753 ((rdev
->family
) == CHIP_RV620
) ||
1754 ((rdev
->family
) == CHIP_RS780
) ||
1755 ((rdev
->family
) == CHIP_RS880
)) {
1756 /* no vertex cache */
1757 sq_config
&= ~VC_ENABLE
;
1759 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1761 NUM_CLAUSE_TEMP_GPRS(2));
1762 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1764 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1765 NUM_VS_THREADS(78) |
1767 NUM_ES_THREADS(31));
1768 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1769 NUM_VS_STACK_ENTRIES(40));
1770 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1771 NUM_ES_STACK_ENTRIES(16));
1772 } else if (((rdev
->family
) == CHIP_RV630
) ||
1773 ((rdev
->family
) == CHIP_RV635
)) {
1774 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1776 NUM_CLAUSE_TEMP_GPRS(2));
1777 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(18) |
1779 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1780 NUM_VS_THREADS(78) |
1782 NUM_ES_THREADS(31));
1783 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1784 NUM_VS_STACK_ENTRIES(40));
1785 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1786 NUM_ES_STACK_ENTRIES(16));
1787 } else if ((rdev
->family
) == CHIP_RV670
) {
1788 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1790 NUM_CLAUSE_TEMP_GPRS(2));
1791 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1793 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1794 NUM_VS_THREADS(78) |
1796 NUM_ES_THREADS(31));
1797 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(64) |
1798 NUM_VS_STACK_ENTRIES(64));
1799 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(64) |
1800 NUM_ES_STACK_ENTRIES(64));
1803 WREG32(SQ_CONFIG
, sq_config
);
1804 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1805 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1806 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1807 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1808 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1810 if (((rdev
->family
) == CHIP_RV610
) ||
1811 ((rdev
->family
) == CHIP_RV620
) ||
1812 ((rdev
->family
) == CHIP_RS780
) ||
1813 ((rdev
->family
) == CHIP_RS880
)) {
1814 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(TC_ONLY
));
1816 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
));
1819 /* More default values. 2D/3D driver should adjust as needed */
1820 WREG32(PA_SC_AA_SAMPLE_LOCS_2S
, (S0_X(0xc) | S0_Y(0x4) |
1821 S1_X(0x4) | S1_Y(0xc)));
1822 WREG32(PA_SC_AA_SAMPLE_LOCS_4S
, (S0_X(0xe) | S0_Y(0xe) |
1823 S1_X(0x2) | S1_Y(0x2) |
1824 S2_X(0xa) | S2_Y(0x6) |
1825 S3_X(0x6) | S3_Y(0xa)));
1826 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (S0_X(0xe) | S0_Y(0xb) |
1827 S1_X(0x4) | S1_Y(0xc) |
1828 S2_X(0x1) | S2_Y(0x6) |
1829 S3_X(0xa) | S3_Y(0xe)));
1830 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (S4_X(0x6) | S4_Y(0x1) |
1831 S5_X(0x0) | S5_Y(0x0) |
1832 S6_X(0xb) | S6_Y(0x4) |
1833 S7_X(0x7) | S7_Y(0x8)));
1835 WREG32(VGT_STRMOUT_EN
, 0);
1836 tmp
= rdev
->config
.r600
.max_pipes
* 16;
1837 switch (rdev
->family
) {
1853 WREG32(VGT_ES_PER_GS
, 128);
1854 WREG32(VGT_GS_PER_ES
, tmp
);
1855 WREG32(VGT_GS_PER_VS
, 2);
1856 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1858 /* more default values. 2D/3D driver should adjust as needed */
1859 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1860 WREG32(VGT_STRMOUT_EN
, 0);
1862 WREG32(PA_SC_MODE_CNTL
, 0);
1863 WREG32(PA_SC_AA_CONFIG
, 0);
1864 WREG32(PA_SC_LINE_STIPPLE
, 0);
1865 WREG32(SPI_INPUT_Z
, 0);
1866 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
1867 WREG32(CB_COLOR7_FRAG
, 0);
1869 /* Clear render buffer base addresses */
1870 WREG32(CB_COLOR0_BASE
, 0);
1871 WREG32(CB_COLOR1_BASE
, 0);
1872 WREG32(CB_COLOR2_BASE
, 0);
1873 WREG32(CB_COLOR3_BASE
, 0);
1874 WREG32(CB_COLOR4_BASE
, 0);
1875 WREG32(CB_COLOR5_BASE
, 0);
1876 WREG32(CB_COLOR6_BASE
, 0);
1877 WREG32(CB_COLOR7_BASE
, 0);
1878 WREG32(CB_COLOR7_FRAG
, 0);
1880 switch (rdev
->family
) {
1885 tmp
= TC_L2_SIZE(8);
1889 tmp
= TC_L2_SIZE(4);
1892 tmp
= TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT
;
1895 tmp
= TC_L2_SIZE(0);
1898 WREG32(TC_CNTL
, tmp
);
1900 tmp
= RREG32(HDP_HOST_PATH_CNTL
);
1901 WREG32(HDP_HOST_PATH_CNTL
, tmp
);
1903 tmp
= RREG32(ARB_POP
);
1904 tmp
|= ENABLE_TC128
;
1905 WREG32(ARB_POP
, tmp
);
1907 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1908 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
1910 WREG32(PA_SC_ENHANCE
, FORCE_EOV_MAX_CLK_CNT(4095));
1915 * Indirect registers accessor
1917 u32
r600_pciep_rreg(struct radeon_device
*rdev
, u32 reg
)
1921 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1922 (void)RREG32(PCIE_PORT_INDEX
);
1923 r
= RREG32(PCIE_PORT_DATA
);
1927 void r600_pciep_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
1929 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1930 (void)RREG32(PCIE_PORT_INDEX
);
1931 WREG32(PCIE_PORT_DATA
, (v
));
1932 (void)RREG32(PCIE_PORT_DATA
);
1938 void r600_cp_stop(struct radeon_device
*rdev
)
1940 rdev
->mc
.active_vram_size
= rdev
->mc
.visible_vram_size
;
1941 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1942 WREG32(SCRATCH_UMSK
, 0);
1945 int r600_init_microcode(struct radeon_device
*rdev
)
1947 struct platform_device
*pdev
;
1948 const char *chip_name
;
1949 const char *rlc_chip_name
;
1950 size_t pfp_req_size
, me_req_size
, rlc_req_size
;
1956 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
1959 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
1963 switch (rdev
->family
) {
1966 rlc_chip_name
= "R600";
1969 chip_name
= "RV610";
1970 rlc_chip_name
= "R600";
1973 chip_name
= "RV630";
1974 rlc_chip_name
= "R600";
1977 chip_name
= "RV620";
1978 rlc_chip_name
= "R600";
1981 chip_name
= "RV635";
1982 rlc_chip_name
= "R600";
1985 chip_name
= "RV670";
1986 rlc_chip_name
= "R600";
1990 chip_name
= "RS780";
1991 rlc_chip_name
= "R600";
1994 chip_name
= "RV770";
1995 rlc_chip_name
= "R700";
1999 chip_name
= "RV730";
2000 rlc_chip_name
= "R700";
2003 chip_name
= "RV710";
2004 rlc_chip_name
= "R700";
2007 chip_name
= "CEDAR";
2008 rlc_chip_name
= "CEDAR";
2011 chip_name
= "REDWOOD";
2012 rlc_chip_name
= "REDWOOD";
2015 chip_name
= "JUNIPER";
2016 rlc_chip_name
= "JUNIPER";
2020 chip_name
= "CYPRESS";
2021 rlc_chip_name
= "CYPRESS";
2025 rlc_chip_name
= "SUMO";
2030 if (rdev
->family
>= CHIP_CEDAR
) {
2031 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
2032 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
2033 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
2034 } else if (rdev
->family
>= CHIP_RV770
) {
2035 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
2036 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
2037 rlc_req_size
= R700_RLC_UCODE_SIZE
* 4;
2039 pfp_req_size
= PFP_UCODE_SIZE
* 4;
2040 me_req_size
= PM4_UCODE_SIZE
* 12;
2041 rlc_req_size
= RLC_UCODE_SIZE
* 4;
2044 DRM_INFO("Loading %s Microcode\n", chip_name
);
2046 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
2047 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, &pdev
->dev
);
2050 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
2052 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2053 rdev
->pfp_fw
->size
, fw_name
);
2058 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
2059 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
2062 if (rdev
->me_fw
->size
!= me_req_size
) {
2064 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2065 rdev
->me_fw
->size
, fw_name
);
2069 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
2070 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, &pdev
->dev
);
2073 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
2075 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2076 rdev
->rlc_fw
->size
, fw_name
);
2081 platform_device_unregister(pdev
);
2086 "r600_cp: Failed to load firmware \"%s\"\n",
2088 release_firmware(rdev
->pfp_fw
);
2089 rdev
->pfp_fw
= NULL
;
2090 release_firmware(rdev
->me_fw
);
2092 release_firmware(rdev
->rlc_fw
);
2093 rdev
->rlc_fw
= NULL
;
2098 static int r600_cp_load_microcode(struct radeon_device
*rdev
)
2100 const __be32
*fw_data
;
2103 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
2108 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
2111 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2112 RREG32(GRBM_SOFT_RESET
);
2114 WREG32(GRBM_SOFT_RESET
, 0);
2116 WREG32(CP_ME_RAM_WADDR
, 0);
2118 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
2119 WREG32(CP_ME_RAM_WADDR
, 0);
2120 for (i
= 0; i
< PM4_UCODE_SIZE
* 3; i
++)
2121 WREG32(CP_ME_RAM_DATA
,
2122 be32_to_cpup(fw_data
++));
2124 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
2125 WREG32(CP_PFP_UCODE_ADDR
, 0);
2126 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
2127 WREG32(CP_PFP_UCODE_DATA
,
2128 be32_to_cpup(fw_data
++));
2130 WREG32(CP_PFP_UCODE_ADDR
, 0);
2131 WREG32(CP_ME_RAM_WADDR
, 0);
2132 WREG32(CP_ME_RAM_RADDR
, 0);
2136 int r600_cp_start(struct radeon_device
*rdev
)
2141 r
= radeon_ring_lock(rdev
, 7);
2143 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2146 radeon_ring_write(rdev
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
2147 radeon_ring_write(rdev
, 0x1);
2148 if (rdev
->family
>= CHIP_RV770
) {
2149 radeon_ring_write(rdev
, 0x0);
2150 radeon_ring_write(rdev
, rdev
->config
.rv770
.max_hw_contexts
- 1);
2152 radeon_ring_write(rdev
, 0x3);
2153 radeon_ring_write(rdev
, rdev
->config
.r600
.max_hw_contexts
- 1);
2155 radeon_ring_write(rdev
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2156 radeon_ring_write(rdev
, 0);
2157 radeon_ring_write(rdev
, 0);
2158 radeon_ring_unlock_commit(rdev
);
2161 WREG32(R_0086D8_CP_ME_CNTL
, cp_me
);
2165 int r600_cp_resume(struct radeon_device
*rdev
)
2172 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2173 RREG32(GRBM_SOFT_RESET
);
2175 WREG32(GRBM_SOFT_RESET
, 0);
2177 /* Set ring buffer size */
2178 rb_bufsz
= drm_order(rdev
->cp
.ring_size
/ 8);
2179 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2181 tmp
|= BUF_SWAP_32BIT
;
2183 WREG32(CP_RB_CNTL
, tmp
);
2184 WREG32(CP_SEM_WAIT_TIMER
, 0x4);
2186 /* Set the write pointer delay */
2187 WREG32(CP_RB_WPTR_DELAY
, 0);
2189 /* Initialize the ring buffer's read and write pointers */
2190 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2191 WREG32(CP_RB_RPTR_WR
, 0);
2192 WREG32(CP_RB_WPTR
, 0);
2194 /* set the wb address whether it's enabled or not */
2195 WREG32(CP_RB_RPTR_ADDR
, (rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC);
2196 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
2197 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
2199 if (rdev
->wb
.enabled
)
2200 WREG32(SCRATCH_UMSK
, 0xff);
2202 tmp
|= RB_NO_UPDATE
;
2203 WREG32(SCRATCH_UMSK
, 0);
2207 WREG32(CP_RB_CNTL
, tmp
);
2209 WREG32(CP_RB_BASE
, rdev
->cp
.gpu_addr
>> 8);
2210 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
2212 rdev
->cp
.rptr
= RREG32(CP_RB_RPTR
);
2213 rdev
->cp
.wptr
= RREG32(CP_RB_WPTR
);
2215 r600_cp_start(rdev
);
2216 rdev
->cp
.ready
= true;
2217 r
= radeon_ring_test(rdev
);
2219 rdev
->cp
.ready
= false;
2225 void r600_cp_commit(struct radeon_device
*rdev
)
2227 WREG32(CP_RB_WPTR
, rdev
->cp
.wptr
);
2228 (void)RREG32(CP_RB_WPTR
);
2231 void r600_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
2235 /* Align ring size */
2236 rb_bufsz
= drm_order(ring_size
/ 8);
2237 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
2238 rdev
->cp
.ring_size
= ring_size
;
2239 rdev
->cp
.align_mask
= 16 - 1;
2242 void r600_cp_fini(struct radeon_device
*rdev
)
2245 radeon_ring_fini(rdev
);
2250 * GPU scratch registers helpers function.
2252 void r600_scratch_init(struct radeon_device
*rdev
)
2256 rdev
->scratch
.num_reg
= 7;
2257 rdev
->scratch
.reg_base
= SCRATCH_REG0
;
2258 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
2259 rdev
->scratch
.free
[i
] = true;
2260 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
2264 int r600_ring_test(struct radeon_device
*rdev
)
2271 r
= radeon_scratch_get(rdev
, &scratch
);
2273 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
2276 WREG32(scratch
, 0xCAFEDEAD);
2277 r
= radeon_ring_lock(rdev
, 3);
2279 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2280 radeon_scratch_free(rdev
, scratch
);
2283 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2284 radeon_ring_write(rdev
, ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2285 radeon_ring_write(rdev
, 0xDEADBEEF);
2286 radeon_ring_unlock_commit(rdev
);
2287 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2288 tmp
= RREG32(scratch
);
2289 if (tmp
== 0xDEADBEEF)
2293 if (i
< rdev
->usec_timeout
) {
2294 DRM_INFO("ring test succeeded in %d usecs\n", i
);
2296 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2300 radeon_scratch_free(rdev
, scratch
);
2304 void r600_fence_ring_emit(struct radeon_device
*rdev
,
2305 struct radeon_fence
*fence
)
2307 if (rdev
->wb
.use_event
) {
2308 u64 addr
= rdev
->wb
.gpu_addr
+ R600_WB_EVENT_OFFSET
+
2309 (u64
)(rdev
->fence_drv
.scratch_reg
- rdev
->scratch
.reg_base
);
2310 /* EVENT_WRITE_EOP - flush caches, send int */
2311 radeon_ring_write(rdev
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2312 radeon_ring_write(rdev
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS
) | EVENT_INDEX(5));
2313 radeon_ring_write(rdev
, addr
& 0xffffffff);
2314 radeon_ring_write(rdev
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2315 radeon_ring_write(rdev
, fence
->seq
);
2316 radeon_ring_write(rdev
, 0);
2318 radeon_ring_write(rdev
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2319 radeon_ring_write(rdev
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0));
2320 /* wait for 3D idle clean */
2321 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2322 radeon_ring_write(rdev
, (WAIT_UNTIL
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2323 radeon_ring_write(rdev
, WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
2324 /* Emit fence sequence & fire IRQ */
2325 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2326 radeon_ring_write(rdev
, ((rdev
->fence_drv
.scratch_reg
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2327 radeon_ring_write(rdev
, fence
->seq
);
2328 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2329 radeon_ring_write(rdev
, PACKET0(CP_INT_STATUS
, 0));
2330 radeon_ring_write(rdev
, RB_INT_STAT
);
2334 int r600_copy_blit(struct radeon_device
*rdev
,
2335 uint64_t src_offset
, uint64_t dst_offset
,
2336 unsigned num_pages
, struct radeon_fence
*fence
)
2340 mutex_lock(&rdev
->r600_blit
.mutex
);
2341 rdev
->r600_blit
.vb_ib
= NULL
;
2342 r
= r600_blit_prepare_copy(rdev
, num_pages
* RADEON_GPU_PAGE_SIZE
);
2344 if (rdev
->r600_blit
.vb_ib
)
2345 radeon_ib_free(rdev
, &rdev
->r600_blit
.vb_ib
);
2346 mutex_unlock(&rdev
->r600_blit
.mutex
);
2349 r600_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_pages
* RADEON_GPU_PAGE_SIZE
);
2350 r600_blit_done_copy(rdev
, fence
);
2351 mutex_unlock(&rdev
->r600_blit
.mutex
);
2355 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
2356 uint32_t tiling_flags
, uint32_t pitch
,
2357 uint32_t offset
, uint32_t obj_size
)
2359 /* FIXME: implement */
2363 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
2365 /* FIXME: implement */
2368 int r600_startup(struct radeon_device
*rdev
)
2372 /* enable pcie gen2 link */
2373 r600_pcie_gen2_enable(rdev
);
2375 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
2376 r
= r600_init_microcode(rdev
);
2378 DRM_ERROR("Failed to load firmware!\n");
2383 r600_mc_program(rdev
);
2384 if (rdev
->flags
& RADEON_IS_AGP
) {
2385 r600_agp_enable(rdev
);
2387 r
= r600_pcie_gart_enable(rdev
);
2391 r600_gpu_init(rdev
);
2392 r
= r600_blit_init(rdev
);
2394 r600_blit_fini(rdev
);
2395 rdev
->asic
->copy
= NULL
;
2396 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
2399 /* allocate wb buffer */
2400 r
= radeon_wb_init(rdev
);
2405 r
= r600_irq_init(rdev
);
2407 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
2408 radeon_irq_kms_fini(rdev
);
2413 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
2416 r
= r600_cp_load_microcode(rdev
);
2419 r
= r600_cp_resume(rdev
);
2426 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
)
2430 temp
= RREG32(CONFIG_CNTL
);
2431 if (state
== false) {
2437 WREG32(CONFIG_CNTL
, temp
);
2440 int r600_resume(struct radeon_device
*rdev
)
2444 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2445 * posting will perform necessary task to bring back GPU into good
2449 atom_asic_init(rdev
->mode_info
.atom_context
);
2451 r
= r600_startup(rdev
);
2453 DRM_ERROR("r600 startup failed on resume\n");
2457 r
= r600_ib_test(rdev
);
2459 DRM_ERROR("radeon: failed testing IB (%d).\n", r
);
2463 r
= r600_audio_init(rdev
);
2465 DRM_ERROR("radeon: audio resume failed\n");
2472 int r600_suspend(struct radeon_device
*rdev
)
2476 r600_audio_fini(rdev
);
2477 /* FIXME: we should wait for ring to be empty */
2479 rdev
->cp
.ready
= false;
2480 r600_irq_suspend(rdev
);
2481 radeon_wb_disable(rdev
);
2482 r600_pcie_gart_disable(rdev
);
2483 /* unpin shaders bo */
2484 if (rdev
->r600_blit
.shader_obj
) {
2485 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
2487 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
2488 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
2494 /* Plan is to move initialization in that function and use
2495 * helper function so that radeon_device_init pretty much
2496 * do nothing more than calling asic specific function. This
2497 * should also allow to remove a bunch of callback function
2500 int r600_init(struct radeon_device
*rdev
)
2504 r
= radeon_dummy_page_init(rdev
);
2507 if (r600_debugfs_mc_info_init(rdev
)) {
2508 DRM_ERROR("Failed to register debugfs file for mc !\n");
2510 /* This don't do much */
2511 r
= radeon_gem_init(rdev
);
2515 if (!radeon_get_bios(rdev
)) {
2516 if (ASIC_IS_AVIVO(rdev
))
2519 /* Must be an ATOMBIOS */
2520 if (!rdev
->is_atom_bios
) {
2521 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
2524 r
= radeon_atombios_init(rdev
);
2527 /* Post card if necessary */
2528 if (!radeon_card_posted(rdev
)) {
2530 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2533 DRM_INFO("GPU not posted. posting now...\n");
2534 atom_asic_init(rdev
->mode_info
.atom_context
);
2536 /* Initialize scratch registers */
2537 r600_scratch_init(rdev
);
2538 /* Initialize surface registers */
2539 radeon_surface_init(rdev
);
2540 /* Initialize clocks */
2541 radeon_get_clock_info(rdev
->ddev
);
2543 r
= radeon_fence_driver_init(rdev
);
2546 if (rdev
->flags
& RADEON_IS_AGP
) {
2547 r
= radeon_agp_init(rdev
);
2549 radeon_agp_disable(rdev
);
2551 r
= r600_mc_init(rdev
);
2554 /* Memory manager */
2555 r
= radeon_bo_init(rdev
);
2559 r
= radeon_irq_kms_init(rdev
);
2563 rdev
->cp
.ring_obj
= NULL
;
2564 r600_ring_init(rdev
, 1024 * 1024);
2566 rdev
->ih
.ring_obj
= NULL
;
2567 r600_ih_ring_init(rdev
, 64 * 1024);
2569 r
= r600_pcie_gart_init(rdev
);
2573 rdev
->accel_working
= true;
2574 r
= r600_startup(rdev
);
2576 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
2578 r600_irq_fini(rdev
);
2579 radeon_wb_fini(rdev
);
2580 radeon_irq_kms_fini(rdev
);
2581 r600_pcie_gart_fini(rdev
);
2582 rdev
->accel_working
= false;
2584 if (rdev
->accel_working
) {
2585 r
= radeon_ib_pool_init(rdev
);
2587 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
2588 rdev
->accel_working
= false;
2590 r
= r600_ib_test(rdev
);
2592 dev_err(rdev
->dev
, "IB test failed (%d).\n", r
);
2593 rdev
->accel_working
= false;
2598 r
= r600_audio_init(rdev
);
2600 return r
; /* TODO error handling */
2604 void r600_fini(struct radeon_device
*rdev
)
2606 r600_audio_fini(rdev
);
2607 r600_blit_fini(rdev
);
2609 r600_irq_fini(rdev
);
2610 radeon_wb_fini(rdev
);
2611 radeon_irq_kms_fini(rdev
);
2612 r600_pcie_gart_fini(rdev
);
2613 radeon_agp_fini(rdev
);
2614 radeon_gem_fini(rdev
);
2615 radeon_fence_driver_fini(rdev
);
2616 radeon_bo_fini(rdev
);
2617 radeon_atombios_fini(rdev
);
2620 radeon_dummy_page_fini(rdev
);
2627 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
2629 /* FIXME: implement */
2630 radeon_ring_write(rdev
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
2631 radeon_ring_write(rdev
, ib
->gpu_addr
& 0xFFFFFFFC);
2632 radeon_ring_write(rdev
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
2633 radeon_ring_write(rdev
, ib
->length_dw
);
2636 int r600_ib_test(struct radeon_device
*rdev
)
2638 struct radeon_ib
*ib
;
2644 r
= radeon_scratch_get(rdev
, &scratch
);
2646 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
2649 WREG32(scratch
, 0xCAFEDEAD);
2650 r
= radeon_ib_get(rdev
, &ib
);
2652 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
2655 ib
->ptr
[0] = PACKET3(PACKET3_SET_CONFIG_REG
, 1);
2656 ib
->ptr
[1] = ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2657 ib
->ptr
[2] = 0xDEADBEEF;
2658 ib
->ptr
[3] = PACKET2(0);
2659 ib
->ptr
[4] = PACKET2(0);
2660 ib
->ptr
[5] = PACKET2(0);
2661 ib
->ptr
[6] = PACKET2(0);
2662 ib
->ptr
[7] = PACKET2(0);
2663 ib
->ptr
[8] = PACKET2(0);
2664 ib
->ptr
[9] = PACKET2(0);
2665 ib
->ptr
[10] = PACKET2(0);
2666 ib
->ptr
[11] = PACKET2(0);
2667 ib
->ptr
[12] = PACKET2(0);
2668 ib
->ptr
[13] = PACKET2(0);
2669 ib
->ptr
[14] = PACKET2(0);
2670 ib
->ptr
[15] = PACKET2(0);
2672 r
= radeon_ib_schedule(rdev
, ib
);
2674 radeon_scratch_free(rdev
, scratch
);
2675 radeon_ib_free(rdev
, &ib
);
2676 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
2679 r
= radeon_fence_wait(ib
->fence
, false);
2681 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
2684 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2685 tmp
= RREG32(scratch
);
2686 if (tmp
== 0xDEADBEEF)
2690 if (i
< rdev
->usec_timeout
) {
2691 DRM_INFO("ib test succeeded in %u usecs\n", i
);
2693 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2697 radeon_scratch_free(rdev
, scratch
);
2698 radeon_ib_free(rdev
, &ib
);
2705 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2706 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2707 * writing to the ring and the GPU consuming, the GPU writes to the ring
2708 * and host consumes. As the host irq handler processes interrupts, it
2709 * increments the rptr. When the rptr catches up with the wptr, all the
2710 * current interrupts have been processed.
2713 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
2717 /* Align ring size */
2718 rb_bufsz
= drm_order(ring_size
/ 4);
2719 ring_size
= (1 << rb_bufsz
) * 4;
2720 rdev
->ih
.ring_size
= ring_size
;
2721 rdev
->ih
.ptr_mask
= rdev
->ih
.ring_size
- 1;
2725 static int r600_ih_ring_alloc(struct radeon_device
*rdev
)
2729 /* Allocate ring buffer */
2730 if (rdev
->ih
.ring_obj
== NULL
) {
2731 r
= radeon_bo_create(rdev
, NULL
, rdev
->ih
.ring_size
,
2733 RADEON_GEM_DOMAIN_GTT
,
2734 &rdev
->ih
.ring_obj
);
2736 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r
);
2739 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2740 if (unlikely(r
!= 0))
2742 r
= radeon_bo_pin(rdev
->ih
.ring_obj
,
2743 RADEON_GEM_DOMAIN_GTT
,
2744 &rdev
->ih
.gpu_addr
);
2746 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2747 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r
);
2750 r
= radeon_bo_kmap(rdev
->ih
.ring_obj
,
2751 (void **)&rdev
->ih
.ring
);
2752 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2754 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r
);
2761 static void r600_ih_ring_fini(struct radeon_device
*rdev
)
2764 if (rdev
->ih
.ring_obj
) {
2765 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2766 if (likely(r
== 0)) {
2767 radeon_bo_kunmap(rdev
->ih
.ring_obj
);
2768 radeon_bo_unpin(rdev
->ih
.ring_obj
);
2769 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2771 radeon_bo_unref(&rdev
->ih
.ring_obj
);
2772 rdev
->ih
.ring
= NULL
;
2773 rdev
->ih
.ring_obj
= NULL
;
2777 void r600_rlc_stop(struct radeon_device
*rdev
)
2780 if ((rdev
->family
>= CHIP_RV770
) &&
2781 (rdev
->family
<= CHIP_RV740
)) {
2782 /* r7xx asics need to soft reset RLC before halting */
2783 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_RLC
);
2784 RREG32(SRBM_SOFT_RESET
);
2786 WREG32(SRBM_SOFT_RESET
, 0);
2787 RREG32(SRBM_SOFT_RESET
);
2790 WREG32(RLC_CNTL
, 0);
2793 static void r600_rlc_start(struct radeon_device
*rdev
)
2795 WREG32(RLC_CNTL
, RLC_ENABLE
);
2798 static int r600_rlc_init(struct radeon_device
*rdev
)
2801 const __be32
*fw_data
;
2806 r600_rlc_stop(rdev
);
2808 WREG32(RLC_HB_BASE
, 0);
2809 WREG32(RLC_HB_CNTL
, 0);
2810 WREG32(RLC_HB_RPTR
, 0);
2811 WREG32(RLC_HB_WPTR
, 0);
2812 WREG32(RLC_HB_WPTR_LSB_ADDR
, 0);
2813 WREG32(RLC_HB_WPTR_MSB_ADDR
, 0);
2814 WREG32(RLC_MC_CNTL
, 0);
2815 WREG32(RLC_UCODE_CNTL
, 0);
2817 fw_data
= (const __be32
*)rdev
->rlc_fw
->data
;
2818 if (rdev
->family
>= CHIP_CEDAR
) {
2819 for (i
= 0; i
< EVERGREEN_RLC_UCODE_SIZE
; i
++) {
2820 WREG32(RLC_UCODE_ADDR
, i
);
2821 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2823 } else if (rdev
->family
>= CHIP_RV770
) {
2824 for (i
= 0; i
< R700_RLC_UCODE_SIZE
; i
++) {
2825 WREG32(RLC_UCODE_ADDR
, i
);
2826 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2829 for (i
= 0; i
< RLC_UCODE_SIZE
; i
++) {
2830 WREG32(RLC_UCODE_ADDR
, i
);
2831 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2834 WREG32(RLC_UCODE_ADDR
, 0);
2836 r600_rlc_start(rdev
);
2841 static void r600_enable_interrupts(struct radeon_device
*rdev
)
2843 u32 ih_cntl
= RREG32(IH_CNTL
);
2844 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2846 ih_cntl
|= ENABLE_INTR
;
2847 ih_rb_cntl
|= IH_RB_ENABLE
;
2848 WREG32(IH_CNTL
, ih_cntl
);
2849 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2850 rdev
->ih
.enabled
= true;
2853 void r600_disable_interrupts(struct radeon_device
*rdev
)
2855 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2856 u32 ih_cntl
= RREG32(IH_CNTL
);
2858 ih_rb_cntl
&= ~IH_RB_ENABLE
;
2859 ih_cntl
&= ~ENABLE_INTR
;
2860 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2861 WREG32(IH_CNTL
, ih_cntl
);
2862 /* set rptr, wptr to 0 */
2863 WREG32(IH_RB_RPTR
, 0);
2864 WREG32(IH_RB_WPTR
, 0);
2865 rdev
->ih
.enabled
= false;
2870 static void r600_disable_interrupt_state(struct radeon_device
*rdev
)
2874 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2875 WREG32(GRBM_INT_CNTL
, 0);
2876 WREG32(DxMODE_INT_MASK
, 0);
2877 WREG32(D1GRPH_INTERRUPT_CONTROL
, 0);
2878 WREG32(D2GRPH_INTERRUPT_CONTROL
, 0);
2879 if (ASIC_IS_DCE3(rdev
)) {
2880 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL
, 0);
2881 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL
, 0);
2882 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2883 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2884 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2885 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2886 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2887 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2888 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2889 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2890 if (ASIC_IS_DCE32(rdev
)) {
2891 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2892 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2893 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2894 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2897 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2898 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2899 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2900 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
2901 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2902 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
2903 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2904 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
2908 int r600_irq_init(struct radeon_device
*rdev
)
2912 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
2915 ret
= r600_ih_ring_alloc(rdev
);
2920 r600_disable_interrupts(rdev
);
2923 ret
= r600_rlc_init(rdev
);
2925 r600_ih_ring_fini(rdev
);
2929 /* setup interrupt control */
2930 /* set dummy read address to ring address */
2931 WREG32(INTERRUPT_CNTL2
, rdev
->ih
.gpu_addr
>> 8);
2932 interrupt_cntl
= RREG32(INTERRUPT_CNTL
);
2933 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2934 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2936 interrupt_cntl
&= ~IH_DUMMY_RD_OVERRIDE
;
2937 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2938 interrupt_cntl
&= ~IH_REQ_NONSNOOP_EN
;
2939 WREG32(INTERRUPT_CNTL
, interrupt_cntl
);
2941 WREG32(IH_RB_BASE
, rdev
->ih
.gpu_addr
>> 8);
2942 rb_bufsz
= drm_order(rdev
->ih
.ring_size
/ 4);
2944 ih_rb_cntl
= (IH_WPTR_OVERFLOW_ENABLE
|
2945 IH_WPTR_OVERFLOW_CLEAR
|
2948 if (rdev
->wb
.enabled
)
2949 ih_rb_cntl
|= IH_WPTR_WRITEBACK_ENABLE
;
2951 /* set the writeback address whether it's enabled or not */
2952 WREG32(IH_RB_WPTR_ADDR_LO
, (rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFFFFFFFC);
2953 WREG32(IH_RB_WPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFF);
2955 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2957 /* set rptr, wptr to 0 */
2958 WREG32(IH_RB_RPTR
, 0);
2959 WREG32(IH_RB_WPTR
, 0);
2961 /* Default settings for IH_CNTL (disabled at first) */
2962 ih_cntl
= MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2963 /* RPTR_REARM only works if msi's are enabled */
2964 if (rdev
->msi_enabled
)
2965 ih_cntl
|= RPTR_REARM
;
2968 ih_cntl
|= IH_MC_SWAP(IH_MC_SWAP_32BIT
);
2970 WREG32(IH_CNTL
, ih_cntl
);
2972 /* force the active interrupt state to all disabled */
2973 if (rdev
->family
>= CHIP_CEDAR
)
2974 evergreen_disable_interrupt_state(rdev
);
2976 r600_disable_interrupt_state(rdev
);
2979 r600_enable_interrupts(rdev
);
2984 void r600_irq_suspend(struct radeon_device
*rdev
)
2986 r600_irq_disable(rdev
);
2987 r600_rlc_stop(rdev
);
2990 void r600_irq_fini(struct radeon_device
*rdev
)
2992 r600_irq_suspend(rdev
);
2993 r600_ih_ring_fini(rdev
);
2996 int r600_irq_set(struct radeon_device
*rdev
)
2998 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
3000 u32 hpd1
, hpd2
, hpd3
, hpd4
= 0, hpd5
= 0, hpd6
= 0;
3001 u32 grbm_int_cntl
= 0;
3003 u32 d1grph
= 0, d2grph
= 0;
3005 if (!rdev
->irq
.installed
) {
3006 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3009 /* don't enable anything if the ih is disabled */
3010 if (!rdev
->ih
.enabled
) {
3011 r600_disable_interrupts(rdev
);
3012 /* force the active interrupt state to all disabled */
3013 r600_disable_interrupt_state(rdev
);
3017 hdmi1
= RREG32(R600_HDMI_BLOCK1
+ R600_HDMI_CNTL
) & ~R600_HDMI_INT_EN
;
3018 if (ASIC_IS_DCE3(rdev
)) {
3019 hdmi2
= RREG32(R600_HDMI_BLOCK3
+ R600_HDMI_CNTL
) & ~R600_HDMI_INT_EN
;
3020 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3021 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3022 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3023 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3024 if (ASIC_IS_DCE32(rdev
)) {
3025 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3026 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3029 hdmi2
= RREG32(R600_HDMI_BLOCK2
+ R600_HDMI_CNTL
) & ~R600_HDMI_INT_EN
;
3030 hpd1
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3031 hpd2
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3032 hpd3
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3035 if (rdev
->irq
.sw_int
) {
3036 DRM_DEBUG("r600_irq_set: sw int\n");
3037 cp_int_cntl
|= RB_INT_ENABLE
;
3038 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
3040 if (rdev
->irq
.crtc_vblank_int
[0] ||
3041 rdev
->irq
.pflip
[0]) {
3042 DRM_DEBUG("r600_irq_set: vblank 0\n");
3043 mode_int
|= D1MODE_VBLANK_INT_MASK
;
3045 if (rdev
->irq
.crtc_vblank_int
[1] ||
3046 rdev
->irq
.pflip
[1]) {
3047 DRM_DEBUG("r600_irq_set: vblank 1\n");
3048 mode_int
|= D2MODE_VBLANK_INT_MASK
;
3050 if (rdev
->irq
.hpd
[0]) {
3051 DRM_DEBUG("r600_irq_set: hpd 1\n");
3052 hpd1
|= DC_HPDx_INT_EN
;
3054 if (rdev
->irq
.hpd
[1]) {
3055 DRM_DEBUG("r600_irq_set: hpd 2\n");
3056 hpd2
|= DC_HPDx_INT_EN
;
3058 if (rdev
->irq
.hpd
[2]) {
3059 DRM_DEBUG("r600_irq_set: hpd 3\n");
3060 hpd3
|= DC_HPDx_INT_EN
;
3062 if (rdev
->irq
.hpd
[3]) {
3063 DRM_DEBUG("r600_irq_set: hpd 4\n");
3064 hpd4
|= DC_HPDx_INT_EN
;
3066 if (rdev
->irq
.hpd
[4]) {
3067 DRM_DEBUG("r600_irq_set: hpd 5\n");
3068 hpd5
|= DC_HPDx_INT_EN
;
3070 if (rdev
->irq
.hpd
[5]) {
3071 DRM_DEBUG("r600_irq_set: hpd 6\n");
3072 hpd6
|= DC_HPDx_INT_EN
;
3074 if (rdev
->irq
.hdmi
[0]) {
3075 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3076 hdmi1
|= R600_HDMI_INT_EN
;
3078 if (rdev
->irq
.hdmi
[1]) {
3079 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3080 hdmi2
|= R600_HDMI_INT_EN
;
3082 if (rdev
->irq
.gui_idle
) {
3083 DRM_DEBUG("gui idle\n");
3084 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
3087 WREG32(CP_INT_CNTL
, cp_int_cntl
);
3088 WREG32(DxMODE_INT_MASK
, mode_int
);
3089 WREG32(D1GRPH_INTERRUPT_CONTROL
, d1grph
);
3090 WREG32(D2GRPH_INTERRUPT_CONTROL
, d2grph
);
3091 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
3092 WREG32(R600_HDMI_BLOCK1
+ R600_HDMI_CNTL
, hdmi1
);
3093 if (ASIC_IS_DCE3(rdev
)) {
3094 WREG32(R600_HDMI_BLOCK3
+ R600_HDMI_CNTL
, hdmi2
);
3095 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
3096 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
3097 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
3098 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
3099 if (ASIC_IS_DCE32(rdev
)) {
3100 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
3101 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
3104 WREG32(R600_HDMI_BLOCK2
+ R600_HDMI_CNTL
, hdmi2
);
3105 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
3106 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
3107 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, hpd3
);
3113 static inline void r600_irq_ack(struct radeon_device
*rdev
)
3117 if (ASIC_IS_DCE3(rdev
)) {
3118 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DCE3_DISP_INTERRUPT_STATUS
);
3119 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE
);
3120 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2
);
3122 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
3123 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
3124 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= 0;
3126 rdev
->irq
.stat_regs
.r600
.d1grph_int
= RREG32(D1GRPH_INTERRUPT_STATUS
);
3127 rdev
->irq
.stat_regs
.r600
.d2grph_int
= RREG32(D2GRPH_INTERRUPT_STATUS
);
3129 if (rdev
->irq
.stat_regs
.r600
.d1grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
3130 WREG32(D1GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
3131 if (rdev
->irq
.stat_regs
.r600
.d2grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
3132 WREG32(D2GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
3133 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
3134 WREG32(D1MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
3135 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
)
3136 WREG32(D1MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
3137 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
)
3138 WREG32(D2MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
3139 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
)
3140 WREG32(D2MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
3141 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
3142 if (ASIC_IS_DCE3(rdev
)) {
3143 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
3144 tmp
|= DC_HPDx_INT_ACK
;
3145 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
3147 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
3148 tmp
|= DC_HPDx_INT_ACK
;
3149 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
3152 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
3153 if (ASIC_IS_DCE3(rdev
)) {
3154 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
3155 tmp
|= DC_HPDx_INT_ACK
;
3156 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
3158 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
3159 tmp
|= DC_HPDx_INT_ACK
;
3160 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
3163 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
3164 if (ASIC_IS_DCE3(rdev
)) {
3165 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
3166 tmp
|= DC_HPDx_INT_ACK
;
3167 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
3169 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
3170 tmp
|= DC_HPDx_INT_ACK
;
3171 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
3174 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
3175 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
3176 tmp
|= DC_HPDx_INT_ACK
;
3177 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
3179 if (ASIC_IS_DCE32(rdev
)) {
3180 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
3181 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3182 tmp
|= DC_HPDx_INT_ACK
;
3183 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
3185 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
3186 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3187 tmp
|= DC_HPDx_INT_ACK
;
3188 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
3191 if (RREG32(R600_HDMI_BLOCK1
+ R600_HDMI_STATUS
) & R600_HDMI_INT_PENDING
) {
3192 WREG32_P(R600_HDMI_BLOCK1
+ R600_HDMI_CNTL
, R600_HDMI_INT_ACK
, ~R600_HDMI_INT_ACK
);
3194 if (ASIC_IS_DCE3(rdev
)) {
3195 if (RREG32(R600_HDMI_BLOCK3
+ R600_HDMI_STATUS
) & R600_HDMI_INT_PENDING
) {
3196 WREG32_P(R600_HDMI_BLOCK3
+ R600_HDMI_CNTL
, R600_HDMI_INT_ACK
, ~R600_HDMI_INT_ACK
);
3199 if (RREG32(R600_HDMI_BLOCK2
+ R600_HDMI_STATUS
) & R600_HDMI_INT_PENDING
) {
3200 WREG32_P(R600_HDMI_BLOCK2
+ R600_HDMI_CNTL
, R600_HDMI_INT_ACK
, ~R600_HDMI_INT_ACK
);
3205 void r600_irq_disable(struct radeon_device
*rdev
)
3207 r600_disable_interrupts(rdev
);
3208 /* Wait and acknowledge irq */
3211 r600_disable_interrupt_state(rdev
);
3214 static inline u32
r600_get_ih_wptr(struct radeon_device
*rdev
)
3218 if (rdev
->wb
.enabled
)
3219 wptr
= rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4];
3221 wptr
= RREG32(IH_RB_WPTR
);
3223 if (wptr
& RB_OVERFLOW
) {
3224 /* When a ring buffer overflow happen start parsing interrupt
3225 * from the last not overwritten vector (wptr + 16). Hopefully
3226 * this should allow us to catchup.
3228 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3229 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
3230 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
3231 tmp
= RREG32(IH_RB_CNTL
);
3232 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
3233 WREG32(IH_RB_CNTL
, tmp
);
3235 return (wptr
& rdev
->ih
.ptr_mask
);
3239 * Each IV ring entry is 128 bits:
3240 * [7:0] - interrupt source id
3242 * [59:32] - interrupt source data
3243 * [127:60] - reserved
3245 * The basic interrupt vector entries
3246 * are decoded as follows:
3247 * src_id src_data description
3252 * 19 0 FP Hot plug detection A
3253 * 19 1 FP Hot plug detection B
3254 * 19 2 DAC A auto-detection
3255 * 19 3 DAC B auto-detection
3261 * 181 - EOP Interrupt
3264 * Note, these are based on r600 and may need to be
3265 * adjusted or added to on newer asics
3268 int r600_irq_process(struct radeon_device
*rdev
)
3270 u32 wptr
= r600_get_ih_wptr(rdev
);
3271 u32 rptr
= rdev
->ih
.rptr
;
3272 u32 src_id
, src_data
;
3274 unsigned long flags
;
3275 bool queue_hotplug
= false;
3277 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
3278 if (!rdev
->ih
.enabled
)
3281 spin_lock_irqsave(&rdev
->ih
.lock
, flags
);
3284 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3287 if (rdev
->shutdown
) {
3288 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3293 /* display interrupts */
3296 rdev
->ih
.wptr
= wptr
;
3297 while (rptr
!= wptr
) {
3298 /* wptr/rptr are in bytes! */
3299 ring_index
= rptr
/ 4;
3300 src_id
= rdev
->ih
.ring
[ring_index
] & 0xff;
3301 src_data
= rdev
->ih
.ring
[ring_index
+ 1] & 0xfffffff;
3304 case 1: /* D1 vblank/vline */
3306 case 0: /* D1 vblank */
3307 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
3308 if (rdev
->irq
.crtc_vblank_int
[0]) {
3309 drm_handle_vblank(rdev
->ddev
, 0);
3310 rdev
->pm
.vblank_sync
= true;
3311 wake_up(&rdev
->irq
.vblank_queue
);
3313 if (rdev
->irq
.pflip
[0])
3314 radeon_crtc_handle_flip(rdev
, 0);
3315 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
3316 DRM_DEBUG("IH: D1 vblank\n");
3319 case 1: /* D1 vline */
3320 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
3321 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
3322 DRM_DEBUG("IH: D1 vline\n");
3326 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3330 case 5: /* D2 vblank/vline */
3332 case 0: /* D2 vblank */
3333 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
) {
3334 if (rdev
->irq
.crtc_vblank_int
[1]) {
3335 drm_handle_vblank(rdev
->ddev
, 1);
3336 rdev
->pm
.vblank_sync
= true;
3337 wake_up(&rdev
->irq
.vblank_queue
);
3339 if (rdev
->irq
.pflip
[1])
3340 radeon_crtc_handle_flip(rdev
, 1);
3341 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VBLANK_INTERRUPT
;
3342 DRM_DEBUG("IH: D2 vblank\n");
3345 case 1: /* D1 vline */
3346 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
) {
3347 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VLINE_INTERRUPT
;
3348 DRM_DEBUG("IH: D2 vline\n");
3352 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3356 case 19: /* HPD/DAC hotplug */
3359 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
3360 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD1_INTERRUPT
;
3361 queue_hotplug
= true;
3362 DRM_DEBUG("IH: HPD1\n");
3366 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
3367 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD2_INTERRUPT
;
3368 queue_hotplug
= true;
3369 DRM_DEBUG("IH: HPD2\n");
3373 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
3374 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD3_INTERRUPT
;
3375 queue_hotplug
= true;
3376 DRM_DEBUG("IH: HPD3\n");
3380 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
3381 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD4_INTERRUPT
;
3382 queue_hotplug
= true;
3383 DRM_DEBUG("IH: HPD4\n");
3387 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
3388 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD5_INTERRUPT
;
3389 queue_hotplug
= true;
3390 DRM_DEBUG("IH: HPD5\n");
3394 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
3395 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD6_INTERRUPT
;
3396 queue_hotplug
= true;
3397 DRM_DEBUG("IH: HPD6\n");
3401 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3406 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data
);
3407 r600_audio_schedule_polling(rdev
);
3409 case 176: /* CP_INT in ring buffer */
3410 case 177: /* CP_INT in IB1 */
3411 case 178: /* CP_INT in IB2 */
3412 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
3413 radeon_fence_process(rdev
);
3415 case 181: /* CP EOP event */
3416 DRM_DEBUG("IH: CP EOP\n");
3417 radeon_fence_process(rdev
);
3419 case 233: /* GUI IDLE */
3420 DRM_DEBUG("IH: CP EOP\n");
3421 rdev
->pm
.gui_idle
= true;
3422 wake_up(&rdev
->irq
.idle_queue
);
3425 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3429 /* wptr/rptr are in bytes! */
3431 rptr
&= rdev
->ih
.ptr_mask
;
3433 /* make sure wptr hasn't changed while processing */
3434 wptr
= r600_get_ih_wptr(rdev
);
3435 if (wptr
!= rdev
->ih
.wptr
)
3438 schedule_work(&rdev
->hotplug_work
);
3439 rdev
->ih
.rptr
= rptr
;
3440 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3441 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3448 #if defined(CONFIG_DEBUG_FS)
3450 static int r600_debugfs_cp_ring_info(struct seq_file
*m
, void *data
)
3452 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3453 struct drm_device
*dev
= node
->minor
->dev
;
3454 struct radeon_device
*rdev
= dev
->dev_private
;
3455 unsigned count
, i
, j
;
3457 radeon_ring_free_size(rdev
);
3458 count
= (rdev
->cp
.ring_size
/ 4) - rdev
->cp
.ring_free_dw
;
3459 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(CP_STAT
));
3460 seq_printf(m
, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR
));
3461 seq_printf(m
, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR
));
3462 seq_printf(m
, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev
->cp
.wptr
);
3463 seq_printf(m
, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev
->cp
.rptr
);
3464 seq_printf(m
, "%u free dwords in ring\n", rdev
->cp
.ring_free_dw
);
3465 seq_printf(m
, "%u dwords in ring\n", count
);
3467 for (j
= 0; j
<= count
; j
++) {
3468 seq_printf(m
, "r[%04d]=0x%08x\n", i
, rdev
->cp
.ring
[i
]);
3469 i
= (i
+ 1) & rdev
->cp
.ptr_mask
;
3474 static int r600_debugfs_mc_info(struct seq_file
*m
, void *data
)
3476 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3477 struct drm_device
*dev
= node
->minor
->dev
;
3478 struct radeon_device
*rdev
= dev
->dev_private
;
3480 DREG32_SYS(m
, rdev
, R_000E50_SRBM_STATUS
);
3481 DREG32_SYS(m
, rdev
, VM_L2_STATUS
);
3485 static struct drm_info_list r600_mc_info_list
[] = {
3486 {"r600_mc_info", r600_debugfs_mc_info
, 0, NULL
},
3487 {"r600_ring_info", r600_debugfs_cp_ring_info
, 0, NULL
},
3491 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
)
3493 #if defined(CONFIG_DEBUG_FS)
3494 return radeon_debugfs_add_files(rdev
, r600_mc_info_list
, ARRAY_SIZE(r600_mc_info_list
));
3501 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3502 * rdev: radeon device structure
3503 * bo: buffer object struct which userspace is waiting for idle
3505 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3506 * through ring buffer, this leads to corruption in rendering, see
3507 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3508 * directly perform HDP flush by writing register through MMIO.
3510 void r600_ioctl_wait_idle(struct radeon_device
*rdev
, struct radeon_bo
*bo
)
3512 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3513 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3514 * This seems to cause problems on some AGP cards. Just use the old
3517 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
3518 rdev
->vram_scratch
.ptr
&& !(rdev
->flags
& RADEON_IS_AGP
)) {
3519 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
3522 WREG32(HDP_DEBUG1
, 0);
3523 tmp
= readl((void __iomem
*)ptr
);
3525 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
3528 void r600_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
3530 u32 link_width_cntl
, mask
, target_reg
;
3532 if (rdev
->flags
& RADEON_IS_IGP
)
3535 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3538 /* x2 cards have a special sequence */
3539 if (ASIC_IS_X2(rdev
))
3542 /* FIXME wait for idle */
3546 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
3549 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
3552 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
3555 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
3558 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
3561 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
3565 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
3569 link_width_cntl
= RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
3571 if ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) ==
3572 (mask
<< RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
))
3575 if (link_width_cntl
& R600_PCIE_LC_UPCONFIGURE_DIS
)
3578 link_width_cntl
&= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK
|
3579 RADEON_PCIE_LC_RECONFIG_NOW
|
3580 R600_PCIE_LC_RENEGOTIATE_EN
|
3581 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
);
3582 link_width_cntl
|= mask
;
3584 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3586 /* some northbridges can renegotiate the link rather than requiring
3587 * a complete re-config.
3588 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3590 if (link_width_cntl
& R600_PCIE_LC_RENEGOTIATION_SUPPORT
)
3591 link_width_cntl
|= R600_PCIE_LC_RENEGOTIATE_EN
| R600_PCIE_LC_UPCONFIGURE_SUPPORT
;
3593 link_width_cntl
|= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
;
3595 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, (link_width_cntl
|
3596 RADEON_PCIE_LC_RECONFIG_NOW
));
3598 if (rdev
->family
>= CHIP_RV770
)
3599 target_reg
= R700_TARGET_AND_CURRENT_PROFILE_INDEX
;
3601 target_reg
= R600_TARGET_AND_CURRENT_PROFILE_INDEX
;
3603 /* wait for lane set to complete */
3604 link_width_cntl
= RREG32(target_reg
);
3605 while (link_width_cntl
== 0xffffffff)
3606 link_width_cntl
= RREG32(target_reg
);
3610 int r600_get_pcie_lanes(struct radeon_device
*rdev
)
3612 u32 link_width_cntl
;
3614 if (rdev
->flags
& RADEON_IS_IGP
)
3617 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3620 /* x2 cards have a special sequence */
3621 if (ASIC_IS_X2(rdev
))
3624 /* FIXME wait for idle */
3626 link_width_cntl
= RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
3628 switch ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
) {
3629 case RADEON_PCIE_LC_LINK_WIDTH_X0
:
3631 case RADEON_PCIE_LC_LINK_WIDTH_X1
:
3633 case RADEON_PCIE_LC_LINK_WIDTH_X2
:
3635 case RADEON_PCIE_LC_LINK_WIDTH_X4
:
3637 case RADEON_PCIE_LC_LINK_WIDTH_X8
:
3639 case RADEON_PCIE_LC_LINK_WIDTH_X16
:
3645 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
)
3647 u32 link_width_cntl
, lanes
, speed_cntl
, training_cntl
, tmp
;
3650 if (radeon_pcie_gen2
== 0)
3653 if (rdev
->flags
& RADEON_IS_IGP
)
3656 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3659 /* x2 cards have a special sequence */
3660 if (ASIC_IS_X2(rdev
))
3663 /* only RV6xx+ chips are supported */
3664 if (rdev
->family
<= CHIP_R600
)
3667 /* 55 nm r6xx asics */
3668 if ((rdev
->family
== CHIP_RV670
) ||
3669 (rdev
->family
== CHIP_RV620
) ||
3670 (rdev
->family
== CHIP_RV635
)) {
3671 /* advertise upconfig capability */
3672 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3673 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3674 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3675 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3676 if (link_width_cntl
& LC_RENEGOTIATION_SUPPORT
) {
3677 lanes
= (link_width_cntl
& LC_LINK_WIDTH_RD_MASK
) >> LC_LINK_WIDTH_RD_SHIFT
;
3678 link_width_cntl
&= ~(LC_LINK_WIDTH_MASK
|
3679 LC_RECONFIG_ARC_MISSING_ESCAPE
);
3680 link_width_cntl
|= lanes
| LC_RECONFIG_NOW
| LC_RENEGOTIATE_EN
;
3681 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3683 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3684 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3688 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3689 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) &&
3690 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3692 /* 55 nm r6xx asics */
3693 if ((rdev
->family
== CHIP_RV670
) ||
3694 (rdev
->family
== CHIP_RV620
) ||
3695 (rdev
->family
== CHIP_RV635
)) {
3696 WREG32(MM_CFGREGS_CNTL
, 0x8);
3697 link_cntl2
= RREG32(0x4088);
3698 WREG32(MM_CFGREGS_CNTL
, 0);
3699 /* not supported yet */
3700 if (link_cntl2
& SELECTABLE_DEEMPHASIS
)
3704 speed_cntl
&= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
;
3705 speed_cntl
|= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT
);
3706 speed_cntl
&= ~LC_VOLTAGE_TIMER_SEL_MASK
;
3707 speed_cntl
&= ~LC_FORCE_DIS_HW_SPEED_CHANGE
;
3708 speed_cntl
|= LC_FORCE_EN_HW_SPEED_CHANGE
;
3709 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3711 tmp
= RREG32(0x541c);
3712 WREG32(0x541c, tmp
| 0x8);
3713 WREG32(MM_CFGREGS_CNTL
, MM_WR_TO_CFG_EN
);
3714 link_cntl2
= RREG16(0x4088);
3715 link_cntl2
&= ~TARGET_LINK_SPEED_MASK
;
3717 WREG16(0x4088, link_cntl2
);
3718 WREG32(MM_CFGREGS_CNTL
, 0);
3720 if ((rdev
->family
== CHIP_RV670
) ||
3721 (rdev
->family
== CHIP_RV620
) ||
3722 (rdev
->family
== CHIP_RV635
)) {
3723 training_cntl
= RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL
);
3724 training_cntl
&= ~LC_POINT_7_PLUS_EN
;
3725 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL
, training_cntl
);
3727 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3728 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3729 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3732 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3733 speed_cntl
|= LC_GEN2_EN_STRAP
;
3734 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3737 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3738 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3740 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3742 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3743 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);