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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / r600.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
31 #include "drmP.h"
32 #include "radeon_drm.h"
33 #include "radeon.h"
34 #include "radeon_mode.h"
35 #include "r600d.h"
36 #include "atom.h"
37 #include "avivod.h"
38
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define R700_PFP_UCODE_SIZE 848
42 #define R700_PM4_UCODE_SIZE 1360
43
44 /* Firmware Names */
45 MODULE_FIRMWARE("radeon/R600_pfp.bin");
46 MODULE_FIRMWARE("radeon/R600_me.bin");
47 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
48 MODULE_FIRMWARE("radeon/RV610_me.bin");
49 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV630_me.bin");
51 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV620_me.bin");
53 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV635_me.bin");
55 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV670_me.bin");
57 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
58 MODULE_FIRMWARE("radeon/RS780_me.bin");
59 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV770_me.bin");
61 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV730_me.bin");
63 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV710_me.bin");
65
66 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
67
68 /* This files gather functions specifics to:
69 * r600,rv610,rv630,rv620,rv635,rv670
70 *
71 * Some of these functions might be used by newer ASICs.
72 */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
76
77
78 /*
79 * R600 PCIE GART
80 */
81 int r600_gart_clear_page(struct radeon_device *rdev, int i)
82 {
83 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
84 u64 pte;
85
86 if (i < 0 || i > rdev->gart.num_gpu_pages)
87 return -EINVAL;
88 pte = 0;
89 writeq(pte, ((void __iomem *)ptr) + (i * 8));
90 return 0;
91 }
92
93 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
94 {
95 unsigned i;
96 u32 tmp;
97
98 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
99 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
100 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
101 for (i = 0; i < rdev->usec_timeout; i++) {
102 /* read MC_STATUS */
103 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
104 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
105 if (tmp == 2) {
106 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
107 return;
108 }
109 if (tmp) {
110 return;
111 }
112 udelay(1);
113 }
114 }
115
116 int r600_pcie_gart_init(struct radeon_device *rdev)
117 {
118 int r;
119
120 if (rdev->gart.table.vram.robj) {
121 WARN(1, "R600 PCIE GART already initialized.\n");
122 return 0;
123 }
124 /* Initialize common gart structure */
125 r = radeon_gart_init(rdev);
126 if (r)
127 return r;
128 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
129 return radeon_gart_table_vram_alloc(rdev);
130 }
131
132 int r600_pcie_gart_enable(struct radeon_device *rdev)
133 {
134 u32 tmp;
135 int r, i;
136
137 if (rdev->gart.table.vram.robj == NULL) {
138 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
139 return -EINVAL;
140 }
141 r = radeon_gart_table_vram_pin(rdev);
142 if (r)
143 return r;
144
145 /* Setup L2 cache */
146 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
147 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
148 EFFECTIVE_L2_QUEUE_SIZE(7));
149 WREG32(VM_L2_CNTL2, 0);
150 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
151 /* Setup TLB control */
152 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
153 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
154 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
155 ENABLE_WAIT_L2_QUERY;
156 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
157 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
158 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
159 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
160 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
161 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
162 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
163 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
164 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
165 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
166 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
167 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
168 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
169 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
170 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
171 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
172 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
173 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
174 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
175 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
176 (u32)(rdev->dummy_page.addr >> 12));
177 for (i = 1; i < 7; i++)
178 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
179
180 r600_pcie_gart_tlb_flush(rdev);
181 rdev->gart.ready = true;
182 return 0;
183 }
184
185 void r600_pcie_gart_disable(struct radeon_device *rdev)
186 {
187 u32 tmp;
188 int i;
189
190 /* Disable all tables */
191 for (i = 0; i < 7; i++)
192 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
193
194 /* Disable L2 cache */
195 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
196 EFFECTIVE_L2_QUEUE_SIZE(7));
197 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
198 /* Setup L1 TLB control */
199 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
200 ENABLE_WAIT_L2_QUERY;
201 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
202 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
203 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
204 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
205 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
206 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
207 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
210 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
211 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
212 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
213 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
214 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
215 if (rdev->gart.table.vram.robj) {
216 radeon_object_kunmap(rdev->gart.table.vram.robj);
217 radeon_object_unpin(rdev->gart.table.vram.robj);
218 }
219 }
220
221 void r600_pcie_gart_fini(struct radeon_device *rdev)
222 {
223 r600_pcie_gart_disable(rdev);
224 radeon_gart_table_vram_free(rdev);
225 radeon_gart_fini(rdev);
226 }
227
228 int r600_mc_wait_for_idle(struct radeon_device *rdev)
229 {
230 unsigned i;
231 u32 tmp;
232
233 for (i = 0; i < rdev->usec_timeout; i++) {
234 /* read MC_STATUS */
235 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
236 if (!tmp)
237 return 0;
238 udelay(1);
239 }
240 return -1;
241 }
242
243 static void r600_mc_resume(struct radeon_device *rdev)
244 {
245 u32 d1vga_control, d2vga_control;
246 u32 vga_render_control, vga_hdp_control;
247 u32 d1crtc_control, d2crtc_control;
248 u32 new_d1grph_primary, new_d1grph_secondary;
249 u32 new_d2grph_primary, new_d2grph_secondary;
250 u64 old_vram_start;
251 u32 tmp;
252 int i, j;
253
254 /* Initialize HDP */
255 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
256 WREG32((0x2c14 + j), 0x00000000);
257 WREG32((0x2c18 + j), 0x00000000);
258 WREG32((0x2c1c + j), 0x00000000);
259 WREG32((0x2c20 + j), 0x00000000);
260 WREG32((0x2c24 + j), 0x00000000);
261 }
262 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
263
264 d1vga_control = RREG32(D1VGA_CONTROL);
265 d2vga_control = RREG32(D2VGA_CONTROL);
266 vga_render_control = RREG32(VGA_RENDER_CONTROL);
267 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
268 d1crtc_control = RREG32(D1CRTC_CONTROL);
269 d2crtc_control = RREG32(D2CRTC_CONTROL);
270 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
271 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
272 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
273 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
274 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
275 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
276 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
277 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
278 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
279
280 /* Stop all video */
281 WREG32(D1VGA_CONTROL, 0);
282 WREG32(D2VGA_CONTROL, 0);
283 WREG32(VGA_RENDER_CONTROL, 0);
284 WREG32(D1CRTC_UPDATE_LOCK, 1);
285 WREG32(D2CRTC_UPDATE_LOCK, 1);
286 WREG32(D1CRTC_CONTROL, 0);
287 WREG32(D2CRTC_CONTROL, 0);
288 WREG32(D1CRTC_UPDATE_LOCK, 0);
289 WREG32(D2CRTC_UPDATE_LOCK, 0);
290
291 mdelay(1);
292 if (r600_mc_wait_for_idle(rdev)) {
293 printk(KERN_WARNING "[drm] MC not idle !\n");
294 }
295
296 /* Lockout access through VGA aperture*/
297 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
298
299 /* Update configuration */
300 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
301 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
302 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
303 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
304 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
305 WREG32(MC_VM_FB_LOCATION, tmp);
306 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
307 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
308 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
309 if (rdev->flags & RADEON_IS_AGP) {
310 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
311 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
312 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
313 } else {
314 WREG32(MC_VM_AGP_BASE, 0);
315 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
316 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
317 }
318 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
319 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
320 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
321 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
322 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
323
324 /* Unlock host access */
325 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
326
327 mdelay(1);
328 if (r600_mc_wait_for_idle(rdev)) {
329 printk(KERN_WARNING "[drm] MC not idle !\n");
330 }
331
332 /* Restore video state */
333 WREG32(D1CRTC_UPDATE_LOCK, 1);
334 WREG32(D2CRTC_UPDATE_LOCK, 1);
335 WREG32(D1CRTC_CONTROL, d1crtc_control);
336 WREG32(D2CRTC_CONTROL, d2crtc_control);
337 WREG32(D1CRTC_UPDATE_LOCK, 0);
338 WREG32(D2CRTC_UPDATE_LOCK, 0);
339 WREG32(D1VGA_CONTROL, d1vga_control);
340 WREG32(D2VGA_CONTROL, d2vga_control);
341 WREG32(VGA_RENDER_CONTROL, vga_render_control);
342
343 /* we need to own VRAM, so turn off the VGA renderer here
344 * to stop it overwriting our objects */
345 rv515_vga_render_disable(rdev);
346 }
347
348 int r600_mc_init(struct radeon_device *rdev)
349 {
350 fixed20_12 a;
351 u32 tmp;
352 int chansize;
353 int r;
354
355 /* Get VRAM informations */
356 rdev->mc.vram_width = 128;
357 rdev->mc.vram_is_ddr = true;
358 tmp = RREG32(RAMCFG);
359 if (tmp & CHANSIZE_OVERRIDE) {
360 chansize = 16;
361 } else if (tmp & CHANSIZE_MASK) {
362 chansize = 64;
363 } else {
364 chansize = 32;
365 }
366 if (rdev->family == CHIP_R600) {
367 rdev->mc.vram_width = 8 * chansize;
368 } else if (rdev->family == CHIP_RV670) {
369 rdev->mc.vram_width = 4 * chansize;
370 } else if ((rdev->family == CHIP_RV610) ||
371 (rdev->family == CHIP_RV620)) {
372 rdev->mc.vram_width = chansize;
373 } else if ((rdev->family == CHIP_RV630) ||
374 (rdev->family == CHIP_RV635)) {
375 rdev->mc.vram_width = 2 * chansize;
376 }
377 /* Could aper size report 0 ? */
378 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
379 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
380 /* Setup GPU memory space */
381 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
382 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
383
384 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
385 rdev->mc.mc_vram_size = rdev->mc.aper_size;
386
387 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
388 rdev->mc.real_vram_size = rdev->mc.aper_size;
389
390 if (rdev->flags & RADEON_IS_AGP) {
391 r = radeon_agp_init(rdev);
392 if (r)
393 return r;
394 /* gtt_size is setup by radeon_agp_init */
395 rdev->mc.gtt_location = rdev->mc.agp_base;
396 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
397 /* Try to put vram before or after AGP because we
398 * we want SYSTEM_APERTURE to cover both VRAM and
399 * AGP so that GPU can catch out of VRAM/AGP access
400 */
401 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
402 /* Enought place before */
403 rdev->mc.vram_location = rdev->mc.gtt_location -
404 rdev->mc.mc_vram_size;
405 } else if (tmp > rdev->mc.mc_vram_size) {
406 /* Enought place after */
407 rdev->mc.vram_location = rdev->mc.gtt_location +
408 rdev->mc.gtt_size;
409 } else {
410 /* Try to setup VRAM then AGP might not
411 * not work on some card
412 */
413 rdev->mc.vram_location = 0x00000000UL;
414 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
415 }
416 } else {
417 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
418 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
419 0xFFFF) << 24;
420 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
421 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
422 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
423 /* Enough place after vram */
424 rdev->mc.gtt_location = tmp;
425 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
426 /* Enough place before vram */
427 rdev->mc.gtt_location = 0;
428 } else {
429 /* Not enough place after or before shrink
430 * gart size
431 */
432 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
433 rdev->mc.gtt_location = 0;
434 rdev->mc.gtt_size = rdev->mc.vram_location;
435 } else {
436 rdev->mc.gtt_location = tmp;
437 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
438 }
439 }
440 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
441 } else {
442 rdev->mc.vram_location = 0x00000000UL;
443 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
444 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
445 }
446 }
447 rdev->mc.vram_start = rdev->mc.vram_location;
448 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
449 rdev->mc.gtt_start = rdev->mc.gtt_location;
450 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
451 /* FIXME: we should enforce default clock in case GPU is not in
452 * default setup
453 */
454 a.full = rfixed_const(100);
455 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
456 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
457 return 0;
458 }
459
460 /* We doesn't check that the GPU really needs a reset we simply do the
461 * reset, it's up to the caller to determine if the GPU needs one. We
462 * might add an helper function to check that.
463 */
464 int r600_gpu_soft_reset(struct radeon_device *rdev)
465 {
466 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
467 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
468 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
469 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
470 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
471 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
472 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
473 S_008010_GUI_ACTIVE(1);
474 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
475 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
476 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
477 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
478 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
479 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
480 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
481 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
482 u32 srbm_reset = 0;
483
484 /* Disable CP parsing/prefetching */
485 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
486 /* Check if any of the rendering block is busy and reset it */
487 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
488 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
489 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
490 S_008020_SOFT_RESET_DB(1) |
491 S_008020_SOFT_RESET_CB(1) |
492 S_008020_SOFT_RESET_PA(1) |
493 S_008020_SOFT_RESET_SC(1) |
494 S_008020_SOFT_RESET_SMX(1) |
495 S_008020_SOFT_RESET_SPI(1) |
496 S_008020_SOFT_RESET_SX(1) |
497 S_008020_SOFT_RESET_SH(1) |
498 S_008020_SOFT_RESET_TC(1) |
499 S_008020_SOFT_RESET_TA(1) |
500 S_008020_SOFT_RESET_VC(1) |
501 S_008020_SOFT_RESET_VGT(1));
502 (void)RREG32(R_008020_GRBM_SOFT_RESET);
503 udelay(50);
504 WREG32(R_008020_GRBM_SOFT_RESET, 0);
505 (void)RREG32(R_008020_GRBM_SOFT_RESET);
506 }
507 /* Reset CP (we always reset CP) */
508 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
509 (void)RREG32(R_008020_GRBM_SOFT_RESET);
510 udelay(50);
511 WREG32(R_008020_GRBM_SOFT_RESET, 0);
512 (void)RREG32(R_008020_GRBM_SOFT_RESET);
513 /* Reset others GPU block if necessary */
514 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
515 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
516 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
517 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
518 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
519 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
520 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
521 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
522 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
523 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
524 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
525 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
526 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
527 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
528 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
529 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
530 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
531 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
532 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
533 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
534 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
535 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
536 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
537 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
538 udelay(50);
539 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
540 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
541 /* Wait a little for things to settle down */
542 udelay(50);
543 return 0;
544 }
545
546 int r600_gpu_reset(struct radeon_device *rdev)
547 {
548 return r600_gpu_soft_reset(rdev);
549 }
550
551 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
552 u32 num_backends,
553 u32 backend_disable_mask)
554 {
555 u32 backend_map = 0;
556 u32 enabled_backends_mask;
557 u32 enabled_backends_count;
558 u32 cur_pipe;
559 u32 swizzle_pipe[R6XX_MAX_PIPES];
560 u32 cur_backend;
561 u32 i;
562
563 if (num_tile_pipes > R6XX_MAX_PIPES)
564 num_tile_pipes = R6XX_MAX_PIPES;
565 if (num_tile_pipes < 1)
566 num_tile_pipes = 1;
567 if (num_backends > R6XX_MAX_BACKENDS)
568 num_backends = R6XX_MAX_BACKENDS;
569 if (num_backends < 1)
570 num_backends = 1;
571
572 enabled_backends_mask = 0;
573 enabled_backends_count = 0;
574 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
575 if (((backend_disable_mask >> i) & 1) == 0) {
576 enabled_backends_mask |= (1 << i);
577 ++enabled_backends_count;
578 }
579 if (enabled_backends_count == num_backends)
580 break;
581 }
582
583 if (enabled_backends_count == 0) {
584 enabled_backends_mask = 1;
585 enabled_backends_count = 1;
586 }
587
588 if (enabled_backends_count != num_backends)
589 num_backends = enabled_backends_count;
590
591 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
592 switch (num_tile_pipes) {
593 case 1:
594 swizzle_pipe[0] = 0;
595 break;
596 case 2:
597 swizzle_pipe[0] = 0;
598 swizzle_pipe[1] = 1;
599 break;
600 case 3:
601 swizzle_pipe[0] = 0;
602 swizzle_pipe[1] = 1;
603 swizzle_pipe[2] = 2;
604 break;
605 case 4:
606 swizzle_pipe[0] = 0;
607 swizzle_pipe[1] = 1;
608 swizzle_pipe[2] = 2;
609 swizzle_pipe[3] = 3;
610 break;
611 case 5:
612 swizzle_pipe[0] = 0;
613 swizzle_pipe[1] = 1;
614 swizzle_pipe[2] = 2;
615 swizzle_pipe[3] = 3;
616 swizzle_pipe[4] = 4;
617 break;
618 case 6:
619 swizzle_pipe[0] = 0;
620 swizzle_pipe[1] = 2;
621 swizzle_pipe[2] = 4;
622 swizzle_pipe[3] = 5;
623 swizzle_pipe[4] = 1;
624 swizzle_pipe[5] = 3;
625 break;
626 case 7:
627 swizzle_pipe[0] = 0;
628 swizzle_pipe[1] = 2;
629 swizzle_pipe[2] = 4;
630 swizzle_pipe[3] = 6;
631 swizzle_pipe[4] = 1;
632 swizzle_pipe[5] = 3;
633 swizzle_pipe[6] = 5;
634 break;
635 case 8:
636 swizzle_pipe[0] = 0;
637 swizzle_pipe[1] = 2;
638 swizzle_pipe[2] = 4;
639 swizzle_pipe[3] = 6;
640 swizzle_pipe[4] = 1;
641 swizzle_pipe[5] = 3;
642 swizzle_pipe[6] = 5;
643 swizzle_pipe[7] = 7;
644 break;
645 }
646
647 cur_backend = 0;
648 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
649 while (((1 << cur_backend) & enabled_backends_mask) == 0)
650 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
651
652 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
653
654 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
655 }
656
657 return backend_map;
658 }
659
660 int r600_count_pipe_bits(uint32_t val)
661 {
662 int i, ret = 0;
663
664 for (i = 0; i < 32; i++) {
665 ret += val & 1;
666 val >>= 1;
667 }
668 return ret;
669 }
670
671 void r600_gpu_init(struct radeon_device *rdev)
672 {
673 u32 tiling_config;
674 u32 ramcfg;
675 u32 tmp;
676 int i, j;
677 u32 sq_config;
678 u32 sq_gpr_resource_mgmt_1 = 0;
679 u32 sq_gpr_resource_mgmt_2 = 0;
680 u32 sq_thread_resource_mgmt = 0;
681 u32 sq_stack_resource_mgmt_1 = 0;
682 u32 sq_stack_resource_mgmt_2 = 0;
683
684 /* FIXME: implement */
685 switch (rdev->family) {
686 case CHIP_R600:
687 rdev->config.r600.max_pipes = 4;
688 rdev->config.r600.max_tile_pipes = 8;
689 rdev->config.r600.max_simds = 4;
690 rdev->config.r600.max_backends = 4;
691 rdev->config.r600.max_gprs = 256;
692 rdev->config.r600.max_threads = 192;
693 rdev->config.r600.max_stack_entries = 256;
694 rdev->config.r600.max_hw_contexts = 8;
695 rdev->config.r600.max_gs_threads = 16;
696 rdev->config.r600.sx_max_export_size = 128;
697 rdev->config.r600.sx_max_export_pos_size = 16;
698 rdev->config.r600.sx_max_export_smx_size = 128;
699 rdev->config.r600.sq_num_cf_insts = 2;
700 break;
701 case CHIP_RV630:
702 case CHIP_RV635:
703 rdev->config.r600.max_pipes = 2;
704 rdev->config.r600.max_tile_pipes = 2;
705 rdev->config.r600.max_simds = 3;
706 rdev->config.r600.max_backends = 1;
707 rdev->config.r600.max_gprs = 128;
708 rdev->config.r600.max_threads = 192;
709 rdev->config.r600.max_stack_entries = 128;
710 rdev->config.r600.max_hw_contexts = 8;
711 rdev->config.r600.max_gs_threads = 4;
712 rdev->config.r600.sx_max_export_size = 128;
713 rdev->config.r600.sx_max_export_pos_size = 16;
714 rdev->config.r600.sx_max_export_smx_size = 128;
715 rdev->config.r600.sq_num_cf_insts = 2;
716 break;
717 case CHIP_RV610:
718 case CHIP_RV620:
719 case CHIP_RS780:
720 case CHIP_RS880:
721 rdev->config.r600.max_pipes = 1;
722 rdev->config.r600.max_tile_pipes = 1;
723 rdev->config.r600.max_simds = 2;
724 rdev->config.r600.max_backends = 1;
725 rdev->config.r600.max_gprs = 128;
726 rdev->config.r600.max_threads = 192;
727 rdev->config.r600.max_stack_entries = 128;
728 rdev->config.r600.max_hw_contexts = 4;
729 rdev->config.r600.max_gs_threads = 4;
730 rdev->config.r600.sx_max_export_size = 128;
731 rdev->config.r600.sx_max_export_pos_size = 16;
732 rdev->config.r600.sx_max_export_smx_size = 128;
733 rdev->config.r600.sq_num_cf_insts = 1;
734 break;
735 case CHIP_RV670:
736 rdev->config.r600.max_pipes = 4;
737 rdev->config.r600.max_tile_pipes = 4;
738 rdev->config.r600.max_simds = 4;
739 rdev->config.r600.max_backends = 4;
740 rdev->config.r600.max_gprs = 192;
741 rdev->config.r600.max_threads = 192;
742 rdev->config.r600.max_stack_entries = 256;
743 rdev->config.r600.max_hw_contexts = 8;
744 rdev->config.r600.max_gs_threads = 16;
745 rdev->config.r600.sx_max_export_size = 128;
746 rdev->config.r600.sx_max_export_pos_size = 16;
747 rdev->config.r600.sx_max_export_smx_size = 128;
748 rdev->config.r600.sq_num_cf_insts = 2;
749 break;
750 default:
751 break;
752 }
753
754 /* Initialize HDP */
755 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
756 WREG32((0x2c14 + j), 0x00000000);
757 WREG32((0x2c18 + j), 0x00000000);
758 WREG32((0x2c1c + j), 0x00000000);
759 WREG32((0x2c20 + j), 0x00000000);
760 WREG32((0x2c24 + j), 0x00000000);
761 }
762
763 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
764
765 /* Setup tiling */
766 tiling_config = 0;
767 ramcfg = RREG32(RAMCFG);
768 switch (rdev->config.r600.max_tile_pipes) {
769 case 1:
770 tiling_config |= PIPE_TILING(0);
771 break;
772 case 2:
773 tiling_config |= PIPE_TILING(1);
774 break;
775 case 4:
776 tiling_config |= PIPE_TILING(2);
777 break;
778 case 8:
779 tiling_config |= PIPE_TILING(3);
780 break;
781 default:
782 break;
783 }
784 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
785 tiling_config |= GROUP_SIZE(0);
786 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
787 if (tmp > 3) {
788 tiling_config |= ROW_TILING(3);
789 tiling_config |= SAMPLE_SPLIT(3);
790 } else {
791 tiling_config |= ROW_TILING(tmp);
792 tiling_config |= SAMPLE_SPLIT(tmp);
793 }
794 tiling_config |= BANK_SWAPS(1);
795 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
796 rdev->config.r600.max_backends,
797 (0xff << rdev->config.r600.max_backends) & 0xff);
798 tiling_config |= BACKEND_MAP(tmp);
799 WREG32(GB_TILING_CONFIG, tiling_config);
800 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
801 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
802
803 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
804 WREG32(CC_RB_BACKEND_DISABLE, tmp);
805
806 /* Setup pipes */
807 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
808 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
809 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
810 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
811
812 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
813 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
814 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
815
816 /* Setup some CP states */
817 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
818 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
819
820 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
821 SYNC_WALKER | SYNC_ALIGNER));
822 /* Setup various GPU states */
823 if (rdev->family == CHIP_RV670)
824 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
825
826 tmp = RREG32(SX_DEBUG_1);
827 tmp |= SMX_EVENT_RELEASE;
828 if ((rdev->family > CHIP_R600))
829 tmp |= ENABLE_NEW_SMX_ADDRESS;
830 WREG32(SX_DEBUG_1, tmp);
831
832 if (((rdev->family) == CHIP_R600) ||
833 ((rdev->family) == CHIP_RV630) ||
834 ((rdev->family) == CHIP_RV610) ||
835 ((rdev->family) == CHIP_RV620) ||
836 ((rdev->family) == CHIP_RS780)) {
837 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
838 } else {
839 WREG32(DB_DEBUG, 0);
840 }
841 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
842 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
843
844 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
845 WREG32(VGT_NUM_INSTANCES, 0);
846
847 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
848 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
849
850 tmp = RREG32(SQ_MS_FIFO_SIZES);
851 if (((rdev->family) == CHIP_RV610) ||
852 ((rdev->family) == CHIP_RV620) ||
853 ((rdev->family) == CHIP_RS780)) {
854 tmp = (CACHE_FIFO_SIZE(0xa) |
855 FETCH_FIFO_HIWATER(0xa) |
856 DONE_FIFO_HIWATER(0xe0) |
857 ALU_UPDATE_FIFO_HIWATER(0x8));
858 } else if (((rdev->family) == CHIP_R600) ||
859 ((rdev->family) == CHIP_RV630)) {
860 tmp &= ~DONE_FIFO_HIWATER(0xff);
861 tmp |= DONE_FIFO_HIWATER(0x4);
862 }
863 WREG32(SQ_MS_FIFO_SIZES, tmp);
864
865 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
866 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
867 */
868 sq_config = RREG32(SQ_CONFIG);
869 sq_config &= ~(PS_PRIO(3) |
870 VS_PRIO(3) |
871 GS_PRIO(3) |
872 ES_PRIO(3));
873 sq_config |= (DX9_CONSTS |
874 VC_ENABLE |
875 PS_PRIO(0) |
876 VS_PRIO(1) |
877 GS_PRIO(2) |
878 ES_PRIO(3));
879
880 if ((rdev->family) == CHIP_R600) {
881 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
882 NUM_VS_GPRS(124) |
883 NUM_CLAUSE_TEMP_GPRS(4));
884 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
885 NUM_ES_GPRS(0));
886 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
887 NUM_VS_THREADS(48) |
888 NUM_GS_THREADS(4) |
889 NUM_ES_THREADS(4));
890 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
891 NUM_VS_STACK_ENTRIES(128));
892 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
893 NUM_ES_STACK_ENTRIES(0));
894 } else if (((rdev->family) == CHIP_RV610) ||
895 ((rdev->family) == CHIP_RV620) ||
896 ((rdev->family) == CHIP_RS780)) {
897 /* no vertex cache */
898 sq_config &= ~VC_ENABLE;
899
900 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
901 NUM_VS_GPRS(44) |
902 NUM_CLAUSE_TEMP_GPRS(2));
903 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
904 NUM_ES_GPRS(17));
905 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
906 NUM_VS_THREADS(78) |
907 NUM_GS_THREADS(4) |
908 NUM_ES_THREADS(31));
909 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
910 NUM_VS_STACK_ENTRIES(40));
911 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
912 NUM_ES_STACK_ENTRIES(16));
913 } else if (((rdev->family) == CHIP_RV630) ||
914 ((rdev->family) == CHIP_RV635)) {
915 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
916 NUM_VS_GPRS(44) |
917 NUM_CLAUSE_TEMP_GPRS(2));
918 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
919 NUM_ES_GPRS(18));
920 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
921 NUM_VS_THREADS(78) |
922 NUM_GS_THREADS(4) |
923 NUM_ES_THREADS(31));
924 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
925 NUM_VS_STACK_ENTRIES(40));
926 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
927 NUM_ES_STACK_ENTRIES(16));
928 } else if ((rdev->family) == CHIP_RV670) {
929 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
930 NUM_VS_GPRS(44) |
931 NUM_CLAUSE_TEMP_GPRS(2));
932 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
933 NUM_ES_GPRS(17));
934 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
935 NUM_VS_THREADS(78) |
936 NUM_GS_THREADS(4) |
937 NUM_ES_THREADS(31));
938 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
939 NUM_VS_STACK_ENTRIES(64));
940 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
941 NUM_ES_STACK_ENTRIES(64));
942 }
943
944 WREG32(SQ_CONFIG, sq_config);
945 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
946 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
947 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
948 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
949 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
950
951 if (((rdev->family) == CHIP_RV610) ||
952 ((rdev->family) == CHIP_RV620) ||
953 ((rdev->family) == CHIP_RS780)) {
954 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
955 } else {
956 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
957 }
958
959 /* More default values. 2D/3D driver should adjust as needed */
960 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
961 S1_X(0x4) | S1_Y(0xc)));
962 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
963 S1_X(0x2) | S1_Y(0x2) |
964 S2_X(0xa) | S2_Y(0x6) |
965 S3_X(0x6) | S3_Y(0xa)));
966 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
967 S1_X(0x4) | S1_Y(0xc) |
968 S2_X(0x1) | S2_Y(0x6) |
969 S3_X(0xa) | S3_Y(0xe)));
970 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
971 S5_X(0x0) | S5_Y(0x0) |
972 S6_X(0xb) | S6_Y(0x4) |
973 S7_X(0x7) | S7_Y(0x8)));
974
975 WREG32(VGT_STRMOUT_EN, 0);
976 tmp = rdev->config.r600.max_pipes * 16;
977 switch (rdev->family) {
978 case CHIP_RV610:
979 case CHIP_RS780:
980 case CHIP_RV620:
981 tmp += 32;
982 break;
983 case CHIP_RV670:
984 tmp += 128;
985 break;
986 default:
987 break;
988 }
989 if (tmp > 256) {
990 tmp = 256;
991 }
992 WREG32(VGT_ES_PER_GS, 128);
993 WREG32(VGT_GS_PER_ES, tmp);
994 WREG32(VGT_GS_PER_VS, 2);
995 WREG32(VGT_GS_VERTEX_REUSE, 16);
996
997 /* more default values. 2D/3D driver should adjust as needed */
998 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
999 WREG32(VGT_STRMOUT_EN, 0);
1000 WREG32(SX_MISC, 0);
1001 WREG32(PA_SC_MODE_CNTL, 0);
1002 WREG32(PA_SC_AA_CONFIG, 0);
1003 WREG32(PA_SC_LINE_STIPPLE, 0);
1004 WREG32(SPI_INPUT_Z, 0);
1005 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1006 WREG32(CB_COLOR7_FRAG, 0);
1007
1008 /* Clear render buffer base addresses */
1009 WREG32(CB_COLOR0_BASE, 0);
1010 WREG32(CB_COLOR1_BASE, 0);
1011 WREG32(CB_COLOR2_BASE, 0);
1012 WREG32(CB_COLOR3_BASE, 0);
1013 WREG32(CB_COLOR4_BASE, 0);
1014 WREG32(CB_COLOR5_BASE, 0);
1015 WREG32(CB_COLOR6_BASE, 0);
1016 WREG32(CB_COLOR7_BASE, 0);
1017 WREG32(CB_COLOR7_FRAG, 0);
1018
1019 switch (rdev->family) {
1020 case CHIP_RV610:
1021 case CHIP_RS780:
1022 case CHIP_RV620:
1023 tmp = TC_L2_SIZE(8);
1024 break;
1025 case CHIP_RV630:
1026 case CHIP_RV635:
1027 tmp = TC_L2_SIZE(4);
1028 break;
1029 case CHIP_R600:
1030 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1031 break;
1032 default:
1033 tmp = TC_L2_SIZE(0);
1034 break;
1035 }
1036 WREG32(TC_CNTL, tmp);
1037
1038 tmp = RREG32(HDP_HOST_PATH_CNTL);
1039 WREG32(HDP_HOST_PATH_CNTL, tmp);
1040
1041 tmp = RREG32(ARB_POP);
1042 tmp |= ENABLE_TC128;
1043 WREG32(ARB_POP, tmp);
1044
1045 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1046 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1047 NUM_CLIP_SEQ(3)));
1048 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1049 }
1050
1051
1052 /*
1053 * Indirect registers accessor
1054 */
1055 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1056 {
1057 u32 r;
1058
1059 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1060 (void)RREG32(PCIE_PORT_INDEX);
1061 r = RREG32(PCIE_PORT_DATA);
1062 return r;
1063 }
1064
1065 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1066 {
1067 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1068 (void)RREG32(PCIE_PORT_INDEX);
1069 WREG32(PCIE_PORT_DATA, (v));
1070 (void)RREG32(PCIE_PORT_DATA);
1071 }
1072
1073
1074 /*
1075 * CP & Ring
1076 */
1077 void r600_cp_stop(struct radeon_device *rdev)
1078 {
1079 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1080 }
1081
1082 int r600_cp_init_microcode(struct radeon_device *rdev)
1083 {
1084 struct platform_device *pdev;
1085 const char *chip_name;
1086 size_t pfp_req_size, me_req_size;
1087 char fw_name[30];
1088 int err;
1089
1090 DRM_DEBUG("\n");
1091
1092 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1093 err = IS_ERR(pdev);
1094 if (err) {
1095 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1096 return -EINVAL;
1097 }
1098
1099 switch (rdev->family) {
1100 case CHIP_R600: chip_name = "R600"; break;
1101 case CHIP_RV610: chip_name = "RV610"; break;
1102 case CHIP_RV630: chip_name = "RV630"; break;
1103 case CHIP_RV620: chip_name = "RV620"; break;
1104 case CHIP_RV635: chip_name = "RV635"; break;
1105 case CHIP_RV670: chip_name = "RV670"; break;
1106 case CHIP_RS780:
1107 case CHIP_RS880: chip_name = "RS780"; break;
1108 case CHIP_RV770: chip_name = "RV770"; break;
1109 case CHIP_RV730:
1110 case CHIP_RV740: chip_name = "RV730"; break;
1111 case CHIP_RV710: chip_name = "RV710"; break;
1112 default: BUG();
1113 }
1114
1115 if (rdev->family >= CHIP_RV770) {
1116 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1117 me_req_size = R700_PM4_UCODE_SIZE * 4;
1118 } else {
1119 pfp_req_size = PFP_UCODE_SIZE * 4;
1120 me_req_size = PM4_UCODE_SIZE * 12;
1121 }
1122
1123 DRM_INFO("Loading %s CP Microcode\n", chip_name);
1124
1125 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1126 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1127 if (err)
1128 goto out;
1129 if (rdev->pfp_fw->size != pfp_req_size) {
1130 printk(KERN_ERR
1131 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1132 rdev->pfp_fw->size, fw_name);
1133 err = -EINVAL;
1134 goto out;
1135 }
1136
1137 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1138 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1139 if (err)
1140 goto out;
1141 if (rdev->me_fw->size != me_req_size) {
1142 printk(KERN_ERR
1143 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1144 rdev->me_fw->size, fw_name);
1145 err = -EINVAL;
1146 }
1147 out:
1148 platform_device_unregister(pdev);
1149
1150 if (err) {
1151 if (err != -EINVAL)
1152 printk(KERN_ERR
1153 "r600_cp: Failed to load firmware \"%s\"\n",
1154 fw_name);
1155 release_firmware(rdev->pfp_fw);
1156 rdev->pfp_fw = NULL;
1157 release_firmware(rdev->me_fw);
1158 rdev->me_fw = NULL;
1159 }
1160 return err;
1161 }
1162
1163 static int r600_cp_load_microcode(struct radeon_device *rdev)
1164 {
1165 const __be32 *fw_data;
1166 int i;
1167
1168 if (!rdev->me_fw || !rdev->pfp_fw)
1169 return -EINVAL;
1170
1171 r600_cp_stop(rdev);
1172
1173 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1174
1175 /* Reset cp */
1176 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1177 RREG32(GRBM_SOFT_RESET);
1178 mdelay(15);
1179 WREG32(GRBM_SOFT_RESET, 0);
1180
1181 WREG32(CP_ME_RAM_WADDR, 0);
1182
1183 fw_data = (const __be32 *)rdev->me_fw->data;
1184 WREG32(CP_ME_RAM_WADDR, 0);
1185 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1186 WREG32(CP_ME_RAM_DATA,
1187 be32_to_cpup(fw_data++));
1188
1189 fw_data = (const __be32 *)rdev->pfp_fw->data;
1190 WREG32(CP_PFP_UCODE_ADDR, 0);
1191 for (i = 0; i < PFP_UCODE_SIZE; i++)
1192 WREG32(CP_PFP_UCODE_DATA,
1193 be32_to_cpup(fw_data++));
1194
1195 WREG32(CP_PFP_UCODE_ADDR, 0);
1196 WREG32(CP_ME_RAM_WADDR, 0);
1197 WREG32(CP_ME_RAM_RADDR, 0);
1198 return 0;
1199 }
1200
1201 int r600_cp_start(struct radeon_device *rdev)
1202 {
1203 int r;
1204 uint32_t cp_me;
1205
1206 r = radeon_ring_lock(rdev, 7);
1207 if (r) {
1208 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1209 return r;
1210 }
1211 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1212 radeon_ring_write(rdev, 0x1);
1213 if (rdev->family < CHIP_RV770) {
1214 radeon_ring_write(rdev, 0x3);
1215 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1216 } else {
1217 radeon_ring_write(rdev, 0x0);
1218 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1219 }
1220 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1221 radeon_ring_write(rdev, 0);
1222 radeon_ring_write(rdev, 0);
1223 radeon_ring_unlock_commit(rdev);
1224
1225 cp_me = 0xff;
1226 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1227 return 0;
1228 }
1229
1230 int r600_cp_resume(struct radeon_device *rdev)
1231 {
1232 u32 tmp;
1233 u32 rb_bufsz;
1234 int r;
1235
1236 /* Reset cp */
1237 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1238 RREG32(GRBM_SOFT_RESET);
1239 mdelay(15);
1240 WREG32(GRBM_SOFT_RESET, 0);
1241
1242 /* Set ring buffer size */
1243 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1244 #ifdef __BIG_ENDIAN
1245 WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
1246 (drm_order(4096/8) << 8) | rb_bufsz);
1247 #else
1248 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1249 #endif
1250 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1251
1252 /* Set the write pointer delay */
1253 WREG32(CP_RB_WPTR_DELAY, 0);
1254
1255 /* Initialize the ring buffer's read and write pointers */
1256 tmp = RREG32(CP_RB_CNTL);
1257 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1258 WREG32(CP_RB_RPTR_WR, 0);
1259 WREG32(CP_RB_WPTR, 0);
1260 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1261 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1262 mdelay(1);
1263 WREG32(CP_RB_CNTL, tmp);
1264
1265 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1266 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1267
1268 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1269 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1270
1271 r600_cp_start(rdev);
1272 rdev->cp.ready = true;
1273 r = radeon_ring_test(rdev);
1274 if (r) {
1275 rdev->cp.ready = false;
1276 return r;
1277 }
1278 return 0;
1279 }
1280
1281 void r600_cp_commit(struct radeon_device *rdev)
1282 {
1283 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1284 (void)RREG32(CP_RB_WPTR);
1285 }
1286
1287 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1288 {
1289 u32 rb_bufsz;
1290
1291 /* Align ring size */
1292 rb_bufsz = drm_order(ring_size / 8);
1293 ring_size = (1 << (rb_bufsz + 1)) * 4;
1294 rdev->cp.ring_size = ring_size;
1295 rdev->cp.align_mask = 16 - 1;
1296 }
1297
1298
1299 /*
1300 * GPU scratch registers helpers function.
1301 */
1302 void r600_scratch_init(struct radeon_device *rdev)
1303 {
1304 int i;
1305
1306 rdev->scratch.num_reg = 7;
1307 for (i = 0; i < rdev->scratch.num_reg; i++) {
1308 rdev->scratch.free[i] = true;
1309 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1310 }
1311 }
1312
1313 int r600_ring_test(struct radeon_device *rdev)
1314 {
1315 uint32_t scratch;
1316 uint32_t tmp = 0;
1317 unsigned i;
1318 int r;
1319
1320 r = radeon_scratch_get(rdev, &scratch);
1321 if (r) {
1322 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1323 return r;
1324 }
1325 WREG32(scratch, 0xCAFEDEAD);
1326 r = radeon_ring_lock(rdev, 3);
1327 if (r) {
1328 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1329 radeon_scratch_free(rdev, scratch);
1330 return r;
1331 }
1332 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1333 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1334 radeon_ring_write(rdev, 0xDEADBEEF);
1335 radeon_ring_unlock_commit(rdev);
1336 for (i = 0; i < rdev->usec_timeout; i++) {
1337 tmp = RREG32(scratch);
1338 if (tmp == 0xDEADBEEF)
1339 break;
1340 DRM_UDELAY(1);
1341 }
1342 if (i < rdev->usec_timeout) {
1343 DRM_INFO("ring test succeeded in %d usecs\n", i);
1344 } else {
1345 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1346 scratch, tmp);
1347 r = -EINVAL;
1348 }
1349 radeon_scratch_free(rdev, scratch);
1350 return r;
1351 }
1352
1353 /*
1354 * Writeback
1355 */
1356 int r600_wb_init(struct radeon_device *rdev)
1357 {
1358 int r;
1359
1360 if (rdev->wb.wb_obj == NULL) {
1361 r = radeon_object_create(rdev, NULL, 4096,
1362 true,
1363 RADEON_GEM_DOMAIN_GTT,
1364 false, &rdev->wb.wb_obj);
1365 if (r) {
1366 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
1367 return r;
1368 }
1369 r = radeon_object_pin(rdev->wb.wb_obj,
1370 RADEON_GEM_DOMAIN_GTT,
1371 &rdev->wb.gpu_addr);
1372 if (r) {
1373 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
1374 return r;
1375 }
1376 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1377 if (r) {
1378 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
1379 return r;
1380 }
1381 }
1382 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1383 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1384 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1385 WREG32(SCRATCH_UMSK, 0xff);
1386 return 0;
1387 }
1388
1389 void r600_wb_fini(struct radeon_device *rdev)
1390 {
1391 if (rdev->wb.wb_obj) {
1392 radeon_object_kunmap(rdev->wb.wb_obj);
1393 radeon_object_unpin(rdev->wb.wb_obj);
1394 radeon_object_unref(&rdev->wb.wb_obj);
1395 rdev->wb.wb = NULL;
1396 rdev->wb.wb_obj = NULL;
1397 }
1398 }
1399
1400
1401 /*
1402 * CS
1403 */
1404 void r600_fence_ring_emit(struct radeon_device *rdev,
1405 struct radeon_fence *fence)
1406 {
1407 /* Emit fence sequence & fire IRQ */
1408 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1409 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1410 radeon_ring_write(rdev, fence->seq);
1411 }
1412
1413 int r600_copy_dma(struct radeon_device *rdev,
1414 uint64_t src_offset,
1415 uint64_t dst_offset,
1416 unsigned num_pages,
1417 struct radeon_fence *fence)
1418 {
1419 /* FIXME: implement */
1420 return 0;
1421 }
1422
1423 int r600_copy_blit(struct radeon_device *rdev,
1424 uint64_t src_offset, uint64_t dst_offset,
1425 unsigned num_pages, struct radeon_fence *fence)
1426 {
1427 r600_blit_prepare_copy(rdev, num_pages * 4096);
1428 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
1429 r600_blit_done_copy(rdev, fence);
1430 return 0;
1431 }
1432
1433 int r600_irq_process(struct radeon_device *rdev)
1434 {
1435 /* FIXME: implement */
1436 return 0;
1437 }
1438
1439 int r600_irq_set(struct radeon_device *rdev)
1440 {
1441 /* FIXME: implement */
1442 return 0;
1443 }
1444
1445 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1446 uint32_t tiling_flags, uint32_t pitch,
1447 uint32_t offset, uint32_t obj_size)
1448 {
1449 /* FIXME: implement */
1450 return 0;
1451 }
1452
1453 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1454 {
1455 /* FIXME: implement */
1456 }
1457
1458
1459 bool r600_card_posted(struct radeon_device *rdev)
1460 {
1461 uint32_t reg;
1462
1463 /* first check CRTCs */
1464 reg = RREG32(D1CRTC_CONTROL) |
1465 RREG32(D2CRTC_CONTROL);
1466 if (reg & CRTC_EN)
1467 return true;
1468
1469 /* then check MEM_SIZE, in case the crtcs are off */
1470 if (RREG32(CONFIG_MEMSIZE))
1471 return true;
1472
1473 return false;
1474 }
1475
1476 int r600_startup(struct radeon_device *rdev)
1477 {
1478 int r;
1479
1480 r600_gpu_reset(rdev);
1481 r600_mc_resume(rdev);
1482 r = r600_pcie_gart_enable(rdev);
1483 if (r)
1484 return r;
1485 r600_gpu_init(rdev);
1486
1487 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1488 &rdev->r600_blit.shader_gpu_addr);
1489 if (r) {
1490 DRM_ERROR("failed to pin blit object %d\n", r);
1491 return r;
1492 }
1493
1494 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1495 if (r)
1496 return r;
1497 r = r600_cp_load_microcode(rdev);
1498 if (r)
1499 return r;
1500 r = r600_cp_resume(rdev);
1501 if (r)
1502 return r;
1503 r = r600_wb_init(rdev);
1504 if (r)
1505 return r;
1506 return 0;
1507 }
1508
1509 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1510 {
1511 uint32_t temp;
1512
1513 temp = RREG32(CONFIG_CNTL);
1514 if (state == false) {
1515 temp &= ~(1<<0);
1516 temp |= (1<<1);
1517 } else {
1518 temp &= ~(1<<1);
1519 }
1520 WREG32(CONFIG_CNTL, temp);
1521 }
1522
1523 int r600_resume(struct radeon_device *rdev)
1524 {
1525 int r;
1526
1527 if (radeon_gpu_reset(rdev)) {
1528 /* FIXME: what do we want to do here ? */
1529 }
1530 /* post card */
1531 if (rdev->is_atom_bios) {
1532 atom_asic_init(rdev->mode_info.atom_context);
1533 } else {
1534 radeon_combios_asic_init(rdev->ddev);
1535 }
1536 /* Initialize clocks */
1537 r = radeon_clocks_init(rdev);
1538 if (r) {
1539 return r;
1540 }
1541
1542 r = r600_startup(rdev);
1543 if (r) {
1544 DRM_ERROR("r600 startup failed on resume\n");
1545 return r;
1546 }
1547
1548 r = radeon_ib_test(rdev);
1549 if (r) {
1550 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1551 return r;
1552 }
1553 return r;
1554 }
1555
1556
1557 int r600_suspend(struct radeon_device *rdev)
1558 {
1559 /* FIXME: we should wait for ring to be empty */
1560 r600_cp_stop(rdev);
1561 rdev->cp.ready = false;
1562
1563 r600_pcie_gart_disable(rdev);
1564 /* unpin shaders bo */
1565 radeon_object_unpin(rdev->r600_blit.shader_obj);
1566 return 0;
1567 }
1568
1569 /* Plan is to move initialization in that function and use
1570 * helper function so that radeon_device_init pretty much
1571 * do nothing more than calling asic specific function. This
1572 * should also allow to remove a bunch of callback function
1573 * like vram_info.
1574 */
1575 int r600_init(struct radeon_device *rdev)
1576 {
1577 int r;
1578
1579 rdev->new_init_path = true;
1580 r = radeon_dummy_page_init(rdev);
1581 if (r)
1582 return r;
1583 if (r600_debugfs_mc_info_init(rdev)) {
1584 DRM_ERROR("Failed to register debugfs file for mc !\n");
1585 }
1586 /* This don't do much */
1587 r = radeon_gem_init(rdev);
1588 if (r)
1589 return r;
1590 /* Read BIOS */
1591 if (!radeon_get_bios(rdev)) {
1592 if (ASIC_IS_AVIVO(rdev))
1593 return -EINVAL;
1594 }
1595 /* Must be an ATOMBIOS */
1596 if (!rdev->is_atom_bios)
1597 return -EINVAL;
1598 r = radeon_atombios_init(rdev);
1599 if (r)
1600 return r;
1601 /* Post card if necessary */
1602 if (!r600_card_posted(rdev) && rdev->bios) {
1603 DRM_INFO("GPU not posted. posting now...\n");
1604 atom_asic_init(rdev->mode_info.atom_context);
1605 }
1606 /* Initialize scratch registers */
1607 r600_scratch_init(rdev);
1608 /* Initialize surface registers */
1609 radeon_surface_init(rdev);
1610 radeon_get_clock_info(rdev->ddev);
1611 r = radeon_clocks_init(rdev);
1612 if (r)
1613 return r;
1614 /* Fence driver */
1615 r = radeon_fence_driver_init(rdev);
1616 if (r)
1617 return r;
1618 r = r600_mc_init(rdev);
1619 if (r) {
1620 if (rdev->flags & RADEON_IS_AGP) {
1621 /* Retry with disabling AGP */
1622 r600_fini(rdev);
1623 rdev->flags &= ~RADEON_IS_AGP;
1624 return r600_init(rdev);
1625 }
1626 return r;
1627 }
1628 /* Memory manager */
1629 r = radeon_object_init(rdev);
1630 if (r)
1631 return r;
1632 rdev->cp.ring_obj = NULL;
1633 r600_ring_init(rdev, 1024 * 1024);
1634
1635 if (!rdev->me_fw || !rdev->pfp_fw) {
1636 r = r600_cp_init_microcode(rdev);
1637 if (r) {
1638 DRM_ERROR("Failed to load firmware!\n");
1639 return r;
1640 }
1641 }
1642
1643 r = r600_pcie_gart_init(rdev);
1644 if (r)
1645 return r;
1646
1647 rdev->accel_working = true;
1648 r = r600_blit_init(rdev);
1649 if (r) {
1650 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1651 return r;
1652 }
1653
1654 r = r600_startup(rdev);
1655 if (r) {
1656 if (rdev->flags & RADEON_IS_AGP) {
1657 /* Retry with disabling AGP */
1658 r600_fini(rdev);
1659 rdev->flags &= ~RADEON_IS_AGP;
1660 return r600_init(rdev);
1661 }
1662 rdev->accel_working = false;
1663 }
1664 if (rdev->accel_working) {
1665 r = radeon_ib_pool_init(rdev);
1666 if (r) {
1667 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1668 rdev->accel_working = false;
1669 }
1670 r = radeon_ib_test(rdev);
1671 if (r) {
1672 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1673 rdev->accel_working = false;
1674 }
1675 }
1676 return 0;
1677 }
1678
1679 void r600_fini(struct radeon_device *rdev)
1680 {
1681 /* Suspend operations */
1682 r600_suspend(rdev);
1683
1684 r600_blit_fini(rdev);
1685 radeon_ring_fini(rdev);
1686 r600_pcie_gart_fini(rdev);
1687 radeon_gem_fini(rdev);
1688 radeon_fence_driver_fini(rdev);
1689 radeon_clocks_fini(rdev);
1690 #if __OS_HAS_AGP
1691 if (rdev->flags & RADEON_IS_AGP)
1692 radeon_agp_fini(rdev);
1693 #endif
1694 radeon_object_fini(rdev);
1695 if (rdev->is_atom_bios)
1696 radeon_atombios_fini(rdev);
1697 else
1698 radeon_combios_fini(rdev);
1699 kfree(rdev->bios);
1700 rdev->bios = NULL;
1701 radeon_dummy_page_fini(rdev);
1702 }
1703
1704
1705 /*
1706 * CS stuff
1707 */
1708 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1709 {
1710 /* FIXME: implement */
1711 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1712 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1713 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1714 radeon_ring_write(rdev, ib->length_dw);
1715 }
1716
1717 int r600_ib_test(struct radeon_device *rdev)
1718 {
1719 struct radeon_ib *ib;
1720 uint32_t scratch;
1721 uint32_t tmp = 0;
1722 unsigned i;
1723 int r;
1724
1725 r = radeon_scratch_get(rdev, &scratch);
1726 if (r) {
1727 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1728 return r;
1729 }
1730 WREG32(scratch, 0xCAFEDEAD);
1731 r = radeon_ib_get(rdev, &ib);
1732 if (r) {
1733 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1734 return r;
1735 }
1736 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1737 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1738 ib->ptr[2] = 0xDEADBEEF;
1739 ib->ptr[3] = PACKET2(0);
1740 ib->ptr[4] = PACKET2(0);
1741 ib->ptr[5] = PACKET2(0);
1742 ib->ptr[6] = PACKET2(0);
1743 ib->ptr[7] = PACKET2(0);
1744 ib->ptr[8] = PACKET2(0);
1745 ib->ptr[9] = PACKET2(0);
1746 ib->ptr[10] = PACKET2(0);
1747 ib->ptr[11] = PACKET2(0);
1748 ib->ptr[12] = PACKET2(0);
1749 ib->ptr[13] = PACKET2(0);
1750 ib->ptr[14] = PACKET2(0);
1751 ib->ptr[15] = PACKET2(0);
1752 ib->length_dw = 16;
1753 r = radeon_ib_schedule(rdev, ib);
1754 if (r) {
1755 radeon_scratch_free(rdev, scratch);
1756 radeon_ib_free(rdev, &ib);
1757 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1758 return r;
1759 }
1760 r = radeon_fence_wait(ib->fence, false);
1761 if (r) {
1762 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1763 return r;
1764 }
1765 for (i = 0; i < rdev->usec_timeout; i++) {
1766 tmp = RREG32(scratch);
1767 if (tmp == 0xDEADBEEF)
1768 break;
1769 DRM_UDELAY(1);
1770 }
1771 if (i < rdev->usec_timeout) {
1772 DRM_INFO("ib test succeeded in %u usecs\n", i);
1773 } else {
1774 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1775 scratch, tmp);
1776 r = -EINVAL;
1777 }
1778 radeon_scratch_free(rdev, scratch);
1779 radeon_ib_free(rdev, &ib);
1780 return r;
1781 }
1782
1783
1784
1785
1786 /*
1787 * Debugfs info
1788 */
1789 #if defined(CONFIG_DEBUG_FS)
1790
1791 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1792 {
1793 struct drm_info_node *node = (struct drm_info_node *) m->private;
1794 struct drm_device *dev = node->minor->dev;
1795 struct radeon_device *rdev = dev->dev_private;
1796 uint32_t rdp, wdp;
1797 unsigned count, i, j;
1798
1799 radeon_ring_free_size(rdev);
1800 rdp = RREG32(CP_RB_RPTR);
1801 wdp = RREG32(CP_RB_WPTR);
1802 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1803 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1804 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1805 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1806 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1807 seq_printf(m, "%u dwords in ring\n", count);
1808 for (j = 0; j <= count; j++) {
1809 i = (rdp + j) & rdev->cp.ptr_mask;
1810 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1811 }
1812 return 0;
1813 }
1814
1815 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1816 {
1817 struct drm_info_node *node = (struct drm_info_node *) m->private;
1818 struct drm_device *dev = node->minor->dev;
1819 struct radeon_device *rdev = dev->dev_private;
1820
1821 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1822 DREG32_SYS(m, rdev, VM_L2_STATUS);
1823 return 0;
1824 }
1825
1826 static struct drm_info_list r600_mc_info_list[] = {
1827 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1828 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1829 };
1830 #endif
1831
1832 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1833 {
1834 #if defined(CONFIG_DEBUG_FS)
1835 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1836 #else
1837 return 0;
1838 #endif
1839 }
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