2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
29 #include <linux/module.h>
32 #include <drm/radeon_drm.h>
33 #include "radeon_drv.h"
35 #define PFP_UCODE_SIZE 576
36 #define PM4_UCODE_SIZE 1792
37 #define R700_PFP_UCODE_SIZE 848
38 #define R700_PM4_UCODE_SIZE 1360
41 MODULE_FIRMWARE("radeon/R600_pfp.bin");
42 MODULE_FIRMWARE("radeon/R600_me.bin");
43 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
44 MODULE_FIRMWARE("radeon/RV610_me.bin");
45 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
46 MODULE_FIRMWARE("radeon/RV630_me.bin");
47 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
48 MODULE_FIRMWARE("radeon/RV620_me.bin");
49 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV635_me.bin");
51 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV670_me.bin");
53 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
54 MODULE_FIRMWARE("radeon/RS780_me.bin");
55 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV770_me.bin");
57 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV730_me.bin");
59 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV710_me.bin");
63 int r600_cs_legacy(struct drm_device
*dev
, void *data
, struct drm_file
*filp
,
64 unsigned family
, u32
*ib
, int *l
);
65 void r600_cs_legacy_init(void);
68 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
69 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
71 #define R600_PTE_VALID (1 << 0)
72 #define R600_PTE_SYSTEM (1 << 1)
73 #define R600_PTE_SNOOPED (1 << 2)
74 #define R600_PTE_READABLE (1 << 5)
75 #define R600_PTE_WRITEABLE (1 << 6)
77 /* MAX values used for gfx init */
78 #define R6XX_MAX_SH_GPRS 256
79 #define R6XX_MAX_TEMP_GPRS 16
80 #define R6XX_MAX_SH_THREADS 256
81 #define R6XX_MAX_SH_STACK_ENTRIES 4096
82 #define R6XX_MAX_BACKENDS 8
83 #define R6XX_MAX_BACKENDS_MASK 0xff
84 #define R6XX_MAX_SIMDS 8
85 #define R6XX_MAX_SIMDS_MASK 0xff
86 #define R6XX_MAX_PIPES 8
87 #define R6XX_MAX_PIPES_MASK 0xff
89 #define R7XX_MAX_SH_GPRS 256
90 #define R7XX_MAX_TEMP_GPRS 16
91 #define R7XX_MAX_SH_THREADS 256
92 #define R7XX_MAX_SH_STACK_ENTRIES 4096
93 #define R7XX_MAX_BACKENDS 8
94 #define R7XX_MAX_BACKENDS_MASK 0xff
95 #define R7XX_MAX_SIMDS 16
96 #define R7XX_MAX_SIMDS_MASK 0xffff
97 #define R7XX_MAX_PIPES 8
98 #define R7XX_MAX_PIPES_MASK 0xff
100 static int r600_do_wait_for_fifo(drm_radeon_private_t
*dev_priv
, int entries
)
104 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
106 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
108 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
109 slots
= (RADEON_READ(R600_GRBM_STATUS
)
110 & R700_CMDFIFO_AVAIL_MASK
);
112 slots
= (RADEON_READ(R600_GRBM_STATUS
)
113 & R600_CMDFIFO_AVAIL_MASK
);
114 if (slots
>= entries
)
118 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
119 RADEON_READ(R600_GRBM_STATUS
),
120 RADEON_READ(R600_GRBM_STATUS2
));
125 static int r600_do_wait_for_idle(drm_radeon_private_t
*dev_priv
)
129 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
131 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)
132 ret
= r600_do_wait_for_fifo(dev_priv
, 8);
134 ret
= r600_do_wait_for_fifo(dev_priv
, 16);
137 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
138 if (!(RADEON_READ(R600_GRBM_STATUS
) & R600_GUI_ACTIVE
))
142 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
143 RADEON_READ(R600_GRBM_STATUS
),
144 RADEON_READ(R600_GRBM_STATUS2
));
149 void r600_page_table_cleanup(struct drm_device
*dev
, struct drm_ati_pcigart_info
*gart_info
)
151 struct drm_sg_mem
*entry
= dev
->sg
;
159 if (gart_info
->bus_addr
) {
160 max_pages
= (gart_info
->table_size
/ sizeof(u64
));
161 pages
= (entry
->pages
<= max_pages
)
162 ? entry
->pages
: max_pages
;
164 for (i
= 0; i
< pages
; i
++) {
165 if (!entry
->busaddr
[i
])
167 pci_unmap_page(dev
->pdev
, entry
->busaddr
[i
],
168 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
170 if (gart_info
->gart_table_location
== DRM_ATI_GART_MAIN
)
171 gart_info
->bus_addr
= 0;
175 /* R600 has page table setup */
176 int r600_page_table_init(struct drm_device
*dev
)
178 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
179 struct drm_ati_pcigart_info
*gart_info
= &dev_priv
->gart_info
;
180 struct drm_local_map
*map
= &gart_info
->mapping
;
181 struct drm_sg_mem
*entry
= dev
->sg
;
186 dma_addr_t entry_addr
;
187 int max_ati_pages
, max_real_pages
, gart_idx
;
189 /* okay page table is available - lets rock */
190 max_ati_pages
= (gart_info
->table_size
/ sizeof(u64
));
191 max_real_pages
= max_ati_pages
/ (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
);
193 pages
= (entry
->pages
<= max_real_pages
) ?
194 entry
->pages
: max_real_pages
;
196 memset_io((void __iomem
*)map
->handle
, 0, max_ati_pages
* sizeof(u64
));
199 for (i
= 0; i
< pages
; i
++) {
200 entry
->busaddr
[i
] = pci_map_page(dev
->pdev
,
201 entry
->pagelist
[i
], 0,
203 PCI_DMA_BIDIRECTIONAL
);
204 if (pci_dma_mapping_error(dev
->pdev
, entry
->busaddr
[i
])) {
205 DRM_ERROR("unable to map PCIGART pages!\n");
206 r600_page_table_cleanup(dev
, gart_info
);
209 entry_addr
= entry
->busaddr
[i
];
210 for (j
= 0; j
< (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
); j
++) {
211 page_base
= (u64
) entry_addr
& ATI_PCIGART_PAGE_MASK
;
212 page_base
|= R600_PTE_VALID
| R600_PTE_SYSTEM
| R600_PTE_SNOOPED
;
213 page_base
|= R600_PTE_READABLE
| R600_PTE_WRITEABLE
;
215 DRM_WRITE64(map
, gart_idx
* sizeof(u64
), page_base
);
220 DRM_DEBUG("page entry %d: 0x%016llx\n",
221 i
, (unsigned long long)page_base
);
222 entry_addr
+= ATI_PCIGART_PAGE_SIZE
;
230 static void r600_vm_flush_gart_range(struct drm_device
*dev
)
232 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
233 u32 resp
, countdown
= 1000;
234 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
235 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
236 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE
, 2);
239 resp
= RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE
);
242 } while (((resp
& 0xf0) == 0) && countdown
);
245 static void r600_vm_init(struct drm_device
*dev
)
247 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
248 /* initialise the VM to use the page table we constructed up there */
251 u32 vm_l2_cntl
, vm_l2_cntl3
;
252 /* okay set up the PCIE aperture type thingo */
253 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
255 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
258 mc_rd_a
= R600_MCD_L1_TLB
| R600_MCD_L1_FRAG_PROC
| R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS
|
259 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
| R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
260 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY
;
262 RADEON_WRITE(R600_MCD_RD_A_CNTL
, mc_rd_a
);
263 RADEON_WRITE(R600_MCD_RD_B_CNTL
, mc_rd_a
);
265 RADEON_WRITE(R600_MCD_WR_A_CNTL
, mc_rd_a
);
266 RADEON_WRITE(R600_MCD_WR_B_CNTL
, mc_rd_a
);
268 RADEON_WRITE(R600_MCD_RD_GFX_CNTL
, mc_rd_a
);
269 RADEON_WRITE(R600_MCD_WR_GFX_CNTL
, mc_rd_a
);
271 RADEON_WRITE(R600_MCD_RD_SYS_CNTL
, mc_rd_a
);
272 RADEON_WRITE(R600_MCD_WR_SYS_CNTL
, mc_rd_a
);
274 RADEON_WRITE(R600_MCD_RD_HDP_CNTL
, mc_rd_a
| R600_MCD_L1_STRICT_ORDERING
);
275 RADEON_WRITE(R600_MCD_WR_HDP_CNTL
, mc_rd_a
/*| R600_MCD_L1_STRICT_ORDERING*/);
277 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL
, mc_rd_a
);
278 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL
, mc_rd_a
);
280 RADEON_WRITE(R600_MCD_RD_SEM_CNTL
, mc_rd_a
| R600_MCD_SEMAPHORE_MODE
);
281 RADEON_WRITE(R600_MCD_WR_SEM_CNTL
, mc_rd_a
);
283 vm_l2_cntl
= R600_VM_L2_CACHE_EN
| R600_VM_L2_FRAG_PROC
| R600_VM_ENABLE_PTE_CACHE_LRU_W
;
284 vm_l2_cntl
|= R600_VM_L2_CNTL_QUEUE_SIZE(7);
285 RADEON_WRITE(R600_VM_L2_CNTL
, vm_l2_cntl
);
287 RADEON_WRITE(R600_VM_L2_CNTL2
, 0);
288 vm_l2_cntl3
= (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
289 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
290 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
291 RADEON_WRITE(R600_VM_L2_CNTL3
, vm_l2_cntl3
);
293 vm_c0
= R600_VM_ENABLE_CONTEXT
| R600_VM_PAGE_TABLE_DEPTH_FLAT
;
295 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
, vm_c0
);
297 vm_c0
&= ~R600_VM_ENABLE_CONTEXT
;
299 /* disable all other contexts */
300 for (i
= 1; i
< 8; i
++)
301 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
+ (i
* 4), vm_c0
);
303 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, dev_priv
->gart_info
.bus_addr
>> 12);
304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR
, dev_priv
->gart_vm_start
>> 12);
305 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
307 r600_vm_flush_gart_range(dev
);
310 static int r600_cp_init_microcode(drm_radeon_private_t
*dev_priv
)
312 struct platform_device
*pdev
;
313 const char *chip_name
;
314 size_t pfp_req_size
, me_req_size
;
318 pdev
= platform_device_register_simple("r600_cp", 0, NULL
, 0);
321 printk(KERN_ERR
"r600_cp: Failed to register firmware\n");
325 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
326 case CHIP_R600
: chip_name
= "R600"; break;
327 case CHIP_RV610
: chip_name
= "RV610"; break;
328 case CHIP_RV630
: chip_name
= "RV630"; break;
329 case CHIP_RV620
: chip_name
= "RV620"; break;
330 case CHIP_RV635
: chip_name
= "RV635"; break;
331 case CHIP_RV670
: chip_name
= "RV670"; break;
333 case CHIP_RS880
: chip_name
= "RS780"; break;
334 case CHIP_RV770
: chip_name
= "RV770"; break;
336 case CHIP_RV740
: chip_name
= "RV730"; break;
337 case CHIP_RV710
: chip_name
= "RV710"; break;
341 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
) {
342 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
343 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
345 pfp_req_size
= PFP_UCODE_SIZE
* 4;
346 me_req_size
= PM4_UCODE_SIZE
* 12;
349 DRM_INFO("Loading %s CP Microcode\n", chip_name
);
351 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
352 err
= request_firmware(&dev_priv
->pfp_fw
, fw_name
, &pdev
->dev
);
355 if (dev_priv
->pfp_fw
->size
!= pfp_req_size
) {
357 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
358 dev_priv
->pfp_fw
->size
, fw_name
);
363 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
364 err
= request_firmware(&dev_priv
->me_fw
, fw_name
, &pdev
->dev
);
367 if (dev_priv
->me_fw
->size
!= me_req_size
) {
369 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
370 dev_priv
->me_fw
->size
, fw_name
);
374 platform_device_unregister(pdev
);
379 "r600_cp: Failed to load firmware \"%s\"\n",
381 release_firmware(dev_priv
->pfp_fw
);
382 dev_priv
->pfp_fw
= NULL
;
383 release_firmware(dev_priv
->me_fw
);
384 dev_priv
->me_fw
= NULL
;
389 static void r600_cp_load_microcode(drm_radeon_private_t
*dev_priv
)
391 const __be32
*fw_data
;
394 if (!dev_priv
->me_fw
|| !dev_priv
->pfp_fw
)
397 r600_do_cp_stop(dev_priv
);
399 RADEON_WRITE(R600_CP_RB_CNTL
,
401 R600_BUF_SWAP_32BIT
|
407 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
408 RADEON_READ(R600_GRBM_SOFT_RESET
);
410 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
412 fw_data
= (const __be32
*)dev_priv
->me_fw
->data
;
413 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
414 for (i
= 0; i
< PM4_UCODE_SIZE
* 3; i
++)
415 RADEON_WRITE(R600_CP_ME_RAM_DATA
,
416 be32_to_cpup(fw_data
++));
418 fw_data
= (const __be32
*)dev_priv
->pfp_fw
->data
;
419 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
420 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
421 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
,
422 be32_to_cpup(fw_data
++));
424 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
425 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
426 RADEON_WRITE(R600_CP_ME_RAM_RADDR
, 0);
430 static void r700_vm_init(struct drm_device
*dev
)
432 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
433 /* initialise the VM to use the page table we constructed up there */
436 u32 vm_l2_cntl
, vm_l2_cntl3
;
437 /* okay set up the PCIE aperture type thingo */
438 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR
, dev_priv
->gart_vm_start
>> 12);
439 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
440 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
442 mc_vm_md_l1
= R700_ENABLE_L1_TLB
|
443 R700_ENABLE_L1_FRAGMENT_PROCESSING
|
444 R700_SYSTEM_ACCESS_MODE_IN_SYS
|
445 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
446 R700_EFFECTIVE_L1_TLB_SIZE(5) |
447 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
449 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL
, mc_vm_md_l1
);
450 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL
, mc_vm_md_l1
);
451 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL
, mc_vm_md_l1
);
452 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL
, mc_vm_md_l1
);
453 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL
, mc_vm_md_l1
);
454 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL
, mc_vm_md_l1
);
455 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL
, mc_vm_md_l1
);
457 vm_l2_cntl
= R600_VM_L2_CACHE_EN
| R600_VM_L2_FRAG_PROC
| R600_VM_ENABLE_PTE_CACHE_LRU_W
;
458 vm_l2_cntl
|= R700_VM_L2_CNTL_QUEUE_SIZE(7);
459 RADEON_WRITE(R600_VM_L2_CNTL
, vm_l2_cntl
);
461 RADEON_WRITE(R600_VM_L2_CNTL2
, 0);
462 vm_l2_cntl3
= R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
463 RADEON_WRITE(R600_VM_L2_CNTL3
, vm_l2_cntl3
);
465 vm_c0
= R600_VM_ENABLE_CONTEXT
| R600_VM_PAGE_TABLE_DEPTH_FLAT
;
467 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
, vm_c0
);
469 vm_c0
&= ~R600_VM_ENABLE_CONTEXT
;
471 /* disable all other contexts */
472 for (i
= 1; i
< 8; i
++)
473 RADEON_WRITE(R600_VM_CONTEXT0_CNTL
+ (i
* 4), vm_c0
);
475 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, dev_priv
->gart_info
.bus_addr
>> 12);
476 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR
, dev_priv
->gart_vm_start
>> 12);
477 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR
, (dev_priv
->gart_vm_start
+ dev_priv
->gart_size
- 1) >> 12);
479 r600_vm_flush_gart_range(dev
);
482 static void r700_cp_load_microcode(drm_radeon_private_t
*dev_priv
)
484 const __be32
*fw_data
;
487 if (!dev_priv
->me_fw
|| !dev_priv
->pfp_fw
)
490 r600_do_cp_stop(dev_priv
);
492 RADEON_WRITE(R600_CP_RB_CNTL
,
494 R600_BUF_SWAP_32BIT
|
500 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
501 RADEON_READ(R600_GRBM_SOFT_RESET
);
503 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
505 fw_data
= (const __be32
*)dev_priv
->pfp_fw
->data
;
506 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
507 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
508 RADEON_WRITE(R600_CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
509 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
511 fw_data
= (const __be32
*)dev_priv
->me_fw
->data
;
512 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
513 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
514 RADEON_WRITE(R600_CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
515 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
517 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR
, 0);
518 RADEON_WRITE(R600_CP_ME_RAM_WADDR
, 0);
519 RADEON_WRITE(R600_CP_ME_RAM_RADDR
, 0);
523 static void r600_test_writeback(drm_radeon_private_t
*dev_priv
)
527 /* Start with assuming that writeback doesn't work */
528 dev_priv
->writeback_works
= 0;
530 /* Writeback doesn't seem to work everywhere, test it here and possibly
531 * enable it if it appears to work
533 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(1), 0);
535 RADEON_WRITE(R600_SCRATCH_REG1
, 0xdeadbeef);
537 for (tmp
= 0; tmp
< dev_priv
->usec_timeout
; tmp
++) {
540 val
= radeon_read_ring_rptr(dev_priv
, R600_SCRATCHOFF(1));
541 if (val
== 0xdeadbeef)
546 if (tmp
< dev_priv
->usec_timeout
) {
547 dev_priv
->writeback_works
= 1;
548 DRM_INFO("writeback test succeeded in %d usecs\n", tmp
);
550 dev_priv
->writeback_works
= 0;
551 DRM_INFO("writeback test failed\n");
553 if (radeon_no_wb
== 1) {
554 dev_priv
->writeback_works
= 0;
555 DRM_INFO("writeback forced off\n");
558 if (!dev_priv
->writeback_works
) {
559 /* Disable writeback to avoid unnecessary bus master transfer */
560 RADEON_WRITE(R600_CP_RB_CNTL
,
562 R600_BUF_SWAP_32BIT
|
564 RADEON_READ(R600_CP_RB_CNTL
) |
566 RADEON_WRITE(R600_SCRATCH_UMSK
, 0);
570 int r600_do_engine_reset(struct drm_device
*dev
)
572 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
573 u32 cp_ptr
, cp_me_cntl
, cp_rb_cntl
;
575 DRM_INFO("Resetting GPU\n");
577 cp_ptr
= RADEON_READ(R600_CP_RB_WPTR
);
578 cp_me_cntl
= RADEON_READ(R600_CP_ME_CNTL
);
579 RADEON_WRITE(R600_CP_ME_CNTL
, R600_CP_ME_HALT
);
581 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0x7fff);
582 RADEON_READ(R600_GRBM_SOFT_RESET
);
584 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
585 RADEON_READ(R600_GRBM_SOFT_RESET
);
587 RADEON_WRITE(R600_CP_RB_WPTR_DELAY
, 0);
588 cp_rb_cntl
= RADEON_READ(R600_CP_RB_CNTL
);
589 RADEON_WRITE(R600_CP_RB_CNTL
,
591 R600_BUF_SWAP_32BIT
|
593 R600_RB_RPTR_WR_ENA
);
595 RADEON_WRITE(R600_CP_RB_RPTR_WR
, cp_ptr
);
596 RADEON_WRITE(R600_CP_RB_WPTR
, cp_ptr
);
597 RADEON_WRITE(R600_CP_RB_CNTL
, cp_rb_cntl
);
598 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me_cntl
);
600 /* Reset the CP ring */
601 r600_do_cp_reset(dev_priv
);
603 /* The CP is no longer running after an engine reset */
604 dev_priv
->cp_running
= 0;
606 /* Reset any pending vertex, indirect buffers */
607 radeon_freelist_reset(dev
);
613 static u32
r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
615 u32 backend_disable_mask
)
618 u32 enabled_backends_mask
;
619 u32 enabled_backends_count
;
621 u32 swizzle_pipe
[R6XX_MAX_PIPES
];
625 if (num_tile_pipes
> R6XX_MAX_PIPES
)
626 num_tile_pipes
= R6XX_MAX_PIPES
;
627 if (num_tile_pipes
< 1)
629 if (num_backends
> R6XX_MAX_BACKENDS
)
630 num_backends
= R6XX_MAX_BACKENDS
;
631 if (num_backends
< 1)
634 enabled_backends_mask
= 0;
635 enabled_backends_count
= 0;
636 for (i
= 0; i
< R6XX_MAX_BACKENDS
; ++i
) {
637 if (((backend_disable_mask
>> i
) & 1) == 0) {
638 enabled_backends_mask
|= (1 << i
);
639 ++enabled_backends_count
;
641 if (enabled_backends_count
== num_backends
)
645 if (enabled_backends_count
== 0) {
646 enabled_backends_mask
= 1;
647 enabled_backends_count
= 1;
650 if (enabled_backends_count
!= num_backends
)
651 num_backends
= enabled_backends_count
;
653 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R6XX_MAX_PIPES
);
654 switch (num_tile_pipes
) {
710 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
711 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
712 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
714 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
716 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
722 static int r600_count_pipe_bits(uint32_t val
)
725 for (i
= 0; i
< 32; i
++) {
732 static void r600_gfx_init(struct drm_device
*dev
,
733 drm_radeon_private_t
*dev_priv
)
735 int i
, j
, num_qd_pipes
;
739 u32 num_gs_verts_per_thread
;
741 u32 gs_prim_buffer_depth
= 0;
742 u32 sq_ms_fifo_sizes
;
744 u32 sq_gpr_resource_mgmt_1
= 0;
745 u32 sq_gpr_resource_mgmt_2
= 0;
746 u32 sq_thread_resource_mgmt
= 0;
747 u32 sq_stack_resource_mgmt_1
= 0;
748 u32 sq_stack_resource_mgmt_2
= 0;
749 u32 hdp_host_path_cntl
;
751 u32 gb_tiling_config
= 0;
752 u32 cc_rb_backend_disable
;
753 u32 cc_gc_shader_pipe_config
;
756 /* setup chip specs */
757 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
759 dev_priv
->r600_max_pipes
= 4;
760 dev_priv
->r600_max_tile_pipes
= 8;
761 dev_priv
->r600_max_simds
= 4;
762 dev_priv
->r600_max_backends
= 4;
763 dev_priv
->r600_max_gprs
= 256;
764 dev_priv
->r600_max_threads
= 192;
765 dev_priv
->r600_max_stack_entries
= 256;
766 dev_priv
->r600_max_hw_contexts
= 8;
767 dev_priv
->r600_max_gs_threads
= 16;
768 dev_priv
->r600_sx_max_export_size
= 128;
769 dev_priv
->r600_sx_max_export_pos_size
= 16;
770 dev_priv
->r600_sx_max_export_smx_size
= 128;
771 dev_priv
->r600_sq_num_cf_insts
= 2;
775 dev_priv
->r600_max_pipes
= 2;
776 dev_priv
->r600_max_tile_pipes
= 2;
777 dev_priv
->r600_max_simds
= 3;
778 dev_priv
->r600_max_backends
= 1;
779 dev_priv
->r600_max_gprs
= 128;
780 dev_priv
->r600_max_threads
= 192;
781 dev_priv
->r600_max_stack_entries
= 128;
782 dev_priv
->r600_max_hw_contexts
= 8;
783 dev_priv
->r600_max_gs_threads
= 4;
784 dev_priv
->r600_sx_max_export_size
= 128;
785 dev_priv
->r600_sx_max_export_pos_size
= 16;
786 dev_priv
->r600_sx_max_export_smx_size
= 128;
787 dev_priv
->r600_sq_num_cf_insts
= 2;
793 dev_priv
->r600_max_pipes
= 1;
794 dev_priv
->r600_max_tile_pipes
= 1;
795 dev_priv
->r600_max_simds
= 2;
796 dev_priv
->r600_max_backends
= 1;
797 dev_priv
->r600_max_gprs
= 128;
798 dev_priv
->r600_max_threads
= 192;
799 dev_priv
->r600_max_stack_entries
= 128;
800 dev_priv
->r600_max_hw_contexts
= 4;
801 dev_priv
->r600_max_gs_threads
= 4;
802 dev_priv
->r600_sx_max_export_size
= 128;
803 dev_priv
->r600_sx_max_export_pos_size
= 16;
804 dev_priv
->r600_sx_max_export_smx_size
= 128;
805 dev_priv
->r600_sq_num_cf_insts
= 1;
808 dev_priv
->r600_max_pipes
= 4;
809 dev_priv
->r600_max_tile_pipes
= 4;
810 dev_priv
->r600_max_simds
= 4;
811 dev_priv
->r600_max_backends
= 4;
812 dev_priv
->r600_max_gprs
= 192;
813 dev_priv
->r600_max_threads
= 192;
814 dev_priv
->r600_max_stack_entries
= 256;
815 dev_priv
->r600_max_hw_contexts
= 8;
816 dev_priv
->r600_max_gs_threads
= 16;
817 dev_priv
->r600_sx_max_export_size
= 128;
818 dev_priv
->r600_sx_max_export_pos_size
= 16;
819 dev_priv
->r600_sx_max_export_smx_size
= 128;
820 dev_priv
->r600_sq_num_cf_insts
= 2;
828 for (i
= 0; i
< 32; i
++) {
829 RADEON_WRITE((0x2c14 + j
), 0x00000000);
830 RADEON_WRITE((0x2c18 + j
), 0x00000000);
831 RADEON_WRITE((0x2c1c + j
), 0x00000000);
832 RADEON_WRITE((0x2c20 + j
), 0x00000000);
833 RADEON_WRITE((0x2c24 + j
), 0x00000000);
837 RADEON_WRITE(R600_GRBM_CNTL
, R600_GRBM_READ_TIMEOUT(0xff));
839 /* setup tiling, simd, pipe config */
840 ramcfg
= RADEON_READ(R600_RAMCFG
);
842 switch (dev_priv
->r600_max_tile_pipes
) {
844 gb_tiling_config
|= R600_PIPE_TILING(0);
847 gb_tiling_config
|= R600_PIPE_TILING(1);
850 gb_tiling_config
|= R600_PIPE_TILING(2);
853 gb_tiling_config
|= R600_PIPE_TILING(3);
859 gb_tiling_config
|= R600_BANK_TILING((ramcfg
>> R600_NOOFBANK_SHIFT
) & R600_NOOFBANK_MASK
);
861 gb_tiling_config
|= R600_GROUP_SIZE(0);
863 if (((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
) > 3) {
864 gb_tiling_config
|= R600_ROW_TILING(3);
865 gb_tiling_config
|= R600_SAMPLE_SPLIT(3);
868 R600_ROW_TILING(((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
));
870 R600_SAMPLE_SPLIT(((ramcfg
>> R600_NOOFROWS_SHIFT
) & R600_NOOFROWS_MASK
));
873 gb_tiling_config
|= R600_BANK_SWAPS(1);
875 cc_rb_backend_disable
= RADEON_READ(R600_CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
876 cc_rb_backend_disable
|=
877 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK
<< dev_priv
->r600_max_backends
) & R6XX_MAX_BACKENDS_MASK
);
879 cc_gc_shader_pipe_config
= RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
880 cc_gc_shader_pipe_config
|=
881 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK
<< dev_priv
->r600_max_pipes
) & R6XX_MAX_PIPES_MASK
);
882 cc_gc_shader_pipe_config
|=
883 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK
<< dev_priv
->r600_max_simds
) & R6XX_MAX_SIMDS_MASK
);
885 backend_map
= r600_get_tile_pipe_to_backend_map(dev_priv
->r600_max_tile_pipes
,
887 r600_count_pipe_bits((cc_rb_backend_disable
&
888 R6XX_MAX_BACKENDS_MASK
) >> 16)),
889 (cc_rb_backend_disable
>> 16));
890 gb_tiling_config
|= R600_BACKEND_MAP(backend_map
);
892 RADEON_WRITE(R600_GB_TILING_CONFIG
, gb_tiling_config
);
893 RADEON_WRITE(R600_DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
894 RADEON_WRITE(R600_HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
895 if (gb_tiling_config
& 0xc0) {
896 dev_priv
->r600_group_size
= 512;
898 dev_priv
->r600_group_size
= 256;
900 dev_priv
->r600_npipes
= 1 << ((gb_tiling_config
>> 1) & 0x7);
901 if (gb_tiling_config
& 0x30) {
902 dev_priv
->r600_nbanks
= 8;
904 dev_priv
->r600_nbanks
= 4;
907 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
908 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
909 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
912 R6XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& R600_INACTIVE_QD_PIPES_MASK
) >> 8);
913 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & R600_DEALLOC_DIST_MASK
);
914 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & R600_VTX_REUSE_DEPTH_MASK
);
916 /* set HW defaults for 3D engine */
917 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS
, (R600_ROQ_IB1_START(0x16) |
918 R600_ROQ_IB2_START(0x2b)));
920 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS
, (R600_MEQ_END(0x40) |
921 R600_ROQ_END(0x40)));
923 RADEON_WRITE(R600_TA_CNTL_AUX
, (R600_DISABLE_CUBE_ANISO
|
928 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV670
)
929 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL
, 0x00000021);
931 sx_debug_1
= RADEON_READ(R600_SX_DEBUG_1
);
932 sx_debug_1
|= R600_SMX_EVENT_RELEASE
;
933 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) > CHIP_R600
))
934 sx_debug_1
|= R600_ENABLE_NEW_SMX_ADDRESS
;
935 RADEON_WRITE(R600_SX_DEBUG_1
, sx_debug_1
);
937 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) ||
938 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
) ||
939 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
940 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
941 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
942 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
))
943 RADEON_WRITE(R600_DB_DEBUG
, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
945 RADEON_WRITE(R600_DB_DEBUG
, 0);
947 RADEON_WRITE(R600_DB_WATERMARKS
, (R600_DEPTH_FREE(4) |
948 R600_DEPTH_FLUSH(16) |
949 R600_DEPTH_PENDING_FREE(4) |
950 R600_DEPTH_CACHELINE_FREE(16)));
951 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
952 RADEON_WRITE(R600_VGT_NUM_INSTANCES
, 0);
954 RADEON_WRITE(R600_SPI_CONFIG_CNTL
, R600_GPR_WRITE_PRIORITY(0));
955 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1
, R600_VTX_DONE_DELAY(0));
957 sq_ms_fifo_sizes
= RADEON_READ(R600_SQ_MS_FIFO_SIZES
);
958 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
959 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
960 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
961 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
)) {
962 sq_ms_fifo_sizes
= (R600_CACHE_FIFO_SIZE(0xa) |
963 R600_FETCH_FIFO_HIWATER(0xa) |
964 R600_DONE_FIFO_HIWATER(0xe0) |
965 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
966 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) ||
967 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
)) {
968 sq_ms_fifo_sizes
&= ~R600_DONE_FIFO_HIWATER(0xff);
969 sq_ms_fifo_sizes
|= R600_DONE_FIFO_HIWATER(0x4);
971 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
973 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
974 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
976 sq_config
= RADEON_READ(R600_SQ_CONFIG
);
977 sq_config
&= ~(R600_PS_PRIO(3) |
981 sq_config
|= (R600_DX9_CONSTS
|
988 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_R600
) {
989 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(124) |
990 R600_NUM_VS_GPRS(124) |
991 R600_NUM_CLAUSE_TEMP_GPRS(4));
992 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(0) |
993 R600_NUM_ES_GPRS(0));
994 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(136) |
995 R600_NUM_VS_THREADS(48) |
996 R600_NUM_GS_THREADS(4) |
997 R600_NUM_ES_THREADS(4));
998 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(128) |
999 R600_NUM_VS_STACK_ENTRIES(128));
1000 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(0) |
1001 R600_NUM_ES_STACK_ENTRIES(0));
1002 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
1003 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
1004 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
1005 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
)) {
1006 /* no vertex cache */
1007 sq_config
&= ~R600_VC_ENABLE
;
1009 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
1010 R600_NUM_VS_GPRS(44) |
1011 R600_NUM_CLAUSE_TEMP_GPRS(2));
1012 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(17) |
1013 R600_NUM_ES_GPRS(17));
1014 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1015 R600_NUM_VS_THREADS(78) |
1016 R600_NUM_GS_THREADS(4) |
1017 R600_NUM_ES_THREADS(31));
1018 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(40) |
1019 R600_NUM_VS_STACK_ENTRIES(40));
1020 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(32) |
1021 R600_NUM_ES_STACK_ENTRIES(16));
1022 } else if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV630
) ||
1023 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV635
)) {
1024 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
1025 R600_NUM_VS_GPRS(44) |
1026 R600_NUM_CLAUSE_TEMP_GPRS(2));
1027 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(18) |
1028 R600_NUM_ES_GPRS(18));
1029 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1030 R600_NUM_VS_THREADS(78) |
1031 R600_NUM_GS_THREADS(4) |
1032 R600_NUM_ES_THREADS(31));
1033 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(40) |
1034 R600_NUM_VS_STACK_ENTRIES(40));
1035 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(32) |
1036 R600_NUM_ES_STACK_ENTRIES(16));
1037 } else if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV670
) {
1038 sq_gpr_resource_mgmt_1
= (R600_NUM_PS_GPRS(44) |
1039 R600_NUM_VS_GPRS(44) |
1040 R600_NUM_CLAUSE_TEMP_GPRS(2));
1041 sq_gpr_resource_mgmt_2
= (R600_NUM_GS_GPRS(17) |
1042 R600_NUM_ES_GPRS(17));
1043 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS(79) |
1044 R600_NUM_VS_THREADS(78) |
1045 R600_NUM_GS_THREADS(4) |
1046 R600_NUM_ES_THREADS(31));
1047 sq_stack_resource_mgmt_1
= (R600_NUM_PS_STACK_ENTRIES(64) |
1048 R600_NUM_VS_STACK_ENTRIES(64));
1049 sq_stack_resource_mgmt_2
= (R600_NUM_GS_STACK_ENTRIES(64) |
1050 R600_NUM_ES_STACK_ENTRIES(64));
1053 RADEON_WRITE(R600_SQ_CONFIG
, sq_config
);
1054 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1055 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1056 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1057 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1058 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1060 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV610
) ||
1061 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV620
) ||
1062 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS780
) ||
1063 ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RS880
))
1064 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, R600_CACHE_INVALIDATION(R600_TC_ONLY
));
1066 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, R600_CACHE_INVALIDATION(R600_VC_AND_TC
));
1068 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S
, (R600_S0_X(0xc) |
1072 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S
, (R600_S0_X(0xe) |
1080 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (R600_S0_X(0xe) |
1088 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (R600_S4_X(0x6) |
1098 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1102 gs_prim_buffer_depth
= 0;
1108 gs_prim_buffer_depth
= 32;
1111 gs_prim_buffer_depth
= 128;
1117 num_gs_verts_per_thread
= dev_priv
->r600_max_pipes
* 16;
1118 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
1119 /* Max value for this is 256 */
1120 if (vgt_gs_per_es
> 256)
1121 vgt_gs_per_es
= 256;
1123 RADEON_WRITE(R600_VGT_ES_PER_GS
, 128);
1124 RADEON_WRITE(R600_VGT_GS_PER_ES
, vgt_gs_per_es
);
1125 RADEON_WRITE(R600_VGT_GS_PER_VS
, 2);
1126 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE
, 16);
1128 /* more default values. 2D/3D driver should adjust as needed */
1129 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE
, 0);
1130 RADEON_WRITE(R600_VGT_STRMOUT_EN
, 0);
1131 RADEON_WRITE(R600_SX_MISC
, 0);
1132 RADEON_WRITE(R600_PA_SC_MODE_CNTL
, 0);
1133 RADEON_WRITE(R600_PA_SC_AA_CONFIG
, 0);
1134 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE
, 0);
1135 RADEON_WRITE(R600_SPI_INPUT_Z
, 0);
1136 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0
, R600_NUM_INTERP(2));
1137 RADEON_WRITE(R600_CB_COLOR7_FRAG
, 0);
1139 /* clear render buffer base addresses */
1140 RADEON_WRITE(R600_CB_COLOR0_BASE
, 0);
1141 RADEON_WRITE(R600_CB_COLOR1_BASE
, 0);
1142 RADEON_WRITE(R600_CB_COLOR2_BASE
, 0);
1143 RADEON_WRITE(R600_CB_COLOR3_BASE
, 0);
1144 RADEON_WRITE(R600_CB_COLOR4_BASE
, 0);
1145 RADEON_WRITE(R600_CB_COLOR5_BASE
, 0);
1146 RADEON_WRITE(R600_CB_COLOR6_BASE
, 0);
1147 RADEON_WRITE(R600_CB_COLOR7_BASE
, 0);
1149 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1154 tc_cntl
= R600_TC_L2_SIZE(8);
1158 tc_cntl
= R600_TC_L2_SIZE(4);
1161 tc_cntl
= R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT
;
1164 tc_cntl
= R600_TC_L2_SIZE(0);
1168 RADEON_WRITE(R600_TC_CNTL
, tc_cntl
);
1170 hdp_host_path_cntl
= RADEON_READ(R600_HDP_HOST_PATH_CNTL
);
1171 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1173 arb_pop
= RADEON_READ(R600_ARB_POP
);
1174 arb_pop
|= R600_ENABLE_TC128
;
1175 RADEON_WRITE(R600_ARB_POP
, arb_pop
);
1177 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1178 RADEON_WRITE(R600_PA_CL_ENHANCE
, (R600_CLIP_VTX_REORDER_ENA
|
1179 R600_NUM_CLIP_SEQ(3)));
1180 RADEON_WRITE(R600_PA_SC_ENHANCE
, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1184 static u32
r700_get_tile_pipe_to_backend_map(drm_radeon_private_t
*dev_priv
,
1187 u32 backend_disable_mask
)
1189 u32 backend_map
= 0;
1190 u32 enabled_backends_mask
;
1191 u32 enabled_backends_count
;
1193 u32 swizzle_pipe
[R7XX_MAX_PIPES
];
1196 bool force_no_swizzle
;
1198 if (num_tile_pipes
> R7XX_MAX_PIPES
)
1199 num_tile_pipes
= R7XX_MAX_PIPES
;
1200 if (num_tile_pipes
< 1)
1202 if (num_backends
> R7XX_MAX_BACKENDS
)
1203 num_backends
= R7XX_MAX_BACKENDS
;
1204 if (num_backends
< 1)
1207 enabled_backends_mask
= 0;
1208 enabled_backends_count
= 0;
1209 for (i
= 0; i
< R7XX_MAX_BACKENDS
; ++i
) {
1210 if (((backend_disable_mask
>> i
) & 1) == 0) {
1211 enabled_backends_mask
|= (1 << i
);
1212 ++enabled_backends_count
;
1214 if (enabled_backends_count
== num_backends
)
1218 if (enabled_backends_count
== 0) {
1219 enabled_backends_mask
= 1;
1220 enabled_backends_count
= 1;
1223 if (enabled_backends_count
!= num_backends
)
1224 num_backends
= enabled_backends_count
;
1226 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1229 force_no_swizzle
= false;
1234 force_no_swizzle
= true;
1238 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R7XX_MAX_PIPES
);
1239 switch (num_tile_pipes
) {
1241 swizzle_pipe
[0] = 0;
1244 swizzle_pipe
[0] = 0;
1245 swizzle_pipe
[1] = 1;
1248 if (force_no_swizzle
) {
1249 swizzle_pipe
[0] = 0;
1250 swizzle_pipe
[1] = 1;
1251 swizzle_pipe
[2] = 2;
1253 swizzle_pipe
[0] = 0;
1254 swizzle_pipe
[1] = 2;
1255 swizzle_pipe
[2] = 1;
1259 if (force_no_swizzle
) {
1260 swizzle_pipe
[0] = 0;
1261 swizzle_pipe
[1] = 1;
1262 swizzle_pipe
[2] = 2;
1263 swizzle_pipe
[3] = 3;
1265 swizzle_pipe
[0] = 0;
1266 swizzle_pipe
[1] = 2;
1267 swizzle_pipe
[2] = 3;
1268 swizzle_pipe
[3] = 1;
1272 if (force_no_swizzle
) {
1273 swizzle_pipe
[0] = 0;
1274 swizzle_pipe
[1] = 1;
1275 swizzle_pipe
[2] = 2;
1276 swizzle_pipe
[3] = 3;
1277 swizzle_pipe
[4] = 4;
1279 swizzle_pipe
[0] = 0;
1280 swizzle_pipe
[1] = 2;
1281 swizzle_pipe
[2] = 4;
1282 swizzle_pipe
[3] = 1;
1283 swizzle_pipe
[4] = 3;
1287 if (force_no_swizzle
) {
1288 swizzle_pipe
[0] = 0;
1289 swizzle_pipe
[1] = 1;
1290 swizzle_pipe
[2] = 2;
1291 swizzle_pipe
[3] = 3;
1292 swizzle_pipe
[4] = 4;
1293 swizzle_pipe
[5] = 5;
1295 swizzle_pipe
[0] = 0;
1296 swizzle_pipe
[1] = 2;
1297 swizzle_pipe
[2] = 4;
1298 swizzle_pipe
[3] = 5;
1299 swizzle_pipe
[4] = 3;
1300 swizzle_pipe
[5] = 1;
1304 if (force_no_swizzle
) {
1305 swizzle_pipe
[0] = 0;
1306 swizzle_pipe
[1] = 1;
1307 swizzle_pipe
[2] = 2;
1308 swizzle_pipe
[3] = 3;
1309 swizzle_pipe
[4] = 4;
1310 swizzle_pipe
[5] = 5;
1311 swizzle_pipe
[6] = 6;
1313 swizzle_pipe
[0] = 0;
1314 swizzle_pipe
[1] = 2;
1315 swizzle_pipe
[2] = 4;
1316 swizzle_pipe
[3] = 6;
1317 swizzle_pipe
[4] = 3;
1318 swizzle_pipe
[5] = 1;
1319 swizzle_pipe
[6] = 5;
1323 if (force_no_swizzle
) {
1324 swizzle_pipe
[0] = 0;
1325 swizzle_pipe
[1] = 1;
1326 swizzle_pipe
[2] = 2;
1327 swizzle_pipe
[3] = 3;
1328 swizzle_pipe
[4] = 4;
1329 swizzle_pipe
[5] = 5;
1330 swizzle_pipe
[6] = 6;
1331 swizzle_pipe
[7] = 7;
1333 swizzle_pipe
[0] = 0;
1334 swizzle_pipe
[1] = 2;
1335 swizzle_pipe
[2] = 4;
1336 swizzle_pipe
[3] = 6;
1337 swizzle_pipe
[4] = 3;
1338 swizzle_pipe
[5] = 1;
1339 swizzle_pipe
[6] = 7;
1340 swizzle_pipe
[7] = 5;
1346 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
1347 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
1348 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
1350 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
1352 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
1358 static void r700_gfx_init(struct drm_device
*dev
,
1359 drm_radeon_private_t
*dev_priv
)
1361 int i
, j
, num_qd_pipes
;
1366 u32 num_gs_verts_per_thread
;
1368 u32 gs_prim_buffer_depth
= 0;
1369 u32 sq_ms_fifo_sizes
;
1371 u32 sq_thread_resource_mgmt
;
1372 u32 hdp_host_path_cntl
;
1373 u32 sq_dyn_gpr_size_simd_ab_0
;
1375 u32 gb_tiling_config
= 0;
1376 u32 cc_rb_backend_disable
;
1377 u32 cc_gc_shader_pipe_config
;
1381 /* setup chip specs */
1382 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1384 dev_priv
->r600_max_pipes
= 4;
1385 dev_priv
->r600_max_tile_pipes
= 8;
1386 dev_priv
->r600_max_simds
= 10;
1387 dev_priv
->r600_max_backends
= 4;
1388 dev_priv
->r600_max_gprs
= 256;
1389 dev_priv
->r600_max_threads
= 248;
1390 dev_priv
->r600_max_stack_entries
= 512;
1391 dev_priv
->r600_max_hw_contexts
= 8;
1392 dev_priv
->r600_max_gs_threads
= 16 * 2;
1393 dev_priv
->r600_sx_max_export_size
= 128;
1394 dev_priv
->r600_sx_max_export_pos_size
= 16;
1395 dev_priv
->r600_sx_max_export_smx_size
= 112;
1396 dev_priv
->r600_sq_num_cf_insts
= 2;
1398 dev_priv
->r700_sx_num_of_sets
= 7;
1399 dev_priv
->r700_sc_prim_fifo_size
= 0xF9;
1400 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1401 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1404 dev_priv
->r600_max_pipes
= 2;
1405 dev_priv
->r600_max_tile_pipes
= 4;
1406 dev_priv
->r600_max_simds
= 8;
1407 dev_priv
->r600_max_backends
= 2;
1408 dev_priv
->r600_max_gprs
= 128;
1409 dev_priv
->r600_max_threads
= 248;
1410 dev_priv
->r600_max_stack_entries
= 256;
1411 dev_priv
->r600_max_hw_contexts
= 8;
1412 dev_priv
->r600_max_gs_threads
= 16 * 2;
1413 dev_priv
->r600_sx_max_export_size
= 256;
1414 dev_priv
->r600_sx_max_export_pos_size
= 32;
1415 dev_priv
->r600_sx_max_export_smx_size
= 224;
1416 dev_priv
->r600_sq_num_cf_insts
= 2;
1418 dev_priv
->r700_sx_num_of_sets
= 7;
1419 dev_priv
->r700_sc_prim_fifo_size
= 0xf9;
1420 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1421 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1422 if (dev_priv
->r600_sx_max_export_pos_size
> 16) {
1423 dev_priv
->r600_sx_max_export_pos_size
-= 16;
1424 dev_priv
->r600_sx_max_export_smx_size
+= 16;
1428 dev_priv
->r600_max_pipes
= 2;
1429 dev_priv
->r600_max_tile_pipes
= 2;
1430 dev_priv
->r600_max_simds
= 2;
1431 dev_priv
->r600_max_backends
= 1;
1432 dev_priv
->r600_max_gprs
= 256;
1433 dev_priv
->r600_max_threads
= 192;
1434 dev_priv
->r600_max_stack_entries
= 256;
1435 dev_priv
->r600_max_hw_contexts
= 4;
1436 dev_priv
->r600_max_gs_threads
= 8 * 2;
1437 dev_priv
->r600_sx_max_export_size
= 128;
1438 dev_priv
->r600_sx_max_export_pos_size
= 16;
1439 dev_priv
->r600_sx_max_export_smx_size
= 112;
1440 dev_priv
->r600_sq_num_cf_insts
= 1;
1442 dev_priv
->r700_sx_num_of_sets
= 7;
1443 dev_priv
->r700_sc_prim_fifo_size
= 0x40;
1444 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1445 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1448 dev_priv
->r600_max_pipes
= 4;
1449 dev_priv
->r600_max_tile_pipes
= 4;
1450 dev_priv
->r600_max_simds
= 8;
1451 dev_priv
->r600_max_backends
= 4;
1452 dev_priv
->r600_max_gprs
= 256;
1453 dev_priv
->r600_max_threads
= 248;
1454 dev_priv
->r600_max_stack_entries
= 512;
1455 dev_priv
->r600_max_hw_contexts
= 8;
1456 dev_priv
->r600_max_gs_threads
= 16 * 2;
1457 dev_priv
->r600_sx_max_export_size
= 256;
1458 dev_priv
->r600_sx_max_export_pos_size
= 32;
1459 dev_priv
->r600_sx_max_export_smx_size
= 224;
1460 dev_priv
->r600_sq_num_cf_insts
= 2;
1462 dev_priv
->r700_sx_num_of_sets
= 7;
1463 dev_priv
->r700_sc_prim_fifo_size
= 0x100;
1464 dev_priv
->r700_sc_hiz_tile_fifo_size
= 0x30;
1465 dev_priv
->r700_sc_earlyz_tile_fifo_fize
= 0x130;
1467 if (dev_priv
->r600_sx_max_export_pos_size
> 16) {
1468 dev_priv
->r600_sx_max_export_pos_size
-= 16;
1469 dev_priv
->r600_sx_max_export_smx_size
+= 16;
1476 /* Initialize HDP */
1478 for (i
= 0; i
< 32; i
++) {
1479 RADEON_WRITE((0x2c14 + j
), 0x00000000);
1480 RADEON_WRITE((0x2c18 + j
), 0x00000000);
1481 RADEON_WRITE((0x2c1c + j
), 0x00000000);
1482 RADEON_WRITE((0x2c20 + j
), 0x00000000);
1483 RADEON_WRITE((0x2c24 + j
), 0x00000000);
1487 RADEON_WRITE(R600_GRBM_CNTL
, R600_GRBM_READ_TIMEOUT(0xff));
1489 /* setup tiling, simd, pipe config */
1490 mc_arb_ramcfg
= RADEON_READ(R700_MC_ARB_RAMCFG
);
1492 switch (dev_priv
->r600_max_tile_pipes
) {
1494 gb_tiling_config
|= R600_PIPE_TILING(0);
1497 gb_tiling_config
|= R600_PIPE_TILING(1);
1500 gb_tiling_config
|= R600_PIPE_TILING(2);
1503 gb_tiling_config
|= R600_PIPE_TILING(3);
1509 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV770
)
1510 gb_tiling_config
|= R600_BANK_TILING(1);
1512 gb_tiling_config
|= R600_BANK_TILING((mc_arb_ramcfg
>> R700_NOOFBANK_SHIFT
) & R700_NOOFBANK_MASK
);
1514 gb_tiling_config
|= R600_GROUP_SIZE(0);
1516 if (((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
) > 3) {
1517 gb_tiling_config
|= R600_ROW_TILING(3);
1518 gb_tiling_config
|= R600_SAMPLE_SPLIT(3);
1521 R600_ROW_TILING(((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
));
1523 R600_SAMPLE_SPLIT(((mc_arb_ramcfg
>> R700_NOOFROWS_SHIFT
) & R700_NOOFROWS_MASK
));
1526 gb_tiling_config
|= R600_BANK_SWAPS(1);
1528 cc_rb_backend_disable
= RADEON_READ(R600_CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
1529 cc_rb_backend_disable
|=
1530 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK
<< dev_priv
->r600_max_backends
) & R7XX_MAX_BACKENDS_MASK
);
1532 cc_gc_shader_pipe_config
= RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
1533 cc_gc_shader_pipe_config
|=
1534 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK
<< dev_priv
->r600_max_pipes
) & R7XX_MAX_PIPES_MASK
);
1535 cc_gc_shader_pipe_config
|=
1536 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK
<< dev_priv
->r600_max_simds
) & R7XX_MAX_SIMDS_MASK
);
1538 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV740
)
1541 backend_map
= r700_get_tile_pipe_to_backend_map(dev_priv
,
1542 dev_priv
->r600_max_tile_pipes
,
1543 (R7XX_MAX_BACKENDS
-
1544 r600_count_pipe_bits((cc_rb_backend_disable
&
1545 R7XX_MAX_BACKENDS_MASK
) >> 16)),
1546 (cc_rb_backend_disable
>> 16));
1547 gb_tiling_config
|= R600_BACKEND_MAP(backend_map
);
1549 RADEON_WRITE(R600_GB_TILING_CONFIG
, gb_tiling_config
);
1550 RADEON_WRITE(R600_DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
1551 RADEON_WRITE(R600_HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
1552 if (gb_tiling_config
& 0xc0) {
1553 dev_priv
->r600_group_size
= 512;
1555 dev_priv
->r600_group_size
= 256;
1557 dev_priv
->r600_npipes
= 1 << ((gb_tiling_config
>> 1) & 0x7);
1558 if (gb_tiling_config
& 0x30) {
1559 dev_priv
->r600_nbanks
= 8;
1561 dev_priv
->r600_nbanks
= 4;
1564 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1565 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1566 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1568 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1569 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE
, 0);
1570 RADEON_WRITE(R700_CGTS_TCC_DISABLE
, 0);
1571 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE
, 0);
1572 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE
, 0);
1575 R7XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& R600_INACTIVE_QD_PIPES_MASK
) >> 8);
1576 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & R600_DEALLOC_DIST_MASK
);
1577 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & R600_VTX_REUSE_DEPTH_MASK
);
1579 /* set HW defaults for 3D engine */
1580 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS
, (R600_ROQ_IB1_START(0x16) |
1581 R600_ROQ_IB2_START(0x2b)));
1583 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS
, R700_STQ_SPLIT(0x30));
1585 ta_aux_cntl
= RADEON_READ(R600_TA_CNTL_AUX
);
1586 RADEON_WRITE(R600_TA_CNTL_AUX
, ta_aux_cntl
| R600_DISABLE_CUBE_ANISO
);
1588 sx_debug_1
= RADEON_READ(R700_SX_DEBUG_1
);
1589 sx_debug_1
|= R700_ENABLE_NEW_SMX_ADDRESS
;
1590 RADEON_WRITE(R700_SX_DEBUG_1
, sx_debug_1
);
1592 smx_dc_ctl0
= RADEON_READ(R600_SMX_DC_CTL0
);
1593 smx_dc_ctl0
&= ~R700_CACHE_DEPTH(0x1ff);
1594 smx_dc_ctl0
|= R700_CACHE_DEPTH((dev_priv
->r700_sx_num_of_sets
* 64) - 1);
1595 RADEON_WRITE(R600_SMX_DC_CTL0
, smx_dc_ctl0
);
1597 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) != CHIP_RV740
)
1598 RADEON_WRITE(R700_SMX_EVENT_CTL
, (R700_ES_FLUSH_CTL(4) |
1599 R700_GS_FLUSH_CTL(4) |
1600 R700_ACK_FLUSH_CTL(3) |
1601 R700_SYNC_FLUSH_CTL
));
1603 db_debug3
= RADEON_READ(R700_DB_DEBUG3
);
1604 db_debug3
&= ~R700_DB_CLK_OFF_DELAY(0x1f);
1605 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1608 db_debug3
|= R700_DB_CLK_OFF_DELAY(0x1f);
1613 db_debug3
|= R700_DB_CLK_OFF_DELAY(2);
1616 RADEON_WRITE(R700_DB_DEBUG3
, db_debug3
);
1618 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) != CHIP_RV770
) {
1619 db_debug4
= RADEON_READ(RV700_DB_DEBUG4
);
1620 db_debug4
|= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER
;
1621 RADEON_WRITE(RV700_DB_DEBUG4
, db_debug4
);
1624 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES
, (R600_COLOR_BUFFER_SIZE((dev_priv
->r600_sx_max_export_size
/ 4) - 1) |
1625 R600_POSITION_BUFFER_SIZE((dev_priv
->r600_sx_max_export_pos_size
/ 4) - 1) |
1626 R600_SMX_BUFFER_SIZE((dev_priv
->r600_sx_max_export_smx_size
/ 4) - 1)));
1628 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX
, (R700_SC_PRIM_FIFO_SIZE(dev_priv
->r700_sc_prim_fifo_size
) |
1629 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv
->r700_sc_hiz_tile_fifo_size
) |
1630 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv
->r700_sc_earlyz_tile_fifo_fize
)));
1632 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1634 RADEON_WRITE(R600_VGT_NUM_INSTANCES
, 1);
1636 RADEON_WRITE(R600_SPI_CONFIG_CNTL
, R600_GPR_WRITE_PRIORITY(0));
1638 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1
, R600_VTX_DONE_DELAY(4));
1640 RADEON_WRITE(R600_CP_PERFMON_CNTL
, 0);
1642 sq_ms_fifo_sizes
= (R600_CACHE_FIFO_SIZE(16 * dev_priv
->r600_sq_num_cf_insts
) |
1643 R600_DONE_FIFO_HIWATER(0xe0) |
1644 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1645 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1649 sq_ms_fifo_sizes
|= R600_FETCH_FIFO_HIWATER(0x1);
1653 sq_ms_fifo_sizes
|= R600_FETCH_FIFO_HIWATER(0x4);
1656 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
1658 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1659 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1661 sq_config
= RADEON_READ(R600_SQ_CONFIG
);
1662 sq_config
&= ~(R600_PS_PRIO(3) |
1666 sq_config
|= (R600_DX9_CONSTS
|
1673 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
)
1674 /* no vertex cache */
1675 sq_config
&= ~R600_VC_ENABLE
;
1677 RADEON_WRITE(R600_SQ_CONFIG
, sq_config
);
1679 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1
, (R600_NUM_PS_GPRS((dev_priv
->r600_max_gprs
* 24)/64) |
1680 R600_NUM_VS_GPRS((dev_priv
->r600_max_gprs
* 24)/64) |
1681 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv
->r600_max_gprs
* 24)/64)/2)));
1683 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2
, (R600_NUM_GS_GPRS((dev_priv
->r600_max_gprs
* 7)/64) |
1684 R600_NUM_ES_GPRS((dev_priv
->r600_max_gprs
* 7)/64)));
1686 sq_thread_resource_mgmt
= (R600_NUM_PS_THREADS((dev_priv
->r600_max_threads
* 4)/8) |
1687 R600_NUM_VS_THREADS((dev_priv
->r600_max_threads
* 2)/8) |
1688 R600_NUM_ES_THREADS((dev_priv
->r600_max_threads
* 1)/8));
1689 if (((dev_priv
->r600_max_threads
* 1) / 8) > dev_priv
->r600_max_gs_threads
)
1690 sq_thread_resource_mgmt
|= R600_NUM_GS_THREADS(dev_priv
->r600_max_gs_threads
);
1692 sq_thread_resource_mgmt
|= R600_NUM_GS_THREADS((dev_priv
->r600_max_gs_threads
* 1)/8);
1693 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1695 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1
, (R600_NUM_PS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4) |
1696 R600_NUM_VS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4)));
1698 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2
, (R600_NUM_GS_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4) |
1699 R600_NUM_ES_STACK_ENTRIES((dev_priv
->r600_max_stack_entries
* 1)/4)));
1701 sq_dyn_gpr_size_simd_ab_0
= (R700_SIMDA_RING0((dev_priv
->r600_max_gprs
* 38)/64) |
1702 R700_SIMDA_RING1((dev_priv
->r600_max_gprs
* 38)/64) |
1703 R700_SIMDB_RING0((dev_priv
->r600_max_gprs
* 38)/64) |
1704 R700_SIMDB_RING1((dev_priv
->r600_max_gprs
* 38)/64));
1706 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0
, sq_dyn_gpr_size_simd_ab_0
);
1707 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1
, sq_dyn_gpr_size_simd_ab_0
);
1708 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2
, sq_dyn_gpr_size_simd_ab_0
);
1709 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3
, sq_dyn_gpr_size_simd_ab_0
);
1710 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4
, sq_dyn_gpr_size_simd_ab_0
);
1711 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5
, sq_dyn_gpr_size_simd_ab_0
);
1712 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6
, sq_dyn_gpr_size_simd_ab_0
);
1713 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7
, sq_dyn_gpr_size_simd_ab_0
);
1715 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS
, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1716 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1718 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) == CHIP_RV710
)
1719 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, (R600_CACHE_INVALIDATION(R600_TC_ONLY
) |
1720 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO
)));
1722 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION
, (R600_CACHE_INVALIDATION(R600_VC_AND_TC
) |
1723 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO
)));
1725 switch (dev_priv
->flags
& RADEON_FAMILY_MASK
) {
1729 gs_prim_buffer_depth
= 384;
1732 gs_prim_buffer_depth
= 128;
1738 num_gs_verts_per_thread
= dev_priv
->r600_max_pipes
* 16;
1739 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
1740 /* Max value for this is 256 */
1741 if (vgt_gs_per_es
> 256)
1742 vgt_gs_per_es
= 256;
1744 RADEON_WRITE(R600_VGT_ES_PER_GS
, 128);
1745 RADEON_WRITE(R600_VGT_GS_PER_ES
, vgt_gs_per_es
);
1746 RADEON_WRITE(R600_VGT_GS_PER_VS
, 2);
1748 /* more default values. 2D/3D driver should adjust as needed */
1749 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE
, 16);
1750 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE
, 0);
1751 RADEON_WRITE(R600_VGT_STRMOUT_EN
, 0);
1752 RADEON_WRITE(R600_SX_MISC
, 0);
1753 RADEON_WRITE(R600_PA_SC_MODE_CNTL
, 0);
1754 RADEON_WRITE(R700_PA_SC_EDGERULE
, 0xaaaaaaaa);
1755 RADEON_WRITE(R600_PA_SC_AA_CONFIG
, 0);
1756 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE
, 0xffff);
1757 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE
, 0);
1758 RADEON_WRITE(R600_SPI_INPUT_Z
, 0);
1759 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0
, R600_NUM_INTERP(2));
1760 RADEON_WRITE(R600_CB_COLOR7_FRAG
, 0);
1762 /* clear render buffer base addresses */
1763 RADEON_WRITE(R600_CB_COLOR0_BASE
, 0);
1764 RADEON_WRITE(R600_CB_COLOR1_BASE
, 0);
1765 RADEON_WRITE(R600_CB_COLOR2_BASE
, 0);
1766 RADEON_WRITE(R600_CB_COLOR3_BASE
, 0);
1767 RADEON_WRITE(R600_CB_COLOR4_BASE
, 0);
1768 RADEON_WRITE(R600_CB_COLOR5_BASE
, 0);
1769 RADEON_WRITE(R600_CB_COLOR6_BASE
, 0);
1770 RADEON_WRITE(R600_CB_COLOR7_BASE
, 0);
1772 RADEON_WRITE(R700_TCP_CNTL
, 0);
1774 hdp_host_path_cntl
= RADEON_READ(R600_HDP_HOST_PATH_CNTL
);
1775 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1777 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL
, 0);
1779 RADEON_WRITE(R600_PA_CL_ENHANCE
, (R600_CLIP_VTX_REORDER_ENA
|
1780 R600_NUM_CLIP_SEQ(3)));
1784 static void r600_cp_init_ring_buffer(struct drm_device
*dev
,
1785 drm_radeon_private_t
*dev_priv
,
1786 struct drm_file
*file_priv
)
1788 struct drm_radeon_master_private
*master_priv
;
1792 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
1793 r700_gfx_init(dev
, dev_priv
);
1795 r600_gfx_init(dev
, dev_priv
);
1797 RADEON_WRITE(R600_GRBM_SOFT_RESET
, R600_SOFT_RESET_CP
);
1798 RADEON_READ(R600_GRBM_SOFT_RESET
);
1800 RADEON_WRITE(R600_GRBM_SOFT_RESET
, 0);
1803 /* Set ring buffer size */
1805 RADEON_WRITE(R600_CP_RB_CNTL
,
1806 R600_BUF_SWAP_32BIT
|
1808 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1809 dev_priv
->ring
.size_l2qw
);
1811 RADEON_WRITE(R600_CP_RB_CNTL
,
1812 RADEON_RB_NO_UPDATE
|
1813 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1814 dev_priv
->ring
.size_l2qw
);
1817 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER
, 0x0);
1819 /* Set the write pointer delay */
1820 RADEON_WRITE(R600_CP_RB_WPTR_DELAY
, 0);
1823 RADEON_WRITE(R600_CP_RB_CNTL
,
1824 R600_BUF_SWAP_32BIT
|
1826 R600_RB_RPTR_WR_ENA
|
1827 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1828 dev_priv
->ring
.size_l2qw
);
1830 RADEON_WRITE(R600_CP_RB_CNTL
,
1832 R600_RB_RPTR_WR_ENA
|
1833 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1834 dev_priv
->ring
.size_l2qw
);
1837 /* Initialize the ring buffer's read and write pointers */
1838 RADEON_WRITE(R600_CP_RB_RPTR_WR
, 0);
1839 RADEON_WRITE(R600_CP_RB_WPTR
, 0);
1840 SET_RING_HEAD(dev_priv
, 0);
1841 dev_priv
->ring
.tail
= 0;
1844 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1845 rptr_addr
= dev_priv
->ring_rptr
->offset
1847 dev_priv
->gart_vm_start
;
1851 rptr_addr
= dev_priv
->ring_rptr
->offset
1852 - ((unsigned long) dev
->sg
->virtual)
1853 + dev_priv
->gart_vm_start
;
1855 RADEON_WRITE(R600_CP_RB_RPTR_ADDR
, (rptr_addr
& 0xfffffffc));
1856 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI
, upper_32_bits(rptr_addr
));
1859 RADEON_WRITE(R600_CP_RB_CNTL
,
1860 RADEON_BUF_SWAP_32BIT
|
1861 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1862 dev_priv
->ring
.size_l2qw
);
1864 RADEON_WRITE(R600_CP_RB_CNTL
,
1865 (dev_priv
->ring
.rptr_update_l2qw
<< 8) |
1866 dev_priv
->ring
.size_l2qw
);
1870 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1872 radeon_write_agp_base(dev_priv
, dev
->agp
->base
);
1875 radeon_write_agp_location(dev_priv
,
1876 (((dev_priv
->gart_vm_start
- 1 +
1877 dev_priv
->gart_size
) & 0xffff0000) |
1878 (dev_priv
->gart_vm_start
>> 16)));
1880 ring_start
= (dev_priv
->cp_ring
->offset
1882 + dev_priv
->gart_vm_start
);
1885 ring_start
= (dev_priv
->cp_ring
->offset
1886 - (unsigned long)dev
->sg
->virtual
1887 + dev_priv
->gart_vm_start
);
1889 RADEON_WRITE(R600_CP_RB_BASE
, ring_start
>> 8);
1891 RADEON_WRITE(R600_CP_ME_CNTL
, 0xff);
1893 RADEON_WRITE(R600_CP_DEBUG
, (1 << 27) | (1 << 28));
1895 /* Initialize the scratch register pointer. This will cause
1896 * the scratch register values to be written out to memory
1897 * whenever they are updated.
1899 * We simply put this behind the ring read pointer, this works
1900 * with PCI GART as well as (whatever kind of) AGP GART
1905 scratch_addr
= RADEON_READ(R600_CP_RB_RPTR_ADDR
) & 0xFFFFFFFC;
1906 scratch_addr
|= ((u64
)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI
)) << 32;
1907 scratch_addr
+= R600_SCRATCH_REG_OFFSET
;
1909 scratch_addr
&= 0xffffffff;
1911 RADEON_WRITE(R600_SCRATCH_ADDR
, (uint32_t)scratch_addr
);
1914 RADEON_WRITE(R600_SCRATCH_UMSK
, 0x7);
1916 /* Turn on bus mastering */
1917 radeon_enable_bm(dev_priv
);
1919 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(0), 0);
1920 RADEON_WRITE(R600_LAST_FRAME_REG
, 0);
1922 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(1), 0);
1923 RADEON_WRITE(R600_LAST_DISPATCH_REG
, 0);
1925 radeon_write_ring_rptr(dev_priv
, R600_SCRATCHOFF(2), 0);
1926 RADEON_WRITE(R600_LAST_CLEAR_REG
, 0);
1928 /* reset sarea copies of these */
1929 master_priv
= file_priv
->master
->driver_priv
;
1930 if (master_priv
->sarea_priv
) {
1931 master_priv
->sarea_priv
->last_frame
= 0;
1932 master_priv
->sarea_priv
->last_dispatch
= 0;
1933 master_priv
->sarea_priv
->last_clear
= 0;
1936 r600_do_wait_for_idle(dev_priv
);
1940 int r600_do_cleanup_cp(struct drm_device
*dev
)
1942 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1945 /* Make sure interrupts are disabled here because the uninstall ioctl
1946 * may not have been called from userspace and after dev_private
1947 * is freed, it's too late.
1949 if (dev
->irq_enabled
)
1950 drm_irq_uninstall(dev
);
1953 if (dev_priv
->flags
& RADEON_IS_AGP
) {
1954 if (dev_priv
->cp_ring
!= NULL
) {
1955 drm_core_ioremapfree(dev_priv
->cp_ring
, dev
);
1956 dev_priv
->cp_ring
= NULL
;
1958 if (dev_priv
->ring_rptr
!= NULL
) {
1959 drm_core_ioremapfree(dev_priv
->ring_rptr
, dev
);
1960 dev_priv
->ring_rptr
= NULL
;
1962 if (dev
->agp_buffer_map
!= NULL
) {
1963 drm_core_ioremapfree(dev
->agp_buffer_map
, dev
);
1964 dev
->agp_buffer_map
= NULL
;
1970 if (dev_priv
->gart_info
.bus_addr
)
1971 r600_page_table_cleanup(dev
, &dev_priv
->gart_info
);
1973 if (dev_priv
->gart_info
.gart_table_location
== DRM_ATI_GART_FB
) {
1974 drm_core_ioremapfree(&dev_priv
->gart_info
.mapping
, dev
);
1975 dev_priv
->gart_info
.addr
= NULL
;
1978 /* only clear to the start of flags */
1979 memset(dev_priv
, 0, offsetof(drm_radeon_private_t
, flags
));
1984 int r600_do_init_cp(struct drm_device
*dev
, drm_radeon_init_t
*init
,
1985 struct drm_file
*file_priv
)
1987 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1988 struct drm_radeon_master_private
*master_priv
= file_priv
->master
->driver_priv
;
1992 mutex_init(&dev_priv
->cs_mutex
);
1993 r600_cs_legacy_init();
1994 /* if we require new memory map but we don't have it fail */
1995 if ((dev_priv
->flags
& RADEON_NEW_MEMMAP
) && !dev_priv
->new_memmap
) {
1996 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1997 r600_do_cleanup_cp(dev
);
2001 if (init
->is_pci
&& (dev_priv
->flags
& RADEON_IS_AGP
)) {
2002 DRM_DEBUG("Forcing AGP card to PCI mode\n");
2003 dev_priv
->flags
&= ~RADEON_IS_AGP
;
2004 /* The writeback test succeeds, but when writeback is enabled,
2005 * the ring buffer read ptr update fails after first 128 bytes.
2008 } else if (!(dev_priv
->flags
& (RADEON_IS_AGP
| RADEON_IS_PCI
| RADEON_IS_PCIE
))
2010 DRM_DEBUG("Restoring AGP flag\n");
2011 dev_priv
->flags
|= RADEON_IS_AGP
;
2014 dev_priv
->usec_timeout
= init
->usec_timeout
;
2015 if (dev_priv
->usec_timeout
< 1 ||
2016 dev_priv
->usec_timeout
> RADEON_MAX_USEC_TIMEOUT
) {
2017 DRM_DEBUG("TIMEOUT problem!\n");
2018 r600_do_cleanup_cp(dev
);
2022 /* Enable vblank on CRTC1 for older X servers
2024 dev_priv
->vblank_crtc
= DRM_RADEON_VBLANK_CRTC1
;
2025 dev_priv
->do_boxes
= 0;
2026 dev_priv
->cp_mode
= init
->cp_mode
;
2028 /* We don't support anything other than bus-mastering ring mode,
2029 * but the ring can be in either AGP or PCI space for the ring
2032 if ((init
->cp_mode
!= RADEON_CSQ_PRIBM_INDDIS
) &&
2033 (init
->cp_mode
!= RADEON_CSQ_PRIBM_INDBM
)) {
2034 DRM_DEBUG("BAD cp_mode (%x)!\n", init
->cp_mode
);
2035 r600_do_cleanup_cp(dev
);
2039 switch (init
->fb_bpp
) {
2041 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
2045 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
2048 dev_priv
->front_offset
= init
->front_offset
;
2049 dev_priv
->front_pitch
= init
->front_pitch
;
2050 dev_priv
->back_offset
= init
->back_offset
;
2051 dev_priv
->back_pitch
= init
->back_pitch
;
2053 dev_priv
->ring_offset
= init
->ring_offset
;
2054 dev_priv
->ring_rptr_offset
= init
->ring_rptr_offset
;
2055 dev_priv
->buffers_offset
= init
->buffers_offset
;
2056 dev_priv
->gart_textures_offset
= init
->gart_textures_offset
;
2058 master_priv
->sarea
= drm_getsarea(dev
);
2059 if (!master_priv
->sarea
) {
2060 DRM_ERROR("could not find sarea!\n");
2061 r600_do_cleanup_cp(dev
);
2065 dev_priv
->cp_ring
= drm_core_findmap(dev
, init
->ring_offset
);
2066 if (!dev_priv
->cp_ring
) {
2067 DRM_ERROR("could not find cp ring region!\n");
2068 r600_do_cleanup_cp(dev
);
2071 dev_priv
->ring_rptr
= drm_core_findmap(dev
, init
->ring_rptr_offset
);
2072 if (!dev_priv
->ring_rptr
) {
2073 DRM_ERROR("could not find ring read pointer!\n");
2074 r600_do_cleanup_cp(dev
);
2077 dev
->agp_buffer_token
= init
->buffers_offset
;
2078 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
2079 if (!dev
->agp_buffer_map
) {
2080 DRM_ERROR("could not find dma buffer region!\n");
2081 r600_do_cleanup_cp(dev
);
2085 if (init
->gart_textures_offset
) {
2086 dev_priv
->gart_textures
=
2087 drm_core_findmap(dev
, init
->gart_textures_offset
);
2088 if (!dev_priv
->gart_textures
) {
2089 DRM_ERROR("could not find GART texture region!\n");
2090 r600_do_cleanup_cp(dev
);
2097 if (dev_priv
->flags
& RADEON_IS_AGP
) {
2098 drm_core_ioremap_wc(dev_priv
->cp_ring
, dev
);
2099 drm_core_ioremap_wc(dev_priv
->ring_rptr
, dev
);
2100 drm_core_ioremap_wc(dev
->agp_buffer_map
, dev
);
2101 if (!dev_priv
->cp_ring
->handle
||
2102 !dev_priv
->ring_rptr
->handle
||
2103 !dev
->agp_buffer_map
->handle
) {
2104 DRM_ERROR("could not find ioremap agp regions!\n");
2105 r600_do_cleanup_cp(dev
);
2111 dev_priv
->cp_ring
->handle
= (void *)(unsigned long)dev_priv
->cp_ring
->offset
;
2112 dev_priv
->ring_rptr
->handle
=
2113 (void *)(unsigned long)dev_priv
->ring_rptr
->offset
;
2114 dev
->agp_buffer_map
->handle
=
2115 (void *)(unsigned long)dev
->agp_buffer_map
->offset
;
2117 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2118 dev_priv
->cp_ring
->handle
);
2119 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2120 dev_priv
->ring_rptr
->handle
);
2121 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2122 dev
->agp_buffer_map
->handle
);
2125 dev_priv
->fb_location
= (radeon_read_fb_location(dev_priv
) & 0xffff) << 24;
2127 (((radeon_read_fb_location(dev_priv
) & 0xffff0000u
) << 8) + 0x1000000)
2128 - dev_priv
->fb_location
;
2130 dev_priv
->front_pitch_offset
= (((dev_priv
->front_pitch
/ 64) << 22) |
2131 ((dev_priv
->front_offset
2132 + dev_priv
->fb_location
) >> 10));
2134 dev_priv
->back_pitch_offset
= (((dev_priv
->back_pitch
/ 64) << 22) |
2135 ((dev_priv
->back_offset
2136 + dev_priv
->fb_location
) >> 10));
2138 dev_priv
->depth_pitch_offset
= (((dev_priv
->depth_pitch
/ 64) << 22) |
2139 ((dev_priv
->depth_offset
2140 + dev_priv
->fb_location
) >> 10));
2142 dev_priv
->gart_size
= init
->gart_size
;
2144 /* New let's set the memory map ... */
2145 if (dev_priv
->new_memmap
) {
2148 DRM_INFO("Setting GART location based on new memory map\n");
2150 /* If using AGP, try to locate the AGP aperture at the same
2151 * location in the card and on the bus, though we have to
2156 if (dev_priv
->flags
& RADEON_IS_AGP
) {
2157 base
= dev
->agp
->base
;
2158 /* Check if valid */
2159 if ((base
+ dev_priv
->gart_size
- 1) >= dev_priv
->fb_location
&&
2160 base
< (dev_priv
->fb_location
+ dev_priv
->fb_size
- 1)) {
2161 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2167 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2169 base
= dev_priv
->fb_location
+ dev_priv
->fb_size
;
2170 if (base
< dev_priv
->fb_location
||
2171 ((base
+ dev_priv
->gart_size
) & 0xfffffffful
) < base
)
2172 base
= dev_priv
->fb_location
2173 - dev_priv
->gart_size
;
2175 dev_priv
->gart_vm_start
= base
& 0xffc00000u
;
2176 if (dev_priv
->gart_vm_start
!= base
)
2177 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2178 base
, dev_priv
->gart_vm_start
);
2183 if (dev_priv
->flags
& RADEON_IS_AGP
)
2184 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
2186 + dev_priv
->gart_vm_start
);
2189 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
2190 - (unsigned long)dev
->sg
->virtual
2191 + dev_priv
->gart_vm_start
);
2193 DRM_DEBUG("fb 0x%08x size %d\n",
2194 (unsigned int) dev_priv
->fb_location
,
2195 (unsigned int) dev_priv
->fb_size
);
2196 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv
->gart_size
);
2197 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2198 (unsigned int) dev_priv
->gart_vm_start
);
2199 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2200 dev_priv
->gart_buffers_offset
);
2202 dev_priv
->ring
.start
= (u32
*) dev_priv
->cp_ring
->handle
;
2203 dev_priv
->ring
.end
= ((u32
*) dev_priv
->cp_ring
->handle
2204 + init
->ring_size
/ sizeof(u32
));
2205 dev_priv
->ring
.size
= init
->ring_size
;
2206 dev_priv
->ring
.size_l2qw
= drm_order(init
->ring_size
/ 8);
2208 dev_priv
->ring
.rptr_update
= /* init->rptr_update */ 4096;
2209 dev_priv
->ring
.rptr_update_l2qw
= drm_order(/* init->rptr_update */ 4096 / 8);
2211 dev_priv
->ring
.fetch_size
= /* init->fetch_size */ 32;
2212 dev_priv
->ring
.fetch_size_l2ow
= drm_order(/* init->fetch_size */ 32 / 16);
2214 dev_priv
->ring
.tail_mask
= (dev_priv
->ring
.size
/ sizeof(u32
)) - 1;
2216 dev_priv
->ring
.high_mark
= RADEON_RING_HIGH_MARK
;
2219 if (dev_priv
->flags
& RADEON_IS_AGP
) {
2220 /* XXX turn off pcie gart */
2224 dev_priv
->gart_info
.table_mask
= DMA_BIT_MASK(32);
2225 /* if we have an offset set from userspace */
2226 if (!dev_priv
->pcigart_offset_set
) {
2227 DRM_ERROR("Need gart offset from userspace\n");
2228 r600_do_cleanup_cp(dev
);
2232 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv
->pcigart_offset
);
2234 dev_priv
->gart_info
.bus_addr
=
2235 dev_priv
->pcigart_offset
+ dev_priv
->fb_location
;
2236 dev_priv
->gart_info
.mapping
.offset
=
2237 dev_priv
->pcigart_offset
+ dev_priv
->fb_aper_offset
;
2238 dev_priv
->gart_info
.mapping
.size
=
2239 dev_priv
->gart_info
.table_size
;
2241 drm_core_ioremap_wc(&dev_priv
->gart_info
.mapping
, dev
);
2242 if (!dev_priv
->gart_info
.mapping
.handle
) {
2243 DRM_ERROR("ioremap failed.\n");
2244 r600_do_cleanup_cp(dev
);
2248 dev_priv
->gart_info
.addr
=
2249 dev_priv
->gart_info
.mapping
.handle
;
2251 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2252 dev_priv
->gart_info
.addr
,
2253 dev_priv
->pcigart_offset
);
2255 if (!r600_page_table_init(dev
)) {
2256 DRM_ERROR("Failed to init GART table\n");
2257 r600_do_cleanup_cp(dev
);
2261 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
2267 if (!dev_priv
->me_fw
|| !dev_priv
->pfp_fw
) {
2268 int err
= r600_cp_init_microcode(dev_priv
);
2270 DRM_ERROR("Failed to load firmware!\n");
2271 r600_do_cleanup_cp(dev
);
2275 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
))
2276 r700_cp_load_microcode(dev_priv
);
2278 r600_cp_load_microcode(dev_priv
);
2280 r600_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
2282 dev_priv
->last_buf
= 0;
2284 r600_do_engine_reset(dev
);
2285 r600_test_writeback(dev_priv
);
2290 int r600_do_resume_cp(struct drm_device
*dev
, struct drm_file
*file_priv
)
2292 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2295 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RV770
)) {
2297 r700_cp_load_microcode(dev_priv
);
2300 r600_cp_load_microcode(dev_priv
);
2302 r600_cp_init_ring_buffer(dev
, dev_priv
, file_priv
);
2303 r600_do_engine_reset(dev
);
2308 /* Wait for the CP to go idle.
2310 int r600_do_cp_idle(drm_radeon_private_t
*dev_priv
)
2316 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
2317 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT
);
2318 /* wait for 3D idle clean */
2319 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
2320 OUT_RING((R600_WAIT_UNTIL
- R600_SET_CONFIG_REG_OFFSET
) >> 2);
2321 OUT_RING(RADEON_WAIT_3D_IDLE
| RADEON_WAIT_3D_IDLECLEAN
);
2326 return r600_do_wait_for_idle(dev_priv
);
2329 /* Start the Command Processor.
2331 void r600_do_cp_start(drm_radeon_private_t
*dev_priv
)
2338 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE
, 5));
2339 OUT_RING(0x00000001);
2340 if (((dev_priv
->flags
& RADEON_FAMILY_MASK
) < CHIP_RV770
))
2341 OUT_RING(0x00000003);
2343 OUT_RING(0x00000000);
2344 OUT_RING((dev_priv
->r600_max_hw_contexts
- 1));
2345 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2346 OUT_RING(0x00000000);
2347 OUT_RING(0x00000000);
2351 /* set the mux and reset the halt bit */
2353 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me
);
2355 dev_priv
->cp_running
= 1;
2359 void r600_do_cp_reset(drm_radeon_private_t
*dev_priv
)
2364 cur_read_ptr
= RADEON_READ(R600_CP_RB_RPTR
);
2365 RADEON_WRITE(R600_CP_RB_WPTR
, cur_read_ptr
);
2366 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
2367 dev_priv
->ring
.tail
= cur_read_ptr
;
2370 void r600_do_cp_stop(drm_radeon_private_t
*dev_priv
)
2376 cp_me
= 0xff | R600_CP_ME_HALT
;
2378 RADEON_WRITE(R600_CP_ME_CNTL
, cp_me
);
2380 dev_priv
->cp_running
= 0;
2383 int r600_cp_dispatch_indirect(struct drm_device
*dev
,
2384 struct drm_buf
*buf
, int start
, int end
)
2386 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2390 unsigned long offset
= (dev_priv
->gart_buffers_offset
2391 + buf
->offset
+ start
);
2392 int dwords
= (end
- start
+ 3) / sizeof(u32
);
2394 DRM_DEBUG("dwords:%d\n", dwords
);
2395 DRM_DEBUG("offset 0x%lx\n", offset
);
2398 /* Indirect buffer data must be a multiple of 16 dwords.
2399 * pad the data with a Type-2 CP packet.
2401 while (dwords
& 0xf) {
2403 ((char *)dev
->agp_buffer_map
->handle
2404 + buf
->offset
+ start
);
2405 data
[dwords
++] = RADEON_CP_PACKET2
;
2408 /* Fire off the indirect buffer */
2410 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER
, 2));
2411 OUT_RING((offset
& 0xfffffffc));
2412 OUT_RING((upper_32_bits(offset
) & 0xff));
2420 void r600_cp_dispatch_swap(struct drm_device
*dev
, struct drm_file
*file_priv
)
2422 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2423 struct drm_master
*master
= file_priv
->master
;
2424 struct drm_radeon_master_private
*master_priv
= master
->driver_priv
;
2425 drm_radeon_sarea_t
*sarea_priv
= master_priv
->sarea_priv
;
2426 int nbox
= sarea_priv
->nbox
;
2427 struct drm_clip_rect
*pbox
= sarea_priv
->boxes
;
2428 int i
, cpp
, src_pitch
, dst_pitch
;
2433 if (dev_priv
->color_fmt
== RADEON_COLOR_FORMAT_ARGB8888
)
2438 if (sarea_priv
->pfCurrentPage
== 0) {
2439 src_pitch
= dev_priv
->back_pitch
;
2440 dst_pitch
= dev_priv
->front_pitch
;
2441 src
= dev_priv
->back_offset
+ dev_priv
->fb_location
;
2442 dst
= dev_priv
->front_offset
+ dev_priv
->fb_location
;
2444 src_pitch
= dev_priv
->front_pitch
;
2445 dst_pitch
= dev_priv
->back_pitch
;
2446 src
= dev_priv
->front_offset
+ dev_priv
->fb_location
;
2447 dst
= dev_priv
->back_offset
+ dev_priv
->fb_location
;
2450 if (r600_prepare_blit_copy(dev
, file_priv
)) {
2451 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2454 for (i
= 0; i
< nbox
; i
++) {
2457 int w
= pbox
[i
].x2
- x
;
2458 int h
= pbox
[i
].y2
- y
;
2460 DRM_DEBUG("%d,%d-%d,%d\n", x
, y
, w
, h
);
2465 src_pitch
, dst_pitch
, cpp
);
2467 r600_done_blit_copy(dev
);
2469 /* Increment the frame counter. The client-side 3D driver must
2470 * throttle the framerate by waiting for this value before
2471 * performing the swapbuffer ioctl.
2473 sarea_priv
->last_frame
++;
2476 R600_FRAME_AGE(sarea_priv
->last_frame
);
2480 int r600_cp_dispatch_texture(struct drm_device
*dev
,
2481 struct drm_file
*file_priv
,
2482 drm_radeon_texture_t
*tex
,
2483 drm_radeon_tex_image_t
*image
)
2485 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2486 struct drm_buf
*buf
;
2488 const u8 __user
*data
;
2489 int size
, pass_size
;
2490 u64 src_offset
, dst_offset
;
2492 if (!radeon_check_offset(dev_priv
, tex
->offset
)) {
2493 DRM_ERROR("Invalid destination offset\n");
2497 /* this might fail for zero-sized uploads - are those illegal? */
2498 if (!radeon_check_offset(dev_priv
, tex
->offset
+ tex
->height
* tex
->pitch
- 1)) {
2499 DRM_ERROR("Invalid final destination offset\n");
2503 size
= tex
->height
* tex
->pitch
;
2508 dst_offset
= tex
->offset
;
2510 if (r600_prepare_blit_copy(dev
, file_priv
)) {
2511 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2515 data
= (const u8 __user
*)image
->data
;
2518 buf
= radeon_freelist_get(dev
);
2520 DRM_DEBUG("EAGAIN\n");
2521 if (DRM_COPY_TO_USER(tex
->image
, image
, sizeof(*image
)))
2526 if (pass_size
> buf
->total
)
2527 pass_size
= buf
->total
;
2529 /* Dispatch the indirect buffer.
2532 (u32
*) ((char *)dev
->agp_buffer_map
->handle
+ buf
->offset
);
2534 if (DRM_COPY_FROM_USER(buffer
, data
, pass_size
)) {
2535 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size
);
2539 buf
->file_priv
= file_priv
;
2540 buf
->used
= pass_size
;
2541 src_offset
= dev_priv
->gart_buffers_offset
+ buf
->offset
;
2543 r600_blit_copy(dev
, src_offset
, dst_offset
, pass_size
);
2545 radeon_cp_discard_buffer(dev
, file_priv
->master
, buf
);
2547 /* Update the input parameters for next time */
2548 image
->data
= (const u8 __user
*)image
->data
+ pass_size
;
2549 dst_offset
+= pass_size
;
2552 r600_done_blit_copy(dev
);
2560 static u32
radeon_cs_id_get(struct drm_radeon_private
*radeon
)
2562 /* FIXME: check if wrap affect last reported wrap & sequence */
2563 radeon
->cs_id_scnt
= (radeon
->cs_id_scnt
+ 1) & 0x00FFFFFF;
2564 if (!radeon
->cs_id_scnt
) {
2565 /* increment wrap counter */
2566 radeon
->cs_id_wcnt
+= 0x01000000;
2567 /* valid sequence counter start at 1 */
2568 radeon
->cs_id_scnt
= 1;
2570 return (radeon
->cs_id_scnt
| radeon
->cs_id_wcnt
);
2573 static void r600_cs_id_emit(drm_radeon_private_t
*dev_priv
, u32
*id
)
2577 *id
= radeon_cs_id_get(dev_priv
);
2581 R600_CLEAR_AGE(*id
);
2586 static int r600_ib_get(struct drm_device
*dev
,
2587 struct drm_file
*fpriv
,
2588 struct drm_buf
**buffer
)
2590 struct drm_buf
*buf
;
2593 buf
= radeon_freelist_get(dev
);
2597 buf
->file_priv
= fpriv
;
2602 static void r600_ib_free(struct drm_device
*dev
, struct drm_buf
*buf
,
2603 struct drm_file
*fpriv
, int l
, int r
)
2605 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2609 r600_cp_dispatch_indirect(dev
, buf
, 0, l
* 4);
2610 radeon_cp_discard_buffer(dev
, fpriv
->master
, buf
);
2615 int r600_cs_legacy_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*fpriv
)
2617 struct drm_radeon_private
*dev_priv
= dev
->dev_private
;
2618 struct drm_radeon_cs
*cs
= data
;
2619 struct drm_buf
*buf
;
2624 if (dev_priv
== NULL
) {
2625 DRM_ERROR("called with no initialization\n");
2628 family
= dev_priv
->flags
& RADEON_FAMILY_MASK
;
2629 if (family
< CHIP_R600
) {
2630 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2633 mutex_lock(&dev_priv
->cs_mutex
);
2635 r
= r600_ib_get(dev
, fpriv
, &buf
);
2637 DRM_ERROR("ib_get failed\n");
2640 ib
= dev
->agp_buffer_map
->handle
+ buf
->offset
;
2641 /* now parse command stream */
2642 r
= r600_cs_legacy(dev
, data
, fpriv
, family
, ib
, &l
);
2648 r600_ib_free(dev
, buf
, fpriv
, l
, r
);
2649 /* emit cs id sequence */
2650 r600_cs_id_emit(dev_priv
, &cs_id
);
2652 mutex_unlock(&dev_priv
->cs_mutex
);
2656 void r600_cs_legacy_get_tiling_conf(struct drm_device
*dev
, u32
*npipes
, u32
*nbanks
, u32
*group_size
)
2658 struct drm_radeon_private
*dev_priv
= dev
->dev_private
;
2660 *npipes
= dev_priv
->r600_npipes
;
2661 *nbanks
= dev_priv
->r600_nbanks
;
2662 *group_size
= dev_priv
->r600_group_size
;