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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99
100 /*
101 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 * symbol;
103 */
104 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
105 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
106 /* RADEON_IB_POOL_SIZE must be a power of 2 */
107 #define RADEON_IB_POOL_SIZE 16
108 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
109 #define RADEONFB_CONN_LIMIT 4
110 #define RADEON_BIOS_NUM_SCRATCH 8
111
112 /* max number of rings */
113 #define RADEON_NUM_RINGS 6
114
115 /* fence seq are set to this number when signaled */
116 #define RADEON_FENCE_SIGNALED_SEQ 0LL
117
118 /* internal ring indices */
119 /* r1xx+ has gfx CP ring */
120 #define RADEON_RING_TYPE_GFX_INDEX 0
121
122 /* cayman has 2 compute CP rings */
123 #define CAYMAN_RING_TYPE_CP1_INDEX 1
124 #define CAYMAN_RING_TYPE_CP2_INDEX 2
125
126 /* R600+ has an async dma ring */
127 #define R600_RING_TYPE_DMA_INDEX 3
128 /* cayman add a second async dma ring */
129 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
130
131 /* R600+ */
132 #define R600_RING_TYPE_UVD_INDEX 5
133
134 /* hardcode those limit for now */
135 #define RADEON_VA_IB_OFFSET (1 << 20)
136 #define RADEON_VA_RESERVED_SIZE (8 << 20)
137 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
138
139 /* reset flags */
140 #define RADEON_RESET_GFX (1 << 0)
141 #define RADEON_RESET_COMPUTE (1 << 1)
142 #define RADEON_RESET_DMA (1 << 2)
143 #define RADEON_RESET_CP (1 << 3)
144 #define RADEON_RESET_GRBM (1 << 4)
145 #define RADEON_RESET_DMA1 (1 << 5)
146 #define RADEON_RESET_RLC (1 << 6)
147 #define RADEON_RESET_SEM (1 << 7)
148 #define RADEON_RESET_IH (1 << 8)
149 #define RADEON_RESET_VMC (1 << 9)
150 #define RADEON_RESET_MC (1 << 10)
151 #define RADEON_RESET_DISPLAY (1 << 11)
152
153 /*
154 * Errata workarounds.
155 */
156 enum radeon_pll_errata {
157 CHIP_ERRATA_R300_CG = 0x00000001,
158 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
159 CHIP_ERRATA_PLL_DELAY = 0x00000004
160 };
161
162
163 struct radeon_device;
164
165
166 /*
167 * BIOS.
168 */
169 bool radeon_get_bios(struct radeon_device *rdev);
170
171 /*
172 * Dummy page
173 */
174 struct radeon_dummy_page {
175 struct page *page;
176 dma_addr_t addr;
177 };
178 int radeon_dummy_page_init(struct radeon_device *rdev);
179 void radeon_dummy_page_fini(struct radeon_device *rdev);
180
181
182 /*
183 * Clocks
184 */
185 struct radeon_clock {
186 struct radeon_pll p1pll;
187 struct radeon_pll p2pll;
188 struct radeon_pll dcpll;
189 struct radeon_pll spll;
190 struct radeon_pll mpll;
191 /* 10 Khz units */
192 uint32_t default_mclk;
193 uint32_t default_sclk;
194 uint32_t default_dispclk;
195 uint32_t dp_extclk;
196 uint32_t max_pixel_clock;
197 };
198
199 /*
200 * Power management
201 */
202 int radeon_pm_init(struct radeon_device *rdev);
203 void radeon_pm_fini(struct radeon_device *rdev);
204 void radeon_pm_compute_clocks(struct radeon_device *rdev);
205 void radeon_pm_suspend(struct radeon_device *rdev);
206 void radeon_pm_resume(struct radeon_device *rdev);
207 void radeon_combios_get_power_modes(struct radeon_device *rdev);
208 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
209 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
210 u8 clock_type,
211 u32 clock,
212 bool strobe_mode,
213 struct atom_clock_dividers *dividers);
214 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
215 void rs690_pm_info(struct radeon_device *rdev);
216 extern int rv6xx_get_temp(struct radeon_device *rdev);
217 extern int rv770_get_temp(struct radeon_device *rdev);
218 extern int evergreen_get_temp(struct radeon_device *rdev);
219 extern int sumo_get_temp(struct radeon_device *rdev);
220 extern int si_get_temp(struct radeon_device *rdev);
221 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
222 unsigned *bankh, unsigned *mtaspect,
223 unsigned *tile_split);
224
225 /*
226 * Fences.
227 */
228 struct radeon_fence_driver {
229 uint32_t scratch_reg;
230 uint64_t gpu_addr;
231 volatile uint32_t *cpu_addr;
232 /* sync_seq is protected by ring emission lock */
233 uint64_t sync_seq[RADEON_NUM_RINGS];
234 atomic64_t last_seq;
235 unsigned long last_activity;
236 bool initialized;
237 };
238
239 struct radeon_fence {
240 struct radeon_device *rdev;
241 struct kref kref;
242 /* protected by radeon_fence.lock */
243 uint64_t seq;
244 /* RB, DMA, etc. */
245 unsigned ring;
246 };
247
248 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
249 int radeon_fence_driver_init(struct radeon_device *rdev);
250 void radeon_fence_driver_fini(struct radeon_device *rdev);
251 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
252 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
253 void radeon_fence_process(struct radeon_device *rdev, int ring);
254 bool radeon_fence_signaled(struct radeon_fence *fence);
255 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
256 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
257 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
258 int radeon_fence_wait_any(struct radeon_device *rdev,
259 struct radeon_fence **fences,
260 bool intr);
261 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
262 void radeon_fence_unref(struct radeon_fence **fence);
263 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
264 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
265 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
266 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
267 struct radeon_fence *b)
268 {
269 if (!a) {
270 return b;
271 }
272
273 if (!b) {
274 return a;
275 }
276
277 BUG_ON(a->ring != b->ring);
278
279 if (a->seq > b->seq) {
280 return a;
281 } else {
282 return b;
283 }
284 }
285
286 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
287 struct radeon_fence *b)
288 {
289 if (!a) {
290 return false;
291 }
292
293 if (!b) {
294 return true;
295 }
296
297 BUG_ON(a->ring != b->ring);
298
299 return a->seq < b->seq;
300 }
301
302 /*
303 * Tiling registers
304 */
305 struct radeon_surface_reg {
306 struct radeon_bo *bo;
307 };
308
309 #define RADEON_GEM_MAX_SURFACES 8
310
311 /*
312 * TTM.
313 */
314 struct radeon_mman {
315 struct ttm_bo_global_ref bo_global_ref;
316 struct drm_global_reference mem_global_ref;
317 struct ttm_bo_device bdev;
318 bool mem_global_referenced;
319 bool initialized;
320 };
321
322 /* bo virtual address in a specific vm */
323 struct radeon_bo_va {
324 /* protected by bo being reserved */
325 struct list_head bo_list;
326 uint64_t soffset;
327 uint64_t eoffset;
328 uint32_t flags;
329 bool valid;
330 unsigned ref_count;
331
332 /* protected by vm mutex */
333 struct list_head vm_list;
334
335 /* constant after initialization */
336 struct radeon_vm *vm;
337 struct radeon_bo *bo;
338 };
339
340 struct radeon_bo {
341 /* Protected by gem.mutex */
342 struct list_head list;
343 /* Protected by tbo.reserved */
344 u32 placements[3];
345 struct ttm_placement placement;
346 struct ttm_buffer_object tbo;
347 struct ttm_bo_kmap_obj kmap;
348 unsigned pin_count;
349 void *kptr;
350 u32 tiling_flags;
351 u32 pitch;
352 int surface_reg;
353 /* list of all virtual address to which this bo
354 * is associated to
355 */
356 struct list_head va;
357 /* Constant after initialization */
358 struct radeon_device *rdev;
359 struct drm_gem_object gem_base;
360
361 struct ttm_bo_kmap_obj dma_buf_vmap;
362 pid_t pid;
363 };
364 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
365
366 struct radeon_bo_list {
367 struct ttm_validate_buffer tv;
368 struct radeon_bo *bo;
369 uint64_t gpu_offset;
370 bool written;
371 unsigned domain;
372 unsigned alt_domain;
373 u32 tiling_flags;
374 };
375
376 int radeon_gem_debugfs_init(struct radeon_device *rdev);
377
378 /* sub-allocation manager, it has to be protected by another lock.
379 * By conception this is an helper for other part of the driver
380 * like the indirect buffer or semaphore, which both have their
381 * locking.
382 *
383 * Principe is simple, we keep a list of sub allocation in offset
384 * order (first entry has offset == 0, last entry has the highest
385 * offset).
386 *
387 * When allocating new object we first check if there is room at
388 * the end total_size - (last_object_offset + last_object_size) >=
389 * alloc_size. If so we allocate new object there.
390 *
391 * When there is not enough room at the end, we start waiting for
392 * each sub object until we reach object_offset+object_size >=
393 * alloc_size, this object then become the sub object we return.
394 *
395 * Alignment can't be bigger than page size.
396 *
397 * Hole are not considered for allocation to keep things simple.
398 * Assumption is that there won't be hole (all object on same
399 * alignment).
400 */
401 struct radeon_sa_manager {
402 wait_queue_head_t wq;
403 struct radeon_bo *bo;
404 struct list_head *hole;
405 struct list_head flist[RADEON_NUM_RINGS];
406 struct list_head olist;
407 unsigned size;
408 uint64_t gpu_addr;
409 void *cpu_ptr;
410 uint32_t domain;
411 };
412
413 struct radeon_sa_bo;
414
415 /* sub-allocation buffer */
416 struct radeon_sa_bo {
417 struct list_head olist;
418 struct list_head flist;
419 struct radeon_sa_manager *manager;
420 unsigned soffset;
421 unsigned eoffset;
422 struct radeon_fence *fence;
423 };
424
425 /*
426 * GEM objects.
427 */
428 struct radeon_gem {
429 struct mutex mutex;
430 struct list_head objects;
431 };
432
433 int radeon_gem_init(struct radeon_device *rdev);
434 void radeon_gem_fini(struct radeon_device *rdev);
435 int radeon_gem_object_create(struct radeon_device *rdev, int size,
436 int alignment, int initial_domain,
437 bool discardable, bool kernel,
438 struct drm_gem_object **obj);
439
440 int radeon_mode_dumb_create(struct drm_file *file_priv,
441 struct drm_device *dev,
442 struct drm_mode_create_dumb *args);
443 int radeon_mode_dumb_mmap(struct drm_file *filp,
444 struct drm_device *dev,
445 uint32_t handle, uint64_t *offset_p);
446 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
447 struct drm_device *dev,
448 uint32_t handle);
449
450 /*
451 * Semaphores.
452 */
453 /* everything here is constant */
454 struct radeon_semaphore {
455 struct radeon_sa_bo *sa_bo;
456 signed waiters;
457 uint64_t gpu_addr;
458 };
459
460 int radeon_semaphore_create(struct radeon_device *rdev,
461 struct radeon_semaphore **semaphore);
462 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
463 struct radeon_semaphore *semaphore);
464 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
465 struct radeon_semaphore *semaphore);
466 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
467 struct radeon_semaphore *semaphore,
468 int signaler, int waiter);
469 void radeon_semaphore_free(struct radeon_device *rdev,
470 struct radeon_semaphore **semaphore,
471 struct radeon_fence *fence);
472
473 /*
474 * GART structures, functions & helpers
475 */
476 struct radeon_mc;
477
478 #define RADEON_GPU_PAGE_SIZE 4096
479 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
480 #define RADEON_GPU_PAGE_SHIFT 12
481 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
482
483 struct radeon_gart {
484 dma_addr_t table_addr;
485 struct radeon_bo *robj;
486 void *ptr;
487 unsigned num_gpu_pages;
488 unsigned num_cpu_pages;
489 unsigned table_size;
490 struct page **pages;
491 dma_addr_t *pages_addr;
492 bool ready;
493 };
494
495 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
496 void radeon_gart_table_ram_free(struct radeon_device *rdev);
497 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
498 void radeon_gart_table_vram_free(struct radeon_device *rdev);
499 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
500 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
501 int radeon_gart_init(struct radeon_device *rdev);
502 void radeon_gart_fini(struct radeon_device *rdev);
503 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
504 int pages);
505 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
506 int pages, struct page **pagelist,
507 dma_addr_t *dma_addr);
508 void radeon_gart_restore(struct radeon_device *rdev);
509
510
511 /*
512 * GPU MC structures, functions & helpers
513 */
514 struct radeon_mc {
515 resource_size_t aper_size;
516 resource_size_t aper_base;
517 resource_size_t agp_base;
518 /* for some chips with <= 32MB we need to lie
519 * about vram size near mc fb location */
520 u64 mc_vram_size;
521 u64 visible_vram_size;
522 u64 gtt_size;
523 u64 gtt_start;
524 u64 gtt_end;
525 u64 vram_start;
526 u64 vram_end;
527 unsigned vram_width;
528 u64 real_vram_size;
529 int vram_mtrr;
530 bool vram_is_ddr;
531 bool igp_sideport_enabled;
532 u64 gtt_base_align;
533 u64 mc_mask;
534 };
535
536 bool radeon_combios_sideport_present(struct radeon_device *rdev);
537 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
538
539 /*
540 * GPU scratch registers structures, functions & helpers
541 */
542 struct radeon_scratch {
543 unsigned num_reg;
544 uint32_t reg_base;
545 bool free[32];
546 uint32_t reg[32];
547 };
548
549 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
550 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
551
552
553 /*
554 * IRQS.
555 */
556
557 struct radeon_unpin_work {
558 struct work_struct work;
559 struct radeon_device *rdev;
560 int crtc_id;
561 struct radeon_fence *fence;
562 struct drm_pending_vblank_event *event;
563 struct radeon_bo *old_rbo;
564 u64 new_crtc_base;
565 };
566
567 struct r500_irq_stat_regs {
568 u32 disp_int;
569 u32 hdmi0_status;
570 };
571
572 struct r600_irq_stat_regs {
573 u32 disp_int;
574 u32 disp_int_cont;
575 u32 disp_int_cont2;
576 u32 d1grph_int;
577 u32 d2grph_int;
578 u32 hdmi0_status;
579 u32 hdmi1_status;
580 };
581
582 struct evergreen_irq_stat_regs {
583 u32 disp_int;
584 u32 disp_int_cont;
585 u32 disp_int_cont2;
586 u32 disp_int_cont3;
587 u32 disp_int_cont4;
588 u32 disp_int_cont5;
589 u32 d1grph_int;
590 u32 d2grph_int;
591 u32 d3grph_int;
592 u32 d4grph_int;
593 u32 d5grph_int;
594 u32 d6grph_int;
595 u32 afmt_status1;
596 u32 afmt_status2;
597 u32 afmt_status3;
598 u32 afmt_status4;
599 u32 afmt_status5;
600 u32 afmt_status6;
601 };
602
603 union radeon_irq_stat_regs {
604 struct r500_irq_stat_regs r500;
605 struct r600_irq_stat_regs r600;
606 struct evergreen_irq_stat_regs evergreen;
607 };
608
609 #define RADEON_MAX_HPD_PINS 6
610 #define RADEON_MAX_CRTCS 6
611 #define RADEON_MAX_AFMT_BLOCKS 6
612
613 struct radeon_irq {
614 bool installed;
615 spinlock_t lock;
616 atomic_t ring_int[RADEON_NUM_RINGS];
617 bool crtc_vblank_int[RADEON_MAX_CRTCS];
618 atomic_t pflip[RADEON_MAX_CRTCS];
619 wait_queue_head_t vblank_queue;
620 bool hpd[RADEON_MAX_HPD_PINS];
621 bool afmt[RADEON_MAX_AFMT_BLOCKS];
622 union radeon_irq_stat_regs stat_regs;
623 };
624
625 int radeon_irq_kms_init(struct radeon_device *rdev);
626 void radeon_irq_kms_fini(struct radeon_device *rdev);
627 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
628 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
629 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
630 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
631 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
632 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
633 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
634 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
635
636 /*
637 * CP & rings.
638 */
639
640 struct radeon_ib {
641 struct radeon_sa_bo *sa_bo;
642 uint32_t length_dw;
643 uint64_t gpu_addr;
644 uint32_t *ptr;
645 int ring;
646 struct radeon_fence *fence;
647 struct radeon_vm *vm;
648 bool is_const_ib;
649 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
650 struct radeon_semaphore *semaphore;
651 };
652
653 struct radeon_ring {
654 struct radeon_bo *ring_obj;
655 volatile uint32_t *ring;
656 unsigned rptr;
657 unsigned rptr_offs;
658 unsigned rptr_reg;
659 unsigned rptr_save_reg;
660 u64 next_rptr_gpu_addr;
661 volatile u32 *next_rptr_cpu_addr;
662 unsigned wptr;
663 unsigned wptr_old;
664 unsigned wptr_reg;
665 unsigned ring_size;
666 unsigned ring_free_dw;
667 int count_dw;
668 unsigned long last_activity;
669 unsigned last_rptr;
670 uint64_t gpu_addr;
671 uint32_t align_mask;
672 uint32_t ptr_mask;
673 bool ready;
674 u32 ptr_reg_shift;
675 u32 ptr_reg_mask;
676 u32 nop;
677 u32 idx;
678 u64 last_semaphore_signal_addr;
679 u64 last_semaphore_wait_addr;
680 };
681
682 /*
683 * VM
684 */
685
686 /* maximum number of VMIDs */
687 #define RADEON_NUM_VM 16
688
689 /* defines number of bits in page table versus page directory,
690 * a page is 4KB so we have 12 bits offset, 9 bits in the page
691 * table and the remaining 19 bits are in the page directory */
692 #define RADEON_VM_BLOCK_SIZE 9
693
694 /* number of entries in page table */
695 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
696
697 struct radeon_vm {
698 struct list_head list;
699 struct list_head va;
700 unsigned id;
701
702 /* contains the page directory */
703 struct radeon_sa_bo *page_directory;
704 uint64_t pd_gpu_addr;
705
706 /* array of page tables, one for each page directory entry */
707 struct radeon_sa_bo **page_tables;
708
709 struct mutex mutex;
710 /* last fence for cs using this vm */
711 struct radeon_fence *fence;
712 /* last flush or NULL if we still need to flush */
713 struct radeon_fence *last_flush;
714 };
715
716 struct radeon_vm_manager {
717 struct mutex lock;
718 struct list_head lru_vm;
719 struct radeon_fence *active[RADEON_NUM_VM];
720 struct radeon_sa_manager sa_manager;
721 uint32_t max_pfn;
722 /* number of VMIDs */
723 unsigned nvm;
724 /* vram base address for page table entry */
725 u64 vram_base_offset;
726 /* is vm enabled? */
727 bool enabled;
728 };
729
730 /*
731 * file private structure
732 */
733 struct radeon_fpriv {
734 struct radeon_vm vm;
735 };
736
737 /*
738 * R6xx+ IH ring
739 */
740 struct r600_ih {
741 struct radeon_bo *ring_obj;
742 volatile uint32_t *ring;
743 unsigned rptr;
744 unsigned ring_size;
745 uint64_t gpu_addr;
746 uint32_t ptr_mask;
747 atomic_t lock;
748 bool enabled;
749 };
750
751 struct r600_blit_cp_primitives {
752 void (*set_render_target)(struct radeon_device *rdev, int format,
753 int w, int h, u64 gpu_addr);
754 void (*cp_set_surface_sync)(struct radeon_device *rdev,
755 u32 sync_type, u32 size,
756 u64 mc_addr);
757 void (*set_shaders)(struct radeon_device *rdev);
758 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
759 void (*set_tex_resource)(struct radeon_device *rdev,
760 int format, int w, int h, int pitch,
761 u64 gpu_addr, u32 size);
762 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
763 int x2, int y2);
764 void (*draw_auto)(struct radeon_device *rdev);
765 void (*set_default_state)(struct radeon_device *rdev);
766 };
767
768 struct r600_blit {
769 struct radeon_bo *shader_obj;
770 struct r600_blit_cp_primitives primitives;
771 int max_dim;
772 int ring_size_common;
773 int ring_size_per_loop;
774 u64 shader_gpu_addr;
775 u32 vs_offset, ps_offset;
776 u32 state_offset;
777 u32 state_len;
778 };
779
780 /*
781 * SI RLC stuff
782 */
783 struct si_rlc {
784 /* for power gating */
785 struct radeon_bo *save_restore_obj;
786 uint64_t save_restore_gpu_addr;
787 /* for clear state */
788 struct radeon_bo *clear_state_obj;
789 uint64_t clear_state_gpu_addr;
790 };
791
792 int radeon_ib_get(struct radeon_device *rdev, int ring,
793 struct radeon_ib *ib, struct radeon_vm *vm,
794 unsigned size);
795 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
796 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
797 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
798 struct radeon_ib *const_ib);
799 int radeon_ib_pool_init(struct radeon_device *rdev);
800 void radeon_ib_pool_fini(struct radeon_device *rdev);
801 int radeon_ib_ring_tests(struct radeon_device *rdev);
802 /* Ring access between begin & end cannot sleep */
803 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
804 struct radeon_ring *ring);
805 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
806 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
807 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
808 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
809 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
810 void radeon_ring_undo(struct radeon_ring *ring);
811 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
812 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
813 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
814 void radeon_ring_lockup_update(struct radeon_ring *ring);
815 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
816 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
817 uint32_t **data);
818 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
819 unsigned size, uint32_t *data);
820 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
821 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
822 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
823 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
824
825
826 /* r600 async dma */
827 void r600_dma_stop(struct radeon_device *rdev);
828 int r600_dma_resume(struct radeon_device *rdev);
829 void r600_dma_fini(struct radeon_device *rdev);
830
831 void cayman_dma_stop(struct radeon_device *rdev);
832 int cayman_dma_resume(struct radeon_device *rdev);
833 void cayman_dma_fini(struct radeon_device *rdev);
834
835 /*
836 * CS.
837 */
838 struct radeon_cs_reloc {
839 struct drm_gem_object *gobj;
840 struct radeon_bo *robj;
841 struct radeon_bo_list lobj;
842 uint32_t handle;
843 uint32_t flags;
844 };
845
846 struct radeon_cs_chunk {
847 uint32_t chunk_id;
848 uint32_t length_dw;
849 int kpage_idx[2];
850 uint32_t *kpage[2];
851 uint32_t *kdata;
852 void __user *user_ptr;
853 int last_copied_page;
854 int last_page_index;
855 };
856
857 struct radeon_cs_parser {
858 struct device *dev;
859 struct radeon_device *rdev;
860 struct drm_file *filp;
861 /* chunks */
862 unsigned nchunks;
863 struct radeon_cs_chunk *chunks;
864 uint64_t *chunks_array;
865 /* IB */
866 unsigned idx;
867 /* relocations */
868 unsigned nrelocs;
869 struct radeon_cs_reloc *relocs;
870 struct radeon_cs_reloc **relocs_ptr;
871 struct list_head validated;
872 unsigned dma_reloc_idx;
873 /* indices of various chunks */
874 int chunk_ib_idx;
875 int chunk_relocs_idx;
876 int chunk_flags_idx;
877 int chunk_const_ib_idx;
878 struct radeon_ib ib;
879 struct radeon_ib const_ib;
880 void *track;
881 unsigned family;
882 int parser_error;
883 u32 cs_flags;
884 u32 ring;
885 s32 priority;
886 };
887
888 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
889 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
890
891 struct radeon_cs_packet {
892 unsigned idx;
893 unsigned type;
894 unsigned reg;
895 unsigned opcode;
896 int count;
897 unsigned one_reg_wr;
898 };
899
900 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
901 struct radeon_cs_packet *pkt,
902 unsigned idx, unsigned reg);
903 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
904 struct radeon_cs_packet *pkt);
905
906
907 /*
908 * AGP
909 */
910 int radeon_agp_init(struct radeon_device *rdev);
911 void radeon_agp_resume(struct radeon_device *rdev);
912 void radeon_agp_suspend(struct radeon_device *rdev);
913 void radeon_agp_fini(struct radeon_device *rdev);
914
915
916 /*
917 * Writeback
918 */
919 struct radeon_wb {
920 struct radeon_bo *wb_obj;
921 volatile uint32_t *wb;
922 uint64_t gpu_addr;
923 bool enabled;
924 bool use_event;
925 };
926
927 #define RADEON_WB_SCRATCH_OFFSET 0
928 #define RADEON_WB_RING0_NEXT_RPTR 256
929 #define RADEON_WB_CP_RPTR_OFFSET 1024
930 #define RADEON_WB_CP1_RPTR_OFFSET 1280
931 #define RADEON_WB_CP2_RPTR_OFFSET 1536
932 #define R600_WB_DMA_RPTR_OFFSET 1792
933 #define R600_WB_IH_WPTR_OFFSET 2048
934 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
935 #define R600_WB_UVD_RPTR_OFFSET 2560
936 #define R600_WB_EVENT_OFFSET 3072
937
938 /**
939 * struct radeon_pm - power management datas
940 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
941 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
942 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
943 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
944 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
945 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
946 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
947 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
948 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
949 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
950 * @needed_bandwidth: current bandwidth needs
951 *
952 * It keeps track of various data needed to take powermanagement decision.
953 * Bandwidth need is used to determine minimun clock of the GPU and memory.
954 * Equation between gpu/memory clock and available bandwidth is hw dependent
955 * (type of memory, bus size, efficiency, ...)
956 */
957
958 enum radeon_pm_method {
959 PM_METHOD_PROFILE,
960 PM_METHOD_DYNPM,
961 };
962
963 enum radeon_dynpm_state {
964 DYNPM_STATE_DISABLED,
965 DYNPM_STATE_MINIMUM,
966 DYNPM_STATE_PAUSED,
967 DYNPM_STATE_ACTIVE,
968 DYNPM_STATE_SUSPENDED,
969 };
970 enum radeon_dynpm_action {
971 DYNPM_ACTION_NONE,
972 DYNPM_ACTION_MINIMUM,
973 DYNPM_ACTION_DOWNCLOCK,
974 DYNPM_ACTION_UPCLOCK,
975 DYNPM_ACTION_DEFAULT
976 };
977
978 enum radeon_voltage_type {
979 VOLTAGE_NONE = 0,
980 VOLTAGE_GPIO,
981 VOLTAGE_VDDC,
982 VOLTAGE_SW
983 };
984
985 enum radeon_pm_state_type {
986 POWER_STATE_TYPE_DEFAULT,
987 POWER_STATE_TYPE_POWERSAVE,
988 POWER_STATE_TYPE_BATTERY,
989 POWER_STATE_TYPE_BALANCED,
990 POWER_STATE_TYPE_PERFORMANCE,
991 };
992
993 enum radeon_pm_profile_type {
994 PM_PROFILE_DEFAULT,
995 PM_PROFILE_AUTO,
996 PM_PROFILE_LOW,
997 PM_PROFILE_MID,
998 PM_PROFILE_HIGH,
999 };
1000
1001 #define PM_PROFILE_DEFAULT_IDX 0
1002 #define PM_PROFILE_LOW_SH_IDX 1
1003 #define PM_PROFILE_MID_SH_IDX 2
1004 #define PM_PROFILE_HIGH_SH_IDX 3
1005 #define PM_PROFILE_LOW_MH_IDX 4
1006 #define PM_PROFILE_MID_MH_IDX 5
1007 #define PM_PROFILE_HIGH_MH_IDX 6
1008 #define PM_PROFILE_MAX 7
1009
1010 struct radeon_pm_profile {
1011 int dpms_off_ps_idx;
1012 int dpms_on_ps_idx;
1013 int dpms_off_cm_idx;
1014 int dpms_on_cm_idx;
1015 };
1016
1017 enum radeon_int_thermal_type {
1018 THERMAL_TYPE_NONE,
1019 THERMAL_TYPE_RV6XX,
1020 THERMAL_TYPE_RV770,
1021 THERMAL_TYPE_EVERGREEN,
1022 THERMAL_TYPE_SUMO,
1023 THERMAL_TYPE_NI,
1024 THERMAL_TYPE_SI,
1025 };
1026
1027 struct radeon_voltage {
1028 enum radeon_voltage_type type;
1029 /* gpio voltage */
1030 struct radeon_gpio_rec gpio;
1031 u32 delay; /* delay in usec from voltage drop to sclk change */
1032 bool active_high; /* voltage drop is active when bit is high */
1033 /* VDDC voltage */
1034 u8 vddc_id; /* index into vddc voltage table */
1035 u8 vddci_id; /* index into vddci voltage table */
1036 bool vddci_enabled;
1037 /* r6xx+ sw */
1038 u16 voltage;
1039 /* evergreen+ vddci */
1040 u16 vddci;
1041 };
1042
1043 /* clock mode flags */
1044 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1045
1046 struct radeon_pm_clock_info {
1047 /* memory clock */
1048 u32 mclk;
1049 /* engine clock */
1050 u32 sclk;
1051 /* voltage info */
1052 struct radeon_voltage voltage;
1053 /* standardized clock flags */
1054 u32 flags;
1055 };
1056
1057 /* state flags */
1058 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1059
1060 struct radeon_power_state {
1061 enum radeon_pm_state_type type;
1062 struct radeon_pm_clock_info *clock_info;
1063 /* number of valid clock modes in this power state */
1064 int num_clock_modes;
1065 struct radeon_pm_clock_info *default_clock_mode;
1066 /* standardized state flags */
1067 u32 flags;
1068 u32 misc; /* vbios specific flags */
1069 u32 misc2; /* vbios specific flags */
1070 int pcie_lanes; /* pcie lanes */
1071 };
1072
1073 /*
1074 * Some modes are overclocked by very low value, accept them
1075 */
1076 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1077
1078 struct radeon_pm {
1079 struct mutex mutex;
1080 /* write locked while reprogramming mclk */
1081 struct rw_semaphore mclk_lock;
1082 u32 active_crtcs;
1083 int active_crtc_count;
1084 int req_vblank;
1085 bool vblank_sync;
1086 fixed20_12 max_bandwidth;
1087 fixed20_12 igp_sideport_mclk;
1088 fixed20_12 igp_system_mclk;
1089 fixed20_12 igp_ht_link_clk;
1090 fixed20_12 igp_ht_link_width;
1091 fixed20_12 k8_bandwidth;
1092 fixed20_12 sideport_bandwidth;
1093 fixed20_12 ht_bandwidth;
1094 fixed20_12 core_bandwidth;
1095 fixed20_12 sclk;
1096 fixed20_12 mclk;
1097 fixed20_12 needed_bandwidth;
1098 struct radeon_power_state *power_state;
1099 /* number of valid power states */
1100 int num_power_states;
1101 int current_power_state_index;
1102 int current_clock_mode_index;
1103 int requested_power_state_index;
1104 int requested_clock_mode_index;
1105 int default_power_state_index;
1106 u32 current_sclk;
1107 u32 current_mclk;
1108 u16 current_vddc;
1109 u16 current_vddci;
1110 u32 default_sclk;
1111 u32 default_mclk;
1112 u16 default_vddc;
1113 u16 default_vddci;
1114 struct radeon_i2c_chan *i2c_bus;
1115 /* selected pm method */
1116 enum radeon_pm_method pm_method;
1117 /* dynpm power management */
1118 struct delayed_work dynpm_idle_work;
1119 enum radeon_dynpm_state dynpm_state;
1120 enum radeon_dynpm_action dynpm_planned_action;
1121 unsigned long dynpm_action_timeout;
1122 bool dynpm_can_upclock;
1123 bool dynpm_can_downclock;
1124 /* profile-based power management */
1125 enum radeon_pm_profile_type profile;
1126 int profile_index;
1127 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1128 /* internal thermal controller on rv6xx+ */
1129 enum radeon_int_thermal_type int_thermal_type;
1130 struct device *int_hwmon_dev;
1131 };
1132
1133 int radeon_pm_get_type_index(struct radeon_device *rdev,
1134 enum radeon_pm_state_type ps_type,
1135 int instance);
1136 /*
1137 * UVD
1138 */
1139 #define RADEON_MAX_UVD_HANDLES 10
1140 #define RADEON_UVD_STACK_SIZE (1024*1024)
1141 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1142
1143 struct radeon_uvd {
1144 struct radeon_bo *vcpu_bo;
1145 void *cpu_addr;
1146 uint64_t gpu_addr;
1147 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1148 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1149 struct delayed_work idle_work;
1150 };
1151
1152 int radeon_uvd_init(struct radeon_device *rdev);
1153 void radeon_uvd_fini(struct radeon_device *rdev);
1154 int radeon_uvd_suspend(struct radeon_device *rdev);
1155 int radeon_uvd_resume(struct radeon_device *rdev);
1156 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1157 uint32_t handle, struct radeon_fence **fence);
1158 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1159 uint32_t handle, struct radeon_fence **fence);
1160 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1161 void radeon_uvd_free_handles(struct radeon_device *rdev,
1162 struct drm_file *filp);
1163 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1164 void radeon_uvd_note_usage(struct radeon_device *rdev);
1165 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1166 unsigned vclk, unsigned dclk,
1167 unsigned vco_min, unsigned vco_max,
1168 unsigned fb_factor, unsigned fb_mask,
1169 unsigned pd_min, unsigned pd_max,
1170 unsigned pd_even,
1171 unsigned *optimal_fb_div,
1172 unsigned *optimal_vclk_div,
1173 unsigned *optimal_dclk_div);
1174 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1175 unsigned cg_upll_func_cntl);
1176
1177 struct r600_audio {
1178 int channels;
1179 int rate;
1180 int bits_per_sample;
1181 u8 status_bits;
1182 u8 category_code;
1183 };
1184
1185 /*
1186 * Benchmarking
1187 */
1188 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1189
1190
1191 /*
1192 * Testing
1193 */
1194 void radeon_test_moves(struct radeon_device *rdev);
1195 void radeon_test_ring_sync(struct radeon_device *rdev,
1196 struct radeon_ring *cpA,
1197 struct radeon_ring *cpB);
1198 void radeon_test_syncing(struct radeon_device *rdev);
1199
1200
1201 /*
1202 * Debugfs
1203 */
1204 struct radeon_debugfs {
1205 struct drm_info_list *files;
1206 unsigned num_files;
1207 };
1208
1209 int radeon_debugfs_add_files(struct radeon_device *rdev,
1210 struct drm_info_list *files,
1211 unsigned nfiles);
1212 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1213
1214
1215 /*
1216 * ASIC specific functions.
1217 */
1218 struct radeon_asic {
1219 int (*init)(struct radeon_device *rdev);
1220 void (*fini)(struct radeon_device *rdev);
1221 int (*resume)(struct radeon_device *rdev);
1222 int (*suspend)(struct radeon_device *rdev);
1223 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1224 int (*asic_reset)(struct radeon_device *rdev);
1225 /* ioctl hw specific callback. Some hw might want to perform special
1226 * operation on specific ioctl. For instance on wait idle some hw
1227 * might want to perform and HDP flush through MMIO as it seems that
1228 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1229 * through ring.
1230 */
1231 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1232 /* check if 3D engine is idle */
1233 bool (*gui_idle)(struct radeon_device *rdev);
1234 /* wait for mc_idle */
1235 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1236 /* get the reference clock */
1237 u32 (*get_xclk)(struct radeon_device *rdev);
1238 /* get the gpu clock counter */
1239 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1240 /* gart */
1241 struct {
1242 void (*tlb_flush)(struct radeon_device *rdev);
1243 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1244 } gart;
1245 struct {
1246 int (*init)(struct radeon_device *rdev);
1247 void (*fini)(struct radeon_device *rdev);
1248
1249 u32 pt_ring_index;
1250 void (*set_page)(struct radeon_device *rdev,
1251 struct radeon_ib *ib,
1252 uint64_t pe,
1253 uint64_t addr, unsigned count,
1254 uint32_t incr, uint32_t flags);
1255 } vm;
1256 /* ring specific callbacks */
1257 struct {
1258 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1259 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1260 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1261 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1262 struct radeon_semaphore *semaphore, bool emit_wait);
1263 int (*cs_parse)(struct radeon_cs_parser *p);
1264 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1265 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1266 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1267 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1268 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1269 } ring[RADEON_NUM_RINGS];
1270 /* irqs */
1271 struct {
1272 int (*set)(struct radeon_device *rdev);
1273 int (*process)(struct radeon_device *rdev);
1274 } irq;
1275 /* displays */
1276 struct {
1277 /* display watermarks */
1278 void (*bandwidth_update)(struct radeon_device *rdev);
1279 /* get frame count */
1280 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1281 /* wait for vblank */
1282 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1283 /* set backlight level */
1284 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1285 /* get backlight level */
1286 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1287 /* audio callbacks */
1288 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1289 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1290 } display;
1291 /* copy functions for bo handling */
1292 struct {
1293 int (*blit)(struct radeon_device *rdev,
1294 uint64_t src_offset,
1295 uint64_t dst_offset,
1296 unsigned num_gpu_pages,
1297 struct radeon_fence **fence);
1298 u32 blit_ring_index;
1299 int (*dma)(struct radeon_device *rdev,
1300 uint64_t src_offset,
1301 uint64_t dst_offset,
1302 unsigned num_gpu_pages,
1303 struct radeon_fence **fence);
1304 u32 dma_ring_index;
1305 /* method used for bo copy */
1306 int (*copy)(struct radeon_device *rdev,
1307 uint64_t src_offset,
1308 uint64_t dst_offset,
1309 unsigned num_gpu_pages,
1310 struct radeon_fence **fence);
1311 /* ring used for bo copies */
1312 u32 copy_ring_index;
1313 } copy;
1314 /* surfaces */
1315 struct {
1316 int (*set_reg)(struct radeon_device *rdev, int reg,
1317 uint32_t tiling_flags, uint32_t pitch,
1318 uint32_t offset, uint32_t obj_size);
1319 void (*clear_reg)(struct radeon_device *rdev, int reg);
1320 } surface;
1321 /* hotplug detect */
1322 struct {
1323 void (*init)(struct radeon_device *rdev);
1324 void (*fini)(struct radeon_device *rdev);
1325 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1326 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1327 } hpd;
1328 /* power management */
1329 struct {
1330 void (*misc)(struct radeon_device *rdev);
1331 void (*prepare)(struct radeon_device *rdev);
1332 void (*finish)(struct radeon_device *rdev);
1333 void (*init_profile)(struct radeon_device *rdev);
1334 void (*get_dynpm_state)(struct radeon_device *rdev);
1335 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1336 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1337 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1338 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1339 int (*get_pcie_lanes)(struct radeon_device *rdev);
1340 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1341 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1342 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1343 } pm;
1344 /* pageflipping */
1345 struct {
1346 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1347 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1348 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1349 } pflip;
1350 };
1351
1352 /*
1353 * Asic structures
1354 */
1355 struct r100_asic {
1356 const unsigned *reg_safe_bm;
1357 unsigned reg_safe_bm_size;
1358 u32 hdp_cntl;
1359 };
1360
1361 struct r300_asic {
1362 const unsigned *reg_safe_bm;
1363 unsigned reg_safe_bm_size;
1364 u32 resync_scratch;
1365 u32 hdp_cntl;
1366 };
1367
1368 struct r600_asic {
1369 unsigned max_pipes;
1370 unsigned max_tile_pipes;
1371 unsigned max_simds;
1372 unsigned max_backends;
1373 unsigned max_gprs;
1374 unsigned max_threads;
1375 unsigned max_stack_entries;
1376 unsigned max_hw_contexts;
1377 unsigned max_gs_threads;
1378 unsigned sx_max_export_size;
1379 unsigned sx_max_export_pos_size;
1380 unsigned sx_max_export_smx_size;
1381 unsigned sq_num_cf_insts;
1382 unsigned tiling_nbanks;
1383 unsigned tiling_npipes;
1384 unsigned tiling_group_size;
1385 unsigned tile_config;
1386 unsigned backend_map;
1387 };
1388
1389 struct rv770_asic {
1390 unsigned max_pipes;
1391 unsigned max_tile_pipes;
1392 unsigned max_simds;
1393 unsigned max_backends;
1394 unsigned max_gprs;
1395 unsigned max_threads;
1396 unsigned max_stack_entries;
1397 unsigned max_hw_contexts;
1398 unsigned max_gs_threads;
1399 unsigned sx_max_export_size;
1400 unsigned sx_max_export_pos_size;
1401 unsigned sx_max_export_smx_size;
1402 unsigned sq_num_cf_insts;
1403 unsigned sx_num_of_sets;
1404 unsigned sc_prim_fifo_size;
1405 unsigned sc_hiz_tile_fifo_size;
1406 unsigned sc_earlyz_tile_fifo_fize;
1407 unsigned tiling_nbanks;
1408 unsigned tiling_npipes;
1409 unsigned tiling_group_size;
1410 unsigned tile_config;
1411 unsigned backend_map;
1412 };
1413
1414 struct evergreen_asic {
1415 unsigned num_ses;
1416 unsigned max_pipes;
1417 unsigned max_tile_pipes;
1418 unsigned max_simds;
1419 unsigned max_backends;
1420 unsigned max_gprs;
1421 unsigned max_threads;
1422 unsigned max_stack_entries;
1423 unsigned max_hw_contexts;
1424 unsigned max_gs_threads;
1425 unsigned sx_max_export_size;
1426 unsigned sx_max_export_pos_size;
1427 unsigned sx_max_export_smx_size;
1428 unsigned sq_num_cf_insts;
1429 unsigned sx_num_of_sets;
1430 unsigned sc_prim_fifo_size;
1431 unsigned sc_hiz_tile_fifo_size;
1432 unsigned sc_earlyz_tile_fifo_size;
1433 unsigned tiling_nbanks;
1434 unsigned tiling_npipes;
1435 unsigned tiling_group_size;
1436 unsigned tile_config;
1437 unsigned backend_map;
1438 };
1439
1440 struct cayman_asic {
1441 unsigned max_shader_engines;
1442 unsigned max_pipes_per_simd;
1443 unsigned max_tile_pipes;
1444 unsigned max_simds_per_se;
1445 unsigned max_backends_per_se;
1446 unsigned max_texture_channel_caches;
1447 unsigned max_gprs;
1448 unsigned max_threads;
1449 unsigned max_gs_threads;
1450 unsigned max_stack_entries;
1451 unsigned sx_num_of_sets;
1452 unsigned sx_max_export_size;
1453 unsigned sx_max_export_pos_size;
1454 unsigned sx_max_export_smx_size;
1455 unsigned max_hw_contexts;
1456 unsigned sq_num_cf_insts;
1457 unsigned sc_prim_fifo_size;
1458 unsigned sc_hiz_tile_fifo_size;
1459 unsigned sc_earlyz_tile_fifo_size;
1460
1461 unsigned num_shader_engines;
1462 unsigned num_shader_pipes_per_simd;
1463 unsigned num_tile_pipes;
1464 unsigned num_simds_per_se;
1465 unsigned num_backends_per_se;
1466 unsigned backend_disable_mask_per_asic;
1467 unsigned backend_map;
1468 unsigned num_texture_channel_caches;
1469 unsigned mem_max_burst_length_bytes;
1470 unsigned mem_row_size_in_kb;
1471 unsigned shader_engine_tile_size;
1472 unsigned num_gpus;
1473 unsigned multi_gpu_tile_size;
1474
1475 unsigned tile_config;
1476 };
1477
1478 struct si_asic {
1479 unsigned max_shader_engines;
1480 unsigned max_tile_pipes;
1481 unsigned max_cu_per_sh;
1482 unsigned max_sh_per_se;
1483 unsigned max_backends_per_se;
1484 unsigned max_texture_channel_caches;
1485 unsigned max_gprs;
1486 unsigned max_gs_threads;
1487 unsigned max_hw_contexts;
1488 unsigned sc_prim_fifo_size_frontend;
1489 unsigned sc_prim_fifo_size_backend;
1490 unsigned sc_hiz_tile_fifo_size;
1491 unsigned sc_earlyz_tile_fifo_size;
1492
1493 unsigned num_tile_pipes;
1494 unsigned num_backends_per_se;
1495 unsigned backend_disable_mask_per_asic;
1496 unsigned backend_map;
1497 unsigned num_texture_channel_caches;
1498 unsigned mem_max_burst_length_bytes;
1499 unsigned mem_row_size_in_kb;
1500 unsigned shader_engine_tile_size;
1501 unsigned num_gpus;
1502 unsigned multi_gpu_tile_size;
1503
1504 unsigned tile_config;
1505 uint32_t tile_mode_array[32];
1506 };
1507
1508 union radeon_asic_config {
1509 struct r300_asic r300;
1510 struct r100_asic r100;
1511 struct r600_asic r600;
1512 struct rv770_asic rv770;
1513 struct evergreen_asic evergreen;
1514 struct cayman_asic cayman;
1515 struct si_asic si;
1516 };
1517
1518 /*
1519 * asic initizalization from radeon_asic.c
1520 */
1521 void radeon_agp_disable(struct radeon_device *rdev);
1522 int radeon_asic_init(struct radeon_device *rdev);
1523
1524
1525 /*
1526 * IOCTL.
1527 */
1528 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1529 struct drm_file *filp);
1530 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1531 struct drm_file *filp);
1532 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1533 struct drm_file *file_priv);
1534 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1535 struct drm_file *file_priv);
1536 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1537 struct drm_file *file_priv);
1538 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1539 struct drm_file *file_priv);
1540 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1541 struct drm_file *filp);
1542 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1543 struct drm_file *filp);
1544 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1545 struct drm_file *filp);
1546 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1547 struct drm_file *filp);
1548 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1549 struct drm_file *filp);
1550 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1551 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1552 struct drm_file *filp);
1553 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1554 struct drm_file *filp);
1555
1556 /* VRAM scratch page for HDP bug, default vram page */
1557 struct r600_vram_scratch {
1558 struct radeon_bo *robj;
1559 volatile uint32_t *ptr;
1560 u64 gpu_addr;
1561 };
1562
1563 /*
1564 * ACPI
1565 */
1566 struct radeon_atif_notification_cfg {
1567 bool enabled;
1568 int command_code;
1569 };
1570
1571 struct radeon_atif_notifications {
1572 bool display_switch;
1573 bool expansion_mode_change;
1574 bool thermal_state;
1575 bool forced_power_state;
1576 bool system_power_state;
1577 bool display_conf_change;
1578 bool px_gfx_switch;
1579 bool brightness_change;
1580 bool dgpu_display_event;
1581 };
1582
1583 struct radeon_atif_functions {
1584 bool system_params;
1585 bool sbios_requests;
1586 bool select_active_disp;
1587 bool lid_state;
1588 bool get_tv_standard;
1589 bool set_tv_standard;
1590 bool get_panel_expansion_mode;
1591 bool set_panel_expansion_mode;
1592 bool temperature_change;
1593 bool graphics_device_types;
1594 };
1595
1596 struct radeon_atif {
1597 struct radeon_atif_notifications notifications;
1598 struct radeon_atif_functions functions;
1599 struct radeon_atif_notification_cfg notification_cfg;
1600 struct radeon_encoder *encoder_for_bl;
1601 };
1602
1603 struct radeon_atcs_functions {
1604 bool get_ext_state;
1605 bool pcie_perf_req;
1606 bool pcie_dev_rdy;
1607 bool pcie_bus_width;
1608 };
1609
1610 struct radeon_atcs {
1611 struct radeon_atcs_functions functions;
1612 };
1613
1614 /*
1615 * Core structure, functions and helpers.
1616 */
1617 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1618 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1619
1620 struct radeon_device {
1621 struct device *dev;
1622 struct drm_device *ddev;
1623 struct pci_dev *pdev;
1624 struct rw_semaphore exclusive_lock;
1625 /* ASIC */
1626 union radeon_asic_config config;
1627 enum radeon_family family;
1628 unsigned long flags;
1629 int usec_timeout;
1630 enum radeon_pll_errata pll_errata;
1631 int num_gb_pipes;
1632 int num_z_pipes;
1633 int disp_priority;
1634 /* BIOS */
1635 uint8_t *bios;
1636 bool is_atom_bios;
1637 uint16_t bios_header_start;
1638 struct radeon_bo *stollen_vga_memory;
1639 /* Register mmio */
1640 resource_size_t rmmio_base;
1641 resource_size_t rmmio_size;
1642 /* protects concurrent MM_INDEX/DATA based register access */
1643 spinlock_t mmio_idx_lock;
1644 void __iomem *rmmio;
1645 radeon_rreg_t mc_rreg;
1646 radeon_wreg_t mc_wreg;
1647 radeon_rreg_t pll_rreg;
1648 radeon_wreg_t pll_wreg;
1649 uint32_t pcie_reg_mask;
1650 radeon_rreg_t pciep_rreg;
1651 radeon_wreg_t pciep_wreg;
1652 /* io port */
1653 void __iomem *rio_mem;
1654 resource_size_t rio_mem_size;
1655 struct radeon_clock clock;
1656 struct radeon_mc mc;
1657 struct radeon_gart gart;
1658 struct radeon_mode_info mode_info;
1659 struct radeon_scratch scratch;
1660 struct radeon_mman mman;
1661 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1662 wait_queue_head_t fence_queue;
1663 struct mutex ring_lock;
1664 struct radeon_ring ring[RADEON_NUM_RINGS];
1665 bool ib_pool_ready;
1666 struct radeon_sa_manager ring_tmp_bo;
1667 struct radeon_irq irq;
1668 struct radeon_asic *asic;
1669 struct radeon_gem gem;
1670 struct radeon_pm pm;
1671 struct radeon_uvd uvd;
1672 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1673 struct radeon_wb wb;
1674 struct radeon_dummy_page dummy_page;
1675 bool shutdown;
1676 bool suspend;
1677 bool need_dma32;
1678 bool accel_working;
1679 bool fastfb_working; /* IGP feature*/
1680 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1681 const struct firmware *me_fw; /* all family ME firmware */
1682 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1683 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1684 const struct firmware *mc_fw; /* NI MC firmware */
1685 const struct firmware *ce_fw; /* SI CE firmware */
1686 const struct firmware *uvd_fw; /* UVD firmware */
1687 struct r600_blit r600_blit;
1688 struct r600_vram_scratch vram_scratch;
1689 int msi_enabled; /* msi enabled */
1690 struct r600_ih ih; /* r6/700 interrupt ring */
1691 struct si_rlc rlc;
1692 struct work_struct hotplug_work;
1693 struct work_struct audio_work;
1694 int num_crtc; /* number of crtcs */
1695 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1696 bool audio_enabled;
1697 struct r600_audio audio_status; /* audio stuff */
1698 struct notifier_block acpi_nb;
1699 /* only one userspace can use Hyperz features or CMASK at a time */
1700 struct drm_file *hyperz_filp;
1701 struct drm_file *cmask_filp;
1702 /* i2c buses */
1703 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1704 /* debugfs */
1705 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1706 unsigned debugfs_count;
1707 /* virtual memory */
1708 struct radeon_vm_manager vm_manager;
1709 struct mutex gpu_clock_mutex;
1710 /* ACPI interface */
1711 struct radeon_atif atif;
1712 struct radeon_atcs atcs;
1713 };
1714
1715 int radeon_device_init(struct radeon_device *rdev,
1716 struct drm_device *ddev,
1717 struct pci_dev *pdev,
1718 uint32_t flags);
1719 void radeon_device_fini(struct radeon_device *rdev);
1720 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1721
1722 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1723 bool always_indirect);
1724 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1725 bool always_indirect);
1726 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1727 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1728
1729 /*
1730 * Cast helper
1731 */
1732 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1733
1734 /*
1735 * Registers read & write functions.
1736 */
1737 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1738 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1739 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1740 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1741 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1742 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1743 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1744 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1745 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1746 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1747 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1748 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1749 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1750 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1751 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1752 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1753 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1754 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1755 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1756 #define WREG32_P(reg, val, mask) \
1757 do { \
1758 uint32_t tmp_ = RREG32(reg); \
1759 tmp_ &= (mask); \
1760 tmp_ |= ((val) & ~(mask)); \
1761 WREG32(reg, tmp_); \
1762 } while (0)
1763 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1764 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
1765 #define WREG32_PLL_P(reg, val, mask) \
1766 do { \
1767 uint32_t tmp_ = RREG32_PLL(reg); \
1768 tmp_ &= (mask); \
1769 tmp_ |= ((val) & ~(mask)); \
1770 WREG32_PLL(reg, tmp_); \
1771 } while (0)
1772 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1773 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1774 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1775
1776 /*
1777 * Indirect registers accessor
1778 */
1779 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1780 {
1781 uint32_t r;
1782
1783 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1784 r = RREG32(RADEON_PCIE_DATA);
1785 return r;
1786 }
1787
1788 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1789 {
1790 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1791 WREG32(RADEON_PCIE_DATA, (v));
1792 }
1793
1794 void r100_pll_errata_after_index(struct radeon_device *rdev);
1795
1796
1797 /*
1798 * ASICs helpers.
1799 */
1800 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1801 (rdev->pdev->device == 0x5969))
1802 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1803 (rdev->family == CHIP_RV200) || \
1804 (rdev->family == CHIP_RS100) || \
1805 (rdev->family == CHIP_RS200) || \
1806 (rdev->family == CHIP_RV250) || \
1807 (rdev->family == CHIP_RV280) || \
1808 (rdev->family == CHIP_RS300))
1809 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1810 (rdev->family == CHIP_RV350) || \
1811 (rdev->family == CHIP_R350) || \
1812 (rdev->family == CHIP_RV380) || \
1813 (rdev->family == CHIP_R420) || \
1814 (rdev->family == CHIP_R423) || \
1815 (rdev->family == CHIP_RV410) || \
1816 (rdev->family == CHIP_RS400) || \
1817 (rdev->family == CHIP_RS480))
1818 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1819 (rdev->ddev->pdev->device == 0x9443) || \
1820 (rdev->ddev->pdev->device == 0x944B) || \
1821 (rdev->ddev->pdev->device == 0x9506) || \
1822 (rdev->ddev->pdev->device == 0x9509) || \
1823 (rdev->ddev->pdev->device == 0x950F) || \
1824 (rdev->ddev->pdev->device == 0x689C) || \
1825 (rdev->ddev->pdev->device == 0x689D))
1826 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1827 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1828 (rdev->family == CHIP_RS690) || \
1829 (rdev->family == CHIP_RS740) || \
1830 (rdev->family >= CHIP_R600))
1831 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1832 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1833 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1834 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1835 (rdev->flags & RADEON_IS_IGP))
1836 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1837 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1838 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1839 (rdev->flags & RADEON_IS_IGP))
1840 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1841
1842 /*
1843 * BIOS helpers.
1844 */
1845 #define RBIOS8(i) (rdev->bios[i])
1846 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1847 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1848
1849 int radeon_combios_init(struct radeon_device *rdev);
1850 void radeon_combios_fini(struct radeon_device *rdev);
1851 int radeon_atombios_init(struct radeon_device *rdev);
1852 void radeon_atombios_fini(struct radeon_device *rdev);
1853
1854
1855 /*
1856 * RING helpers.
1857 */
1858 #if DRM_DEBUG_CODE == 0
1859 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1860 {
1861 ring->ring[ring->wptr++] = v;
1862 ring->wptr &= ring->ptr_mask;
1863 ring->count_dw--;
1864 ring->ring_free_dw--;
1865 }
1866 #else
1867 /* With debugging this is just too big to inline */
1868 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1869 #endif
1870
1871 /*
1872 * ASICs macro.
1873 */
1874 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1875 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1876 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1877 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1878 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1879 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1880 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1881 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1882 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1883 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1884 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1885 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
1886 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1887 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1888 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1889 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1890 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1891 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1892 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1893 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1894 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1895 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1896 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1897 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1898 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
1899 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
1900 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1901 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1902 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1903 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1904 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1905 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1906 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1907 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1908 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1909 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1910 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1911 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1912 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1913 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1914 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1915 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
1916 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1917 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1918 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1919 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1920 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1921 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1922 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1923 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1924 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1925 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1926 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1927 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1928 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1929 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1930 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1931 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1932 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1933 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1934 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
1935 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
1936
1937 /* Common functions */
1938 /* AGP */
1939 extern int radeon_gpu_reset(struct radeon_device *rdev);
1940 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1941 extern void radeon_agp_disable(struct radeon_device *rdev);
1942 extern int radeon_modeset_init(struct radeon_device *rdev);
1943 extern void radeon_modeset_fini(struct radeon_device *rdev);
1944 extern bool radeon_card_posted(struct radeon_device *rdev);
1945 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1946 extern void radeon_update_display_priority(struct radeon_device *rdev);
1947 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1948 extern void radeon_scratch_init(struct radeon_device *rdev);
1949 extern void radeon_wb_fini(struct radeon_device *rdev);
1950 extern int radeon_wb_init(struct radeon_device *rdev);
1951 extern void radeon_wb_disable(struct radeon_device *rdev);
1952 extern void radeon_surface_init(struct radeon_device *rdev);
1953 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1954 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1955 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1956 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1957 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1958 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1959 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1960 extern int radeon_resume_kms(struct drm_device *dev);
1961 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1962 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1963 extern void radeon_program_register_sequence(struct radeon_device *rdev,
1964 const u32 *registers,
1965 const u32 array_size);
1966
1967 /*
1968 * vm
1969 */
1970 int radeon_vm_manager_init(struct radeon_device *rdev);
1971 void radeon_vm_manager_fini(struct radeon_device *rdev);
1972 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1973 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1974 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1975 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1976 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1977 struct radeon_vm *vm, int ring);
1978 void radeon_vm_fence(struct radeon_device *rdev,
1979 struct radeon_vm *vm,
1980 struct radeon_fence *fence);
1981 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1982 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1983 struct radeon_vm *vm,
1984 struct radeon_bo *bo,
1985 struct ttm_mem_reg *mem);
1986 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1987 struct radeon_bo *bo);
1988 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1989 struct radeon_bo *bo);
1990 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1991 struct radeon_vm *vm,
1992 struct radeon_bo *bo);
1993 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1994 struct radeon_bo_va *bo_va,
1995 uint64_t offset,
1996 uint32_t flags);
1997 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1998 struct radeon_bo_va *bo_va);
1999
2000 /* audio */
2001 void r600_audio_update_hdmi(struct work_struct *work);
2002
2003 /*
2004 * R600 vram scratch functions
2005 */
2006 int r600_vram_scratch_init(struct radeon_device *rdev);
2007 void r600_vram_scratch_fini(struct radeon_device *rdev);
2008
2009 /*
2010 * r600 cs checking helper
2011 */
2012 unsigned r600_mip_minify(unsigned size, unsigned level);
2013 bool r600_fmt_is_valid_color(u32 format);
2014 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2015 int r600_fmt_get_blocksize(u32 format);
2016 int r600_fmt_get_nblocksx(u32 format, u32 w);
2017 int r600_fmt_get_nblocksy(u32 format, u32 h);
2018
2019 /*
2020 * r600 functions used by radeon_encoder.c
2021 */
2022 struct radeon_hdmi_acr {
2023 u32 clock;
2024
2025 int n_32khz;
2026 int cts_32khz;
2027
2028 int n_44_1khz;
2029 int cts_44_1khz;
2030
2031 int n_48khz;
2032 int cts_48khz;
2033
2034 };
2035
2036 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2037
2038 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2039 u32 tiling_pipe_num,
2040 u32 max_rb_num,
2041 u32 total_max_rb_num,
2042 u32 enabled_rb_mask);
2043
2044 /*
2045 * evergreen functions used by radeon_encoder.c
2046 */
2047
2048 extern int ni_init_microcode(struct radeon_device *rdev);
2049 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2050
2051 /* radeon_acpi.c */
2052 #if defined(CONFIG_ACPI)
2053 extern int radeon_acpi_init(struct radeon_device *rdev);
2054 extern void radeon_acpi_fini(struct radeon_device *rdev);
2055 #else
2056 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2057 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2058 #endif
2059
2060 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2061 struct radeon_cs_packet *pkt,
2062 unsigned idx);
2063 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2064 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2065 struct radeon_cs_packet *pkt);
2066 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2067 struct radeon_cs_reloc **cs_reloc,
2068 int nomm);
2069 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2070 uint32_t *vline_start_end,
2071 uint32_t *vline_status);
2072
2073 #include "radeon_object.h"
2074
2075 #endif
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