2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb
;
82 extern int radeon_modeset
;
83 extern int radeon_dynclks
;
84 extern int radeon_r4xx_atom
;
85 extern int radeon_agpmode
;
86 extern int radeon_vram_limit
;
87 extern int radeon_gart_size
;
88 extern int radeon_benchmarking
;
89 extern int radeon_testing
;
90 extern int radeon_connector_table
;
92 extern int radeon_audio
;
93 extern int radeon_disp_priority
;
94 extern int radeon_hw_i2c
;
95 extern int radeon_pcie_gen2
;
96 extern int radeon_msi
;
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
110 /* max number of rings */
111 #define RADEON_NUM_RINGS 3
113 /* internal ring indices */
114 /* r1xx+ has gfx CP ring */
115 #define RADEON_RING_TYPE_GFX_INDEX 0
117 /* cayman has 2 compute CP rings */
118 #define CAYMAN_RING_TYPE_CP1_INDEX 1
119 #define CAYMAN_RING_TYPE_CP2_INDEX 2
121 /* hardcode those limit for now */
122 #define RADEON_VA_RESERVED_SIZE (8 << 20)
123 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
126 * Errata workarounds.
128 enum radeon_pll_errata
{
129 CHIP_ERRATA_R300_CG
= 0x00000001,
130 CHIP_ERRATA_PLL_DUMMYREADS
= 0x00000002,
131 CHIP_ERRATA_PLL_DELAY
= 0x00000004
135 struct radeon_device
;
141 #define ATRM_BIOS_PAGE 4096
143 #if defined(CONFIG_VGA_SWITCHEROO)
144 bool radeon_atrm_supported(struct pci_dev
*pdev
);
145 int radeon_atrm_get_bios_chunk(uint8_t *bios
, int offset
, int len
);
147 static inline bool radeon_atrm_supported(struct pci_dev
*pdev
)
152 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios
, int offset
, int len
){
156 bool radeon_get_bios(struct radeon_device
*rdev
);
160 * Mutex which allows recursive locking from the same process.
162 struct radeon_mutex
{
164 struct task_struct
*owner
;
168 static inline void radeon_mutex_init(struct radeon_mutex
*mutex
)
170 mutex_init(&mutex
->mutex
);
175 static inline void radeon_mutex_lock(struct radeon_mutex
*mutex
)
177 if (mutex_trylock(&mutex
->mutex
)) {
178 /* The mutex was unlocked before, so it's ours now */
179 mutex
->owner
= current
;
180 } else if (mutex
->owner
!= current
) {
181 /* Another process locked the mutex, take it */
182 mutex_lock(&mutex
->mutex
);
183 mutex
->owner
= current
;
185 /* Otherwise the mutex was already locked by this process */
190 static inline void radeon_mutex_unlock(struct radeon_mutex
*mutex
)
192 if (--mutex
->level
> 0)
196 mutex_unlock(&mutex
->mutex
);
203 struct radeon_dummy_page
{
207 int radeon_dummy_page_init(struct radeon_device
*rdev
);
208 void radeon_dummy_page_fini(struct radeon_device
*rdev
);
214 struct radeon_clock
{
215 struct radeon_pll p1pll
;
216 struct radeon_pll p2pll
;
217 struct radeon_pll dcpll
;
218 struct radeon_pll spll
;
219 struct radeon_pll mpll
;
221 uint32_t default_mclk
;
222 uint32_t default_sclk
;
223 uint32_t default_dispclk
;
225 uint32_t max_pixel_clock
;
231 int radeon_pm_init(struct radeon_device
*rdev
);
232 void radeon_pm_fini(struct radeon_device
*rdev
);
233 void radeon_pm_compute_clocks(struct radeon_device
*rdev
);
234 void radeon_pm_suspend(struct radeon_device
*rdev
);
235 void radeon_pm_resume(struct radeon_device
*rdev
);
236 void radeon_combios_get_power_modes(struct radeon_device
*rdev
);
237 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
);
238 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 voltage_level
, u8 voltage_type
);
239 int radeon_atom_get_max_vddc(struct radeon_device
*rdev
, u16
*voltage
);
240 void rs690_pm_info(struct radeon_device
*rdev
);
241 extern int rv6xx_get_temp(struct radeon_device
*rdev
);
242 extern int rv770_get_temp(struct radeon_device
*rdev
);
243 extern int evergreen_get_temp(struct radeon_device
*rdev
);
244 extern int sumo_get_temp(struct radeon_device
*rdev
);
245 extern void evergreen_tiling_fields(unsigned tiling_flags
, unsigned *bankw
,
246 unsigned *bankh
, unsigned *mtaspect
,
247 unsigned *tile_split
);
252 struct radeon_fence_driver
{
253 uint32_t scratch_reg
;
255 volatile uint32_t *cpu_addr
;
258 unsigned long last_jiffies
;
259 unsigned long last_timeout
;
260 wait_queue_head_t queue
;
261 struct list_head created
;
262 struct list_head emitted
;
263 struct list_head signaled
;
267 struct radeon_fence
{
268 struct radeon_device
*rdev
;
270 struct list_head list
;
271 /* protected by radeon_fence.lock */
277 struct radeon_semaphore
*semaphore
;
280 int radeon_fence_driver_start_ring(struct radeon_device
*rdev
, int ring
);
281 int radeon_fence_driver_init(struct radeon_device
*rdev
);
282 void radeon_fence_driver_fini(struct radeon_device
*rdev
);
283 int radeon_fence_create(struct radeon_device
*rdev
, struct radeon_fence
**fence
, int ring
);
284 int radeon_fence_emit(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
285 void radeon_fence_process(struct radeon_device
*rdev
, int ring
);
286 bool radeon_fence_signaled(struct radeon_fence
*fence
);
287 int radeon_fence_wait(struct radeon_fence
*fence
, bool interruptible
);
288 int radeon_fence_wait_next(struct radeon_device
*rdev
, int ring
);
289 int radeon_fence_wait_last(struct radeon_device
*rdev
, int ring
);
290 struct radeon_fence
*radeon_fence_ref(struct radeon_fence
*fence
);
291 void radeon_fence_unref(struct radeon_fence
**fence
);
292 int radeon_fence_count_emitted(struct radeon_device
*rdev
, int ring
);
297 struct radeon_surface_reg
{
298 struct radeon_bo
*bo
;
301 #define RADEON_GEM_MAX_SURFACES 8
307 struct ttm_bo_global_ref bo_global_ref
;
308 struct drm_global_reference mem_global_ref
;
309 struct ttm_bo_device bdev
;
310 bool mem_global_referenced
;
314 /* bo virtual address in a specific vm */
315 struct radeon_bo_va
{
316 /* bo list is protected by bo being reserved */
317 struct list_head bo_list
;
318 /* vm list is protected by vm mutex */
319 struct list_head vm_list
;
320 /* constant after initialization */
321 struct radeon_vm
*vm
;
322 struct radeon_bo
*bo
;
330 /* Protected by gem.mutex */
331 struct list_head list
;
332 /* Protected by tbo.reserved */
334 struct ttm_placement placement
;
335 struct ttm_buffer_object tbo
;
336 struct ttm_bo_kmap_obj kmap
;
342 /* list of all virtual address to which this bo
346 /* Constant after initialization */
347 struct radeon_device
*rdev
;
348 struct drm_gem_object gem_base
;
350 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
352 struct radeon_bo_list
{
353 struct ttm_validate_buffer tv
;
354 struct radeon_bo
*bo
;
361 /* sub-allocation manager, it has to be protected by another lock.
362 * By conception this is an helper for other part of the driver
363 * like the indirect buffer or semaphore, which both have their
366 * Principe is simple, we keep a list of sub allocation in offset
367 * order (first entry has offset == 0, last entry has the highest
370 * When allocating new object we first check if there is room at
371 * the end total_size - (last_object_offset + last_object_size) >=
372 * alloc_size. If so we allocate new object there.
374 * When there is not enough room at the end, we start waiting for
375 * each sub object until we reach object_offset+object_size >=
376 * alloc_size, this object then become the sub object we return.
378 * Alignment can't be bigger than page size.
380 * Hole are not considered for allocation to keep things simple.
381 * Assumption is that there won't be hole (all object on same
384 struct radeon_sa_manager
{
385 struct radeon_bo
*bo
;
386 struct list_head sa_bo
;
395 /* sub-allocation buffer */
396 struct radeon_sa_bo
{
397 struct list_head list
;
398 struct radeon_sa_manager
*manager
;
408 struct list_head objects
;
411 int radeon_gem_init(struct radeon_device
*rdev
);
412 void radeon_gem_fini(struct radeon_device
*rdev
);
413 int radeon_gem_object_create(struct radeon_device
*rdev
, int size
,
414 int alignment
, int initial_domain
,
415 bool discardable
, bool kernel
,
416 struct drm_gem_object
**obj
);
417 int radeon_gem_object_pin(struct drm_gem_object
*obj
, uint32_t pin_domain
,
419 void radeon_gem_object_unpin(struct drm_gem_object
*obj
);
421 int radeon_mode_dumb_create(struct drm_file
*file_priv
,
422 struct drm_device
*dev
,
423 struct drm_mode_create_dumb
*args
);
424 int radeon_mode_dumb_mmap(struct drm_file
*filp
,
425 struct drm_device
*dev
,
426 uint32_t handle
, uint64_t *offset_p
);
427 int radeon_mode_dumb_destroy(struct drm_file
*file_priv
,
428 struct drm_device
*dev
,
436 #define RADEON_SEMAPHORE_BO_SIZE 256
438 struct radeon_semaphore_driver
{
443 struct radeon_semaphore_bo
;
445 /* everything here is constant */
446 struct radeon_semaphore
{
447 struct list_head list
;
450 struct radeon_semaphore_bo
*bo
;
453 struct radeon_semaphore_bo
{
454 struct list_head list
;
455 struct radeon_ib
*ib
;
456 struct list_head free
;
457 struct radeon_semaphore semaphores
[RADEON_SEMAPHORE_BO_SIZE
/8];
461 void radeon_semaphore_driver_fini(struct radeon_device
*rdev
);
462 int radeon_semaphore_create(struct radeon_device
*rdev
,
463 struct radeon_semaphore
**semaphore
);
464 void radeon_semaphore_emit_signal(struct radeon_device
*rdev
, int ring
,
465 struct radeon_semaphore
*semaphore
);
466 void radeon_semaphore_emit_wait(struct radeon_device
*rdev
, int ring
,
467 struct radeon_semaphore
*semaphore
);
468 void radeon_semaphore_free(struct radeon_device
*rdev
,
469 struct radeon_semaphore
*semaphore
);
472 * GART structures, functions & helpers
476 #define RADEON_GPU_PAGE_SIZE 4096
477 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
478 #define RADEON_GPU_PAGE_SHIFT 12
479 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
482 dma_addr_t table_addr
;
483 struct radeon_bo
*robj
;
485 unsigned num_gpu_pages
;
486 unsigned num_cpu_pages
;
489 dma_addr_t
*pages_addr
;
493 int radeon_gart_table_ram_alloc(struct radeon_device
*rdev
);
494 void radeon_gart_table_ram_free(struct radeon_device
*rdev
);
495 int radeon_gart_table_vram_alloc(struct radeon_device
*rdev
);
496 void radeon_gart_table_vram_free(struct radeon_device
*rdev
);
497 int radeon_gart_table_vram_pin(struct radeon_device
*rdev
);
498 void radeon_gart_table_vram_unpin(struct radeon_device
*rdev
);
499 int radeon_gart_init(struct radeon_device
*rdev
);
500 void radeon_gart_fini(struct radeon_device
*rdev
);
501 void radeon_gart_unbind(struct radeon_device
*rdev
, unsigned offset
,
503 int radeon_gart_bind(struct radeon_device
*rdev
, unsigned offset
,
504 int pages
, struct page
**pagelist
,
505 dma_addr_t
*dma_addr
);
506 void radeon_gart_restore(struct radeon_device
*rdev
);
510 * GPU MC structures, functions & helpers
513 resource_size_t aper_size
;
514 resource_size_t aper_base
;
515 resource_size_t agp_base
;
516 /* for some chips with <= 32MB we need to lie
517 * about vram size near mc fb location */
519 u64 visible_vram_size
;
529 bool igp_sideport_enabled
;
533 bool radeon_combios_sideport_present(struct radeon_device
*rdev
);
534 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
);
537 * GPU scratch registers structures, functions & helpers
539 struct radeon_scratch
{
546 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
);
547 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
);
554 struct radeon_unpin_work
{
555 struct work_struct work
;
556 struct radeon_device
*rdev
;
558 struct radeon_fence
*fence
;
559 struct drm_pending_vblank_event
*event
;
560 struct radeon_bo
*old_rbo
;
564 struct r500_irq_stat_regs
{
568 struct r600_irq_stat_regs
{
576 struct evergreen_irq_stat_regs
{
591 union radeon_irq_stat_regs
{
592 struct r500_irq_stat_regs r500
;
593 struct r600_irq_stat_regs r600
;
594 struct evergreen_irq_stat_regs evergreen
;
597 #define RADEON_MAX_HPD_PINS 6
598 #define RADEON_MAX_CRTCS 6
599 #define RADEON_MAX_HDMI_BLOCKS 2
603 bool sw_int
[RADEON_NUM_RINGS
];
604 bool crtc_vblank_int
[RADEON_MAX_CRTCS
];
605 bool pflip
[RADEON_MAX_CRTCS
];
606 wait_queue_head_t vblank_queue
;
607 bool hpd
[RADEON_MAX_HPD_PINS
];
610 wait_queue_head_t idle_queue
;
611 bool hdmi
[RADEON_MAX_HDMI_BLOCKS
];
613 int sw_refcount
[RADEON_NUM_RINGS
];
614 union radeon_irq_stat_regs stat_regs
;
615 spinlock_t pflip_lock
[RADEON_MAX_CRTCS
];
616 int pflip_refcount
[RADEON_MAX_CRTCS
];
619 int radeon_irq_kms_init(struct radeon_device
*rdev
);
620 void radeon_irq_kms_fini(struct radeon_device
*rdev
);
621 void radeon_irq_kms_sw_irq_get(struct radeon_device
*rdev
, int ring
);
622 void radeon_irq_kms_sw_irq_put(struct radeon_device
*rdev
, int ring
);
623 void radeon_irq_kms_pflip_irq_get(struct radeon_device
*rdev
, int crtc
);
624 void radeon_irq_kms_pflip_irq_put(struct radeon_device
*rdev
, int crtc
);
631 struct radeon_sa_bo sa_bo
;
636 struct radeon_fence
*fence
;
642 * mutex protects scheduled_ibs, ready, alloc_bm
644 struct radeon_ib_pool
{
645 struct radeon_mutex mutex
;
646 struct radeon_sa_manager sa_manager
;
647 struct radeon_ib ibs
[RADEON_IB_POOL_SIZE
];
653 struct radeon_bo
*ring_obj
;
654 volatile uint32_t *ring
;
662 unsigned ring_free_dw
;
678 struct list_head list
;
684 struct radeon_sa_bo sa_bo
;
686 /* last fence for cs using this vm */
687 struct radeon_fence
*fence
;
690 struct radeon_vm_funcs
{
691 int (*init
)(struct radeon_device
*rdev
);
692 void (*fini
)(struct radeon_device
*rdev
);
693 /* cs mutex must be lock for schedule_ib */
694 int (*bind
)(struct radeon_device
*rdev
, struct radeon_vm
*vm
, int id
);
695 void (*unbind
)(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
696 void (*tlb_flush
)(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
697 uint32_t (*page_flags
)(struct radeon_device
*rdev
,
698 struct radeon_vm
*vm
,
700 void (*set_page
)(struct radeon_device
*rdev
, struct radeon_vm
*vm
,
701 unsigned pfn
, uint64_t addr
, uint32_t flags
);
704 struct radeon_vm_manager
{
705 struct list_head lru_vm
;
707 struct radeon_sa_manager sa_manager
;
709 /* fields constant after init */
710 const struct radeon_vm_funcs
*funcs
;
711 /* number of VMIDs */
713 /* vram base address for page table entry */
714 u64 vram_base_offset
;
720 * file private structure
722 struct radeon_fpriv
{
730 struct radeon_bo
*ring_obj
;
731 volatile uint32_t *ring
;
743 struct r600_blit_cp_primitives
{
744 void (*set_render_target
)(struct radeon_device
*rdev
, int format
,
745 int w
, int h
, u64 gpu_addr
);
746 void (*cp_set_surface_sync
)(struct radeon_device
*rdev
,
747 u32 sync_type
, u32 size
,
749 void (*set_shaders
)(struct radeon_device
*rdev
);
750 void (*set_vtx_resource
)(struct radeon_device
*rdev
, u64 gpu_addr
);
751 void (*set_tex_resource
)(struct radeon_device
*rdev
,
752 int format
, int w
, int h
, int pitch
,
753 u64 gpu_addr
, u32 size
);
754 void (*set_scissors
)(struct radeon_device
*rdev
, int x1
, int y1
,
756 void (*draw_auto
)(struct radeon_device
*rdev
);
757 void (*set_default_state
)(struct radeon_device
*rdev
);
762 struct radeon_bo
*shader_obj
;
763 struct r600_blit_cp_primitives primitives
;
765 int ring_size_common
;
766 int ring_size_per_loop
;
768 u32 vs_offset
, ps_offset
;
771 u32 vb_used
, vb_total
;
772 struct radeon_ib
*vb_ib
;
775 void r600_blit_suspend(struct radeon_device
*rdev
);
777 int radeon_ib_get(struct radeon_device
*rdev
, int ring
,
778 struct radeon_ib
**ib
, unsigned size
);
779 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
780 bool radeon_ib_try_free(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
781 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
782 int radeon_ib_pool_init(struct radeon_device
*rdev
);
783 void radeon_ib_pool_fini(struct radeon_device
*rdev
);
784 int radeon_ib_pool_start(struct radeon_device
*rdev
);
785 int radeon_ib_pool_suspend(struct radeon_device
*rdev
);
786 int radeon_ib_test(struct radeon_device
*rdev
);
787 /* Ring access between begin & end cannot sleep */
788 int radeon_ring_index(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
789 void radeon_ring_free_size(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
790 int radeon_ring_alloc(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ndw
);
791 int radeon_ring_lock(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ndw
);
792 void radeon_ring_commit(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
793 void radeon_ring_unlock_commit(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
794 void radeon_ring_unlock_undo(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
795 int radeon_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
796 int radeon_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ring_size
,
797 unsigned rptr_offs
, unsigned rptr_reg
, unsigned wptr_reg
,
798 u32 ptr_reg_shift
, u32 ptr_reg_mask
, u32 nop
);
799 void radeon_ring_fini(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
805 struct radeon_cs_reloc
{
806 struct drm_gem_object
*gobj
;
807 struct radeon_bo
*robj
;
808 struct radeon_bo_list lobj
;
813 struct radeon_cs_chunk
{
819 void __user
*user_ptr
;
820 int last_copied_page
;
824 struct radeon_cs_parser
{
826 struct radeon_device
*rdev
;
827 struct drm_file
*filp
;
830 struct radeon_cs_chunk
*chunks
;
831 uint64_t *chunks_array
;
836 struct radeon_cs_reloc
*relocs
;
837 struct radeon_cs_reloc
**relocs_ptr
;
838 struct list_head validated
;
839 /* indices of various chunks */
841 int chunk_relocs_idx
;
843 struct radeon_ib
*ib
;
852 extern int radeon_cs_update_pages(struct radeon_cs_parser
*p
, int pg_idx
);
853 extern int radeon_cs_finish_pages(struct radeon_cs_parser
*p
);
854 extern u32
radeon_get_ib_value(struct radeon_cs_parser
*p
, int idx
);
856 struct radeon_cs_packet
{
865 typedef int (*radeon_packet0_check_t
)(struct radeon_cs_parser
*p
,
866 struct radeon_cs_packet
*pkt
,
867 unsigned idx
, unsigned reg
);
868 typedef int (*radeon_packet3_check_t
)(struct radeon_cs_parser
*p
,
869 struct radeon_cs_packet
*pkt
);
875 int radeon_agp_init(struct radeon_device
*rdev
);
876 void radeon_agp_resume(struct radeon_device
*rdev
);
877 void radeon_agp_suspend(struct radeon_device
*rdev
);
878 void radeon_agp_fini(struct radeon_device
*rdev
);
885 struct radeon_bo
*wb_obj
;
886 volatile uint32_t *wb
;
892 #define RADEON_WB_SCRATCH_OFFSET 0
893 #define RADEON_WB_CP_RPTR_OFFSET 1024
894 #define RADEON_WB_CP1_RPTR_OFFSET 1280
895 #define RADEON_WB_CP2_RPTR_OFFSET 1536
896 #define R600_WB_IH_WPTR_OFFSET 2048
897 #define R600_WB_EVENT_OFFSET 3072
900 * struct radeon_pm - power management datas
901 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
902 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
903 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
904 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
905 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
906 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
907 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
908 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
909 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
910 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
911 * @needed_bandwidth: current bandwidth needs
913 * It keeps track of various data needed to take powermanagement decision.
914 * Bandwidth need is used to determine minimun clock of the GPU and memory.
915 * Equation between gpu/memory clock and available bandwidth is hw dependent
916 * (type of memory, bus size, efficiency, ...)
919 enum radeon_pm_method
{
924 enum radeon_dynpm_state
{
925 DYNPM_STATE_DISABLED
,
929 DYNPM_STATE_SUSPENDED
,
931 enum radeon_dynpm_action
{
933 DYNPM_ACTION_MINIMUM
,
934 DYNPM_ACTION_DOWNCLOCK
,
935 DYNPM_ACTION_UPCLOCK
,
939 enum radeon_voltage_type
{
946 enum radeon_pm_state_type
{
947 POWER_STATE_TYPE_DEFAULT
,
948 POWER_STATE_TYPE_POWERSAVE
,
949 POWER_STATE_TYPE_BATTERY
,
950 POWER_STATE_TYPE_BALANCED
,
951 POWER_STATE_TYPE_PERFORMANCE
,
954 enum radeon_pm_profile_type
{
962 #define PM_PROFILE_DEFAULT_IDX 0
963 #define PM_PROFILE_LOW_SH_IDX 1
964 #define PM_PROFILE_MID_SH_IDX 2
965 #define PM_PROFILE_HIGH_SH_IDX 3
966 #define PM_PROFILE_LOW_MH_IDX 4
967 #define PM_PROFILE_MID_MH_IDX 5
968 #define PM_PROFILE_HIGH_MH_IDX 6
969 #define PM_PROFILE_MAX 7
971 struct radeon_pm_profile
{
978 enum radeon_int_thermal_type
{
982 THERMAL_TYPE_EVERGREEN
,
987 struct radeon_voltage
{
988 enum radeon_voltage_type type
;
990 struct radeon_gpio_rec gpio
;
991 u32 delay
; /* delay in usec from voltage drop to sclk change */
992 bool active_high
; /* voltage drop is active when bit is high */
994 u8 vddc_id
; /* index into vddc voltage table */
995 u8 vddci_id
; /* index into vddci voltage table */
999 /* evergreen+ vddci */
1003 /* clock mode flags */
1004 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1006 struct radeon_pm_clock_info
{
1012 struct radeon_voltage voltage
;
1013 /* standardized clock flags */
1018 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1020 struct radeon_power_state
{
1021 enum radeon_pm_state_type type
;
1022 struct radeon_pm_clock_info
*clock_info
;
1023 /* number of valid clock modes in this power state */
1024 int num_clock_modes
;
1025 struct radeon_pm_clock_info
*default_clock_mode
;
1026 /* standardized state flags */
1028 u32 misc
; /* vbios specific flags */
1029 u32 misc2
; /* vbios specific flags */
1030 int pcie_lanes
; /* pcie lanes */
1034 * Some modes are overclocked by very low value, accept them
1036 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1041 int active_crtc_count
;
1045 fixed20_12 max_bandwidth
;
1046 fixed20_12 igp_sideport_mclk
;
1047 fixed20_12 igp_system_mclk
;
1048 fixed20_12 igp_ht_link_clk
;
1049 fixed20_12 igp_ht_link_width
;
1050 fixed20_12 k8_bandwidth
;
1051 fixed20_12 sideport_bandwidth
;
1052 fixed20_12 ht_bandwidth
;
1053 fixed20_12 core_bandwidth
;
1056 fixed20_12 needed_bandwidth
;
1057 struct radeon_power_state
*power_state
;
1058 /* number of valid power states */
1059 int num_power_states
;
1060 int current_power_state_index
;
1061 int current_clock_mode_index
;
1062 int requested_power_state_index
;
1063 int requested_clock_mode_index
;
1064 int default_power_state_index
;
1073 struct radeon_i2c_chan
*i2c_bus
;
1074 /* selected pm method */
1075 enum radeon_pm_method pm_method
;
1076 /* dynpm power management */
1077 struct delayed_work dynpm_idle_work
;
1078 enum radeon_dynpm_state dynpm_state
;
1079 enum radeon_dynpm_action dynpm_planned_action
;
1080 unsigned long dynpm_action_timeout
;
1081 bool dynpm_can_upclock
;
1082 bool dynpm_can_downclock
;
1083 /* profile-based power management */
1084 enum radeon_pm_profile_type profile
;
1086 struct radeon_pm_profile profiles
[PM_PROFILE_MAX
];
1087 /* internal thermal controller on rv6xx+ */
1088 enum radeon_int_thermal_type int_thermal_type
;
1089 struct device
*int_hwmon_dev
;
1092 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
1093 enum radeon_pm_state_type ps_type
,
1099 void radeon_benchmark(struct radeon_device
*rdev
, int test_number
);
1105 void radeon_test_moves(struct radeon_device
*rdev
);
1106 void radeon_test_ring_sync(struct radeon_device
*rdev
,
1107 struct radeon_ring
*cpA
,
1108 struct radeon_ring
*cpB
);
1109 void radeon_test_syncing(struct radeon_device
*rdev
);
1115 struct radeon_debugfs
{
1116 struct drm_info_list
*files
;
1120 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1121 struct drm_info_list
*files
,
1123 int radeon_debugfs_fence_init(struct radeon_device
*rdev
);
1127 * ASIC specific functions.
1129 struct radeon_asic
{
1130 int (*init
)(struct radeon_device
*rdev
);
1131 void (*fini
)(struct radeon_device
*rdev
);
1132 int (*resume
)(struct radeon_device
*rdev
);
1133 int (*suspend
)(struct radeon_device
*rdev
);
1134 void (*vga_set_state
)(struct radeon_device
*rdev
, bool state
);
1135 bool (*gpu_is_lockup
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
1136 int (*asic_reset
)(struct radeon_device
*rdev
);
1137 void (*gart_tlb_flush
)(struct radeon_device
*rdev
);
1138 int (*gart_set_page
)(struct radeon_device
*rdev
, int i
, uint64_t addr
);
1139 void (*ring_start
)(struct radeon_device
*rdev
);
1142 void (*ib_execute
)(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
1143 int (*ib_parse
)(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
1144 void (*emit_fence
)(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
1145 void (*emit_semaphore
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
,
1146 struct radeon_semaphore
*semaphore
, bool emit_wait
);
1147 int (*cs_parse
)(struct radeon_cs_parser
*p
);
1148 } ring
[RADEON_NUM_RINGS
];
1150 int (*ring_test
)(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
1153 int (*set
)(struct radeon_device
*rdev
);
1154 int (*process
)(struct radeon_device
*rdev
);
1157 u32 (*get_vblank_counter
)(struct radeon_device
*rdev
, int crtc
);
1160 int (*blit
)(struct radeon_device
*rdev
,
1161 uint64_t src_offset
,
1162 uint64_t dst_offset
,
1163 unsigned num_gpu_pages
,
1164 struct radeon_fence
*fence
);
1165 u32 blit_ring_index
;
1166 int (*dma
)(struct radeon_device
*rdev
,
1167 uint64_t src_offset
,
1168 uint64_t dst_offset
,
1169 unsigned num_gpu_pages
,
1170 struct radeon_fence
*fence
);
1172 /* method used for bo copy */
1173 int (*copy
)(struct radeon_device
*rdev
,
1174 uint64_t src_offset
,
1175 uint64_t dst_offset
,
1176 unsigned num_gpu_pages
,
1177 struct radeon_fence
*fence
);
1178 /* ring used for bo copies */
1179 u32 copy_ring_index
;
1182 uint32_t (*get_engine_clock
)(struct radeon_device
*rdev
);
1183 void (*set_engine_clock
)(struct radeon_device
*rdev
, uint32_t eng_clock
);
1184 uint32_t (*get_memory_clock
)(struct radeon_device
*rdev
);
1185 void (*set_memory_clock
)(struct radeon_device
*rdev
, uint32_t mem_clock
);
1186 int (*get_pcie_lanes
)(struct radeon_device
*rdev
);
1187 void (*set_pcie_lanes
)(struct radeon_device
*rdev
, int lanes
);
1188 void (*set_clock_gating
)(struct radeon_device
*rdev
, int enable
);
1189 int (*set_surface_reg
)(struct radeon_device
*rdev
, int reg
,
1190 uint32_t tiling_flags
, uint32_t pitch
,
1191 uint32_t offset
, uint32_t obj_size
);
1192 void (*clear_surface_reg
)(struct radeon_device
*rdev
, int reg
);
1193 void (*bandwidth_update
)(struct radeon_device
*rdev
);
1196 void (*init
)(struct radeon_device
*rdev
);
1197 void (*fini
)(struct radeon_device
*rdev
);
1198 bool (*sense
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
1199 void (*set_polarity
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
1202 /* ioctl hw specific callback. Some hw might want to perform special
1203 * operation on specific ioctl. For instance on wait idle some hw
1204 * might want to perform and HDP flush through MMIO as it seems that
1205 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1208 void (*ioctl_wait_idle
)(struct radeon_device
*rdev
, struct radeon_bo
*bo
);
1209 /* check if 3D engine is idle */
1210 bool (*gui_idle
)(struct radeon_device
*rdev
);
1211 /* power management */
1213 void (*misc
)(struct radeon_device
*rdev
);
1214 void (*prepare
)(struct radeon_device
*rdev
);
1215 void (*finish
)(struct radeon_device
*rdev
);
1216 void (*init_profile
)(struct radeon_device
*rdev
);
1217 void (*get_dynpm_state
)(struct radeon_device
*rdev
);
1221 void (*pre_page_flip
)(struct radeon_device
*rdev
, int crtc
);
1222 u32 (*page_flip
)(struct radeon_device
*rdev
, int crtc
, u64 crtc_base
);
1223 void (*post_page_flip
)(struct radeon_device
*rdev
, int crtc
);
1225 /* wait for vblank */
1226 void (*wait_for_vblank
)(struct radeon_device
*rdev
, int crtc
);
1227 /* wait for mc_idle */
1228 int (*mc_wait_for_idle
)(struct radeon_device
*rdev
);
1234 struct r100_gpu_lockup
{
1235 unsigned long last_jiffies
;
1240 const unsigned *reg_safe_bm
;
1241 unsigned reg_safe_bm_size
;
1243 struct r100_gpu_lockup lockup
;
1247 const unsigned *reg_safe_bm
;
1248 unsigned reg_safe_bm_size
;
1251 struct r100_gpu_lockup lockup
;
1256 unsigned max_tile_pipes
;
1258 unsigned max_backends
;
1260 unsigned max_threads
;
1261 unsigned max_stack_entries
;
1262 unsigned max_hw_contexts
;
1263 unsigned max_gs_threads
;
1264 unsigned sx_max_export_size
;
1265 unsigned sx_max_export_pos_size
;
1266 unsigned sx_max_export_smx_size
;
1267 unsigned sq_num_cf_insts
;
1268 unsigned tiling_nbanks
;
1269 unsigned tiling_npipes
;
1270 unsigned tiling_group_size
;
1271 unsigned tile_config
;
1272 unsigned backend_map
;
1273 struct r100_gpu_lockup lockup
;
1278 unsigned max_tile_pipes
;
1280 unsigned max_backends
;
1282 unsigned max_threads
;
1283 unsigned max_stack_entries
;
1284 unsigned max_hw_contexts
;
1285 unsigned max_gs_threads
;
1286 unsigned sx_max_export_size
;
1287 unsigned sx_max_export_pos_size
;
1288 unsigned sx_max_export_smx_size
;
1289 unsigned sq_num_cf_insts
;
1290 unsigned sx_num_of_sets
;
1291 unsigned sc_prim_fifo_size
;
1292 unsigned sc_hiz_tile_fifo_size
;
1293 unsigned sc_earlyz_tile_fifo_fize
;
1294 unsigned tiling_nbanks
;
1295 unsigned tiling_npipes
;
1296 unsigned tiling_group_size
;
1297 unsigned tile_config
;
1298 unsigned backend_map
;
1299 struct r100_gpu_lockup lockup
;
1302 struct evergreen_asic
{
1305 unsigned max_tile_pipes
;
1307 unsigned max_backends
;
1309 unsigned max_threads
;
1310 unsigned max_stack_entries
;
1311 unsigned max_hw_contexts
;
1312 unsigned max_gs_threads
;
1313 unsigned sx_max_export_size
;
1314 unsigned sx_max_export_pos_size
;
1315 unsigned sx_max_export_smx_size
;
1316 unsigned sq_num_cf_insts
;
1317 unsigned sx_num_of_sets
;
1318 unsigned sc_prim_fifo_size
;
1319 unsigned sc_hiz_tile_fifo_size
;
1320 unsigned sc_earlyz_tile_fifo_size
;
1321 unsigned tiling_nbanks
;
1322 unsigned tiling_npipes
;
1323 unsigned tiling_group_size
;
1324 unsigned tile_config
;
1325 unsigned backend_map
;
1326 struct r100_gpu_lockup lockup
;
1329 struct cayman_asic
{
1330 unsigned max_shader_engines
;
1331 unsigned max_pipes_per_simd
;
1332 unsigned max_tile_pipes
;
1333 unsigned max_simds_per_se
;
1334 unsigned max_backends_per_se
;
1335 unsigned max_texture_channel_caches
;
1337 unsigned max_threads
;
1338 unsigned max_gs_threads
;
1339 unsigned max_stack_entries
;
1340 unsigned sx_num_of_sets
;
1341 unsigned sx_max_export_size
;
1342 unsigned sx_max_export_pos_size
;
1343 unsigned sx_max_export_smx_size
;
1344 unsigned max_hw_contexts
;
1345 unsigned sq_num_cf_insts
;
1346 unsigned sc_prim_fifo_size
;
1347 unsigned sc_hiz_tile_fifo_size
;
1348 unsigned sc_earlyz_tile_fifo_size
;
1350 unsigned num_shader_engines
;
1351 unsigned num_shader_pipes_per_simd
;
1352 unsigned num_tile_pipes
;
1353 unsigned num_simds_per_se
;
1354 unsigned num_backends_per_se
;
1355 unsigned backend_disable_mask_per_asic
;
1356 unsigned backend_map
;
1357 unsigned num_texture_channel_caches
;
1358 unsigned mem_max_burst_length_bytes
;
1359 unsigned mem_row_size_in_kb
;
1360 unsigned shader_engine_tile_size
;
1362 unsigned multi_gpu_tile_size
;
1364 unsigned tile_config
;
1365 struct r100_gpu_lockup lockup
;
1368 union radeon_asic_config
{
1369 struct r300_asic r300
;
1370 struct r100_asic r100
;
1371 struct r600_asic r600
;
1372 struct rv770_asic rv770
;
1373 struct evergreen_asic evergreen
;
1374 struct cayman_asic cayman
;
1378 * asic initizalization from radeon_asic.c
1380 void radeon_agp_disable(struct radeon_device
*rdev
);
1381 int radeon_asic_init(struct radeon_device
*rdev
);
1387 int radeon_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1388 struct drm_file
*filp
);
1389 int radeon_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1390 struct drm_file
*filp
);
1391 int radeon_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1392 struct drm_file
*file_priv
);
1393 int radeon_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1394 struct drm_file
*file_priv
);
1395 int radeon_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1396 struct drm_file
*file_priv
);
1397 int radeon_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1398 struct drm_file
*file_priv
);
1399 int radeon_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1400 struct drm_file
*filp
);
1401 int radeon_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1402 struct drm_file
*filp
);
1403 int radeon_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1404 struct drm_file
*filp
);
1405 int radeon_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1406 struct drm_file
*filp
);
1407 int radeon_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1408 struct drm_file
*filp
);
1409 int radeon_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1410 int radeon_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
1411 struct drm_file
*filp
);
1412 int radeon_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
1413 struct drm_file
*filp
);
1415 /* VRAM scratch page for HDP bug, default vram page */
1416 struct r600_vram_scratch
{
1417 struct radeon_bo
*robj
;
1418 volatile uint32_t *ptr
;
1424 * Core structure, functions and helpers.
1426 typedef uint32_t (*radeon_rreg_t
)(struct radeon_device
*, uint32_t);
1427 typedef void (*radeon_wreg_t
)(struct radeon_device
*, uint32_t, uint32_t);
1429 struct radeon_device
{
1431 struct drm_device
*ddev
;
1432 struct pci_dev
*pdev
;
1434 union radeon_asic_config config
;
1435 enum radeon_family family
;
1436 unsigned long flags
;
1438 enum radeon_pll_errata pll_errata
;
1445 uint16_t bios_header_start
;
1446 struct radeon_bo
*stollen_vga_memory
;
1448 resource_size_t rmmio_base
;
1449 resource_size_t rmmio_size
;
1450 void __iomem
*rmmio
;
1451 radeon_rreg_t mc_rreg
;
1452 radeon_wreg_t mc_wreg
;
1453 radeon_rreg_t pll_rreg
;
1454 radeon_wreg_t pll_wreg
;
1455 uint32_t pcie_reg_mask
;
1456 radeon_rreg_t pciep_rreg
;
1457 radeon_wreg_t pciep_wreg
;
1459 void __iomem
*rio_mem
;
1460 resource_size_t rio_mem_size
;
1461 struct radeon_clock clock
;
1462 struct radeon_mc mc
;
1463 struct radeon_gart gart
;
1464 struct radeon_mode_info mode_info
;
1465 struct radeon_scratch scratch
;
1466 struct radeon_mman mman
;
1467 rwlock_t fence_lock
;
1468 struct radeon_fence_driver fence_drv
[RADEON_NUM_RINGS
];
1469 struct radeon_semaphore_driver semaphore_drv
;
1470 struct radeon_ring ring
[RADEON_NUM_RINGS
];
1471 struct radeon_ib_pool ib_pool
;
1472 struct radeon_irq irq
;
1473 struct radeon_asic
*asic
;
1474 struct radeon_gem gem
;
1475 struct radeon_pm pm
;
1476 uint32_t bios_scratch
[RADEON_BIOS_NUM_SCRATCH
];
1477 struct radeon_mutex cs_mutex
;
1478 struct radeon_wb wb
;
1479 struct radeon_dummy_page dummy_page
;
1485 struct radeon_surface_reg surface_regs
[RADEON_GEM_MAX_SURFACES
];
1486 const struct firmware
*me_fw
; /* all family ME firmware */
1487 const struct firmware
*pfp_fw
; /* r6/700 PFP firmware */
1488 const struct firmware
*rlc_fw
; /* r6/700 RLC firmware */
1489 const struct firmware
*mc_fw
; /* NI MC firmware */
1490 struct r600_blit r600_blit
;
1491 struct r600_vram_scratch vram_scratch
;
1492 int msi_enabled
; /* msi enabled */
1493 struct r600_ih ih
; /* r6/700 interrupt ring */
1494 struct work_struct hotplug_work
;
1495 int num_crtc
; /* number of crtcs */
1496 struct mutex dc_hw_i2c_mutex
; /* display controller hw i2c mutex */
1497 struct mutex vram_mutex
;
1501 struct timer_list audio_timer
;
1504 int audio_bits_per_sample
;
1505 uint8_t audio_status_bits
;
1506 uint8_t audio_category_code
;
1508 struct notifier_block acpi_nb
;
1509 /* only one userspace can use Hyperz features or CMASK at a time */
1510 struct drm_file
*hyperz_filp
;
1511 struct drm_file
*cmask_filp
;
1513 struct radeon_i2c_chan
*i2c_bus
[RADEON_MAX_I2C_BUS
];
1515 struct radeon_debugfs debugfs
[RADEON_DEBUGFS_MAX_COMPONENTS
];
1516 unsigned debugfs_count
;
1517 /* virtual memory */
1518 struct radeon_vm_manager vm_manager
;
1521 int radeon_device_init(struct radeon_device
*rdev
,
1522 struct drm_device
*ddev
,
1523 struct pci_dev
*pdev
,
1525 void radeon_device_fini(struct radeon_device
*rdev
);
1526 int radeon_gpu_wait_for_idle(struct radeon_device
*rdev
);
1528 uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
);
1529 void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
1530 u32
r100_io_rreg(struct radeon_device
*rdev
, u32 reg
);
1531 void r100_io_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
);
1536 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1539 * Registers read & write functions.
1541 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1542 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1543 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1544 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1545 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1546 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1547 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1548 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1549 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1550 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1551 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1552 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1553 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1554 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1555 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1556 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1557 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1558 #define WREG32_P(reg, val, mask) \
1560 uint32_t tmp_ = RREG32(reg); \
1562 tmp_ |= ((val) & ~(mask)); \
1563 WREG32(reg, tmp_); \
1565 #define WREG32_PLL_P(reg, val, mask) \
1567 uint32_t tmp_ = RREG32_PLL(reg); \
1569 tmp_ |= ((val) & ~(mask)); \
1570 WREG32_PLL(reg, tmp_); \
1572 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1573 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1574 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1577 * Indirect registers accessor
1579 static inline uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
)
1583 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
1584 r
= RREG32(RADEON_PCIE_DATA
);
1588 static inline void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
1590 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
1591 WREG32(RADEON_PCIE_DATA
, (v
));
1594 void r100_pll_errata_after_index(struct radeon_device
*rdev
);
1600 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1601 (rdev->pdev->device == 0x5969))
1602 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1603 (rdev->family == CHIP_RV200) || \
1604 (rdev->family == CHIP_RS100) || \
1605 (rdev->family == CHIP_RS200) || \
1606 (rdev->family == CHIP_RV250) || \
1607 (rdev->family == CHIP_RV280) || \
1608 (rdev->family == CHIP_RS300))
1609 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1610 (rdev->family == CHIP_RV350) || \
1611 (rdev->family == CHIP_R350) || \
1612 (rdev->family == CHIP_RV380) || \
1613 (rdev->family == CHIP_R420) || \
1614 (rdev->family == CHIP_R423) || \
1615 (rdev->family == CHIP_RV410) || \
1616 (rdev->family == CHIP_RS400) || \
1617 (rdev->family == CHIP_RS480))
1618 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1619 (rdev->ddev->pdev->device == 0x9443) || \
1620 (rdev->ddev->pdev->device == 0x944B) || \
1621 (rdev->ddev->pdev->device == 0x9506) || \
1622 (rdev->ddev->pdev->device == 0x9509) || \
1623 (rdev->ddev->pdev->device == 0x950F) || \
1624 (rdev->ddev->pdev->device == 0x689C) || \
1625 (rdev->ddev->pdev->device == 0x689D))
1626 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1627 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1628 (rdev->family == CHIP_RS690) || \
1629 (rdev->family == CHIP_RS740) || \
1630 (rdev->family >= CHIP_R600))
1631 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1632 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1633 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1634 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1635 (rdev->flags & RADEON_IS_IGP))
1636 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1641 #define RBIOS8(i) (rdev->bios[i])
1642 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1643 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1645 int radeon_combios_init(struct radeon_device
*rdev
);
1646 void radeon_combios_fini(struct radeon_device
*rdev
);
1647 int radeon_atombios_init(struct radeon_device
*rdev
);
1648 void radeon_atombios_fini(struct radeon_device
*rdev
);
1654 #if DRM_DEBUG_CODE == 0
1655 static inline void radeon_ring_write(struct radeon_ring
*ring
, uint32_t v
)
1657 ring
->ring
[ring
->wptr
++] = v
;
1658 ring
->wptr
&= ring
->ptr_mask
;
1660 ring
->ring_free_dw
--;
1663 /* With debugging this is just too big to inline */
1664 void radeon_ring_write(struct radeon_ring
*ring
, uint32_t v
);
1670 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1671 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1672 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1673 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1674 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1675 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1676 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1677 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1678 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1679 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1680 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1681 #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
1682 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1683 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1684 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1685 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1686 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1687 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1688 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1689 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1690 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1691 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1692 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1693 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1694 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1695 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1696 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1697 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1698 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1699 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1700 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1701 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1702 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1703 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1704 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1705 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1706 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1707 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1708 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1709 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1710 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1711 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1712 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1713 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1714 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1715 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1716 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1717 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1718 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->wait_for_vblank((rdev), (crtc))
1719 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1721 /* Common functions */
1723 extern int radeon_gpu_reset(struct radeon_device
*rdev
);
1724 extern void radeon_agp_disable(struct radeon_device
*rdev
);
1725 extern int radeon_modeset_init(struct radeon_device
*rdev
);
1726 extern void radeon_modeset_fini(struct radeon_device
*rdev
);
1727 extern bool radeon_card_posted(struct radeon_device
*rdev
);
1728 extern void radeon_update_bandwidth_info(struct radeon_device
*rdev
);
1729 extern void radeon_update_display_priority(struct radeon_device
*rdev
);
1730 extern bool radeon_boot_test_post_card(struct radeon_device
*rdev
);
1731 extern void radeon_scratch_init(struct radeon_device
*rdev
);
1732 extern void radeon_wb_fini(struct radeon_device
*rdev
);
1733 extern int radeon_wb_init(struct radeon_device
*rdev
);
1734 extern void radeon_wb_disable(struct radeon_device
*rdev
);
1735 extern void radeon_surface_init(struct radeon_device
*rdev
);
1736 extern int radeon_cs_parser_init(struct radeon_cs_parser
*p
, void *data
);
1737 extern void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1738 extern void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1739 extern void radeon_ttm_placement_from_domain(struct radeon_bo
*rbo
, u32 domain
);
1740 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo
);
1741 extern void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
);
1742 extern void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
);
1743 extern int radeon_resume_kms(struct drm_device
*dev
);
1744 extern int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
);
1745 extern void radeon_ttm_set_active_vram_size(struct radeon_device
*rdev
, u64 size
);
1750 int radeon_vm_manager_init(struct radeon_device
*rdev
);
1751 void radeon_vm_manager_fini(struct radeon_device
*rdev
);
1752 int radeon_vm_manager_start(struct radeon_device
*rdev
);
1753 int radeon_vm_manager_suspend(struct radeon_device
*rdev
);
1754 int radeon_vm_init(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
1755 void radeon_vm_fini(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
1756 int radeon_vm_bind(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
1757 void radeon_vm_unbind(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
1758 int radeon_vm_bo_update_pte(struct radeon_device
*rdev
,
1759 struct radeon_vm
*vm
,
1760 struct radeon_bo
*bo
,
1761 struct ttm_mem_reg
*mem
);
1762 void radeon_vm_bo_invalidate(struct radeon_device
*rdev
,
1763 struct radeon_bo
*bo
);
1764 int radeon_vm_bo_add(struct radeon_device
*rdev
,
1765 struct radeon_vm
*vm
,
1766 struct radeon_bo
*bo
,
1769 int radeon_vm_bo_rmv(struct radeon_device
*rdev
,
1770 struct radeon_vm
*vm
,
1771 struct radeon_bo
*bo
);
1775 * R600 vram scratch functions
1777 int r600_vram_scratch_init(struct radeon_device
*rdev
);
1778 void r600_vram_scratch_fini(struct radeon_device
*rdev
);
1781 * r600 cs checking helper
1783 unsigned r600_mip_minify(unsigned size
, unsigned level
);
1784 bool r600_fmt_is_valid_color(u32 format
);
1785 bool r600_fmt_is_valid_texture(u32 format
, enum radeon_family family
);
1786 int r600_fmt_get_blocksize(u32 format
);
1787 int r600_fmt_get_nblocksx(u32 format
, u32 w
);
1788 int r600_fmt_get_nblocksy(u32 format
, u32 h
);
1791 * r600 functions used by radeon_encoder.c
1793 extern void r600_hdmi_enable(struct drm_encoder
*encoder
);
1794 extern void r600_hdmi_disable(struct drm_encoder
*encoder
);
1795 extern void r600_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
1797 extern int ni_init_microcode(struct radeon_device
*rdev
);
1798 extern int ni_mc_load_microcode(struct radeon_device
*rdev
);
1801 #if defined(CONFIG_ACPI)
1802 extern int radeon_acpi_init(struct radeon_device
*rdev
);
1804 static inline int radeon_acpi_init(struct radeon_device
*rdev
) { return 0; }
1807 #include "radeon_object.h"