2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb
;
81 extern int radeon_modeset
;
82 extern int radeon_dynclks
;
83 extern int radeon_r4xx_atom
;
84 extern int radeon_agpmode
;
85 extern int radeon_vram_limit
;
86 extern int radeon_gart_size
;
87 extern int radeon_benchmarking
;
88 extern int radeon_testing
;
89 extern int radeon_connector_table
;
91 extern int radeon_new_pll
;
92 extern int radeon_dynpm
;
93 extern int radeon_audio
;
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100 #define RADEON_IB_POOL_SIZE 16
101 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
102 #define RADEONFB_CONN_LIMIT 4
103 #define RADEON_BIOS_NUM_SCRATCH 8
106 * Errata workarounds.
108 enum radeon_pll_errata
{
109 CHIP_ERRATA_R300_CG
= 0x00000001,
110 CHIP_ERRATA_PLL_DUMMYREADS
= 0x00000002,
111 CHIP_ERRATA_PLL_DELAY
= 0x00000004
115 struct radeon_device
;
121 bool radeon_get_bios(struct radeon_device
*rdev
);
127 struct radeon_dummy_page
{
131 int radeon_dummy_page_init(struct radeon_device
*rdev
);
132 void radeon_dummy_page_fini(struct radeon_device
*rdev
);
138 struct radeon_clock
{
139 struct radeon_pll p1pll
;
140 struct radeon_pll p2pll
;
141 struct radeon_pll spll
;
142 struct radeon_pll mpll
;
144 uint32_t default_mclk
;
145 uint32_t default_sclk
;
151 int radeon_pm_init(struct radeon_device
*rdev
);
152 void radeon_pm_compute_clocks(struct radeon_device
*rdev
);
153 void radeon_combios_get_power_modes(struct radeon_device
*rdev
);
154 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
);
159 struct radeon_fence_driver
{
160 uint32_t scratch_reg
;
163 unsigned long count_timeout
;
164 wait_queue_head_t queue
;
166 struct list_head created
;
167 struct list_head emited
;
168 struct list_head signaled
;
172 struct radeon_fence
{
173 struct radeon_device
*rdev
;
175 struct list_head list
;
176 /* protected by radeon_fence.lock */
178 unsigned long timeout
;
183 int radeon_fence_driver_init(struct radeon_device
*rdev
);
184 void radeon_fence_driver_fini(struct radeon_device
*rdev
);
185 int radeon_fence_create(struct radeon_device
*rdev
, struct radeon_fence
**fence
);
186 int radeon_fence_emit(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
187 void radeon_fence_process(struct radeon_device
*rdev
);
188 bool radeon_fence_signaled(struct radeon_fence
*fence
);
189 int radeon_fence_wait(struct radeon_fence
*fence
, bool interruptible
);
190 int radeon_fence_wait_next(struct radeon_device
*rdev
);
191 int radeon_fence_wait_last(struct radeon_device
*rdev
);
192 struct radeon_fence
*radeon_fence_ref(struct radeon_fence
*fence
);
193 void radeon_fence_unref(struct radeon_fence
**fence
);
198 struct radeon_surface_reg
{
199 struct radeon_bo
*bo
;
202 #define RADEON_GEM_MAX_SURFACES 8
208 struct ttm_bo_global_ref bo_global_ref
;
209 struct ttm_global_reference mem_global_ref
;
210 struct ttm_bo_device bdev
;
211 bool mem_global_referenced
;
216 /* Protected by gem.mutex */
217 struct list_head list
;
218 /* Protected by tbo.reserved */
220 struct ttm_placement placement
;
221 struct ttm_buffer_object tbo
;
222 struct ttm_bo_kmap_obj kmap
;
228 /* Constant after initialization */
229 struct radeon_device
*rdev
;
230 struct drm_gem_object
*gobj
;
233 struct radeon_bo_list
{
234 struct list_head list
;
235 struct radeon_bo
*bo
;
247 struct list_head objects
;
250 int radeon_gem_init(struct radeon_device
*rdev
);
251 void radeon_gem_fini(struct radeon_device
*rdev
);
252 int radeon_gem_object_create(struct radeon_device
*rdev
, int size
,
253 int alignment
, int initial_domain
,
254 bool discardable
, bool kernel
,
255 struct drm_gem_object
**obj
);
256 int radeon_gem_object_pin(struct drm_gem_object
*obj
, uint32_t pin_domain
,
258 void radeon_gem_object_unpin(struct drm_gem_object
*obj
);
262 * GART structures, functions & helpers
266 struct radeon_gart_table_ram
{
267 volatile uint32_t *ptr
;
270 struct radeon_gart_table_vram
{
271 struct radeon_bo
*robj
;
272 volatile uint32_t *ptr
;
275 union radeon_gart_table
{
276 struct radeon_gart_table_ram ram
;
277 struct radeon_gart_table_vram vram
;
280 #define RADEON_GPU_PAGE_SIZE 4096
283 dma_addr_t table_addr
;
284 unsigned num_gpu_pages
;
285 unsigned num_cpu_pages
;
287 union radeon_gart_table table
;
289 dma_addr_t
*pages_addr
;
293 int radeon_gart_table_ram_alloc(struct radeon_device
*rdev
);
294 void radeon_gart_table_ram_free(struct radeon_device
*rdev
);
295 int radeon_gart_table_vram_alloc(struct radeon_device
*rdev
);
296 void radeon_gart_table_vram_free(struct radeon_device
*rdev
);
297 int radeon_gart_init(struct radeon_device
*rdev
);
298 void radeon_gart_fini(struct radeon_device
*rdev
);
299 void radeon_gart_unbind(struct radeon_device
*rdev
, unsigned offset
,
301 int radeon_gart_bind(struct radeon_device
*rdev
, unsigned offset
,
302 int pages
, struct page
**pagelist
);
306 * GPU MC structures, functions & helpers
309 resource_size_t aper_size
;
310 resource_size_t aper_base
;
311 resource_size_t agp_base
;
312 /* for some chips with <= 32MB we need to lie
313 * about vram size near mc fb location */
326 bool igp_sideport_enabled
;
329 int radeon_mc_setup(struct radeon_device
*rdev
);
330 bool radeon_combios_sideport_present(struct radeon_device
*rdev
);
331 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
);
334 * GPU scratch registers structures, functions & helpers
336 struct radeon_scratch
{
342 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
);
343 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
);
352 /* FIXME: use a define max crtc rather than hardcode it */
353 bool crtc_vblank_int
[2];
354 wait_queue_head_t vblank_queue
;
355 /* FIXME: use defines for max hpd/dacs */
361 int radeon_irq_kms_init(struct radeon_device
*rdev
);
362 void radeon_irq_kms_fini(struct radeon_device
*rdev
);
363 void radeon_irq_kms_sw_irq_get(struct radeon_device
*rdev
);
364 void radeon_irq_kms_sw_irq_put(struct radeon_device
*rdev
);
370 struct list_head list
;
373 struct radeon_fence
*fence
;
380 * mutex protects scheduled_ibs, ready, alloc_bm
382 struct radeon_ib_pool
{
384 struct radeon_bo
*robj
;
385 struct list_head scheduled_ibs
;
386 struct radeon_ib ibs
[RADEON_IB_POOL_SIZE
];
388 DECLARE_BITMAP(alloc_bm
, RADEON_IB_POOL_SIZE
);
392 struct radeon_bo
*ring_obj
;
393 volatile uint32_t *ring
;
398 unsigned ring_free_dw
;
411 struct radeon_bo
*ring_obj
;
412 volatile uint32_t *ring
;
425 struct radeon_bo
*shader_obj
;
427 u32 vs_offset
, ps_offset
;
430 u32 vb_used
, vb_total
;
431 struct radeon_ib
*vb_ib
;
434 int radeon_ib_get(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
435 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
**ib
);
436 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
437 int radeon_ib_pool_init(struct radeon_device
*rdev
);
438 void radeon_ib_pool_fini(struct radeon_device
*rdev
);
439 int radeon_ib_test(struct radeon_device
*rdev
);
440 /* Ring access between begin & end cannot sleep */
441 void radeon_ring_free_size(struct radeon_device
*rdev
);
442 int radeon_ring_lock(struct radeon_device
*rdev
, unsigned ndw
);
443 void radeon_ring_unlock_commit(struct radeon_device
*rdev
);
444 void radeon_ring_unlock_undo(struct radeon_device
*rdev
);
445 int radeon_ring_test(struct radeon_device
*rdev
);
446 int radeon_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
447 void radeon_ring_fini(struct radeon_device
*rdev
);
453 struct radeon_cs_reloc
{
454 struct drm_gem_object
*gobj
;
455 struct radeon_bo
*robj
;
456 struct radeon_bo_list lobj
;
461 struct radeon_cs_chunk
{
467 void __user
*user_ptr
;
468 int last_copied_page
;
472 struct radeon_cs_parser
{
474 struct radeon_device
*rdev
;
475 struct drm_file
*filp
;
478 struct radeon_cs_chunk
*chunks
;
479 uint64_t *chunks_array
;
484 struct radeon_cs_reloc
*relocs
;
485 struct radeon_cs_reloc
**relocs_ptr
;
486 struct list_head validated
;
487 /* indices of various chunks */
489 int chunk_relocs_idx
;
490 struct radeon_ib
*ib
;
496 extern int radeon_cs_update_pages(struct radeon_cs_parser
*p
, int pg_idx
);
497 extern int radeon_cs_finish_pages(struct radeon_cs_parser
*p
);
500 static inline u32
radeon_get_ib_value(struct radeon_cs_parser
*p
, int idx
)
502 struct radeon_cs_chunk
*ibc
= &p
->chunks
[p
->chunk_ib_idx
];
503 u32 pg_idx
, pg_offset
;
507 pg_idx
= (idx
* 4) / PAGE_SIZE
;
508 pg_offset
= (idx
* 4) % PAGE_SIZE
;
510 if (ibc
->kpage_idx
[0] == pg_idx
)
511 return ibc
->kpage
[0][pg_offset
/4];
512 if (ibc
->kpage_idx
[1] == pg_idx
)
513 return ibc
->kpage
[1][pg_offset
/4];
515 new_page
= radeon_cs_update_pages(p
, pg_idx
);
517 p
->parser_error
= new_page
;
521 idx_value
= ibc
->kpage
[new_page
][pg_offset
/4];
525 struct radeon_cs_packet
{
534 typedef int (*radeon_packet0_check_t
)(struct radeon_cs_parser
*p
,
535 struct radeon_cs_packet
*pkt
,
536 unsigned idx
, unsigned reg
);
537 typedef int (*radeon_packet3_check_t
)(struct radeon_cs_parser
*p
,
538 struct radeon_cs_packet
*pkt
);
544 int radeon_agp_init(struct radeon_device
*rdev
);
545 void radeon_agp_resume(struct radeon_device
*rdev
);
546 void radeon_agp_fini(struct radeon_device
*rdev
);
553 struct radeon_bo
*wb_obj
;
554 volatile uint32_t *wb
;
559 * struct radeon_pm - power management datas
560 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
561 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
562 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
563 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
564 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
565 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
566 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
567 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
568 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
569 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
570 * @needed_bandwidth: current bandwidth needs
572 * It keeps track of various data needed to take powermanagement decision.
573 * Bandwith need is used to determine minimun clock of the GPU and memory.
574 * Equation between gpu/memory clock and available bandwidth is hw dependent
575 * (type of memory, bus size, efficiency, ...)
577 enum radeon_pm_state
{
583 enum radeon_pm_action
{
590 enum radeon_voltage_type
{
597 enum radeon_pm_state_type
{
598 POWER_STATE_TYPE_DEFAULT
,
599 POWER_STATE_TYPE_POWERSAVE
,
600 POWER_STATE_TYPE_BATTERY
,
601 POWER_STATE_TYPE_BALANCED
,
602 POWER_STATE_TYPE_PERFORMANCE
,
605 enum radeon_pm_clock_mode_type
{
606 POWER_MODE_TYPE_DEFAULT
,
609 POWER_MODE_TYPE_HIGH
,
612 struct radeon_voltage
{
613 enum radeon_voltage_type type
;
615 struct radeon_gpio_rec gpio
;
616 u32 delay
; /* delay in usec from voltage drop to sclk change */
617 bool active_high
; /* voltage drop is active when bit is high */
619 u8 vddc_id
; /* index into vddc voltage table */
620 u8 vddci_id
; /* index into vddci voltage table */
626 struct radeon_pm_non_clock_info
{
629 /* standardized non-clock flags */
633 struct radeon_pm_clock_info
{
639 struct radeon_voltage voltage
;
640 /* standardized clock flags - not sure we'll need these */
644 struct radeon_power_state
{
645 enum radeon_pm_state_type type
;
646 /* XXX: use a define for num clock modes */
647 struct radeon_pm_clock_info clock_info
[8];
648 /* number of valid clock modes in this power state */
650 /* currently selected clock mode */
651 struct radeon_pm_clock_info
*current_clock_mode
;
652 struct radeon_pm_clock_info
*requested_clock_mode
;
653 struct radeon_pm_clock_info
*default_clock_mode
;
654 /* non clock info about this state */
655 struct radeon_pm_non_clock_info non_clock_info
;
656 bool voltage_drop_active
;
661 struct delayed_work idle_work
;
662 enum radeon_pm_state state
;
663 enum radeon_pm_action planned_action
;
664 unsigned long action_timeout
;
668 fixed20_12 max_bandwidth
;
669 fixed20_12 igp_sideport_mclk
;
670 fixed20_12 igp_system_mclk
;
671 fixed20_12 igp_ht_link_clk
;
672 fixed20_12 igp_ht_link_width
;
673 fixed20_12 k8_bandwidth
;
674 fixed20_12 sideport_bandwidth
;
675 fixed20_12 ht_bandwidth
;
676 fixed20_12 core_bandwidth
;
678 fixed20_12 needed_bandwidth
;
679 /* XXX: use a define for num power modes */
680 struct radeon_power_state power_state
[8];
681 /* number of valid power states */
682 int num_power_states
;
683 struct radeon_power_state
*current_power_state
;
684 struct radeon_power_state
*requested_power_state
;
685 struct radeon_power_state
*default_power_state
;
692 void radeon_benchmark(struct radeon_device
*rdev
);
698 void radeon_test_moves(struct radeon_device
*rdev
);
704 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
705 struct drm_info_list
*files
,
707 int radeon_debugfs_fence_init(struct radeon_device
*rdev
);
708 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
);
709 int r100_debugfs_cp_init(struct radeon_device
*rdev
);
713 * ASIC specific functions.
716 int (*init
)(struct radeon_device
*rdev
);
717 void (*fini
)(struct radeon_device
*rdev
);
718 int (*resume
)(struct radeon_device
*rdev
);
719 int (*suspend
)(struct radeon_device
*rdev
);
720 void (*vga_set_state
)(struct radeon_device
*rdev
, bool state
);
721 int (*gpu_reset
)(struct radeon_device
*rdev
);
722 void (*gart_tlb_flush
)(struct radeon_device
*rdev
);
723 int (*gart_set_page
)(struct radeon_device
*rdev
, int i
, uint64_t addr
);
724 int (*cp_init
)(struct radeon_device
*rdev
, unsigned ring_size
);
725 void (*cp_fini
)(struct radeon_device
*rdev
);
726 void (*cp_disable
)(struct radeon_device
*rdev
);
727 void (*cp_commit
)(struct radeon_device
*rdev
);
728 void (*ring_start
)(struct radeon_device
*rdev
);
729 int (*ring_test
)(struct radeon_device
*rdev
);
730 void (*ring_ib_execute
)(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
731 int (*irq_set
)(struct radeon_device
*rdev
);
732 int (*irq_process
)(struct radeon_device
*rdev
);
733 u32 (*get_vblank_counter
)(struct radeon_device
*rdev
, int crtc
);
734 void (*fence_ring_emit
)(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
735 int (*cs_parse
)(struct radeon_cs_parser
*p
);
736 int (*copy_blit
)(struct radeon_device
*rdev
,
740 struct radeon_fence
*fence
);
741 int (*copy_dma
)(struct radeon_device
*rdev
,
745 struct radeon_fence
*fence
);
746 int (*copy
)(struct radeon_device
*rdev
,
750 struct radeon_fence
*fence
);
751 uint32_t (*get_engine_clock
)(struct radeon_device
*rdev
);
752 void (*set_engine_clock
)(struct radeon_device
*rdev
, uint32_t eng_clock
);
753 uint32_t (*get_memory_clock
)(struct radeon_device
*rdev
);
754 void (*set_memory_clock
)(struct radeon_device
*rdev
, uint32_t mem_clock
);
755 int (*get_pcie_lanes
)(struct radeon_device
*rdev
);
756 void (*set_pcie_lanes
)(struct radeon_device
*rdev
, int lanes
);
757 void (*set_clock_gating
)(struct radeon_device
*rdev
, int enable
);
758 int (*set_surface_reg
)(struct radeon_device
*rdev
, int reg
,
759 uint32_t tiling_flags
, uint32_t pitch
,
760 uint32_t offset
, uint32_t obj_size
);
761 int (*clear_surface_reg
)(struct radeon_device
*rdev
, int reg
);
762 void (*bandwidth_update
)(struct radeon_device
*rdev
);
763 void (*hpd_init
)(struct radeon_device
*rdev
);
764 void (*hpd_fini
)(struct radeon_device
*rdev
);
765 bool (*hpd_sense
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
766 void (*hpd_set_polarity
)(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
767 /* ioctl hw specific callback. Some hw might want to perform special
768 * operation on specific ioctl. For instance on wait idle some hw
769 * might want to perform and HDP flush through MMIO as it seems that
770 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
773 void (*ioctl_wait_idle
)(struct radeon_device
*rdev
, struct radeon_bo
*bo
);
780 const unsigned *reg_safe_bm
;
781 unsigned reg_safe_bm_size
;
786 const unsigned *reg_safe_bm
;
787 unsigned reg_safe_bm_size
;
794 unsigned max_tile_pipes
;
796 unsigned max_backends
;
798 unsigned max_threads
;
799 unsigned max_stack_entries
;
800 unsigned max_hw_contexts
;
801 unsigned max_gs_threads
;
802 unsigned sx_max_export_size
;
803 unsigned sx_max_export_pos_size
;
804 unsigned sx_max_export_smx_size
;
805 unsigned sq_num_cf_insts
;
810 unsigned max_tile_pipes
;
812 unsigned max_backends
;
814 unsigned max_threads
;
815 unsigned max_stack_entries
;
816 unsigned max_hw_contexts
;
817 unsigned max_gs_threads
;
818 unsigned sx_max_export_size
;
819 unsigned sx_max_export_pos_size
;
820 unsigned sx_max_export_smx_size
;
821 unsigned sq_num_cf_insts
;
822 unsigned sx_num_of_sets
;
823 unsigned sc_prim_fifo_size
;
824 unsigned sc_hiz_tile_fifo_size
;
825 unsigned sc_earlyz_tile_fifo_fize
;
828 union radeon_asic_config
{
829 struct r300_asic r300
;
830 struct r100_asic r100
;
831 struct r600_asic r600
;
832 struct rv770_asic rv770
;
839 int radeon_gem_info_ioctl(struct drm_device
*dev
, void *data
,
840 struct drm_file
*filp
);
841 int radeon_gem_create_ioctl(struct drm_device
*dev
, void *data
,
842 struct drm_file
*filp
);
843 int radeon_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
844 struct drm_file
*file_priv
);
845 int radeon_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
846 struct drm_file
*file_priv
);
847 int radeon_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
848 struct drm_file
*file_priv
);
849 int radeon_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
850 struct drm_file
*file_priv
);
851 int radeon_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
852 struct drm_file
*filp
);
853 int radeon_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
854 struct drm_file
*filp
);
855 int radeon_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
856 struct drm_file
*filp
);
857 int radeon_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
858 struct drm_file
*filp
);
859 int radeon_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
860 int radeon_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
861 struct drm_file
*filp
);
862 int radeon_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
863 struct drm_file
*filp
);
867 * Core structure, functions and helpers.
869 typedef uint32_t (*radeon_rreg_t
)(struct radeon_device
*, uint32_t);
870 typedef void (*radeon_wreg_t
)(struct radeon_device
*, uint32_t, uint32_t);
872 struct radeon_device
{
874 struct drm_device
*ddev
;
875 struct pci_dev
*pdev
;
877 union radeon_asic_config config
;
878 enum radeon_family family
;
881 enum radeon_pll_errata pll_errata
;
888 uint16_t bios_header_start
;
889 struct radeon_bo
*stollen_vga_memory
;
890 struct fb_info
*fbdev_info
;
891 struct radeon_bo
*fbdev_rbo
;
892 struct radeon_framebuffer
*fbdev_rfb
;
894 resource_size_t rmmio_base
;
895 resource_size_t rmmio_size
;
897 radeon_rreg_t mc_rreg
;
898 radeon_wreg_t mc_wreg
;
899 radeon_rreg_t pll_rreg
;
900 radeon_wreg_t pll_wreg
;
901 uint32_t pcie_reg_mask
;
902 radeon_rreg_t pciep_rreg
;
903 radeon_wreg_t pciep_wreg
;
904 struct radeon_clock clock
;
906 struct radeon_gart gart
;
907 struct radeon_mode_info mode_info
;
908 struct radeon_scratch scratch
;
909 struct radeon_mman mman
;
910 struct radeon_fence_driver fence_drv
;
912 struct radeon_ib_pool ib_pool
;
913 struct radeon_irq irq
;
914 struct radeon_asic
*asic
;
915 struct radeon_gem gem
;
917 uint32_t bios_scratch
[RADEON_BIOS_NUM_SCRATCH
];
918 struct mutex cs_mutex
;
920 struct radeon_dummy_page dummy_page
;
926 struct radeon_surface_reg surface_regs
[RADEON_GEM_MAX_SURFACES
];
927 const struct firmware
*me_fw
; /* all family ME firmware */
928 const struct firmware
*pfp_fw
; /* r6/700 PFP firmware */
929 const struct firmware
*rlc_fw
; /* r6/700 RLC firmware */
930 struct r600_blit r600_blit
;
931 int msi_enabled
; /* msi enabled */
932 struct r600_ih ih
; /* r6/700 interrupt ring */
933 struct workqueue_struct
*wq
;
934 struct work_struct hotplug_work
;
935 int num_crtc
; /* number of crtcs */
936 struct mutex dc_hw_i2c_mutex
; /* display controller hw i2c mutex */
939 struct timer_list audio_timer
;
942 int audio_bits_per_sample
;
943 uint8_t audio_status_bits
;
944 uint8_t audio_category_code
;
947 int radeon_device_init(struct radeon_device
*rdev
,
948 struct drm_device
*ddev
,
949 struct pci_dev
*pdev
,
951 void radeon_device_fini(struct radeon_device
*rdev
);
952 int radeon_gpu_wait_for_idle(struct radeon_device
*rdev
);
955 int r600_blit_prepare_copy(struct radeon_device
*rdev
, int size_bytes
);
956 void r600_blit_done_copy(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
957 void r600_kms_blit_copy(struct radeon_device
*rdev
,
958 u64 src_gpu_addr
, u64 dst_gpu_addr
,
961 static inline uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
)
963 if (reg
< rdev
->rmmio_size
)
964 return readl(((void __iomem
*)rdev
->rmmio
) + reg
);
966 writel(reg
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_INDEX
);
967 return readl(((void __iomem
*)rdev
->rmmio
) + RADEON_MM_DATA
);
971 static inline void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
973 if (reg
< rdev
->rmmio_size
)
974 writel(v
, ((void __iomem
*)rdev
->rmmio
) + reg
);
976 writel(reg
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_INDEX
);
977 writel(v
, ((void __iomem
*)rdev
->rmmio
) + RADEON_MM_DATA
);
984 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
987 * Registers read & write functions.
989 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
990 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
991 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
992 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
993 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
994 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
995 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
996 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
997 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
998 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
999 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1000 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1001 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1002 #define WREG32_P(reg, val, mask) \
1004 uint32_t tmp_ = RREG32(reg); \
1006 tmp_ |= ((val) & ~(mask)); \
1007 WREG32(reg, tmp_); \
1009 #define WREG32_PLL_P(reg, val, mask) \
1011 uint32_t tmp_ = RREG32_PLL(reg); \
1013 tmp_ |= ((val) & ~(mask)); \
1014 WREG32_PLL(reg, tmp_); \
1016 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1019 * Indirect registers accessor
1021 static inline uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
)
1025 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
1026 r
= RREG32(RADEON_PCIE_DATA
);
1030 static inline void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
1032 WREG32(RADEON_PCIE_INDEX
, ((reg
) & rdev
->pcie_reg_mask
));
1033 WREG32(RADEON_PCIE_DATA
, (v
));
1036 void r100_pll_errata_after_index(struct radeon_device
*rdev
);
1042 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1043 (rdev->pdev->device == 0x5969))
1044 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1045 (rdev->family == CHIP_RV200) || \
1046 (rdev->family == CHIP_RS100) || \
1047 (rdev->family == CHIP_RS200) || \
1048 (rdev->family == CHIP_RV250) || \
1049 (rdev->family == CHIP_RV280) || \
1050 (rdev->family == CHIP_RS300))
1051 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1052 (rdev->family == CHIP_RV350) || \
1053 (rdev->family == CHIP_R350) || \
1054 (rdev->family == CHIP_RV380) || \
1055 (rdev->family == CHIP_R420) || \
1056 (rdev->family == CHIP_R423) || \
1057 (rdev->family == CHIP_RV410) || \
1058 (rdev->family == CHIP_RS400) || \
1059 (rdev->family == CHIP_RS480))
1060 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1061 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1062 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1068 #define RBIOS8(i) (rdev->bios[i])
1069 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1070 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1072 int radeon_combios_init(struct radeon_device
*rdev
);
1073 void radeon_combios_fini(struct radeon_device
*rdev
);
1074 int radeon_atombios_init(struct radeon_device
*rdev
);
1075 void radeon_atombios_fini(struct radeon_device
*rdev
);
1081 static inline void radeon_ring_write(struct radeon_device
*rdev
, uint32_t v
)
1084 if (rdev
->cp
.count_dw
<= 0) {
1085 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1088 rdev
->cp
.ring
[rdev
->cp
.wptr
++] = v
;
1089 rdev
->cp
.wptr
&= rdev
->cp
.ptr_mask
;
1090 rdev
->cp
.count_dw
--;
1091 rdev
->cp
.ring_free_dw
--;
1098 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1099 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1100 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1101 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1102 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1103 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1104 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1105 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1106 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1107 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1108 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1109 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1110 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1111 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1112 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1113 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1114 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1115 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1116 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1117 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1118 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1119 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1120 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1121 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1122 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1123 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1124 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1125 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1126 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1127 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1128 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1129 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1130 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1131 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1133 /* Common functions */
1135 extern void radeon_agp_disable(struct radeon_device
*rdev
);
1136 extern int radeon_gart_table_vram_pin(struct radeon_device
*rdev
);
1137 extern int radeon_modeset_init(struct radeon_device
*rdev
);
1138 extern void radeon_modeset_fini(struct radeon_device
*rdev
);
1139 extern bool radeon_card_posted(struct radeon_device
*rdev
);
1140 extern bool radeon_boot_test_post_card(struct radeon_device
*rdev
);
1141 extern int radeon_clocks_init(struct radeon_device
*rdev
);
1142 extern void radeon_clocks_fini(struct radeon_device
*rdev
);
1143 extern void radeon_scratch_init(struct radeon_device
*rdev
);
1144 extern void radeon_surface_init(struct radeon_device
*rdev
);
1145 extern int radeon_cs_parser_init(struct radeon_cs_parser
*p
, void *data
);
1146 extern void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1147 extern void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
1148 extern void radeon_ttm_placement_from_domain(struct radeon_bo
*rbo
, u32 domain
);
1149 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo
);
1151 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1152 struct r100_mc_save
{
1160 extern void r100_cp_disable(struct radeon_device
*rdev
);
1161 extern int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
);
1162 extern void r100_cp_fini(struct radeon_device
*rdev
);
1163 extern void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
);
1164 extern int r100_pci_gart_init(struct radeon_device
*rdev
);
1165 extern void r100_pci_gart_fini(struct radeon_device
*rdev
);
1166 extern int r100_pci_gart_enable(struct radeon_device
*rdev
);
1167 extern void r100_pci_gart_disable(struct radeon_device
*rdev
);
1168 extern int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
1169 extern int r100_debugfs_mc_info_init(struct radeon_device
*rdev
);
1170 extern int r100_gui_wait_for_idle(struct radeon_device
*rdev
);
1171 extern void r100_ib_fini(struct radeon_device
*rdev
);
1172 extern int r100_ib_init(struct radeon_device
*rdev
);
1173 extern void r100_irq_disable(struct radeon_device
*rdev
);
1174 extern int r100_irq_set(struct radeon_device
*rdev
);
1175 extern void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
1176 extern void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
1177 extern void r100_vram_init_sizes(struct radeon_device
*rdev
);
1178 extern void r100_wb_disable(struct radeon_device
*rdev
);
1179 extern void r100_wb_fini(struct radeon_device
*rdev
);
1180 extern int r100_wb_init(struct radeon_device
*rdev
);
1181 extern void r100_hdp_reset(struct radeon_device
*rdev
);
1182 extern int r100_rb2d_reset(struct radeon_device
*rdev
);
1183 extern int r100_cp_reset(struct radeon_device
*rdev
);
1184 extern void r100_vga_render_disable(struct radeon_device
*rdev
);
1185 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
1186 struct radeon_cs_packet
*pkt
,
1187 struct radeon_bo
*robj
);
1188 extern int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
1189 struct radeon_cs_packet
*pkt
,
1190 const unsigned *auth
, unsigned n
,
1191 radeon_packet0_check_t check
);
1192 extern int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
1193 struct radeon_cs_packet
*pkt
,
1195 extern void r100_enable_bm(struct radeon_device
*rdev
);
1196 extern void r100_set_common_regs(struct radeon_device
*rdev
);
1198 /* rv200,rv250,rv280 */
1199 extern void r200_set_safe_registers(struct radeon_device
*rdev
);
1201 /* r300,r350,rv350,rv370,rv380 */
1202 extern void r300_set_reg_safe(struct radeon_device
*rdev
);
1203 extern void r300_mc_program(struct radeon_device
*rdev
);
1204 extern void r300_vram_info(struct radeon_device
*rdev
);
1205 extern void r300_clock_startup(struct radeon_device
*rdev
);
1206 extern int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
1207 extern int rv370_pcie_gart_init(struct radeon_device
*rdev
);
1208 extern void rv370_pcie_gart_fini(struct radeon_device
*rdev
);
1209 extern int rv370_pcie_gart_enable(struct radeon_device
*rdev
);
1210 extern void rv370_pcie_gart_disable(struct radeon_device
*rdev
);
1212 /* r420,r423,rv410 */
1213 extern int r420_mc_init(struct radeon_device
*rdev
);
1214 extern u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
);
1215 extern void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
);
1216 extern int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
);
1217 extern void r420_pipes_init(struct radeon_device
*rdev
);
1220 struct rv515_mc_save
{
1223 u32 vga_render_control
;
1224 u32 vga_hdp_control
;
1228 extern void rv515_bandwidth_avivo_update(struct radeon_device
*rdev
);
1229 extern void rv515_vga_render_disable(struct radeon_device
*rdev
);
1230 extern void rv515_set_safe_registers(struct radeon_device
*rdev
);
1231 extern void rv515_mc_stop(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
1232 extern void rv515_mc_resume(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
1233 extern void rv515_clock_startup(struct radeon_device
*rdev
);
1234 extern void rv515_debugfs(struct radeon_device
*rdev
);
1235 extern int rv515_suspend(struct radeon_device
*rdev
);
1238 extern int rs400_gart_init(struct radeon_device
*rdev
);
1239 extern int rs400_gart_enable(struct radeon_device
*rdev
);
1240 extern void rs400_gart_adjust_size(struct radeon_device
*rdev
);
1241 extern void rs400_gart_disable(struct radeon_device
*rdev
);
1242 extern void rs400_gart_fini(struct radeon_device
*rdev
);
1245 extern void rs600_set_safe_registers(struct radeon_device
*rdev
);
1246 extern int rs600_irq_set(struct radeon_device
*rdev
);
1247 extern void rs600_irq_disable(struct radeon_device
*rdev
);
1250 extern void rs690_line_buffer_adjust(struct radeon_device
*rdev
,
1251 struct drm_display_mode
*mode1
,
1252 struct drm_display_mode
*mode2
);
1254 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1255 extern bool r600_card_posted(struct radeon_device
*rdev
);
1256 extern void r600_cp_stop(struct radeon_device
*rdev
);
1257 extern void r600_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
1258 extern int r600_cp_resume(struct radeon_device
*rdev
);
1259 extern void r600_cp_fini(struct radeon_device
*rdev
);
1260 extern int r600_count_pipe_bits(uint32_t val
);
1261 extern int r600_gart_clear_page(struct radeon_device
*rdev
, int i
);
1262 extern int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
1263 extern int r600_pcie_gart_init(struct radeon_device
*rdev
);
1264 extern void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
1265 extern int r600_ib_test(struct radeon_device
*rdev
);
1266 extern int r600_ring_test(struct radeon_device
*rdev
);
1267 extern void r600_wb_fini(struct radeon_device
*rdev
);
1268 extern int r600_wb_enable(struct radeon_device
*rdev
);
1269 extern void r600_wb_disable(struct radeon_device
*rdev
);
1270 extern void r600_scratch_init(struct radeon_device
*rdev
);
1271 extern int r600_blit_init(struct radeon_device
*rdev
);
1272 extern void r600_blit_fini(struct radeon_device
*rdev
);
1273 extern int r600_init_microcode(struct radeon_device
*rdev
);
1274 extern int r600_gpu_reset(struct radeon_device
*rdev
);
1276 extern int r600_irq_init(struct radeon_device
*rdev
);
1277 extern void r600_irq_fini(struct radeon_device
*rdev
);
1278 extern void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
1279 extern int r600_irq_set(struct radeon_device
*rdev
);
1280 extern void r600_irq_suspend(struct radeon_device
*rdev
);
1282 extern int r600_audio_init(struct radeon_device
*rdev
);
1283 extern int r600_audio_tmds_index(struct drm_encoder
*encoder
);
1284 extern void r600_audio_set_clock(struct drm_encoder
*encoder
, int clock
);
1285 extern void r600_audio_fini(struct radeon_device
*rdev
);
1286 extern void r600_hdmi_init(struct drm_encoder
*encoder
);
1287 extern void r600_hdmi_enable(struct drm_encoder
*encoder
, int enable
);
1288 extern void r600_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
);
1289 extern int r600_hdmi_buffer_status_changed(struct drm_encoder
*encoder
);
1290 extern void r600_hdmi_update_audio_settings(struct drm_encoder
*encoder
,
1294 uint8_t status_bits
,
1295 uint8_t category_code
);
1297 #include "radeon_object.h"