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drm/radeon/dpm: Disable sclk switching on Oland when two 4K 60Hz monitors are connected
[mirror_ubuntu-kernels.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/dma-fence.h>
70
71 #ifdef CONFIG_MMU_NOTIFIER
72 #include <linux/mmu_notifier.h>
73 #endif
74
75 #include <drm/ttm/ttm_bo_api.h>
76 #include <drm/ttm/ttm_bo_driver.h>
77 #include <drm/ttm/ttm_placement.h>
78 #include <drm/ttm/ttm_execbuf_util.h>
79
80 #include <drm/drm_gem.h>
81
82 #include "radeon_family.h"
83 #include "radeon_mode.h"
84 #include "radeon_reg.h"
85
86 /*
87 * Modules parameters.
88 */
89 extern int radeon_no_wb;
90 extern int radeon_modeset;
91 extern int radeon_dynclks;
92 extern int radeon_r4xx_atom;
93 extern int radeon_agpmode;
94 extern int radeon_vram_limit;
95 extern int radeon_gart_size;
96 extern int radeon_benchmarking;
97 extern int radeon_testing;
98 extern int radeon_connector_table;
99 extern int radeon_tv;
100 extern int radeon_audio;
101 extern int radeon_disp_priority;
102 extern int radeon_hw_i2c;
103 extern int radeon_pcie_gen2;
104 extern int radeon_msi;
105 extern int radeon_lockup_timeout;
106 extern int radeon_fastfb;
107 extern int radeon_dpm;
108 extern int radeon_aspm;
109 extern int radeon_runtime_pm;
110 extern int radeon_hard_reset;
111 extern int radeon_vm_size;
112 extern int radeon_vm_block_size;
113 extern int radeon_deep_color;
114 extern int radeon_use_pflipirq;
115 extern int radeon_bapm;
116 extern int radeon_backlight;
117 extern int radeon_auxch;
118 extern int radeon_mst;
119 extern int radeon_uvd;
120 extern int radeon_vce;
121 extern int radeon_si_support;
122 extern int radeon_cik_support;
123
124 /*
125 * Copy from radeon_drv.h so we don't have to include both and have conflicting
126 * symbol;
127 */
128 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
129 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
130 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
131 /* RADEON_IB_POOL_SIZE must be a power of 2 */
132 #define RADEON_IB_POOL_SIZE 16
133 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
134 #define RADEONFB_CONN_LIMIT 4
135 #define RADEON_BIOS_NUM_SCRATCH 8
136
137 /* internal ring indices */
138 /* r1xx+ has gfx CP ring */
139 #define RADEON_RING_TYPE_GFX_INDEX 0
140
141 /* cayman has 2 compute CP rings */
142 #define CAYMAN_RING_TYPE_CP1_INDEX 1
143 #define CAYMAN_RING_TYPE_CP2_INDEX 2
144
145 /* R600+ has an async dma ring */
146 #define R600_RING_TYPE_DMA_INDEX 3
147 /* cayman add a second async dma ring */
148 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
149
150 /* R600+ */
151 #define R600_RING_TYPE_UVD_INDEX 5
152
153 /* TN+ */
154 #define TN_RING_TYPE_VCE1_INDEX 6
155 #define TN_RING_TYPE_VCE2_INDEX 7
156
157 /* max number of rings */
158 #define RADEON_NUM_RINGS 8
159
160 /* number of hw syncs before falling back on blocking */
161 #define RADEON_NUM_SYNCS 4
162
163 /* hardcode those limit for now */
164 #define RADEON_VA_IB_OFFSET (1 << 20)
165 #define RADEON_VA_RESERVED_SIZE (8 << 20)
166 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
167
168 /* hard reset data */
169 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
170
171 /* reset flags */
172 #define RADEON_RESET_GFX (1 << 0)
173 #define RADEON_RESET_COMPUTE (1 << 1)
174 #define RADEON_RESET_DMA (1 << 2)
175 #define RADEON_RESET_CP (1 << 3)
176 #define RADEON_RESET_GRBM (1 << 4)
177 #define RADEON_RESET_DMA1 (1 << 5)
178 #define RADEON_RESET_RLC (1 << 6)
179 #define RADEON_RESET_SEM (1 << 7)
180 #define RADEON_RESET_IH (1 << 8)
181 #define RADEON_RESET_VMC (1 << 9)
182 #define RADEON_RESET_MC (1 << 10)
183 #define RADEON_RESET_DISPLAY (1 << 11)
184
185 /* CG block flags */
186 #define RADEON_CG_BLOCK_GFX (1 << 0)
187 #define RADEON_CG_BLOCK_MC (1 << 1)
188 #define RADEON_CG_BLOCK_SDMA (1 << 2)
189 #define RADEON_CG_BLOCK_UVD (1 << 3)
190 #define RADEON_CG_BLOCK_VCE (1 << 4)
191 #define RADEON_CG_BLOCK_HDP (1 << 5)
192 #define RADEON_CG_BLOCK_BIF (1 << 6)
193
194 /* CG flags */
195 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
196 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
197 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
198 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
199 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
201 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
202 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
203 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
204 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
205 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
206 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
207 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
208 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
209 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
210 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
211 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
212
213 /* PG flags */
214 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
215 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
216 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
217 #define RADEON_PG_SUPPORT_UVD (1 << 3)
218 #define RADEON_PG_SUPPORT_VCE (1 << 4)
219 #define RADEON_PG_SUPPORT_CP (1 << 5)
220 #define RADEON_PG_SUPPORT_GDS (1 << 6)
221 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
222 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
223 #define RADEON_PG_SUPPORT_ACP (1 << 9)
224 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
225
226 /* max cursor sizes (in pixels) */
227 #define CURSOR_WIDTH 64
228 #define CURSOR_HEIGHT 64
229
230 #define CIK_CURSOR_WIDTH 128
231 #define CIK_CURSOR_HEIGHT 128
232
233 /*
234 * Errata workarounds.
235 */
236 enum radeon_pll_errata {
237 CHIP_ERRATA_R300_CG = 0x00000001,
238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
239 CHIP_ERRATA_PLL_DELAY = 0x00000004
240 };
241
242
243 struct radeon_device;
244
245
246 /*
247 * BIOS.
248 */
249 bool radeon_get_bios(struct radeon_device *rdev);
250
251 /*
252 * Dummy page
253 */
254 struct radeon_dummy_page {
255 uint64_t entry;
256 struct page *page;
257 dma_addr_t addr;
258 };
259 int radeon_dummy_page_init(struct radeon_device *rdev);
260 void radeon_dummy_page_fini(struct radeon_device *rdev);
261
262
263 /*
264 * Clocks
265 */
266 struct radeon_clock {
267 struct radeon_pll p1pll;
268 struct radeon_pll p2pll;
269 struct radeon_pll dcpll;
270 struct radeon_pll spll;
271 struct radeon_pll mpll;
272 /* 10 Khz units */
273 uint32_t default_mclk;
274 uint32_t default_sclk;
275 uint32_t default_dispclk;
276 uint32_t current_dispclk;
277 uint32_t dp_extclk;
278 uint32_t max_pixel_clock;
279 uint32_t vco_freq;
280 };
281
282 /*
283 * Power management
284 */
285 int radeon_pm_init(struct radeon_device *rdev);
286 int radeon_pm_late_init(struct radeon_device *rdev);
287 void radeon_pm_fini(struct radeon_device *rdev);
288 void radeon_pm_compute_clocks(struct radeon_device *rdev);
289 void radeon_pm_suspend(struct radeon_device *rdev);
290 void radeon_pm_resume(struct radeon_device *rdev);
291 void radeon_combios_get_power_modes(struct radeon_device *rdev);
292 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
293 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
294 u8 clock_type,
295 u32 clock,
296 bool strobe_mode,
297 struct atom_clock_dividers *dividers);
298 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
299 u32 clock,
300 bool strobe_mode,
301 struct atom_mpll_param *mpll_param);
302 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
303 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
304 u16 voltage_level, u8 voltage_type,
305 u32 *gpio_value, u32 *gpio_mask);
306 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
307 u32 eng_clock, u32 mem_clock);
308 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
309 u8 voltage_type, u16 *voltage_step);
310 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
311 u16 voltage_id, u16 *voltage);
312 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
313 u16 *voltage,
314 u16 leakage_idx);
315 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
316 u16 *leakage_id);
317 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
318 u16 *vddc, u16 *vddci,
319 u16 virtual_voltage_id,
320 u16 vbios_voltage_id);
321 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
322 u16 virtual_voltage_id,
323 u16 *voltage);
324 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
325 u8 voltage_type,
326 u16 nominal_voltage,
327 u16 *true_voltage);
328 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
329 u8 voltage_type, u16 *min_voltage);
330 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
331 u8 voltage_type, u16 *max_voltage);
332 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
333 u8 voltage_type, u8 voltage_mode,
334 struct atom_voltage_table *voltage_table);
335 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
336 u8 voltage_type, u8 voltage_mode);
337 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
338 u8 voltage_type,
339 u8 *svd_gpio_id, u8 *svc_gpio_id);
340 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
341 u32 mem_clock);
342 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
343 u32 mem_clock);
344 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
345 u8 module_index,
346 struct atom_mc_reg_table *reg_table);
347 int radeon_atom_get_memory_info(struct radeon_device *rdev,
348 u8 module_index, struct atom_memory_info *mem_info);
349 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
350 bool gddr5, u8 module_index,
351 struct atom_memory_clock_range_table *mclk_range_table);
352 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
353 u16 voltage_id, u16 *voltage);
354 void rs690_pm_info(struct radeon_device *rdev);
355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
356 unsigned *bankh, unsigned *mtaspect,
357 unsigned *tile_split);
358
359 /*
360 * Fences.
361 */
362 struct radeon_fence_driver {
363 struct radeon_device *rdev;
364 uint32_t scratch_reg;
365 uint64_t gpu_addr;
366 volatile uint32_t *cpu_addr;
367 /* sync_seq is protected by ring emission lock */
368 uint64_t sync_seq[RADEON_NUM_RINGS];
369 atomic64_t last_seq;
370 bool initialized, delayed_irq;
371 struct delayed_work lockup_work;
372 };
373
374 struct radeon_fence {
375 struct dma_fence base;
376
377 struct radeon_device *rdev;
378 uint64_t seq;
379 /* RB, DMA, etc. */
380 unsigned ring;
381 bool is_vm_update;
382
383 wait_queue_entry_t fence_wake;
384 };
385
386 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
387 int radeon_fence_driver_init(struct radeon_device *rdev);
388 void radeon_fence_driver_fini(struct radeon_device *rdev);
389 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
390 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
391 void radeon_fence_process(struct radeon_device *rdev, int ring);
392 bool radeon_fence_signaled(struct radeon_fence *fence);
393 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
394 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
395 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
396 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
397 int radeon_fence_wait_any(struct radeon_device *rdev,
398 struct radeon_fence **fences,
399 bool intr);
400 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
401 void radeon_fence_unref(struct radeon_fence **fence);
402 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
403 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
404 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
405 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
406 struct radeon_fence *b)
407 {
408 if (!a) {
409 return b;
410 }
411
412 if (!b) {
413 return a;
414 }
415
416 BUG_ON(a->ring != b->ring);
417
418 if (a->seq > b->seq) {
419 return a;
420 } else {
421 return b;
422 }
423 }
424
425 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
426 struct radeon_fence *b)
427 {
428 if (!a) {
429 return false;
430 }
431
432 if (!b) {
433 return true;
434 }
435
436 BUG_ON(a->ring != b->ring);
437
438 return a->seq < b->seq;
439 }
440
441 /*
442 * Tiling registers
443 */
444 struct radeon_surface_reg {
445 struct radeon_bo *bo;
446 };
447
448 #define RADEON_GEM_MAX_SURFACES 8
449
450 /*
451 * TTM.
452 */
453 struct radeon_mman {
454 struct ttm_device bdev;
455 bool initialized;
456 };
457
458 struct radeon_bo_list {
459 struct radeon_bo *robj;
460 struct ttm_validate_buffer tv;
461 uint64_t gpu_offset;
462 unsigned preferred_domains;
463 unsigned allowed_domains;
464 uint32_t tiling_flags;
465 };
466
467 /* bo virtual address in a specific vm */
468 struct radeon_bo_va {
469 /* protected by bo being reserved */
470 struct list_head bo_list;
471 uint32_t flags;
472 struct radeon_fence *last_pt_update;
473 unsigned ref_count;
474
475 /* protected by vm mutex */
476 struct interval_tree_node it;
477 struct list_head vm_status;
478
479 /* constant after initialization */
480 struct radeon_vm *vm;
481 struct radeon_bo *bo;
482 };
483
484 struct radeon_bo {
485 /* Protected by gem.mutex */
486 struct list_head list;
487 /* Protected by tbo.reserved */
488 u32 initial_domain;
489 struct ttm_place placements[4];
490 struct ttm_placement placement;
491 struct ttm_buffer_object tbo;
492 struct ttm_bo_kmap_obj kmap;
493 u32 flags;
494 void *kptr;
495 u32 tiling_flags;
496 u32 pitch;
497 int surface_reg;
498 unsigned prime_shared_count;
499 /* list of all virtual address to which this bo
500 * is associated to
501 */
502 struct list_head va;
503 /* Constant after initialization */
504 struct radeon_device *rdev;
505
506 pid_t pid;
507
508 #ifdef CONFIG_MMU_NOTIFIER
509 struct mmu_interval_notifier notifier;
510 #endif
511 };
512 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
513
514 /* sub-allocation manager, it has to be protected by another lock.
515 * By conception this is an helper for other part of the driver
516 * like the indirect buffer or semaphore, which both have their
517 * locking.
518 *
519 * Principe is simple, we keep a list of sub allocation in offset
520 * order (first entry has offset == 0, last entry has the highest
521 * offset).
522 *
523 * When allocating new object we first check if there is room at
524 * the end total_size - (last_object_offset + last_object_size) >=
525 * alloc_size. If so we allocate new object there.
526 *
527 * When there is not enough room at the end, we start waiting for
528 * each sub object until we reach object_offset+object_size >=
529 * alloc_size, this object then become the sub object we return.
530 *
531 * Alignment can't be bigger than page size.
532 *
533 * Hole are not considered for allocation to keep things simple.
534 * Assumption is that there won't be hole (all object on same
535 * alignment).
536 */
537 struct radeon_sa_manager {
538 wait_queue_head_t wq;
539 struct radeon_bo *bo;
540 struct list_head *hole;
541 struct list_head flist[RADEON_NUM_RINGS];
542 struct list_head olist;
543 unsigned size;
544 uint64_t gpu_addr;
545 void *cpu_ptr;
546 uint32_t domain;
547 uint32_t align;
548 };
549
550 struct radeon_sa_bo;
551
552 /* sub-allocation buffer */
553 struct radeon_sa_bo {
554 struct list_head olist;
555 struct list_head flist;
556 struct radeon_sa_manager *manager;
557 unsigned soffset;
558 unsigned eoffset;
559 struct radeon_fence *fence;
560 };
561
562 /*
563 * GEM objects.
564 */
565 struct radeon_gem {
566 struct mutex mutex;
567 struct list_head objects;
568 };
569
570 extern const struct drm_gem_object_funcs radeon_gem_object_funcs;
571
572 int radeon_gem_init(struct radeon_device *rdev);
573 void radeon_gem_fini(struct radeon_device *rdev);
574 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
575 int alignment, int initial_domain,
576 u32 flags, bool kernel,
577 struct drm_gem_object **obj);
578
579 int radeon_mode_dumb_create(struct drm_file *file_priv,
580 struct drm_device *dev,
581 struct drm_mode_create_dumb *args);
582 int radeon_mode_dumb_mmap(struct drm_file *filp,
583 struct drm_device *dev,
584 uint32_t handle, uint64_t *offset_p);
585
586 /*
587 * Semaphores.
588 */
589 struct radeon_semaphore {
590 struct radeon_sa_bo *sa_bo;
591 signed waiters;
592 uint64_t gpu_addr;
593 };
594
595 int radeon_semaphore_create(struct radeon_device *rdev,
596 struct radeon_semaphore **semaphore);
597 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
598 struct radeon_semaphore *semaphore);
599 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
600 struct radeon_semaphore *semaphore);
601 void radeon_semaphore_free(struct radeon_device *rdev,
602 struct radeon_semaphore **semaphore,
603 struct radeon_fence *fence);
604
605 /*
606 * Synchronization
607 */
608 struct radeon_sync {
609 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
610 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
611 struct radeon_fence *last_vm_update;
612 };
613
614 void radeon_sync_create(struct radeon_sync *sync);
615 void radeon_sync_fence(struct radeon_sync *sync,
616 struct radeon_fence *fence);
617 int radeon_sync_resv(struct radeon_device *rdev,
618 struct radeon_sync *sync,
619 struct dma_resv *resv,
620 bool shared);
621 int radeon_sync_rings(struct radeon_device *rdev,
622 struct radeon_sync *sync,
623 int waiting_ring);
624 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
625 struct radeon_fence *fence);
626
627 /*
628 * GART structures, functions & helpers
629 */
630 struct radeon_mc;
631
632 #define RADEON_GPU_PAGE_SIZE 4096
633 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
634 #define RADEON_GPU_PAGE_SHIFT 12
635 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
636
637 #define RADEON_GART_PAGE_DUMMY 0
638 #define RADEON_GART_PAGE_VALID (1 << 0)
639 #define RADEON_GART_PAGE_READ (1 << 1)
640 #define RADEON_GART_PAGE_WRITE (1 << 2)
641 #define RADEON_GART_PAGE_SNOOP (1 << 3)
642
643 struct radeon_gart {
644 dma_addr_t table_addr;
645 struct radeon_bo *robj;
646 void *ptr;
647 unsigned num_gpu_pages;
648 unsigned num_cpu_pages;
649 unsigned table_size;
650 struct page **pages;
651 uint64_t *pages_entry;
652 bool ready;
653 };
654
655 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
656 void radeon_gart_table_ram_free(struct radeon_device *rdev);
657 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
658 void radeon_gart_table_vram_free(struct radeon_device *rdev);
659 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
660 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
661 int radeon_gart_init(struct radeon_device *rdev);
662 void radeon_gart_fini(struct radeon_device *rdev);
663 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
664 int pages);
665 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
666 int pages, struct page **pagelist,
667 dma_addr_t *dma_addr, uint32_t flags);
668
669
670 /*
671 * GPU MC structures, functions & helpers
672 */
673 struct radeon_mc {
674 resource_size_t aper_size;
675 resource_size_t aper_base;
676 resource_size_t agp_base;
677 /* for some chips with <= 32MB we need to lie
678 * about vram size near mc fb location */
679 u64 mc_vram_size;
680 u64 visible_vram_size;
681 u64 gtt_size;
682 u64 gtt_start;
683 u64 gtt_end;
684 u64 vram_start;
685 u64 vram_end;
686 unsigned vram_width;
687 u64 real_vram_size;
688 int vram_mtrr;
689 bool vram_is_ddr;
690 bool igp_sideport_enabled;
691 u64 gtt_base_align;
692 u64 mc_mask;
693 };
694
695 bool radeon_combios_sideport_present(struct radeon_device *rdev);
696 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
697
698 /*
699 * GPU scratch registers structures, functions & helpers
700 */
701 struct radeon_scratch {
702 unsigned num_reg;
703 uint32_t reg_base;
704 bool free[32];
705 uint32_t reg[32];
706 };
707
708 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
709 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
710
711 /*
712 * GPU doorbell structures, functions & helpers
713 */
714 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
715
716 struct radeon_doorbell {
717 /* doorbell mmio */
718 resource_size_t base;
719 resource_size_t size;
720 u32 __iomem *ptr;
721 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
722 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
723 };
724
725 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
726 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
727
728 /*
729 * IRQS.
730 */
731
732 struct radeon_flip_work {
733 struct work_struct flip_work;
734 struct work_struct unpin_work;
735 struct radeon_device *rdev;
736 int crtc_id;
737 u32 target_vblank;
738 uint64_t base;
739 struct drm_pending_vblank_event *event;
740 struct radeon_bo *old_rbo;
741 struct dma_fence *fence;
742 bool async;
743 };
744
745 struct r500_irq_stat_regs {
746 u32 disp_int;
747 u32 hdmi0_status;
748 };
749
750 struct r600_irq_stat_regs {
751 u32 disp_int;
752 u32 disp_int_cont;
753 u32 disp_int_cont2;
754 u32 d1grph_int;
755 u32 d2grph_int;
756 u32 hdmi0_status;
757 u32 hdmi1_status;
758 };
759
760 struct evergreen_irq_stat_regs {
761 u32 disp_int[6];
762 u32 grph_int[6];
763 u32 afmt_status[6];
764 };
765
766 struct cik_irq_stat_regs {
767 u32 disp_int;
768 u32 disp_int_cont;
769 u32 disp_int_cont2;
770 u32 disp_int_cont3;
771 u32 disp_int_cont4;
772 u32 disp_int_cont5;
773 u32 disp_int_cont6;
774 u32 d1grph_int;
775 u32 d2grph_int;
776 u32 d3grph_int;
777 u32 d4grph_int;
778 u32 d5grph_int;
779 u32 d6grph_int;
780 };
781
782 union radeon_irq_stat_regs {
783 struct r500_irq_stat_regs r500;
784 struct r600_irq_stat_regs r600;
785 struct evergreen_irq_stat_regs evergreen;
786 struct cik_irq_stat_regs cik;
787 };
788
789 struct radeon_irq {
790 bool installed;
791 spinlock_t lock;
792 atomic_t ring_int[RADEON_NUM_RINGS];
793 bool crtc_vblank_int[RADEON_MAX_CRTCS];
794 atomic_t pflip[RADEON_MAX_CRTCS];
795 wait_queue_head_t vblank_queue;
796 bool hpd[RADEON_MAX_HPD_PINS];
797 bool afmt[RADEON_MAX_AFMT_BLOCKS];
798 union radeon_irq_stat_regs stat_regs;
799 bool dpm_thermal;
800 };
801
802 int radeon_irq_kms_init(struct radeon_device *rdev);
803 void radeon_irq_kms_fini(struct radeon_device *rdev);
804 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
805 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
806 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
807 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
808 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
809 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
810 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
811 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
812 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
813
814 /*
815 * CP & rings.
816 */
817
818 struct radeon_ib {
819 struct radeon_sa_bo *sa_bo;
820 uint32_t length_dw;
821 uint64_t gpu_addr;
822 uint32_t *ptr;
823 int ring;
824 struct radeon_fence *fence;
825 struct radeon_vm *vm;
826 bool is_const_ib;
827 struct radeon_sync sync;
828 };
829
830 struct radeon_ring {
831 struct radeon_device *rdev;
832 struct radeon_bo *ring_obj;
833 volatile uint32_t *ring;
834 unsigned rptr_offs;
835 unsigned rptr_save_reg;
836 u64 next_rptr_gpu_addr;
837 volatile u32 *next_rptr_cpu_addr;
838 unsigned wptr;
839 unsigned wptr_old;
840 unsigned ring_size;
841 unsigned ring_free_dw;
842 int count_dw;
843 atomic_t last_rptr;
844 atomic64_t last_activity;
845 uint64_t gpu_addr;
846 uint32_t align_mask;
847 uint32_t ptr_mask;
848 bool ready;
849 u32 nop;
850 u32 idx;
851 u64 last_semaphore_signal_addr;
852 u64 last_semaphore_wait_addr;
853 /* for CIK queues */
854 u32 me;
855 u32 pipe;
856 u32 queue;
857 struct radeon_bo *mqd_obj;
858 u32 doorbell_index;
859 unsigned wptr_offs;
860 };
861
862 struct radeon_mec {
863 struct radeon_bo *hpd_eop_obj;
864 u64 hpd_eop_gpu_addr;
865 u32 num_pipe;
866 u32 num_mec;
867 u32 num_queue;
868 };
869
870 /*
871 * VM
872 */
873
874 /* maximum number of VMIDs */
875 #define RADEON_NUM_VM 16
876
877 /* number of entries in page table */
878 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
879
880 /* PTBs (Page Table Blocks) need to be aligned to 32K */
881 #define RADEON_VM_PTB_ALIGN_SIZE 32768
882 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
883 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
884
885 #define R600_PTE_VALID (1 << 0)
886 #define R600_PTE_SYSTEM (1 << 1)
887 #define R600_PTE_SNOOPED (1 << 2)
888 #define R600_PTE_READABLE (1 << 5)
889 #define R600_PTE_WRITEABLE (1 << 6)
890
891 /* PTE (Page Table Entry) fragment field for different page sizes */
892 #define R600_PTE_FRAG_4KB (0 << 7)
893 #define R600_PTE_FRAG_64KB (4 << 7)
894 #define R600_PTE_FRAG_256KB (6 << 7)
895
896 /* flags needed to be set so we can copy directly from the GART table */
897 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
898 R600_PTE_SYSTEM | R600_PTE_VALID )
899
900 struct radeon_vm_pt {
901 struct radeon_bo *bo;
902 uint64_t addr;
903 };
904
905 struct radeon_vm_id {
906 unsigned id;
907 uint64_t pd_gpu_addr;
908 /* last flushed PD/PT update */
909 struct radeon_fence *flushed_updates;
910 /* last use of vmid */
911 struct radeon_fence *last_id_use;
912 };
913
914 struct radeon_vm {
915 struct mutex mutex;
916
917 struct rb_root_cached va;
918
919 /* protecting invalidated and freed */
920 spinlock_t status_lock;
921
922 /* BOs moved, but not yet updated in the PT */
923 struct list_head invalidated;
924
925 /* BOs freed, but not yet updated in the PT */
926 struct list_head freed;
927
928 /* BOs cleared in the PT */
929 struct list_head cleared;
930
931 /* contains the page directory */
932 struct radeon_bo *page_directory;
933 unsigned max_pde_used;
934
935 /* array of page tables, one for each page directory entry */
936 struct radeon_vm_pt *page_tables;
937
938 struct radeon_bo_va *ib_bo_va;
939
940 /* for id and flush management per ring */
941 struct radeon_vm_id ids[RADEON_NUM_RINGS];
942 };
943
944 struct radeon_vm_manager {
945 struct radeon_fence *active[RADEON_NUM_VM];
946 uint32_t max_pfn;
947 /* number of VMIDs */
948 unsigned nvm;
949 /* vram base address for page table entry */
950 u64 vram_base_offset;
951 /* is vm enabled? */
952 bool enabled;
953 /* for hw to save the PD addr on suspend/resume */
954 uint32_t saved_table_addr[RADEON_NUM_VM];
955 };
956
957 /*
958 * file private structure
959 */
960 struct radeon_fpriv {
961 struct radeon_vm vm;
962 };
963
964 /*
965 * R6xx+ IH ring
966 */
967 struct r600_ih {
968 struct radeon_bo *ring_obj;
969 volatile uint32_t *ring;
970 unsigned rptr;
971 unsigned ring_size;
972 uint64_t gpu_addr;
973 uint32_t ptr_mask;
974 atomic_t lock;
975 bool enabled;
976 };
977
978 /*
979 * RLC stuff
980 */
981 #include "clearstate_defs.h"
982
983 struct radeon_rlc {
984 /* for power gating */
985 struct radeon_bo *save_restore_obj;
986 uint64_t save_restore_gpu_addr;
987 volatile uint32_t *sr_ptr;
988 const u32 *reg_list;
989 u32 reg_list_size;
990 /* for clear state */
991 struct radeon_bo *clear_state_obj;
992 uint64_t clear_state_gpu_addr;
993 volatile uint32_t *cs_ptr;
994 const struct cs_section_def *cs_data;
995 u32 clear_state_size;
996 /* for cp tables */
997 struct radeon_bo *cp_table_obj;
998 uint64_t cp_table_gpu_addr;
999 volatile uint32_t *cp_table_ptr;
1000 u32 cp_table_size;
1001 };
1002
1003 int radeon_ib_get(struct radeon_device *rdev, int ring,
1004 struct radeon_ib *ib, struct radeon_vm *vm,
1005 unsigned size);
1006 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1007 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1008 struct radeon_ib *const_ib, bool hdp_flush);
1009 int radeon_ib_pool_init(struct radeon_device *rdev);
1010 void radeon_ib_pool_fini(struct radeon_device *rdev);
1011 int radeon_ib_ring_tests(struct radeon_device *rdev);
1012 /* Ring access between begin & end cannot sleep */
1013 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1014 struct radeon_ring *ring);
1015 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1016 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1017 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1018 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1019 bool hdp_flush);
1020 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1021 bool hdp_flush);
1022 void radeon_ring_undo(struct radeon_ring *ring);
1023 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1024 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1025 void radeon_ring_lockup_update(struct radeon_device *rdev,
1026 struct radeon_ring *ring);
1027 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1028 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1029 uint32_t **data);
1030 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1031 unsigned size, uint32_t *data);
1032 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1033 unsigned rptr_offs, u32 nop);
1034 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1035
1036
1037 /* r600 async dma */
1038 void r600_dma_stop(struct radeon_device *rdev);
1039 int r600_dma_resume(struct radeon_device *rdev);
1040 void r600_dma_fini(struct radeon_device *rdev);
1041
1042 void cayman_dma_stop(struct radeon_device *rdev);
1043 int cayman_dma_resume(struct radeon_device *rdev);
1044 void cayman_dma_fini(struct radeon_device *rdev);
1045
1046 /*
1047 * CS.
1048 */
1049 struct radeon_cs_chunk {
1050 uint32_t length_dw;
1051 uint32_t *kdata;
1052 void __user *user_ptr;
1053 };
1054
1055 struct radeon_cs_parser {
1056 struct device *dev;
1057 struct radeon_device *rdev;
1058 struct drm_file *filp;
1059 /* chunks */
1060 unsigned nchunks;
1061 struct radeon_cs_chunk *chunks;
1062 uint64_t *chunks_array;
1063 /* IB */
1064 unsigned idx;
1065 /* relocations */
1066 unsigned nrelocs;
1067 struct radeon_bo_list *relocs;
1068 struct radeon_bo_list *vm_bos;
1069 struct list_head validated;
1070 unsigned dma_reloc_idx;
1071 /* indices of various chunks */
1072 struct radeon_cs_chunk *chunk_ib;
1073 struct radeon_cs_chunk *chunk_relocs;
1074 struct radeon_cs_chunk *chunk_flags;
1075 struct radeon_cs_chunk *chunk_const_ib;
1076 struct radeon_ib ib;
1077 struct radeon_ib const_ib;
1078 void *track;
1079 unsigned family;
1080 int parser_error;
1081 u32 cs_flags;
1082 u32 ring;
1083 s32 priority;
1084 struct ww_acquire_ctx ticket;
1085 };
1086
1087 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1088 {
1089 struct radeon_cs_chunk *ibc = p->chunk_ib;
1090
1091 if (ibc->kdata)
1092 return ibc->kdata[idx];
1093 return p->ib.ptr[idx];
1094 }
1095
1096
1097 struct radeon_cs_packet {
1098 unsigned idx;
1099 unsigned type;
1100 unsigned reg;
1101 unsigned opcode;
1102 int count;
1103 unsigned one_reg_wr;
1104 };
1105
1106 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1107 struct radeon_cs_packet *pkt,
1108 unsigned idx, unsigned reg);
1109
1110 /*
1111 * AGP
1112 */
1113 int radeon_agp_init(struct radeon_device *rdev);
1114 void radeon_agp_resume(struct radeon_device *rdev);
1115 void radeon_agp_suspend(struct radeon_device *rdev);
1116 void radeon_agp_fini(struct radeon_device *rdev);
1117
1118
1119 /*
1120 * Writeback
1121 */
1122 struct radeon_wb {
1123 struct radeon_bo *wb_obj;
1124 volatile uint32_t *wb;
1125 uint64_t gpu_addr;
1126 bool enabled;
1127 bool use_event;
1128 };
1129
1130 #define RADEON_WB_SCRATCH_OFFSET 0
1131 #define RADEON_WB_RING0_NEXT_RPTR 256
1132 #define RADEON_WB_CP_RPTR_OFFSET 1024
1133 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1134 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1135 #define R600_WB_DMA_RPTR_OFFSET 1792
1136 #define R600_WB_IH_WPTR_OFFSET 2048
1137 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1138 #define R600_WB_EVENT_OFFSET 3072
1139 #define CIK_WB_CP1_WPTR_OFFSET 3328
1140 #define CIK_WB_CP2_WPTR_OFFSET 3584
1141 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1142 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1143
1144 /**
1145 * struct radeon_pm - power management datas
1146 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1147 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1148 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1149 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1150 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1151 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1152 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1153 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1154 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1155 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1156 * @needed_bandwidth: current bandwidth needs
1157 *
1158 * It keeps track of various data needed to take powermanagement decision.
1159 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1160 * Equation between gpu/memory clock and available bandwidth is hw dependent
1161 * (type of memory, bus size, efficiency, ...)
1162 */
1163
1164 enum radeon_pm_method {
1165 PM_METHOD_PROFILE,
1166 PM_METHOD_DYNPM,
1167 PM_METHOD_DPM,
1168 };
1169
1170 enum radeon_dynpm_state {
1171 DYNPM_STATE_DISABLED,
1172 DYNPM_STATE_MINIMUM,
1173 DYNPM_STATE_PAUSED,
1174 DYNPM_STATE_ACTIVE,
1175 DYNPM_STATE_SUSPENDED,
1176 };
1177 enum radeon_dynpm_action {
1178 DYNPM_ACTION_NONE,
1179 DYNPM_ACTION_MINIMUM,
1180 DYNPM_ACTION_DOWNCLOCK,
1181 DYNPM_ACTION_UPCLOCK,
1182 DYNPM_ACTION_DEFAULT
1183 };
1184
1185 enum radeon_voltage_type {
1186 VOLTAGE_NONE = 0,
1187 VOLTAGE_GPIO,
1188 VOLTAGE_VDDC,
1189 VOLTAGE_SW
1190 };
1191
1192 enum radeon_pm_state_type {
1193 /* not used for dpm */
1194 POWER_STATE_TYPE_DEFAULT,
1195 POWER_STATE_TYPE_POWERSAVE,
1196 /* user selectable states */
1197 POWER_STATE_TYPE_BATTERY,
1198 POWER_STATE_TYPE_BALANCED,
1199 POWER_STATE_TYPE_PERFORMANCE,
1200 /* internal states */
1201 POWER_STATE_TYPE_INTERNAL_UVD,
1202 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1203 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1204 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1205 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1206 POWER_STATE_TYPE_INTERNAL_BOOT,
1207 POWER_STATE_TYPE_INTERNAL_THERMAL,
1208 POWER_STATE_TYPE_INTERNAL_ACPI,
1209 POWER_STATE_TYPE_INTERNAL_ULV,
1210 POWER_STATE_TYPE_INTERNAL_3DPERF,
1211 };
1212
1213 enum radeon_pm_profile_type {
1214 PM_PROFILE_DEFAULT,
1215 PM_PROFILE_AUTO,
1216 PM_PROFILE_LOW,
1217 PM_PROFILE_MID,
1218 PM_PROFILE_HIGH,
1219 };
1220
1221 #define PM_PROFILE_DEFAULT_IDX 0
1222 #define PM_PROFILE_LOW_SH_IDX 1
1223 #define PM_PROFILE_MID_SH_IDX 2
1224 #define PM_PROFILE_HIGH_SH_IDX 3
1225 #define PM_PROFILE_LOW_MH_IDX 4
1226 #define PM_PROFILE_MID_MH_IDX 5
1227 #define PM_PROFILE_HIGH_MH_IDX 6
1228 #define PM_PROFILE_MAX 7
1229
1230 struct radeon_pm_profile {
1231 int dpms_off_ps_idx;
1232 int dpms_on_ps_idx;
1233 int dpms_off_cm_idx;
1234 int dpms_on_cm_idx;
1235 };
1236
1237 enum radeon_int_thermal_type {
1238 THERMAL_TYPE_NONE,
1239 THERMAL_TYPE_EXTERNAL,
1240 THERMAL_TYPE_EXTERNAL_GPIO,
1241 THERMAL_TYPE_RV6XX,
1242 THERMAL_TYPE_RV770,
1243 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1244 THERMAL_TYPE_EVERGREEN,
1245 THERMAL_TYPE_SUMO,
1246 THERMAL_TYPE_NI,
1247 THERMAL_TYPE_SI,
1248 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1249 THERMAL_TYPE_CI,
1250 THERMAL_TYPE_KV,
1251 };
1252
1253 struct radeon_voltage {
1254 enum radeon_voltage_type type;
1255 /* gpio voltage */
1256 struct radeon_gpio_rec gpio;
1257 u32 delay; /* delay in usec from voltage drop to sclk change */
1258 bool active_high; /* voltage drop is active when bit is high */
1259 /* VDDC voltage */
1260 u8 vddc_id; /* index into vddc voltage table */
1261 u8 vddci_id; /* index into vddci voltage table */
1262 bool vddci_enabled;
1263 /* r6xx+ sw */
1264 u16 voltage;
1265 /* evergreen+ vddci */
1266 u16 vddci;
1267 };
1268
1269 /* clock mode flags */
1270 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1271
1272 struct radeon_pm_clock_info {
1273 /* memory clock */
1274 u32 mclk;
1275 /* engine clock */
1276 u32 sclk;
1277 /* voltage info */
1278 struct radeon_voltage voltage;
1279 /* standardized clock flags */
1280 u32 flags;
1281 };
1282
1283 /* state flags */
1284 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1285
1286 struct radeon_power_state {
1287 enum radeon_pm_state_type type;
1288 struct radeon_pm_clock_info *clock_info;
1289 /* number of valid clock modes in this power state */
1290 int num_clock_modes;
1291 struct radeon_pm_clock_info *default_clock_mode;
1292 /* standardized state flags */
1293 u32 flags;
1294 u32 misc; /* vbios specific flags */
1295 u32 misc2; /* vbios specific flags */
1296 int pcie_lanes; /* pcie lanes */
1297 };
1298
1299 /*
1300 * Some modes are overclocked by very low value, accept them
1301 */
1302 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1303
1304 enum radeon_dpm_auto_throttle_src {
1305 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1306 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1307 };
1308
1309 enum radeon_dpm_event_src {
1310 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1311 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1312 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1313 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1314 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1315 };
1316
1317 #define RADEON_MAX_VCE_LEVELS 6
1318
1319 enum radeon_vce_level {
1320 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1321 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1322 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1323 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1324 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1325 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1326 };
1327
1328 struct radeon_ps {
1329 u32 caps; /* vbios flags */
1330 u32 class; /* vbios flags */
1331 u32 class2; /* vbios flags */
1332 /* UVD clocks */
1333 u32 vclk;
1334 u32 dclk;
1335 /* VCE clocks */
1336 u32 evclk;
1337 u32 ecclk;
1338 bool vce_active;
1339 enum radeon_vce_level vce_level;
1340 /* asic priv */
1341 void *ps_priv;
1342 };
1343
1344 struct radeon_dpm_thermal {
1345 /* thermal interrupt work */
1346 struct work_struct work;
1347 /* low temperature threshold */
1348 int min_temp;
1349 /* high temperature threshold */
1350 int max_temp;
1351 /* was interrupt low to high or high to low */
1352 bool high_to_low;
1353 };
1354
1355 enum radeon_clk_action
1356 {
1357 RADEON_SCLK_UP = 1,
1358 RADEON_SCLK_DOWN
1359 };
1360
1361 struct radeon_blacklist_clocks
1362 {
1363 u32 sclk;
1364 u32 mclk;
1365 enum radeon_clk_action action;
1366 };
1367
1368 struct radeon_clock_and_voltage_limits {
1369 u32 sclk;
1370 u32 mclk;
1371 u16 vddc;
1372 u16 vddci;
1373 };
1374
1375 struct radeon_clock_array {
1376 u32 count;
1377 u32 *values;
1378 };
1379
1380 struct radeon_clock_voltage_dependency_entry {
1381 u32 clk;
1382 u16 v;
1383 };
1384
1385 struct radeon_clock_voltage_dependency_table {
1386 u32 count;
1387 struct radeon_clock_voltage_dependency_entry *entries;
1388 };
1389
1390 union radeon_cac_leakage_entry {
1391 struct {
1392 u16 vddc;
1393 u32 leakage;
1394 };
1395 struct {
1396 u16 vddc1;
1397 u16 vddc2;
1398 u16 vddc3;
1399 };
1400 };
1401
1402 struct radeon_cac_leakage_table {
1403 u32 count;
1404 union radeon_cac_leakage_entry *entries;
1405 };
1406
1407 struct radeon_phase_shedding_limits_entry {
1408 u16 voltage;
1409 u32 sclk;
1410 u32 mclk;
1411 };
1412
1413 struct radeon_phase_shedding_limits_table {
1414 u32 count;
1415 struct radeon_phase_shedding_limits_entry *entries;
1416 };
1417
1418 struct radeon_uvd_clock_voltage_dependency_entry {
1419 u32 vclk;
1420 u32 dclk;
1421 u16 v;
1422 };
1423
1424 struct radeon_uvd_clock_voltage_dependency_table {
1425 u8 count;
1426 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1427 };
1428
1429 struct radeon_vce_clock_voltage_dependency_entry {
1430 u32 ecclk;
1431 u32 evclk;
1432 u16 v;
1433 };
1434
1435 struct radeon_vce_clock_voltage_dependency_table {
1436 u8 count;
1437 struct radeon_vce_clock_voltage_dependency_entry *entries;
1438 };
1439
1440 struct radeon_ppm_table {
1441 u8 ppm_design;
1442 u16 cpu_core_number;
1443 u32 platform_tdp;
1444 u32 small_ac_platform_tdp;
1445 u32 platform_tdc;
1446 u32 small_ac_platform_tdc;
1447 u32 apu_tdp;
1448 u32 dgpu_tdp;
1449 u32 dgpu_ulv_power;
1450 u32 tj_max;
1451 };
1452
1453 struct radeon_cac_tdp_table {
1454 u16 tdp;
1455 u16 configurable_tdp;
1456 u16 tdc;
1457 u16 battery_power_limit;
1458 u16 small_power_limit;
1459 u16 low_cac_leakage;
1460 u16 high_cac_leakage;
1461 u16 maximum_power_delivery_limit;
1462 };
1463
1464 struct radeon_dpm_dynamic_state {
1465 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1466 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1467 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1468 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1469 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1470 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1471 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1472 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1473 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1474 struct radeon_clock_array valid_sclk_values;
1475 struct radeon_clock_array valid_mclk_values;
1476 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1477 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1478 u32 mclk_sclk_ratio;
1479 u32 sclk_mclk_delta;
1480 u16 vddc_vddci_delta;
1481 u16 min_vddc_for_pcie_gen2;
1482 struct radeon_cac_leakage_table cac_leakage_table;
1483 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1484 struct radeon_ppm_table *ppm_table;
1485 struct radeon_cac_tdp_table *cac_tdp_table;
1486 };
1487
1488 struct radeon_dpm_fan {
1489 u16 t_min;
1490 u16 t_med;
1491 u16 t_high;
1492 u16 pwm_min;
1493 u16 pwm_med;
1494 u16 pwm_high;
1495 u8 t_hyst;
1496 u32 cycle_delay;
1497 u16 t_max;
1498 u8 control_mode;
1499 u16 default_max_fan_pwm;
1500 u16 default_fan_output_sensitivity;
1501 u16 fan_output_sensitivity;
1502 bool ucode_fan_control;
1503 };
1504
1505 enum radeon_pcie_gen {
1506 RADEON_PCIE_GEN1 = 0,
1507 RADEON_PCIE_GEN2 = 1,
1508 RADEON_PCIE_GEN3 = 2,
1509 RADEON_PCIE_GEN_INVALID = 0xffff
1510 };
1511
1512 enum radeon_dpm_forced_level {
1513 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1514 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1515 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1516 };
1517
1518 struct radeon_vce_state {
1519 /* vce clocks */
1520 u32 evclk;
1521 u32 ecclk;
1522 /* gpu clocks */
1523 u32 sclk;
1524 u32 mclk;
1525 u8 clk_idx;
1526 u8 pstate;
1527 };
1528
1529 struct radeon_dpm {
1530 struct radeon_ps *ps;
1531 /* number of valid power states */
1532 int num_ps;
1533 /* current power state that is active */
1534 struct radeon_ps *current_ps;
1535 /* requested power state */
1536 struct radeon_ps *requested_ps;
1537 /* boot up power state */
1538 struct radeon_ps *boot_ps;
1539 /* default uvd power state */
1540 struct radeon_ps *uvd_ps;
1541 /* vce requirements */
1542 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1543 enum radeon_vce_level vce_level;
1544 enum radeon_pm_state_type state;
1545 enum radeon_pm_state_type user_state;
1546 u32 platform_caps;
1547 u32 voltage_response_time;
1548 u32 backbias_response_time;
1549 void *priv;
1550 u32 new_active_crtcs;
1551 int new_active_crtc_count;
1552 int high_pixelclock_count;
1553 u32 current_active_crtcs;
1554 int current_active_crtc_count;
1555 bool single_display;
1556 struct radeon_dpm_dynamic_state dyn_state;
1557 struct radeon_dpm_fan fan;
1558 u32 tdp_limit;
1559 u32 near_tdp_limit;
1560 u32 near_tdp_limit_adjusted;
1561 u32 sq_ramping_threshold;
1562 u32 cac_leakage;
1563 u16 tdp_od_limit;
1564 u32 tdp_adjustment;
1565 u16 load_line_slope;
1566 bool power_control;
1567 bool ac_power;
1568 /* special states active */
1569 bool thermal_active;
1570 bool uvd_active;
1571 bool vce_active;
1572 /* thermal handling */
1573 struct radeon_dpm_thermal thermal;
1574 /* forced levels */
1575 enum radeon_dpm_forced_level forced_level;
1576 /* track UVD streams */
1577 unsigned sd;
1578 unsigned hd;
1579 };
1580
1581 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1582 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1583
1584 struct radeon_pm {
1585 struct mutex mutex;
1586 /* write locked while reprogramming mclk */
1587 struct rw_semaphore mclk_lock;
1588 u32 active_crtcs;
1589 int active_crtc_count;
1590 int req_vblank;
1591 bool vblank_sync;
1592 fixed20_12 max_bandwidth;
1593 fixed20_12 igp_sideport_mclk;
1594 fixed20_12 igp_system_mclk;
1595 fixed20_12 igp_ht_link_clk;
1596 fixed20_12 igp_ht_link_width;
1597 fixed20_12 k8_bandwidth;
1598 fixed20_12 sideport_bandwidth;
1599 fixed20_12 ht_bandwidth;
1600 fixed20_12 core_bandwidth;
1601 fixed20_12 sclk;
1602 fixed20_12 mclk;
1603 fixed20_12 needed_bandwidth;
1604 struct radeon_power_state *power_state;
1605 /* number of valid power states */
1606 int num_power_states;
1607 int current_power_state_index;
1608 int current_clock_mode_index;
1609 int requested_power_state_index;
1610 int requested_clock_mode_index;
1611 int default_power_state_index;
1612 u32 current_sclk;
1613 u32 current_mclk;
1614 u16 current_vddc;
1615 u16 current_vddci;
1616 u32 default_sclk;
1617 u32 default_mclk;
1618 u16 default_vddc;
1619 u16 default_vddci;
1620 struct radeon_i2c_chan *i2c_bus;
1621 /* selected pm method */
1622 enum radeon_pm_method pm_method;
1623 /* dynpm power management */
1624 struct delayed_work dynpm_idle_work;
1625 enum radeon_dynpm_state dynpm_state;
1626 enum radeon_dynpm_action dynpm_planned_action;
1627 unsigned long dynpm_action_timeout;
1628 bool dynpm_can_upclock;
1629 bool dynpm_can_downclock;
1630 /* profile-based power management */
1631 enum radeon_pm_profile_type profile;
1632 int profile_index;
1633 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1634 /* internal thermal controller on rv6xx+ */
1635 enum radeon_int_thermal_type int_thermal_type;
1636 struct device *int_hwmon_dev;
1637 /* fan control parameters */
1638 bool no_fan;
1639 u8 fan_pulses_per_revolution;
1640 u8 fan_min_rpm;
1641 u8 fan_max_rpm;
1642 /* dpm */
1643 bool dpm_enabled;
1644 bool sysfs_initialized;
1645 struct radeon_dpm dpm;
1646 };
1647
1648 #define RADEON_PCIE_SPEED_25 1
1649 #define RADEON_PCIE_SPEED_50 2
1650 #define RADEON_PCIE_SPEED_80 4
1651
1652 int radeon_pm_get_type_index(struct radeon_device *rdev,
1653 enum radeon_pm_state_type ps_type,
1654 int instance);
1655 /*
1656 * UVD
1657 */
1658 #define RADEON_DEFAULT_UVD_HANDLES 10
1659 #define RADEON_MAX_UVD_HANDLES 30
1660 #define RADEON_UVD_STACK_SIZE (200*1024)
1661 #define RADEON_UVD_HEAP_SIZE (256*1024)
1662 #define RADEON_UVD_SESSION_SIZE (50*1024)
1663
1664 struct radeon_uvd {
1665 bool fw_header_present;
1666 struct radeon_bo *vcpu_bo;
1667 void *cpu_addr;
1668 uint64_t gpu_addr;
1669 unsigned max_handles;
1670 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1671 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1672 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1673 struct delayed_work idle_work;
1674 };
1675
1676 int radeon_uvd_init(struct radeon_device *rdev);
1677 void radeon_uvd_fini(struct radeon_device *rdev);
1678 int radeon_uvd_suspend(struct radeon_device *rdev);
1679 int radeon_uvd_resume(struct radeon_device *rdev);
1680 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1681 uint32_t handle, struct radeon_fence **fence);
1682 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1683 uint32_t handle, struct radeon_fence **fence);
1684 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1685 uint32_t allowed_domains);
1686 void radeon_uvd_free_handles(struct radeon_device *rdev,
1687 struct drm_file *filp);
1688 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1689 void radeon_uvd_note_usage(struct radeon_device *rdev);
1690 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1691 unsigned vclk, unsigned dclk,
1692 unsigned vco_min, unsigned vco_max,
1693 unsigned fb_factor, unsigned fb_mask,
1694 unsigned pd_min, unsigned pd_max,
1695 unsigned pd_even,
1696 unsigned *optimal_fb_div,
1697 unsigned *optimal_vclk_div,
1698 unsigned *optimal_dclk_div);
1699 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1700 unsigned cg_upll_func_cntl);
1701
1702 /*
1703 * VCE
1704 */
1705 #define RADEON_MAX_VCE_HANDLES 16
1706
1707 struct radeon_vce {
1708 struct radeon_bo *vcpu_bo;
1709 uint64_t gpu_addr;
1710 unsigned fw_version;
1711 unsigned fb_version;
1712 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1713 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1714 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1715 struct delayed_work idle_work;
1716 uint32_t keyselect;
1717 };
1718
1719 int radeon_vce_init(struct radeon_device *rdev);
1720 void radeon_vce_fini(struct radeon_device *rdev);
1721 int radeon_vce_suspend(struct radeon_device *rdev);
1722 int radeon_vce_resume(struct radeon_device *rdev);
1723 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1724 uint32_t handle, struct radeon_fence **fence);
1725 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1726 uint32_t handle, struct radeon_fence **fence);
1727 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1728 void radeon_vce_note_usage(struct radeon_device *rdev);
1729 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1730 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1731 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1732 struct radeon_ring *ring,
1733 struct radeon_semaphore *semaphore,
1734 bool emit_wait);
1735 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1736 void radeon_vce_fence_emit(struct radeon_device *rdev,
1737 struct radeon_fence *fence);
1738 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1739 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1740
1741 struct r600_audio_pin {
1742 int channels;
1743 int rate;
1744 int bits_per_sample;
1745 u8 status_bits;
1746 u8 category_code;
1747 u32 offset;
1748 bool connected;
1749 u32 id;
1750 };
1751
1752 struct r600_audio {
1753 bool enabled;
1754 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1755 int num_pins;
1756 struct radeon_audio_funcs *hdmi_funcs;
1757 struct radeon_audio_funcs *dp_funcs;
1758 struct radeon_audio_basic_funcs *funcs;
1759 };
1760
1761 /*
1762 * Benchmarking
1763 */
1764 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1765
1766
1767 /*
1768 * Testing
1769 */
1770 void radeon_test_moves(struct radeon_device *rdev);
1771 void radeon_test_ring_sync(struct radeon_device *rdev,
1772 struct radeon_ring *cpA,
1773 struct radeon_ring *cpB);
1774 void radeon_test_syncing(struct radeon_device *rdev);
1775
1776 /*
1777 * MMU Notifier
1778 */
1779 #if defined(CONFIG_MMU_NOTIFIER)
1780 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1781 void radeon_mn_unregister(struct radeon_bo *bo);
1782 #else
1783 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1784 {
1785 return -ENODEV;
1786 }
1787 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1788 #endif
1789
1790 /*
1791 * Debugfs
1792 */
1793 void radeon_debugfs_fence_init(struct radeon_device *rdev);
1794 void radeon_gem_debugfs_init(struct radeon_device *rdev);
1795
1796 /*
1797 * ASIC ring specific functions.
1798 */
1799 struct radeon_asic_ring {
1800 /* ring read/write ptr handling */
1801 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1802 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1803 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1804
1805 /* validating and patching of IBs */
1806 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1807 int (*cs_parse)(struct radeon_cs_parser *p);
1808
1809 /* command emmit functions */
1810 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1811 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1812 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1813 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1814 struct radeon_semaphore *semaphore, bool emit_wait);
1815 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1816 unsigned vm_id, uint64_t pd_addr);
1817
1818 /* testing functions */
1819 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1820 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1821 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1822
1823 /* deprecated */
1824 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1825 };
1826
1827 /*
1828 * ASIC specific functions.
1829 */
1830 struct radeon_asic {
1831 int (*init)(struct radeon_device *rdev);
1832 void (*fini)(struct radeon_device *rdev);
1833 int (*resume)(struct radeon_device *rdev);
1834 int (*suspend)(struct radeon_device *rdev);
1835 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1836 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1837 /* Flush the HDP cache via MMIO */
1838 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1839 /* check if 3D engine is idle */
1840 bool (*gui_idle)(struct radeon_device *rdev);
1841 /* wait for mc_idle */
1842 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1843 /* get the reference clock */
1844 u32 (*get_xclk)(struct radeon_device *rdev);
1845 /* get the gpu clock counter */
1846 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1847 /* get register for info ioctl */
1848 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1849 /* gart */
1850 struct {
1851 void (*tlb_flush)(struct radeon_device *rdev);
1852 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1853 void (*set_page)(struct radeon_device *rdev, unsigned i,
1854 uint64_t entry);
1855 } gart;
1856 struct {
1857 int (*init)(struct radeon_device *rdev);
1858 void (*fini)(struct radeon_device *rdev);
1859 void (*copy_pages)(struct radeon_device *rdev,
1860 struct radeon_ib *ib,
1861 uint64_t pe, uint64_t src,
1862 unsigned count);
1863 void (*write_pages)(struct radeon_device *rdev,
1864 struct radeon_ib *ib,
1865 uint64_t pe,
1866 uint64_t addr, unsigned count,
1867 uint32_t incr, uint32_t flags);
1868 void (*set_pages)(struct radeon_device *rdev,
1869 struct radeon_ib *ib,
1870 uint64_t pe,
1871 uint64_t addr, unsigned count,
1872 uint32_t incr, uint32_t flags);
1873 void (*pad_ib)(struct radeon_ib *ib);
1874 } vm;
1875 /* ring specific callbacks */
1876 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1877 /* irqs */
1878 struct {
1879 int (*set)(struct radeon_device *rdev);
1880 int (*process)(struct radeon_device *rdev);
1881 } irq;
1882 /* displays */
1883 struct {
1884 /* display watermarks */
1885 void (*bandwidth_update)(struct radeon_device *rdev);
1886 /* get frame count */
1887 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1888 /* wait for vblank */
1889 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1890 /* set backlight level */
1891 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1892 /* get backlight level */
1893 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1894 /* audio callbacks */
1895 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1896 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1897 } display;
1898 /* copy functions for bo handling */
1899 struct {
1900 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1901 uint64_t src_offset,
1902 uint64_t dst_offset,
1903 unsigned num_gpu_pages,
1904 struct dma_resv *resv);
1905 u32 blit_ring_index;
1906 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1907 uint64_t src_offset,
1908 uint64_t dst_offset,
1909 unsigned num_gpu_pages,
1910 struct dma_resv *resv);
1911 u32 dma_ring_index;
1912 /* method used for bo copy */
1913 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1914 uint64_t src_offset,
1915 uint64_t dst_offset,
1916 unsigned num_gpu_pages,
1917 struct dma_resv *resv);
1918 /* ring used for bo copies */
1919 u32 copy_ring_index;
1920 } copy;
1921 /* surfaces */
1922 struct {
1923 int (*set_reg)(struct radeon_device *rdev, int reg,
1924 uint32_t tiling_flags, uint32_t pitch,
1925 uint32_t offset, uint32_t obj_size);
1926 void (*clear_reg)(struct radeon_device *rdev, int reg);
1927 } surface;
1928 /* hotplug detect */
1929 struct {
1930 void (*init)(struct radeon_device *rdev);
1931 void (*fini)(struct radeon_device *rdev);
1932 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1933 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1934 } hpd;
1935 /* static power management */
1936 struct {
1937 void (*misc)(struct radeon_device *rdev);
1938 void (*prepare)(struct radeon_device *rdev);
1939 void (*finish)(struct radeon_device *rdev);
1940 void (*init_profile)(struct radeon_device *rdev);
1941 void (*get_dynpm_state)(struct radeon_device *rdev);
1942 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1943 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1944 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1945 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1946 int (*get_pcie_lanes)(struct radeon_device *rdev);
1947 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1948 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1949 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1950 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1951 int (*get_temperature)(struct radeon_device *rdev);
1952 } pm;
1953 /* dynamic power management */
1954 struct {
1955 int (*init)(struct radeon_device *rdev);
1956 void (*setup_asic)(struct radeon_device *rdev);
1957 int (*enable)(struct radeon_device *rdev);
1958 int (*late_enable)(struct radeon_device *rdev);
1959 void (*disable)(struct radeon_device *rdev);
1960 int (*pre_set_power_state)(struct radeon_device *rdev);
1961 int (*set_power_state)(struct radeon_device *rdev);
1962 void (*post_set_power_state)(struct radeon_device *rdev);
1963 void (*display_configuration_changed)(struct radeon_device *rdev);
1964 void (*fini)(struct radeon_device *rdev);
1965 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1966 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1967 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1968 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1969 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1970 bool (*vblank_too_short)(struct radeon_device *rdev);
1971 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1972 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1973 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1974 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1975 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1976 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1977 u32 (*get_current_sclk)(struct radeon_device *rdev);
1978 u32 (*get_current_mclk)(struct radeon_device *rdev);
1979 u16 (*get_current_vddc)(struct radeon_device *rdev);
1980 } dpm;
1981 /* pageflipping */
1982 struct {
1983 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
1984 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1985 } pflip;
1986 };
1987
1988 /*
1989 * Asic structures
1990 */
1991 struct r100_asic {
1992 const unsigned *reg_safe_bm;
1993 unsigned reg_safe_bm_size;
1994 u32 hdp_cntl;
1995 };
1996
1997 struct r300_asic {
1998 const unsigned *reg_safe_bm;
1999 unsigned reg_safe_bm_size;
2000 u32 resync_scratch;
2001 u32 hdp_cntl;
2002 };
2003
2004 struct r600_asic {
2005 unsigned max_pipes;
2006 unsigned max_tile_pipes;
2007 unsigned max_simds;
2008 unsigned max_backends;
2009 unsigned max_gprs;
2010 unsigned max_threads;
2011 unsigned max_stack_entries;
2012 unsigned max_hw_contexts;
2013 unsigned max_gs_threads;
2014 unsigned sx_max_export_size;
2015 unsigned sx_max_export_pos_size;
2016 unsigned sx_max_export_smx_size;
2017 unsigned sq_num_cf_insts;
2018 unsigned tiling_nbanks;
2019 unsigned tiling_npipes;
2020 unsigned tiling_group_size;
2021 unsigned tile_config;
2022 unsigned backend_map;
2023 unsigned active_simds;
2024 };
2025
2026 struct rv770_asic {
2027 unsigned max_pipes;
2028 unsigned max_tile_pipes;
2029 unsigned max_simds;
2030 unsigned max_backends;
2031 unsigned max_gprs;
2032 unsigned max_threads;
2033 unsigned max_stack_entries;
2034 unsigned max_hw_contexts;
2035 unsigned max_gs_threads;
2036 unsigned sx_max_export_size;
2037 unsigned sx_max_export_pos_size;
2038 unsigned sx_max_export_smx_size;
2039 unsigned sq_num_cf_insts;
2040 unsigned sx_num_of_sets;
2041 unsigned sc_prim_fifo_size;
2042 unsigned sc_hiz_tile_fifo_size;
2043 unsigned sc_earlyz_tile_fifo_fize;
2044 unsigned tiling_nbanks;
2045 unsigned tiling_npipes;
2046 unsigned tiling_group_size;
2047 unsigned tile_config;
2048 unsigned backend_map;
2049 unsigned active_simds;
2050 };
2051
2052 struct evergreen_asic {
2053 unsigned num_ses;
2054 unsigned max_pipes;
2055 unsigned max_tile_pipes;
2056 unsigned max_simds;
2057 unsigned max_backends;
2058 unsigned max_gprs;
2059 unsigned max_threads;
2060 unsigned max_stack_entries;
2061 unsigned max_hw_contexts;
2062 unsigned max_gs_threads;
2063 unsigned sx_max_export_size;
2064 unsigned sx_max_export_pos_size;
2065 unsigned sx_max_export_smx_size;
2066 unsigned sq_num_cf_insts;
2067 unsigned sx_num_of_sets;
2068 unsigned sc_prim_fifo_size;
2069 unsigned sc_hiz_tile_fifo_size;
2070 unsigned sc_earlyz_tile_fifo_size;
2071 unsigned tiling_nbanks;
2072 unsigned tiling_npipes;
2073 unsigned tiling_group_size;
2074 unsigned tile_config;
2075 unsigned backend_map;
2076 unsigned active_simds;
2077 };
2078
2079 struct cayman_asic {
2080 unsigned max_shader_engines;
2081 unsigned max_pipes_per_simd;
2082 unsigned max_tile_pipes;
2083 unsigned max_simds_per_se;
2084 unsigned max_backends_per_se;
2085 unsigned max_texture_channel_caches;
2086 unsigned max_gprs;
2087 unsigned max_threads;
2088 unsigned max_gs_threads;
2089 unsigned max_stack_entries;
2090 unsigned sx_num_of_sets;
2091 unsigned sx_max_export_size;
2092 unsigned sx_max_export_pos_size;
2093 unsigned sx_max_export_smx_size;
2094 unsigned max_hw_contexts;
2095 unsigned sq_num_cf_insts;
2096 unsigned sc_prim_fifo_size;
2097 unsigned sc_hiz_tile_fifo_size;
2098 unsigned sc_earlyz_tile_fifo_size;
2099
2100 unsigned num_shader_engines;
2101 unsigned num_shader_pipes_per_simd;
2102 unsigned num_tile_pipes;
2103 unsigned num_simds_per_se;
2104 unsigned num_backends_per_se;
2105 unsigned backend_disable_mask_per_asic;
2106 unsigned backend_map;
2107 unsigned num_texture_channel_caches;
2108 unsigned mem_max_burst_length_bytes;
2109 unsigned mem_row_size_in_kb;
2110 unsigned shader_engine_tile_size;
2111 unsigned num_gpus;
2112 unsigned multi_gpu_tile_size;
2113
2114 unsigned tile_config;
2115 unsigned active_simds;
2116 };
2117
2118 struct si_asic {
2119 unsigned max_shader_engines;
2120 unsigned max_tile_pipes;
2121 unsigned max_cu_per_sh;
2122 unsigned max_sh_per_se;
2123 unsigned max_backends_per_se;
2124 unsigned max_texture_channel_caches;
2125 unsigned max_gprs;
2126 unsigned max_gs_threads;
2127 unsigned max_hw_contexts;
2128 unsigned sc_prim_fifo_size_frontend;
2129 unsigned sc_prim_fifo_size_backend;
2130 unsigned sc_hiz_tile_fifo_size;
2131 unsigned sc_earlyz_tile_fifo_size;
2132
2133 unsigned num_tile_pipes;
2134 unsigned backend_enable_mask;
2135 unsigned backend_disable_mask_per_asic;
2136 unsigned backend_map;
2137 unsigned num_texture_channel_caches;
2138 unsigned mem_max_burst_length_bytes;
2139 unsigned mem_row_size_in_kb;
2140 unsigned shader_engine_tile_size;
2141 unsigned num_gpus;
2142 unsigned multi_gpu_tile_size;
2143
2144 unsigned tile_config;
2145 uint32_t tile_mode_array[32];
2146 uint32_t active_cus;
2147 };
2148
2149 struct cik_asic {
2150 unsigned max_shader_engines;
2151 unsigned max_tile_pipes;
2152 unsigned max_cu_per_sh;
2153 unsigned max_sh_per_se;
2154 unsigned max_backends_per_se;
2155 unsigned max_texture_channel_caches;
2156 unsigned max_gprs;
2157 unsigned max_gs_threads;
2158 unsigned max_hw_contexts;
2159 unsigned sc_prim_fifo_size_frontend;
2160 unsigned sc_prim_fifo_size_backend;
2161 unsigned sc_hiz_tile_fifo_size;
2162 unsigned sc_earlyz_tile_fifo_size;
2163
2164 unsigned num_tile_pipes;
2165 unsigned backend_enable_mask;
2166 unsigned backend_disable_mask_per_asic;
2167 unsigned backend_map;
2168 unsigned num_texture_channel_caches;
2169 unsigned mem_max_burst_length_bytes;
2170 unsigned mem_row_size_in_kb;
2171 unsigned shader_engine_tile_size;
2172 unsigned num_gpus;
2173 unsigned multi_gpu_tile_size;
2174
2175 unsigned tile_config;
2176 uint32_t tile_mode_array[32];
2177 uint32_t macrotile_mode_array[16];
2178 uint32_t active_cus;
2179 };
2180
2181 union radeon_asic_config {
2182 struct r300_asic r300;
2183 struct r100_asic r100;
2184 struct r600_asic r600;
2185 struct rv770_asic rv770;
2186 struct evergreen_asic evergreen;
2187 struct cayman_asic cayman;
2188 struct si_asic si;
2189 struct cik_asic cik;
2190 };
2191
2192 /*
2193 * asic initizalization from radeon_asic.c
2194 */
2195 void radeon_agp_disable(struct radeon_device *rdev);
2196 int radeon_asic_init(struct radeon_device *rdev);
2197
2198
2199 /*
2200 * IOCTL.
2201 */
2202 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2203 struct drm_file *filp);
2204 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2205 struct drm_file *filp);
2206 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2207 struct drm_file *filp);
2208 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2209 struct drm_file *file_priv);
2210 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2211 struct drm_file *file_priv);
2212 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2213 struct drm_file *file_priv);
2214 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2215 struct drm_file *file_priv);
2216 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2217 struct drm_file *filp);
2218 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2219 struct drm_file *filp);
2220 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
2224 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *filp);
2226 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *filp);
2228 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2229 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2230 struct drm_file *filp);
2231 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2232 struct drm_file *filp);
2233 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2234
2235 /* VRAM scratch page for HDP bug, default vram page */
2236 struct r600_vram_scratch {
2237 struct radeon_bo *robj;
2238 volatile uint32_t *ptr;
2239 u64 gpu_addr;
2240 };
2241
2242 /*
2243 * ACPI
2244 */
2245 struct radeon_atif_notification_cfg {
2246 bool enabled;
2247 int command_code;
2248 };
2249
2250 struct radeon_atif_notifications {
2251 bool display_switch;
2252 bool expansion_mode_change;
2253 bool thermal_state;
2254 bool forced_power_state;
2255 bool system_power_state;
2256 bool display_conf_change;
2257 bool px_gfx_switch;
2258 bool brightness_change;
2259 bool dgpu_display_event;
2260 };
2261
2262 struct radeon_atif_functions {
2263 bool system_params;
2264 bool sbios_requests;
2265 bool select_active_disp;
2266 bool lid_state;
2267 bool get_tv_standard;
2268 bool set_tv_standard;
2269 bool get_panel_expansion_mode;
2270 bool set_panel_expansion_mode;
2271 bool temperature_change;
2272 bool graphics_device_types;
2273 };
2274
2275 struct radeon_atif {
2276 struct radeon_atif_notifications notifications;
2277 struct radeon_atif_functions functions;
2278 struct radeon_atif_notification_cfg notification_cfg;
2279 struct radeon_encoder *encoder_for_bl;
2280 };
2281
2282 struct radeon_atcs_functions {
2283 bool get_ext_state;
2284 bool pcie_perf_req;
2285 bool pcie_dev_rdy;
2286 bool pcie_bus_width;
2287 };
2288
2289 struct radeon_atcs {
2290 struct radeon_atcs_functions functions;
2291 };
2292
2293 /*
2294 * Core structure, functions and helpers.
2295 */
2296 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2297 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2298
2299 struct radeon_device {
2300 struct device *dev;
2301 struct drm_device *ddev;
2302 struct pci_dev *pdev;
2303 #ifdef __alpha__
2304 struct pci_controller *hose;
2305 #endif
2306 struct rw_semaphore exclusive_lock;
2307 /* ASIC */
2308 union radeon_asic_config config;
2309 enum radeon_family family;
2310 unsigned long flags;
2311 int usec_timeout;
2312 enum radeon_pll_errata pll_errata;
2313 int num_gb_pipes;
2314 int num_z_pipes;
2315 int disp_priority;
2316 /* BIOS */
2317 uint8_t *bios;
2318 bool is_atom_bios;
2319 uint16_t bios_header_start;
2320 struct radeon_bo *stolen_vga_memory;
2321 /* Register mmio */
2322 resource_size_t rmmio_base;
2323 resource_size_t rmmio_size;
2324 /* protects concurrent MM_INDEX/DATA based register access */
2325 spinlock_t mmio_idx_lock;
2326 /* protects concurrent SMC based register access */
2327 spinlock_t smc_idx_lock;
2328 /* protects concurrent PLL register access */
2329 spinlock_t pll_idx_lock;
2330 /* protects concurrent MC register access */
2331 spinlock_t mc_idx_lock;
2332 /* protects concurrent PCIE register access */
2333 spinlock_t pcie_idx_lock;
2334 /* protects concurrent PCIE_PORT register access */
2335 spinlock_t pciep_idx_lock;
2336 /* protects concurrent PIF register access */
2337 spinlock_t pif_idx_lock;
2338 /* protects concurrent CG register access */
2339 spinlock_t cg_idx_lock;
2340 /* protects concurrent UVD register access */
2341 spinlock_t uvd_idx_lock;
2342 /* protects concurrent RCU register access */
2343 spinlock_t rcu_idx_lock;
2344 /* protects concurrent DIDT register access */
2345 spinlock_t didt_idx_lock;
2346 /* protects concurrent ENDPOINT (audio) register access */
2347 spinlock_t end_idx_lock;
2348 void __iomem *rmmio;
2349 radeon_rreg_t mc_rreg;
2350 radeon_wreg_t mc_wreg;
2351 radeon_rreg_t pll_rreg;
2352 radeon_wreg_t pll_wreg;
2353 uint32_t pcie_reg_mask;
2354 radeon_rreg_t pciep_rreg;
2355 radeon_wreg_t pciep_wreg;
2356 /* io port */
2357 void __iomem *rio_mem;
2358 resource_size_t rio_mem_size;
2359 struct radeon_clock clock;
2360 struct radeon_mc mc;
2361 struct radeon_gart gart;
2362 struct radeon_mode_info mode_info;
2363 struct radeon_scratch scratch;
2364 struct radeon_doorbell doorbell;
2365 struct radeon_mman mman;
2366 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2367 wait_queue_head_t fence_queue;
2368 u64 fence_context;
2369 struct mutex ring_lock;
2370 struct radeon_ring ring[RADEON_NUM_RINGS];
2371 bool ib_pool_ready;
2372 struct radeon_sa_manager ring_tmp_bo;
2373 struct radeon_irq irq;
2374 struct radeon_asic *asic;
2375 struct radeon_gem gem;
2376 struct radeon_pm pm;
2377 struct radeon_uvd uvd;
2378 struct radeon_vce vce;
2379 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2380 struct radeon_wb wb;
2381 struct radeon_dummy_page dummy_page;
2382 bool shutdown;
2383 bool need_swiotlb;
2384 bool accel_working;
2385 bool fastfb_working; /* IGP feature*/
2386 bool needs_reset, in_reset;
2387 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2388 const struct firmware *me_fw; /* all family ME firmware */
2389 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2390 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2391 const struct firmware *mc_fw; /* NI MC firmware */
2392 const struct firmware *ce_fw; /* SI CE firmware */
2393 const struct firmware *mec_fw; /* CIK MEC firmware */
2394 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2395 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2396 const struct firmware *smc_fw; /* SMC firmware */
2397 const struct firmware *uvd_fw; /* UVD firmware */
2398 const struct firmware *vce_fw; /* VCE firmware */
2399 bool new_fw;
2400 struct r600_vram_scratch vram_scratch;
2401 int msi_enabled; /* msi enabled */
2402 struct r600_ih ih; /* r6/700 interrupt ring */
2403 struct radeon_rlc rlc;
2404 struct radeon_mec mec;
2405 struct delayed_work hotplug_work;
2406 struct work_struct dp_work;
2407 struct work_struct audio_work;
2408 int num_crtc; /* number of crtcs */
2409 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2410 bool has_uvd;
2411 bool has_vce;
2412 struct r600_audio audio; /* audio stuff */
2413 struct notifier_block acpi_nb;
2414 /* only one userspace can use Hyperz features or CMASK at a time */
2415 struct drm_file *hyperz_filp;
2416 struct drm_file *cmask_filp;
2417 /* i2c buses */
2418 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2419 /* virtual memory */
2420 struct radeon_vm_manager vm_manager;
2421 struct mutex gpu_clock_mutex;
2422 /* memory stats */
2423 atomic64_t vram_usage;
2424 atomic64_t gtt_usage;
2425 atomic64_t num_bytes_moved;
2426 atomic_t gpu_reset_counter;
2427 /* ACPI interface */
2428 struct radeon_atif atif;
2429 struct radeon_atcs atcs;
2430 /* srbm instance registers */
2431 struct mutex srbm_mutex;
2432 /* clock, powergating flags */
2433 u32 cg_flags;
2434 u32 pg_flags;
2435
2436 struct dev_pm_domain vga_pm_domain;
2437 bool have_disp_power_ref;
2438 u32 px_quirk_flags;
2439
2440 /* tracking pinned memory */
2441 u64 vram_pin_size;
2442 u64 gart_pin_size;
2443 };
2444
2445 bool radeon_is_px(struct drm_device *dev);
2446 int radeon_device_init(struct radeon_device *rdev,
2447 struct drm_device *ddev,
2448 struct pci_dev *pdev,
2449 uint32_t flags);
2450 void radeon_device_fini(struct radeon_device *rdev);
2451 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2452
2453 #define RADEON_MIN_MMIO_SIZE 0x10000
2454
2455 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2456 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2457 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2458 bool always_indirect)
2459 {
2460 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2461 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2462 return readl(((void __iomem *)rdev->rmmio) + reg);
2463 else
2464 return r100_mm_rreg_slow(rdev, reg);
2465 }
2466 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2467 bool always_indirect)
2468 {
2469 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2470 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2471 else
2472 r100_mm_wreg_slow(rdev, reg, v);
2473 }
2474
2475 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2476 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2477
2478 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2479 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2480
2481 /*
2482 * Cast helper
2483 */
2484 extern const struct dma_fence_ops radeon_fence_ops;
2485
2486 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2487 {
2488 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2489
2490 if (__f->base.ops == &radeon_fence_ops)
2491 return __f;
2492
2493 return NULL;
2494 }
2495
2496 /*
2497 * Registers read & write functions.
2498 */
2499 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2500 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2501 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2502 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2503 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2504 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2505 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2506 r100_mm_rreg(rdev, (reg), false))
2507 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2508 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2509 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2510 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2511 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2512 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2513 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2514 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2515 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2516 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2517 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2518 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2519 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2520 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2521 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2522 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2523 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2524 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2525 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2526 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2527 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2528 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2529 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2530 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2531 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2532 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2533 #define WREG32_P(reg, val, mask) \
2534 do { \
2535 uint32_t tmp_ = RREG32(reg); \
2536 tmp_ &= (mask); \
2537 tmp_ |= ((val) & ~(mask)); \
2538 WREG32(reg, tmp_); \
2539 } while (0)
2540 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2541 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2542 #define WREG32_PLL_P(reg, val, mask) \
2543 do { \
2544 uint32_t tmp_ = RREG32_PLL(reg); \
2545 tmp_ &= (mask); \
2546 tmp_ |= ((val) & ~(mask)); \
2547 WREG32_PLL(reg, tmp_); \
2548 } while (0)
2549 #define WREG32_SMC_P(reg, val, mask) \
2550 do { \
2551 uint32_t tmp_ = RREG32_SMC(reg); \
2552 tmp_ &= (mask); \
2553 tmp_ |= ((val) & ~(mask)); \
2554 WREG32_SMC(reg, tmp_); \
2555 } while (0)
2556 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2557 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2558 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2559
2560 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2561 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2562
2563 /*
2564 * Indirect registers accessors.
2565 * They used to be inlined, but this increases code size by ~65 kbytes.
2566 * Since each performs a pair of MMIO ops
2567 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2568 * the cost of call+ret is almost negligible. MMIO and locking
2569 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2570 */
2571 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2572 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2573 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2574 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2575 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2576 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2577 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2578 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2579 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2580 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2581 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2582 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2583 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2584 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2585 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2586 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2587
2588 void r100_pll_errata_after_index(struct radeon_device *rdev);
2589
2590
2591 /*
2592 * ASICs helpers.
2593 */
2594 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2595 (rdev->pdev->device == 0x5969))
2596 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2597 (rdev->family == CHIP_RV200) || \
2598 (rdev->family == CHIP_RS100) || \
2599 (rdev->family == CHIP_RS200) || \
2600 (rdev->family == CHIP_RV250) || \
2601 (rdev->family == CHIP_RV280) || \
2602 (rdev->family == CHIP_RS300))
2603 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2604 (rdev->family == CHIP_RV350) || \
2605 (rdev->family == CHIP_R350) || \
2606 (rdev->family == CHIP_RV380) || \
2607 (rdev->family == CHIP_R420) || \
2608 (rdev->family == CHIP_R423) || \
2609 (rdev->family == CHIP_RV410) || \
2610 (rdev->family == CHIP_RS400) || \
2611 (rdev->family == CHIP_RS480))
2612 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2613 (rdev->pdev->device == 0x9443) || \
2614 (rdev->pdev->device == 0x944B) || \
2615 (rdev->pdev->device == 0x9506) || \
2616 (rdev->pdev->device == 0x9509) || \
2617 (rdev->pdev->device == 0x950F) || \
2618 (rdev->pdev->device == 0x689C) || \
2619 (rdev->pdev->device == 0x689D))
2620 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2621 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2622 (rdev->family == CHIP_RS690) || \
2623 (rdev->family == CHIP_RS740) || \
2624 (rdev->family >= CHIP_R600))
2625 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2626 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2627 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2628 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2629 (rdev->flags & RADEON_IS_IGP))
2630 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2631 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2632 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2633 (rdev->flags & RADEON_IS_IGP))
2634 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2635 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2636 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2637 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2638 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2639 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2640 (rdev->family == CHIP_MULLINS))
2641
2642 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2643 (rdev->pdev->device == 0x6850) || \
2644 (rdev->pdev->device == 0x6858) || \
2645 (rdev->pdev->device == 0x6859) || \
2646 (rdev->pdev->device == 0x6840) || \
2647 (rdev->pdev->device == 0x6841) || \
2648 (rdev->pdev->device == 0x6842) || \
2649 (rdev->pdev->device == 0x6843))
2650
2651 /*
2652 * BIOS helpers.
2653 */
2654 #define RBIOS8(i) (rdev->bios[i])
2655 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2656 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2657
2658 int radeon_combios_init(struct radeon_device *rdev);
2659 void radeon_combios_fini(struct radeon_device *rdev);
2660 int radeon_atombios_init(struct radeon_device *rdev);
2661 void radeon_atombios_fini(struct radeon_device *rdev);
2662
2663
2664 /*
2665 * RING helpers.
2666 */
2667
2668 /**
2669 * radeon_ring_write - write a value to the ring
2670 *
2671 * @ring: radeon_ring structure holding ring information
2672 * @v: dword (dw) value to write
2673 *
2674 * Write a value to the requested ring buffer (all asics).
2675 */
2676 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2677 {
2678 if (ring->count_dw <= 0)
2679 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2680
2681 ring->ring[ring->wptr++] = v;
2682 ring->wptr &= ring->ptr_mask;
2683 ring->count_dw--;
2684 ring->ring_free_dw--;
2685 }
2686
2687 /*
2688 * ASICs macro.
2689 */
2690 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2691 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2692 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2693 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2694 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2695 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2696 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2697 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2698 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2699 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2700 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2701 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2702 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2703 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2704 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2705 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2706 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2707 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2708 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2709 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2710 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2711 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2712 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2713 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2714 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2715 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2716 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2717 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2718 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2719 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2720 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2721 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2722 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2723 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2724 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2725 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2726 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2727 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2728 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2729 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2730 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2731 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2732 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2733 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2734 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2735 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2736 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2737 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2738 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2739 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2740 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2741 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2742 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2743 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2744 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2745 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2746 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2747 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2748 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2749 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2750 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2751 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2752 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2753 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2754 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2755 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2756 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2757 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2758 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2759 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2760 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2761 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2762 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2763 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2764 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2765 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2766 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2767 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2768 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2769 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2770 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2771 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2772 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2773 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2774 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2775 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2776 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2777 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2778 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2779 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2780 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2781
2782 /* Common functions */
2783 /* AGP */
2784 extern int radeon_gpu_reset(struct radeon_device *rdev);
2785 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2786 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2787 extern void radeon_agp_disable(struct radeon_device *rdev);
2788 extern int radeon_modeset_init(struct radeon_device *rdev);
2789 extern void radeon_modeset_fini(struct radeon_device *rdev);
2790 extern bool radeon_card_posted(struct radeon_device *rdev);
2791 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2792 extern void radeon_update_display_priority(struct radeon_device *rdev);
2793 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2794 extern void radeon_scratch_init(struct radeon_device *rdev);
2795 extern void radeon_wb_fini(struct radeon_device *rdev);
2796 extern int radeon_wb_init(struct radeon_device *rdev);
2797 extern void radeon_wb_disable(struct radeon_device *rdev);
2798 extern void radeon_surface_init(struct radeon_device *rdev);
2799 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2800 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2801 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2802 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2803 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2804 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2805 struct ttm_tt *ttm, uint64_t addr,
2806 uint32_t flags);
2807 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2808 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2809 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
2810 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2811 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2812 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2813 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2814 bool fbcon, bool freeze);
2815 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2816 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2817 const u32 *registers,
2818 const u32 array_size);
2819 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev);
2820
2821 /* KMS */
2822
2823 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
2824 int radeon_enable_vblank_kms(struct drm_crtc *crtc);
2825 void radeon_disable_vblank_kms(struct drm_crtc *crtc);
2826
2827 /*
2828 * vm
2829 */
2830 int radeon_vm_manager_init(struct radeon_device *rdev);
2831 void radeon_vm_manager_fini(struct radeon_device *rdev);
2832 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2833 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2834 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2835 struct radeon_vm *vm,
2836 struct list_head *head);
2837 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2838 struct radeon_vm *vm, int ring);
2839 void radeon_vm_flush(struct radeon_device *rdev,
2840 struct radeon_vm *vm,
2841 int ring, struct radeon_fence *fence);
2842 void radeon_vm_fence(struct radeon_device *rdev,
2843 struct radeon_vm *vm,
2844 struct radeon_fence *fence);
2845 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2846 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2847 struct radeon_vm *vm);
2848 int radeon_vm_clear_freed(struct radeon_device *rdev,
2849 struct radeon_vm *vm);
2850 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2851 struct radeon_vm *vm);
2852 int radeon_vm_bo_update(struct radeon_device *rdev,
2853 struct radeon_bo_va *bo_va,
2854 struct ttm_resource *mem);
2855 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2856 struct radeon_bo *bo);
2857 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2858 struct radeon_bo *bo);
2859 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2860 struct radeon_vm *vm,
2861 struct radeon_bo *bo);
2862 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2863 struct radeon_bo_va *bo_va,
2864 uint64_t offset,
2865 uint32_t flags);
2866 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2867 struct radeon_bo_va *bo_va);
2868
2869 /* audio */
2870 void r600_audio_update_hdmi(struct work_struct *work);
2871 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2872 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2873 void r600_audio_enable(struct radeon_device *rdev,
2874 struct r600_audio_pin *pin,
2875 u8 enable_mask);
2876 void dce6_audio_enable(struct radeon_device *rdev,
2877 struct r600_audio_pin *pin,
2878 u8 enable_mask);
2879
2880 /*
2881 * R600 vram scratch functions
2882 */
2883 int r600_vram_scratch_init(struct radeon_device *rdev);
2884 void r600_vram_scratch_fini(struct radeon_device *rdev);
2885
2886 /*
2887 * r600 cs checking helper
2888 */
2889 unsigned r600_mip_minify(unsigned size, unsigned level);
2890 bool r600_fmt_is_valid_color(u32 format);
2891 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2892 int r600_fmt_get_blocksize(u32 format);
2893 int r600_fmt_get_nblocksx(u32 format, u32 w);
2894 int r600_fmt_get_nblocksy(u32 format, u32 h);
2895
2896 /*
2897 * r600 functions used by radeon_encoder.c
2898 */
2899 struct radeon_hdmi_acr {
2900 u32 clock;
2901
2902 int n_32khz;
2903 int cts_32khz;
2904
2905 int n_44_1khz;
2906 int cts_44_1khz;
2907
2908 int n_48khz;
2909 int cts_48khz;
2910
2911 };
2912
2913 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2914
2915 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2916 u32 tiling_pipe_num,
2917 u32 max_rb_num,
2918 u32 total_max_rb_num,
2919 u32 enabled_rb_mask);
2920
2921 /*
2922 * evergreen functions used by radeon_encoder.c
2923 */
2924
2925 extern int ni_init_microcode(struct radeon_device *rdev);
2926 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2927
2928 /* radeon_acpi.c */
2929 #if defined(CONFIG_ACPI)
2930 extern int radeon_acpi_init(struct radeon_device *rdev);
2931 extern void radeon_acpi_fini(struct radeon_device *rdev);
2932 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2933 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2934 u8 perf_req, bool advertise);
2935 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2936 #else
2937 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2938 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2939 #endif
2940
2941 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2942 struct radeon_cs_packet *pkt,
2943 unsigned idx);
2944 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2945 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2946 struct radeon_cs_packet *pkt);
2947 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2948 struct radeon_bo_list **cs_reloc,
2949 int nomm);
2950 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2951 uint32_t *vline_start_end,
2952 uint32_t *vline_status);
2953
2954 /* interrupt control register helpers */
2955 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2956 u32 reg, u32 mask,
2957 bool enable, const char *name,
2958 unsigned n);
2959
2960 #include "radeon_object.h"
2961
2962 #endif
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