]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/radeon/radeon.h
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/radeon/kms: enable the ttm dma pool if swiotlb is on V4
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97
98 /*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
109
110 /*
111 * Errata workarounds.
112 */
113 enum radeon_pll_errata {
114 CHIP_ERRATA_R300_CG = 0x00000001,
115 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
116 CHIP_ERRATA_PLL_DELAY = 0x00000004
117 };
118
119
120 struct radeon_device;
121
122
123 /*
124 * BIOS.
125 */
126 #define ATRM_BIOS_PAGE 4096
127
128 #if defined(CONFIG_VGA_SWITCHEROO)
129 bool radeon_atrm_supported(struct pci_dev *pdev);
130 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
131 #else
132 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
133 {
134 return false;
135 }
136
137 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
138 return -EINVAL;
139 }
140 #endif
141 bool radeon_get_bios(struct radeon_device *rdev);
142
143
144 /*
145 * Dummy page
146 */
147 struct radeon_dummy_page {
148 struct page *page;
149 dma_addr_t addr;
150 };
151 int radeon_dummy_page_init(struct radeon_device *rdev);
152 void radeon_dummy_page_fini(struct radeon_device *rdev);
153
154
155 /*
156 * Clocks
157 */
158 struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
161 struct radeon_pll dcpll;
162 struct radeon_pll spll;
163 struct radeon_pll mpll;
164 /* 10 Khz units */
165 uint32_t default_mclk;
166 uint32_t default_sclk;
167 uint32_t default_dispclk;
168 uint32_t dp_extclk;
169 uint32_t max_pixel_clock;
170 };
171
172 /*
173 * Power management
174 */
175 int radeon_pm_init(struct radeon_device *rdev);
176 void radeon_pm_fini(struct radeon_device *rdev);
177 void radeon_pm_compute_clocks(struct radeon_device *rdev);
178 void radeon_pm_suspend(struct radeon_device *rdev);
179 void radeon_pm_resume(struct radeon_device *rdev);
180 void radeon_combios_get_power_modes(struct radeon_device *rdev);
181 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
182 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
183 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
184 void rs690_pm_info(struct radeon_device *rdev);
185 extern int rv6xx_get_temp(struct radeon_device *rdev);
186 extern int rv770_get_temp(struct radeon_device *rdev);
187 extern int evergreen_get_temp(struct radeon_device *rdev);
188 extern int sumo_get_temp(struct radeon_device *rdev);
189
190 /*
191 * Fences.
192 */
193 struct radeon_fence_driver {
194 uint32_t scratch_reg;
195 atomic_t seq;
196 uint32_t last_seq;
197 unsigned long last_jiffies;
198 unsigned long last_timeout;
199 wait_queue_head_t queue;
200 rwlock_t lock;
201 struct list_head created;
202 struct list_head emited;
203 struct list_head signaled;
204 bool initialized;
205 };
206
207 struct radeon_fence {
208 struct radeon_device *rdev;
209 struct kref kref;
210 struct list_head list;
211 /* protected by radeon_fence.lock */
212 uint32_t seq;
213 bool emited;
214 bool signaled;
215 };
216
217 int radeon_fence_driver_init(struct radeon_device *rdev);
218 void radeon_fence_driver_fini(struct radeon_device *rdev);
219 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
220 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
221 void radeon_fence_process(struct radeon_device *rdev);
222 bool radeon_fence_signaled(struct radeon_fence *fence);
223 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
224 int radeon_fence_wait_next(struct radeon_device *rdev);
225 int radeon_fence_wait_last(struct radeon_device *rdev);
226 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
227 void radeon_fence_unref(struct radeon_fence **fence);
228
229 /*
230 * Tiling registers
231 */
232 struct radeon_surface_reg {
233 struct radeon_bo *bo;
234 };
235
236 #define RADEON_GEM_MAX_SURFACES 8
237
238 /*
239 * TTM.
240 */
241 struct radeon_mman {
242 struct ttm_bo_global_ref bo_global_ref;
243 struct drm_global_reference mem_global_ref;
244 struct ttm_bo_device bdev;
245 bool mem_global_referenced;
246 bool initialized;
247 };
248
249 struct radeon_bo {
250 /* Protected by gem.mutex */
251 struct list_head list;
252 /* Protected by tbo.reserved */
253 u32 placements[3];
254 struct ttm_placement placement;
255 struct ttm_buffer_object tbo;
256 struct ttm_bo_kmap_obj kmap;
257 unsigned pin_count;
258 void *kptr;
259 u32 tiling_flags;
260 u32 pitch;
261 int surface_reg;
262 /* Constant after initialization */
263 struct radeon_device *rdev;
264 struct drm_gem_object gem_base;
265 };
266 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
267
268 struct radeon_bo_list {
269 struct ttm_validate_buffer tv;
270 struct radeon_bo *bo;
271 uint64_t gpu_offset;
272 unsigned rdomain;
273 unsigned wdomain;
274 u32 tiling_flags;
275 };
276
277 /*
278 * GEM objects.
279 */
280 struct radeon_gem {
281 struct mutex mutex;
282 struct list_head objects;
283 };
284
285 int radeon_gem_init(struct radeon_device *rdev);
286 void radeon_gem_fini(struct radeon_device *rdev);
287 int radeon_gem_object_create(struct radeon_device *rdev, int size,
288 int alignment, int initial_domain,
289 bool discardable, bool kernel,
290 struct drm_gem_object **obj);
291 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
292 uint64_t *gpu_addr);
293 void radeon_gem_object_unpin(struct drm_gem_object *obj);
294
295 int radeon_mode_dumb_create(struct drm_file *file_priv,
296 struct drm_device *dev,
297 struct drm_mode_create_dumb *args);
298 int radeon_mode_dumb_mmap(struct drm_file *filp,
299 struct drm_device *dev,
300 uint32_t handle, uint64_t *offset_p);
301 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
302 struct drm_device *dev,
303 uint32_t handle);
304
305 /*
306 * GART structures, functions & helpers
307 */
308 struct radeon_mc;
309
310 #define RADEON_GPU_PAGE_SIZE 4096
311 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
312 #define RADEON_GPU_PAGE_SHIFT 12
313
314 struct radeon_gart {
315 dma_addr_t table_addr;
316 struct radeon_bo *robj;
317 void *ptr;
318 unsigned num_gpu_pages;
319 unsigned num_cpu_pages;
320 unsigned table_size;
321 struct page **pages;
322 dma_addr_t *pages_addr;
323 bool ready;
324 };
325
326 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
327 void radeon_gart_table_ram_free(struct radeon_device *rdev);
328 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
329 void radeon_gart_table_vram_free(struct radeon_device *rdev);
330 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
331 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
332 int radeon_gart_init(struct radeon_device *rdev);
333 void radeon_gart_fini(struct radeon_device *rdev);
334 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
335 int pages);
336 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
337 int pages, struct page **pagelist,
338 dma_addr_t *dma_addr);
339 void radeon_gart_restore(struct radeon_device *rdev);
340
341
342 /*
343 * GPU MC structures, functions & helpers
344 */
345 struct radeon_mc {
346 resource_size_t aper_size;
347 resource_size_t aper_base;
348 resource_size_t agp_base;
349 /* for some chips with <= 32MB we need to lie
350 * about vram size near mc fb location */
351 u64 mc_vram_size;
352 u64 visible_vram_size;
353 u64 gtt_size;
354 u64 gtt_start;
355 u64 gtt_end;
356 u64 vram_start;
357 u64 vram_end;
358 unsigned vram_width;
359 u64 real_vram_size;
360 int vram_mtrr;
361 bool vram_is_ddr;
362 bool igp_sideport_enabled;
363 u64 gtt_base_align;
364 };
365
366 bool radeon_combios_sideport_present(struct radeon_device *rdev);
367 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
368
369 /*
370 * GPU scratch registers structures, functions & helpers
371 */
372 struct radeon_scratch {
373 unsigned num_reg;
374 uint32_t reg_base;
375 bool free[32];
376 uint32_t reg[32];
377 };
378
379 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
380 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
381
382
383 /*
384 * IRQS.
385 */
386
387 struct radeon_unpin_work {
388 struct work_struct work;
389 struct radeon_device *rdev;
390 int crtc_id;
391 struct radeon_fence *fence;
392 struct drm_pending_vblank_event *event;
393 struct radeon_bo *old_rbo;
394 u64 new_crtc_base;
395 };
396
397 struct r500_irq_stat_regs {
398 u32 disp_int;
399 };
400
401 struct r600_irq_stat_regs {
402 u32 disp_int;
403 u32 disp_int_cont;
404 u32 disp_int_cont2;
405 u32 d1grph_int;
406 u32 d2grph_int;
407 };
408
409 struct evergreen_irq_stat_regs {
410 u32 disp_int;
411 u32 disp_int_cont;
412 u32 disp_int_cont2;
413 u32 disp_int_cont3;
414 u32 disp_int_cont4;
415 u32 disp_int_cont5;
416 u32 d1grph_int;
417 u32 d2grph_int;
418 u32 d3grph_int;
419 u32 d4grph_int;
420 u32 d5grph_int;
421 u32 d6grph_int;
422 };
423
424 union radeon_irq_stat_regs {
425 struct r500_irq_stat_regs r500;
426 struct r600_irq_stat_regs r600;
427 struct evergreen_irq_stat_regs evergreen;
428 };
429
430 #define RADEON_MAX_HPD_PINS 6
431 #define RADEON_MAX_CRTCS 6
432 #define RADEON_MAX_HDMI_BLOCKS 2
433
434 struct radeon_irq {
435 bool installed;
436 bool sw_int;
437 bool crtc_vblank_int[RADEON_MAX_CRTCS];
438 bool pflip[RADEON_MAX_CRTCS];
439 wait_queue_head_t vblank_queue;
440 bool hpd[RADEON_MAX_HPD_PINS];
441 bool gui_idle;
442 bool gui_idle_acked;
443 wait_queue_head_t idle_queue;
444 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
445 spinlock_t sw_lock;
446 int sw_refcount;
447 union radeon_irq_stat_regs stat_regs;
448 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
449 int pflip_refcount[RADEON_MAX_CRTCS];
450 };
451
452 int radeon_irq_kms_init(struct radeon_device *rdev);
453 void radeon_irq_kms_fini(struct radeon_device *rdev);
454 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
455 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
456 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
457 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
458
459 /*
460 * CP & ring.
461 */
462 struct radeon_ib {
463 struct list_head list;
464 unsigned idx;
465 uint64_t gpu_addr;
466 struct radeon_fence *fence;
467 uint32_t *ptr;
468 uint32_t length_dw;
469 bool free;
470 };
471
472 /*
473 * locking -
474 * mutex protects scheduled_ibs, ready, alloc_bm
475 */
476 struct radeon_ib_pool {
477 struct mutex mutex;
478 struct radeon_bo *robj;
479 struct list_head bogus_ib;
480 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
481 bool ready;
482 unsigned head_id;
483 };
484
485 struct radeon_cp {
486 struct radeon_bo *ring_obj;
487 volatile uint32_t *ring;
488 unsigned rptr;
489 unsigned wptr;
490 unsigned wptr_old;
491 unsigned ring_size;
492 unsigned ring_free_dw;
493 int count_dw;
494 uint64_t gpu_addr;
495 uint32_t align_mask;
496 uint32_t ptr_mask;
497 struct mutex mutex;
498 bool ready;
499 };
500
501 /*
502 * R6xx+ IH ring
503 */
504 struct r600_ih {
505 struct radeon_bo *ring_obj;
506 volatile uint32_t *ring;
507 unsigned rptr;
508 unsigned wptr;
509 unsigned wptr_old;
510 unsigned ring_size;
511 uint64_t gpu_addr;
512 uint32_t ptr_mask;
513 spinlock_t lock;
514 bool enabled;
515 };
516
517 struct r600_blit_cp_primitives {
518 void (*set_render_target)(struct radeon_device *rdev, int format,
519 int w, int h, u64 gpu_addr);
520 void (*cp_set_surface_sync)(struct radeon_device *rdev,
521 u32 sync_type, u32 size,
522 u64 mc_addr);
523 void (*set_shaders)(struct radeon_device *rdev);
524 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
525 void (*set_tex_resource)(struct radeon_device *rdev,
526 int format, int w, int h, int pitch,
527 u64 gpu_addr, u32 size);
528 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
529 int x2, int y2);
530 void (*draw_auto)(struct radeon_device *rdev);
531 void (*set_default_state)(struct radeon_device *rdev);
532 };
533
534 struct r600_blit {
535 struct mutex mutex;
536 struct radeon_bo *shader_obj;
537 struct r600_blit_cp_primitives primitives;
538 int max_dim;
539 int ring_size_common;
540 int ring_size_per_loop;
541 u64 shader_gpu_addr;
542 u32 vs_offset, ps_offset;
543 u32 state_offset;
544 u32 state_len;
545 u32 vb_used, vb_total;
546 struct radeon_ib *vb_ib;
547 };
548
549 void r600_blit_suspend(struct radeon_device *rdev);
550
551 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
552 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
553 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
554 int radeon_ib_pool_init(struct radeon_device *rdev);
555 void radeon_ib_pool_fini(struct radeon_device *rdev);
556 int radeon_ib_test(struct radeon_device *rdev);
557 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
558 /* Ring access between begin & end cannot sleep */
559 void radeon_ring_free_size(struct radeon_device *rdev);
560 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
561 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
562 void radeon_ring_commit(struct radeon_device *rdev);
563 void radeon_ring_unlock_commit(struct radeon_device *rdev);
564 void radeon_ring_unlock_undo(struct radeon_device *rdev);
565 int radeon_ring_test(struct radeon_device *rdev);
566 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
567 void radeon_ring_fini(struct radeon_device *rdev);
568
569
570 /*
571 * CS.
572 */
573 struct radeon_cs_reloc {
574 struct drm_gem_object *gobj;
575 struct radeon_bo *robj;
576 struct radeon_bo_list lobj;
577 uint32_t handle;
578 uint32_t flags;
579 };
580
581 struct radeon_cs_chunk {
582 uint32_t chunk_id;
583 uint32_t length_dw;
584 int kpage_idx[2];
585 uint32_t *kpage[2];
586 uint32_t *kdata;
587 void __user *user_ptr;
588 int last_copied_page;
589 int last_page_index;
590 };
591
592 struct radeon_cs_parser {
593 struct device *dev;
594 struct radeon_device *rdev;
595 struct drm_file *filp;
596 /* chunks */
597 unsigned nchunks;
598 struct radeon_cs_chunk *chunks;
599 uint64_t *chunks_array;
600 /* IB */
601 unsigned idx;
602 /* relocations */
603 unsigned nrelocs;
604 struct radeon_cs_reloc *relocs;
605 struct radeon_cs_reloc **relocs_ptr;
606 struct list_head validated;
607 /* indices of various chunks */
608 int chunk_ib_idx;
609 int chunk_relocs_idx;
610 struct radeon_ib *ib;
611 void *track;
612 unsigned family;
613 int parser_error;
614 };
615
616 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
617 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
618 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
619
620 struct radeon_cs_packet {
621 unsigned idx;
622 unsigned type;
623 unsigned reg;
624 unsigned opcode;
625 int count;
626 unsigned one_reg_wr;
627 };
628
629 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
630 struct radeon_cs_packet *pkt,
631 unsigned idx, unsigned reg);
632 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
633 struct radeon_cs_packet *pkt);
634
635
636 /*
637 * AGP
638 */
639 int radeon_agp_init(struct radeon_device *rdev);
640 void radeon_agp_resume(struct radeon_device *rdev);
641 void radeon_agp_suspend(struct radeon_device *rdev);
642 void radeon_agp_fini(struct radeon_device *rdev);
643
644
645 /*
646 * Writeback
647 */
648 struct radeon_wb {
649 struct radeon_bo *wb_obj;
650 volatile uint32_t *wb;
651 uint64_t gpu_addr;
652 bool enabled;
653 bool use_event;
654 };
655
656 #define RADEON_WB_SCRATCH_OFFSET 0
657 #define RADEON_WB_CP_RPTR_OFFSET 1024
658 #define RADEON_WB_CP1_RPTR_OFFSET 1280
659 #define RADEON_WB_CP2_RPTR_OFFSET 1536
660 #define R600_WB_IH_WPTR_OFFSET 2048
661 #define R600_WB_EVENT_OFFSET 3072
662
663 /**
664 * struct radeon_pm - power management datas
665 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
666 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
667 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
668 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
669 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
670 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
671 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
672 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
673 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
674 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
675 * @needed_bandwidth: current bandwidth needs
676 *
677 * It keeps track of various data needed to take powermanagement decision.
678 * Bandwidth need is used to determine minimun clock of the GPU and memory.
679 * Equation between gpu/memory clock and available bandwidth is hw dependent
680 * (type of memory, bus size, efficiency, ...)
681 */
682
683 enum radeon_pm_method {
684 PM_METHOD_PROFILE,
685 PM_METHOD_DYNPM,
686 };
687
688 enum radeon_dynpm_state {
689 DYNPM_STATE_DISABLED,
690 DYNPM_STATE_MINIMUM,
691 DYNPM_STATE_PAUSED,
692 DYNPM_STATE_ACTIVE,
693 DYNPM_STATE_SUSPENDED,
694 };
695 enum radeon_dynpm_action {
696 DYNPM_ACTION_NONE,
697 DYNPM_ACTION_MINIMUM,
698 DYNPM_ACTION_DOWNCLOCK,
699 DYNPM_ACTION_UPCLOCK,
700 DYNPM_ACTION_DEFAULT
701 };
702
703 enum radeon_voltage_type {
704 VOLTAGE_NONE = 0,
705 VOLTAGE_GPIO,
706 VOLTAGE_VDDC,
707 VOLTAGE_SW
708 };
709
710 enum radeon_pm_state_type {
711 POWER_STATE_TYPE_DEFAULT,
712 POWER_STATE_TYPE_POWERSAVE,
713 POWER_STATE_TYPE_BATTERY,
714 POWER_STATE_TYPE_BALANCED,
715 POWER_STATE_TYPE_PERFORMANCE,
716 };
717
718 enum radeon_pm_profile_type {
719 PM_PROFILE_DEFAULT,
720 PM_PROFILE_AUTO,
721 PM_PROFILE_LOW,
722 PM_PROFILE_MID,
723 PM_PROFILE_HIGH,
724 };
725
726 #define PM_PROFILE_DEFAULT_IDX 0
727 #define PM_PROFILE_LOW_SH_IDX 1
728 #define PM_PROFILE_MID_SH_IDX 2
729 #define PM_PROFILE_HIGH_SH_IDX 3
730 #define PM_PROFILE_LOW_MH_IDX 4
731 #define PM_PROFILE_MID_MH_IDX 5
732 #define PM_PROFILE_HIGH_MH_IDX 6
733 #define PM_PROFILE_MAX 7
734
735 struct radeon_pm_profile {
736 int dpms_off_ps_idx;
737 int dpms_on_ps_idx;
738 int dpms_off_cm_idx;
739 int dpms_on_cm_idx;
740 };
741
742 enum radeon_int_thermal_type {
743 THERMAL_TYPE_NONE,
744 THERMAL_TYPE_RV6XX,
745 THERMAL_TYPE_RV770,
746 THERMAL_TYPE_EVERGREEN,
747 THERMAL_TYPE_SUMO,
748 THERMAL_TYPE_NI,
749 };
750
751 struct radeon_voltage {
752 enum radeon_voltage_type type;
753 /* gpio voltage */
754 struct radeon_gpio_rec gpio;
755 u32 delay; /* delay in usec from voltage drop to sclk change */
756 bool active_high; /* voltage drop is active when bit is high */
757 /* VDDC voltage */
758 u8 vddc_id; /* index into vddc voltage table */
759 u8 vddci_id; /* index into vddci voltage table */
760 bool vddci_enabled;
761 /* r6xx+ sw */
762 u16 voltage;
763 /* evergreen+ vddci */
764 u16 vddci;
765 };
766
767 /* clock mode flags */
768 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
769
770 struct radeon_pm_clock_info {
771 /* memory clock */
772 u32 mclk;
773 /* engine clock */
774 u32 sclk;
775 /* voltage info */
776 struct radeon_voltage voltage;
777 /* standardized clock flags */
778 u32 flags;
779 };
780
781 /* state flags */
782 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
783
784 struct radeon_power_state {
785 enum radeon_pm_state_type type;
786 /* XXX: use a define for num clock modes */
787 struct radeon_pm_clock_info clock_info[8];
788 /* number of valid clock modes in this power state */
789 int num_clock_modes;
790 struct radeon_pm_clock_info *default_clock_mode;
791 /* standardized state flags */
792 u32 flags;
793 u32 misc; /* vbios specific flags */
794 u32 misc2; /* vbios specific flags */
795 int pcie_lanes; /* pcie lanes */
796 };
797
798 /*
799 * Some modes are overclocked by very low value, accept them
800 */
801 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
802
803 struct radeon_pm {
804 struct mutex mutex;
805 u32 active_crtcs;
806 int active_crtc_count;
807 int req_vblank;
808 bool vblank_sync;
809 bool gui_idle;
810 fixed20_12 max_bandwidth;
811 fixed20_12 igp_sideport_mclk;
812 fixed20_12 igp_system_mclk;
813 fixed20_12 igp_ht_link_clk;
814 fixed20_12 igp_ht_link_width;
815 fixed20_12 k8_bandwidth;
816 fixed20_12 sideport_bandwidth;
817 fixed20_12 ht_bandwidth;
818 fixed20_12 core_bandwidth;
819 fixed20_12 sclk;
820 fixed20_12 mclk;
821 fixed20_12 needed_bandwidth;
822 struct radeon_power_state *power_state;
823 /* number of valid power states */
824 int num_power_states;
825 int current_power_state_index;
826 int current_clock_mode_index;
827 int requested_power_state_index;
828 int requested_clock_mode_index;
829 int default_power_state_index;
830 u32 current_sclk;
831 u32 current_mclk;
832 u16 current_vddc;
833 u16 current_vddci;
834 u32 default_sclk;
835 u32 default_mclk;
836 u16 default_vddc;
837 u16 default_vddci;
838 struct radeon_i2c_chan *i2c_bus;
839 /* selected pm method */
840 enum radeon_pm_method pm_method;
841 /* dynpm power management */
842 struct delayed_work dynpm_idle_work;
843 enum radeon_dynpm_state dynpm_state;
844 enum radeon_dynpm_action dynpm_planned_action;
845 unsigned long dynpm_action_timeout;
846 bool dynpm_can_upclock;
847 bool dynpm_can_downclock;
848 /* profile-based power management */
849 enum radeon_pm_profile_type profile;
850 int profile_index;
851 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
852 /* internal thermal controller on rv6xx+ */
853 enum radeon_int_thermal_type int_thermal_type;
854 struct device *int_hwmon_dev;
855 };
856
857
858 /*
859 * Benchmarking
860 */
861 void radeon_benchmark(struct radeon_device *rdev, int test_number);
862
863
864 /*
865 * Testing
866 */
867 void radeon_test_moves(struct radeon_device *rdev);
868
869
870 /*
871 * Debugfs
872 */
873 int radeon_debugfs_add_files(struct radeon_device *rdev,
874 struct drm_info_list *files,
875 unsigned nfiles);
876 int radeon_debugfs_fence_init(struct radeon_device *rdev);
877
878
879 /*
880 * ASIC specific functions.
881 */
882 struct radeon_asic {
883 int (*init)(struct radeon_device *rdev);
884 void (*fini)(struct radeon_device *rdev);
885 int (*resume)(struct radeon_device *rdev);
886 int (*suspend)(struct radeon_device *rdev);
887 void (*vga_set_state)(struct radeon_device *rdev, bool state);
888 bool (*gpu_is_lockup)(struct radeon_device *rdev);
889 int (*asic_reset)(struct radeon_device *rdev);
890 void (*gart_tlb_flush)(struct radeon_device *rdev);
891 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
892 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
893 void (*cp_fini)(struct radeon_device *rdev);
894 void (*cp_disable)(struct radeon_device *rdev);
895 void (*cp_commit)(struct radeon_device *rdev);
896 void (*ring_start)(struct radeon_device *rdev);
897 int (*ring_test)(struct radeon_device *rdev);
898 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
899 int (*irq_set)(struct radeon_device *rdev);
900 int (*irq_process)(struct radeon_device *rdev);
901 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
902 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
903 int (*cs_parse)(struct radeon_cs_parser *p);
904 int (*copy_blit)(struct radeon_device *rdev,
905 uint64_t src_offset,
906 uint64_t dst_offset,
907 unsigned num_gpu_pages,
908 struct radeon_fence *fence);
909 int (*copy_dma)(struct radeon_device *rdev,
910 uint64_t src_offset,
911 uint64_t dst_offset,
912 unsigned num_gpu_pages,
913 struct radeon_fence *fence);
914 int (*copy)(struct radeon_device *rdev,
915 uint64_t src_offset,
916 uint64_t dst_offset,
917 unsigned num_gpu_pages,
918 struct radeon_fence *fence);
919 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
920 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
921 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
922 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
923 int (*get_pcie_lanes)(struct radeon_device *rdev);
924 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
925 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
926 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
927 uint32_t tiling_flags, uint32_t pitch,
928 uint32_t offset, uint32_t obj_size);
929 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
930 void (*bandwidth_update)(struct radeon_device *rdev);
931 void (*hpd_init)(struct radeon_device *rdev);
932 void (*hpd_fini)(struct radeon_device *rdev);
933 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
934 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
935 /* ioctl hw specific callback. Some hw might want to perform special
936 * operation on specific ioctl. For instance on wait idle some hw
937 * might want to perform and HDP flush through MMIO as it seems that
938 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
939 * through ring.
940 */
941 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
942 bool (*gui_idle)(struct radeon_device *rdev);
943 /* power management */
944 void (*pm_misc)(struct radeon_device *rdev);
945 void (*pm_prepare)(struct radeon_device *rdev);
946 void (*pm_finish)(struct radeon_device *rdev);
947 void (*pm_init_profile)(struct radeon_device *rdev);
948 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
949 /* pageflipping */
950 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
951 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
952 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
953 };
954
955 /*
956 * Asic structures
957 */
958 struct r100_gpu_lockup {
959 unsigned long last_jiffies;
960 u32 last_cp_rptr;
961 };
962
963 struct r100_asic {
964 const unsigned *reg_safe_bm;
965 unsigned reg_safe_bm_size;
966 u32 hdp_cntl;
967 struct r100_gpu_lockup lockup;
968 };
969
970 struct r300_asic {
971 const unsigned *reg_safe_bm;
972 unsigned reg_safe_bm_size;
973 u32 resync_scratch;
974 u32 hdp_cntl;
975 struct r100_gpu_lockup lockup;
976 };
977
978 struct r600_asic {
979 unsigned max_pipes;
980 unsigned max_tile_pipes;
981 unsigned max_simds;
982 unsigned max_backends;
983 unsigned max_gprs;
984 unsigned max_threads;
985 unsigned max_stack_entries;
986 unsigned max_hw_contexts;
987 unsigned max_gs_threads;
988 unsigned sx_max_export_size;
989 unsigned sx_max_export_pos_size;
990 unsigned sx_max_export_smx_size;
991 unsigned sq_num_cf_insts;
992 unsigned tiling_nbanks;
993 unsigned tiling_npipes;
994 unsigned tiling_group_size;
995 unsigned tile_config;
996 unsigned backend_map;
997 struct r100_gpu_lockup lockup;
998 };
999
1000 struct rv770_asic {
1001 unsigned max_pipes;
1002 unsigned max_tile_pipes;
1003 unsigned max_simds;
1004 unsigned max_backends;
1005 unsigned max_gprs;
1006 unsigned max_threads;
1007 unsigned max_stack_entries;
1008 unsigned max_hw_contexts;
1009 unsigned max_gs_threads;
1010 unsigned sx_max_export_size;
1011 unsigned sx_max_export_pos_size;
1012 unsigned sx_max_export_smx_size;
1013 unsigned sq_num_cf_insts;
1014 unsigned sx_num_of_sets;
1015 unsigned sc_prim_fifo_size;
1016 unsigned sc_hiz_tile_fifo_size;
1017 unsigned sc_earlyz_tile_fifo_fize;
1018 unsigned tiling_nbanks;
1019 unsigned tiling_npipes;
1020 unsigned tiling_group_size;
1021 unsigned tile_config;
1022 unsigned backend_map;
1023 struct r100_gpu_lockup lockup;
1024 };
1025
1026 struct evergreen_asic {
1027 unsigned num_ses;
1028 unsigned max_pipes;
1029 unsigned max_tile_pipes;
1030 unsigned max_simds;
1031 unsigned max_backends;
1032 unsigned max_gprs;
1033 unsigned max_threads;
1034 unsigned max_stack_entries;
1035 unsigned max_hw_contexts;
1036 unsigned max_gs_threads;
1037 unsigned sx_max_export_size;
1038 unsigned sx_max_export_pos_size;
1039 unsigned sx_max_export_smx_size;
1040 unsigned sq_num_cf_insts;
1041 unsigned sx_num_of_sets;
1042 unsigned sc_prim_fifo_size;
1043 unsigned sc_hiz_tile_fifo_size;
1044 unsigned sc_earlyz_tile_fifo_size;
1045 unsigned tiling_nbanks;
1046 unsigned tiling_npipes;
1047 unsigned tiling_group_size;
1048 unsigned tile_config;
1049 unsigned backend_map;
1050 struct r100_gpu_lockup lockup;
1051 };
1052
1053 struct cayman_asic {
1054 unsigned max_shader_engines;
1055 unsigned max_pipes_per_simd;
1056 unsigned max_tile_pipes;
1057 unsigned max_simds_per_se;
1058 unsigned max_backends_per_se;
1059 unsigned max_texture_channel_caches;
1060 unsigned max_gprs;
1061 unsigned max_threads;
1062 unsigned max_gs_threads;
1063 unsigned max_stack_entries;
1064 unsigned sx_num_of_sets;
1065 unsigned sx_max_export_size;
1066 unsigned sx_max_export_pos_size;
1067 unsigned sx_max_export_smx_size;
1068 unsigned max_hw_contexts;
1069 unsigned sq_num_cf_insts;
1070 unsigned sc_prim_fifo_size;
1071 unsigned sc_hiz_tile_fifo_size;
1072 unsigned sc_earlyz_tile_fifo_size;
1073
1074 unsigned num_shader_engines;
1075 unsigned num_shader_pipes_per_simd;
1076 unsigned num_tile_pipes;
1077 unsigned num_simds_per_se;
1078 unsigned num_backends_per_se;
1079 unsigned backend_disable_mask_per_asic;
1080 unsigned backend_map;
1081 unsigned num_texture_channel_caches;
1082 unsigned mem_max_burst_length_bytes;
1083 unsigned mem_row_size_in_kb;
1084 unsigned shader_engine_tile_size;
1085 unsigned num_gpus;
1086 unsigned multi_gpu_tile_size;
1087
1088 unsigned tile_config;
1089 struct r100_gpu_lockup lockup;
1090 };
1091
1092 union radeon_asic_config {
1093 struct r300_asic r300;
1094 struct r100_asic r100;
1095 struct r600_asic r600;
1096 struct rv770_asic rv770;
1097 struct evergreen_asic evergreen;
1098 struct cayman_asic cayman;
1099 };
1100
1101 /*
1102 * asic initizalization from radeon_asic.c
1103 */
1104 void radeon_agp_disable(struct radeon_device *rdev);
1105 int radeon_asic_init(struct radeon_device *rdev);
1106
1107
1108 /*
1109 * IOCTL.
1110 */
1111 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1112 struct drm_file *filp);
1113 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1114 struct drm_file *filp);
1115 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1116 struct drm_file *file_priv);
1117 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1118 struct drm_file *file_priv);
1119 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv);
1121 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1122 struct drm_file *file_priv);
1123 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1124 struct drm_file *filp);
1125 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1126 struct drm_file *filp);
1127 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1128 struct drm_file *filp);
1129 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1130 struct drm_file *filp);
1131 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1132 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1133 struct drm_file *filp);
1134 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1135 struct drm_file *filp);
1136
1137 /* VRAM scratch page for HDP bug, default vram page */
1138 struct r600_vram_scratch {
1139 struct radeon_bo *robj;
1140 volatile uint32_t *ptr;
1141 u64 gpu_addr;
1142 };
1143
1144 /*
1145 * Core structure, functions and helpers.
1146 */
1147 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1148 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1149
1150 struct radeon_device {
1151 struct device *dev;
1152 struct drm_device *ddev;
1153 struct pci_dev *pdev;
1154 /* ASIC */
1155 union radeon_asic_config config;
1156 enum radeon_family family;
1157 unsigned long flags;
1158 int usec_timeout;
1159 enum radeon_pll_errata pll_errata;
1160 int num_gb_pipes;
1161 int num_z_pipes;
1162 int disp_priority;
1163 /* BIOS */
1164 uint8_t *bios;
1165 bool is_atom_bios;
1166 uint16_t bios_header_start;
1167 struct radeon_bo *stollen_vga_memory;
1168 /* Register mmio */
1169 resource_size_t rmmio_base;
1170 resource_size_t rmmio_size;
1171 void __iomem *rmmio;
1172 radeon_rreg_t mc_rreg;
1173 radeon_wreg_t mc_wreg;
1174 radeon_rreg_t pll_rreg;
1175 radeon_wreg_t pll_wreg;
1176 uint32_t pcie_reg_mask;
1177 radeon_rreg_t pciep_rreg;
1178 radeon_wreg_t pciep_wreg;
1179 /* io port */
1180 void __iomem *rio_mem;
1181 resource_size_t rio_mem_size;
1182 struct radeon_clock clock;
1183 struct radeon_mc mc;
1184 struct radeon_gart gart;
1185 struct radeon_mode_info mode_info;
1186 struct radeon_scratch scratch;
1187 struct radeon_mman mman;
1188 struct radeon_fence_driver fence_drv;
1189 struct radeon_cp cp;
1190 /* cayman compute rings */
1191 struct radeon_cp cp1;
1192 struct radeon_cp cp2;
1193 struct radeon_ib_pool ib_pool;
1194 struct radeon_irq irq;
1195 struct radeon_asic *asic;
1196 struct radeon_gem gem;
1197 struct radeon_pm pm;
1198 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1199 struct mutex cs_mutex;
1200 struct radeon_wb wb;
1201 struct radeon_dummy_page dummy_page;
1202 bool gpu_lockup;
1203 bool shutdown;
1204 bool suspend;
1205 bool need_dma32;
1206 bool accel_working;
1207 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1208 const struct firmware *me_fw; /* all family ME firmware */
1209 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1210 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1211 const struct firmware *mc_fw; /* NI MC firmware */
1212 struct r600_blit r600_blit;
1213 struct r600_vram_scratch vram_scratch;
1214 int msi_enabled; /* msi enabled */
1215 struct r600_ih ih; /* r6/700 interrupt ring */
1216 struct work_struct hotplug_work;
1217 int num_crtc; /* number of crtcs */
1218 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1219 struct mutex vram_mutex;
1220
1221 /* audio stuff */
1222 bool audio_enabled;
1223 struct timer_list audio_timer;
1224 int audio_channels;
1225 int audio_rate;
1226 int audio_bits_per_sample;
1227 uint8_t audio_status_bits;
1228 uint8_t audio_category_code;
1229
1230 struct notifier_block acpi_nb;
1231 /* only one userspace can use Hyperz features or CMASK at a time */
1232 struct drm_file *hyperz_filp;
1233 struct drm_file *cmask_filp;
1234 /* i2c buses */
1235 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1236 };
1237
1238 int radeon_device_init(struct radeon_device *rdev,
1239 struct drm_device *ddev,
1240 struct pci_dev *pdev,
1241 uint32_t flags);
1242 void radeon_device_fini(struct radeon_device *rdev);
1243 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1244
1245 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1246 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1247 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1248 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1249
1250 /*
1251 * Cast helper
1252 */
1253 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1254
1255 /*
1256 * Registers read & write functions.
1257 */
1258 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1259 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1260 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1261 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1262 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1263 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1264 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1265 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1266 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1267 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1268 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1269 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1270 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1271 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1272 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1273 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1274 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1275 #define WREG32_P(reg, val, mask) \
1276 do { \
1277 uint32_t tmp_ = RREG32(reg); \
1278 tmp_ &= (mask); \
1279 tmp_ |= ((val) & ~(mask)); \
1280 WREG32(reg, tmp_); \
1281 } while (0)
1282 #define WREG32_PLL_P(reg, val, mask) \
1283 do { \
1284 uint32_t tmp_ = RREG32_PLL(reg); \
1285 tmp_ &= (mask); \
1286 tmp_ |= ((val) & ~(mask)); \
1287 WREG32_PLL(reg, tmp_); \
1288 } while (0)
1289 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1290 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1291 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1292
1293 /*
1294 * Indirect registers accessor
1295 */
1296 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1297 {
1298 uint32_t r;
1299
1300 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1301 r = RREG32(RADEON_PCIE_DATA);
1302 return r;
1303 }
1304
1305 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1306 {
1307 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1308 WREG32(RADEON_PCIE_DATA, (v));
1309 }
1310
1311 void r100_pll_errata_after_index(struct radeon_device *rdev);
1312
1313
1314 /*
1315 * ASICs helpers.
1316 */
1317 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1318 (rdev->pdev->device == 0x5969))
1319 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1320 (rdev->family == CHIP_RV200) || \
1321 (rdev->family == CHIP_RS100) || \
1322 (rdev->family == CHIP_RS200) || \
1323 (rdev->family == CHIP_RV250) || \
1324 (rdev->family == CHIP_RV280) || \
1325 (rdev->family == CHIP_RS300))
1326 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1327 (rdev->family == CHIP_RV350) || \
1328 (rdev->family == CHIP_R350) || \
1329 (rdev->family == CHIP_RV380) || \
1330 (rdev->family == CHIP_R420) || \
1331 (rdev->family == CHIP_R423) || \
1332 (rdev->family == CHIP_RV410) || \
1333 (rdev->family == CHIP_RS400) || \
1334 (rdev->family == CHIP_RS480))
1335 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1336 (rdev->ddev->pdev->device == 0x9443) || \
1337 (rdev->ddev->pdev->device == 0x944B) || \
1338 (rdev->ddev->pdev->device == 0x9506) || \
1339 (rdev->ddev->pdev->device == 0x9509) || \
1340 (rdev->ddev->pdev->device == 0x950F) || \
1341 (rdev->ddev->pdev->device == 0x689C) || \
1342 (rdev->ddev->pdev->device == 0x689D))
1343 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1344 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1345 (rdev->family == CHIP_RS690) || \
1346 (rdev->family == CHIP_RS740) || \
1347 (rdev->family >= CHIP_R600))
1348 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1349 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1350 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1351 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1352 (rdev->flags & RADEON_IS_IGP))
1353 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1354
1355 /*
1356 * BIOS helpers.
1357 */
1358 #define RBIOS8(i) (rdev->bios[i])
1359 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1360 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1361
1362 int radeon_combios_init(struct radeon_device *rdev);
1363 void radeon_combios_fini(struct radeon_device *rdev);
1364 int radeon_atombios_init(struct radeon_device *rdev);
1365 void radeon_atombios_fini(struct radeon_device *rdev);
1366
1367
1368 /*
1369 * RING helpers.
1370 */
1371
1372 #if DRM_DEBUG_CODE == 0
1373 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1374 {
1375 rdev->cp.ring[rdev->cp.wptr++] = v;
1376 rdev->cp.wptr &= rdev->cp.ptr_mask;
1377 rdev->cp.count_dw--;
1378 rdev->cp.ring_free_dw--;
1379 }
1380 #else
1381 /* With debugging this is just too big to inline */
1382 void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
1383 #endif
1384
1385 /*
1386 * ASICs macro.
1387 */
1388 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1389 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1390 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1391 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1392 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1393 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1394 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1395 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1396 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1397 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1398 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1399 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1400 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1401 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1402 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1403 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1404 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1405 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1406 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1407 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1408 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1409 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1410 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1411 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1412 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1413 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1414 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1415 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1416 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1417 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1418 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1419 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1420 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1421 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1422 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1423 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1424 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1425 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1426 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1427 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1428 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1429 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1430 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1431 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1432
1433 /* Common functions */
1434 /* AGP */
1435 extern int radeon_gpu_reset(struct radeon_device *rdev);
1436 extern void radeon_agp_disable(struct radeon_device *rdev);
1437 extern int radeon_modeset_init(struct radeon_device *rdev);
1438 extern void radeon_modeset_fini(struct radeon_device *rdev);
1439 extern bool radeon_card_posted(struct radeon_device *rdev);
1440 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1441 extern void radeon_update_display_priority(struct radeon_device *rdev);
1442 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1443 extern void radeon_scratch_init(struct radeon_device *rdev);
1444 extern void radeon_wb_fini(struct radeon_device *rdev);
1445 extern int radeon_wb_init(struct radeon_device *rdev);
1446 extern void radeon_wb_disable(struct radeon_device *rdev);
1447 extern void radeon_surface_init(struct radeon_device *rdev);
1448 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1449 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1450 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1451 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1452 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1453 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1454 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1455 extern int radeon_resume_kms(struct drm_device *dev);
1456 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1457 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1458
1459 /*
1460 * R600 vram scratch functions
1461 */
1462 int r600_vram_scratch_init(struct radeon_device *rdev);
1463 void r600_vram_scratch_fini(struct radeon_device *rdev);
1464
1465 /*
1466 * r600 functions used by radeon_encoder.c
1467 */
1468 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1469 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1470 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1471
1472 extern int ni_init_microcode(struct radeon_device *rdev);
1473 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1474
1475 /* radeon_acpi.c */
1476 #if defined(CONFIG_ACPI)
1477 extern int radeon_acpi_init(struct radeon_device *rdev);
1478 #else
1479 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1480 #endif
1481
1482 #include "radeon_object.h"
1483
1484 #endif
ubuntu-bionic-kernel mirror