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Merge branch 'drm-fixes-3.18' of git://people.freedesktop.org/~agd5f/linux into drm...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/fence.h>
70
71 #include <ttm/ttm_bo_api.h>
72 #include <ttm/ttm_bo_driver.h>
73 #include <ttm/ttm_placement.h>
74 #include <ttm/ttm_module.h>
75 #include <ttm/ttm_execbuf_util.h>
76
77 #include <drm/drm_gem.h>
78
79 #include "radeon_family.h"
80 #include "radeon_mode.h"
81 #include "radeon_reg.h"
82
83 /*
84 * Modules parameters.
85 */
86 extern int radeon_no_wb;
87 extern int radeon_modeset;
88 extern int radeon_dynclks;
89 extern int radeon_r4xx_atom;
90 extern int radeon_agpmode;
91 extern int radeon_vram_limit;
92 extern int radeon_gart_size;
93 extern int radeon_benchmarking;
94 extern int radeon_testing;
95 extern int radeon_connector_table;
96 extern int radeon_tv;
97 extern int radeon_audio;
98 extern int radeon_disp_priority;
99 extern int radeon_hw_i2c;
100 extern int radeon_pcie_gen2;
101 extern int radeon_msi;
102 extern int radeon_lockup_timeout;
103 extern int radeon_fastfb;
104 extern int radeon_dpm;
105 extern int radeon_aspm;
106 extern int radeon_runtime_pm;
107 extern int radeon_hard_reset;
108 extern int radeon_vm_size;
109 extern int radeon_vm_block_size;
110 extern int radeon_deep_color;
111 extern int radeon_use_pflipirq;
112 extern int radeon_bapm;
113 extern int radeon_backlight;
114
115 /*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
119 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
121 /* RADEON_IB_POOL_SIZE must be a power of 2 */
122 #define RADEON_IB_POOL_SIZE 16
123 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
124 #define RADEONFB_CONN_LIMIT 4
125 #define RADEON_BIOS_NUM_SCRATCH 8
126
127 /* internal ring indices */
128 /* r1xx+ has gfx CP ring */
129 #define RADEON_RING_TYPE_GFX_INDEX 0
130
131 /* cayman has 2 compute CP rings */
132 #define CAYMAN_RING_TYPE_CP1_INDEX 1
133 #define CAYMAN_RING_TYPE_CP2_INDEX 2
134
135 /* R600+ has an async dma ring */
136 #define R600_RING_TYPE_DMA_INDEX 3
137 /* cayman add a second async dma ring */
138 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
139
140 /* R600+ */
141 #define R600_RING_TYPE_UVD_INDEX 5
142
143 /* TN+ */
144 #define TN_RING_TYPE_VCE1_INDEX 6
145 #define TN_RING_TYPE_VCE2_INDEX 7
146
147 /* max number of rings */
148 #define RADEON_NUM_RINGS 8
149
150 /* number of hw syncs before falling back on blocking */
151 #define RADEON_NUM_SYNCS 4
152
153 /* number of hw syncs before falling back on blocking */
154 #define RADEON_NUM_SYNCS 4
155
156 /* hardcode those limit for now */
157 #define RADEON_VA_IB_OFFSET (1 << 20)
158 #define RADEON_VA_RESERVED_SIZE (8 << 20)
159 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
160
161 /* hard reset data */
162 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
163
164 /* reset flags */
165 #define RADEON_RESET_GFX (1 << 0)
166 #define RADEON_RESET_COMPUTE (1 << 1)
167 #define RADEON_RESET_DMA (1 << 2)
168 #define RADEON_RESET_CP (1 << 3)
169 #define RADEON_RESET_GRBM (1 << 4)
170 #define RADEON_RESET_DMA1 (1 << 5)
171 #define RADEON_RESET_RLC (1 << 6)
172 #define RADEON_RESET_SEM (1 << 7)
173 #define RADEON_RESET_IH (1 << 8)
174 #define RADEON_RESET_VMC (1 << 9)
175 #define RADEON_RESET_MC (1 << 10)
176 #define RADEON_RESET_DISPLAY (1 << 11)
177
178 /* CG block flags */
179 #define RADEON_CG_BLOCK_GFX (1 << 0)
180 #define RADEON_CG_BLOCK_MC (1 << 1)
181 #define RADEON_CG_BLOCK_SDMA (1 << 2)
182 #define RADEON_CG_BLOCK_UVD (1 << 3)
183 #define RADEON_CG_BLOCK_VCE (1 << 4)
184 #define RADEON_CG_BLOCK_HDP (1 << 5)
185 #define RADEON_CG_BLOCK_BIF (1 << 6)
186
187 /* CG flags */
188 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
189 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
190 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
191 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
192 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
193 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
194 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
195 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
196 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
197 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
198 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
199 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
200 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
201 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
202 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
203 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
204 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
205
206 /* PG flags */
207 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
208 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
209 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
210 #define RADEON_PG_SUPPORT_UVD (1 << 3)
211 #define RADEON_PG_SUPPORT_VCE (1 << 4)
212 #define RADEON_PG_SUPPORT_CP (1 << 5)
213 #define RADEON_PG_SUPPORT_GDS (1 << 6)
214 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
215 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
216 #define RADEON_PG_SUPPORT_ACP (1 << 9)
217 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
218
219 /* max cursor sizes (in pixels) */
220 #define CURSOR_WIDTH 64
221 #define CURSOR_HEIGHT 64
222
223 #define CIK_CURSOR_WIDTH 128
224 #define CIK_CURSOR_HEIGHT 128
225
226 /*
227 * Errata workarounds.
228 */
229 enum radeon_pll_errata {
230 CHIP_ERRATA_R300_CG = 0x00000001,
231 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
232 CHIP_ERRATA_PLL_DELAY = 0x00000004
233 };
234
235
236 struct radeon_device;
237
238
239 /*
240 * BIOS.
241 */
242 bool radeon_get_bios(struct radeon_device *rdev);
243
244 /*
245 * Dummy page
246 */
247 struct radeon_dummy_page {
248 struct page *page;
249 dma_addr_t addr;
250 };
251 int radeon_dummy_page_init(struct radeon_device *rdev);
252 void radeon_dummy_page_fini(struct radeon_device *rdev);
253
254
255 /*
256 * Clocks
257 */
258 struct radeon_clock {
259 struct radeon_pll p1pll;
260 struct radeon_pll p2pll;
261 struct radeon_pll dcpll;
262 struct radeon_pll spll;
263 struct radeon_pll mpll;
264 /* 10 Khz units */
265 uint32_t default_mclk;
266 uint32_t default_sclk;
267 uint32_t default_dispclk;
268 uint32_t current_dispclk;
269 uint32_t dp_extclk;
270 uint32_t max_pixel_clock;
271 };
272
273 /*
274 * Power management
275 */
276 int radeon_pm_init(struct radeon_device *rdev);
277 int radeon_pm_late_init(struct radeon_device *rdev);
278 void radeon_pm_fini(struct radeon_device *rdev);
279 void radeon_pm_compute_clocks(struct radeon_device *rdev);
280 void radeon_pm_suspend(struct radeon_device *rdev);
281 void radeon_pm_resume(struct radeon_device *rdev);
282 void radeon_combios_get_power_modes(struct radeon_device *rdev);
283 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
284 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
285 u8 clock_type,
286 u32 clock,
287 bool strobe_mode,
288 struct atom_clock_dividers *dividers);
289 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
290 u32 clock,
291 bool strobe_mode,
292 struct atom_mpll_param *mpll_param);
293 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
294 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
295 u16 voltage_level, u8 voltage_type,
296 u32 *gpio_value, u32 *gpio_mask);
297 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
298 u32 eng_clock, u32 mem_clock);
299 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
300 u8 voltage_type, u16 *voltage_step);
301 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
302 u16 voltage_id, u16 *voltage);
303 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
304 u16 *voltage,
305 u16 leakage_idx);
306 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
307 u16 *leakage_id);
308 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
309 u16 *vddc, u16 *vddci,
310 u16 virtual_voltage_id,
311 u16 vbios_voltage_id);
312 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
313 u16 virtual_voltage_id,
314 u16 *voltage);
315 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
316 u8 voltage_type,
317 u16 nominal_voltage,
318 u16 *true_voltage);
319 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *min_voltage);
321 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *max_voltage);
323 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode,
325 struct atom_voltage_table *voltage_table);
326 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
327 u8 voltage_type, u8 voltage_mode);
328 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
329 u8 voltage_type,
330 u8 *svd_gpio_id, u8 *svc_gpio_id);
331 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 u32 mem_clock);
333 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 u32 mem_clock);
335 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 u8 module_index,
337 struct atom_mc_reg_table *reg_table);
338 int radeon_atom_get_memory_info(struct radeon_device *rdev,
339 u8 module_index, struct atom_memory_info *mem_info);
340 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
341 bool gddr5, u8 module_index,
342 struct atom_memory_clock_range_table *mclk_range_table);
343 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
344 u16 voltage_id, u16 *voltage);
345 void rs690_pm_info(struct radeon_device *rdev);
346 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
347 unsigned *bankh, unsigned *mtaspect,
348 unsigned *tile_split);
349
350 /*
351 * Fences.
352 */
353 struct radeon_fence_driver {
354 struct radeon_device *rdev;
355 uint32_t scratch_reg;
356 uint64_t gpu_addr;
357 volatile uint32_t *cpu_addr;
358 /* sync_seq is protected by ring emission lock */
359 uint64_t sync_seq[RADEON_NUM_RINGS];
360 atomic64_t last_seq;
361 bool initialized, delayed_irq;
362 struct delayed_work lockup_work;
363 };
364
365 struct radeon_fence {
366 struct fence base;
367
368 struct radeon_device *rdev;
369 uint64_t seq;
370 /* RB, DMA, etc. */
371 unsigned ring;
372
373 wait_queue_t fence_wake;
374 };
375
376 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
377 int radeon_fence_driver_init(struct radeon_device *rdev);
378 void radeon_fence_driver_fini(struct radeon_device *rdev);
379 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
380 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
381 void radeon_fence_process(struct radeon_device *rdev, int ring);
382 bool radeon_fence_signaled(struct radeon_fence *fence);
383 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
384 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
385 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
386 int radeon_fence_wait_any(struct radeon_device *rdev,
387 struct radeon_fence **fences,
388 bool intr);
389 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
390 void radeon_fence_unref(struct radeon_fence **fence);
391 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
392 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
393 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
394 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
395 struct radeon_fence *b)
396 {
397 if (!a) {
398 return b;
399 }
400
401 if (!b) {
402 return a;
403 }
404
405 BUG_ON(a->ring != b->ring);
406
407 if (a->seq > b->seq) {
408 return a;
409 } else {
410 return b;
411 }
412 }
413
414 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
415 struct radeon_fence *b)
416 {
417 if (!a) {
418 return false;
419 }
420
421 if (!b) {
422 return true;
423 }
424
425 BUG_ON(a->ring != b->ring);
426
427 return a->seq < b->seq;
428 }
429
430 /*
431 * Tiling registers
432 */
433 struct radeon_surface_reg {
434 struct radeon_bo *bo;
435 };
436
437 #define RADEON_GEM_MAX_SURFACES 8
438
439 /*
440 * TTM.
441 */
442 struct radeon_mman {
443 struct ttm_bo_global_ref bo_global_ref;
444 struct drm_global_reference mem_global_ref;
445 struct ttm_bo_device bdev;
446 bool mem_global_referenced;
447 bool initialized;
448
449 #if defined(CONFIG_DEBUG_FS)
450 struct dentry *vram;
451 struct dentry *gtt;
452 #endif
453 };
454
455 /* bo virtual address in a specific vm */
456 struct radeon_bo_va {
457 /* protected by bo being reserved */
458 struct list_head bo_list;
459 uint32_t flags;
460 uint64_t addr;
461 unsigned ref_count;
462
463 /* protected by vm mutex */
464 struct interval_tree_node it;
465 struct list_head vm_status;
466
467 /* constant after initialization */
468 struct radeon_vm *vm;
469 struct radeon_bo *bo;
470 };
471
472 struct radeon_bo {
473 /* Protected by gem.mutex */
474 struct list_head list;
475 /* Protected by tbo.reserved */
476 u32 initial_domain;
477 struct ttm_place placements[3];
478 struct ttm_placement placement;
479 struct ttm_buffer_object tbo;
480 struct ttm_bo_kmap_obj kmap;
481 u32 flags;
482 unsigned pin_count;
483 void *kptr;
484 u32 tiling_flags;
485 u32 pitch;
486 int surface_reg;
487 /* list of all virtual address to which this bo
488 * is associated to
489 */
490 struct list_head va;
491 /* Constant after initialization */
492 struct radeon_device *rdev;
493 struct drm_gem_object gem_base;
494
495 struct ttm_bo_kmap_obj dma_buf_vmap;
496 pid_t pid;
497
498 struct radeon_mn *mn;
499 struct interval_tree_node mn_it;
500 };
501 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
502
503 int radeon_gem_debugfs_init(struct radeon_device *rdev);
504
505 /* sub-allocation manager, it has to be protected by another lock.
506 * By conception this is an helper for other part of the driver
507 * like the indirect buffer or semaphore, which both have their
508 * locking.
509 *
510 * Principe is simple, we keep a list of sub allocation in offset
511 * order (first entry has offset == 0, last entry has the highest
512 * offset).
513 *
514 * When allocating new object we first check if there is room at
515 * the end total_size - (last_object_offset + last_object_size) >=
516 * alloc_size. If so we allocate new object there.
517 *
518 * When there is not enough room at the end, we start waiting for
519 * each sub object until we reach object_offset+object_size >=
520 * alloc_size, this object then become the sub object we return.
521 *
522 * Alignment can't be bigger than page size.
523 *
524 * Hole are not considered for allocation to keep things simple.
525 * Assumption is that there won't be hole (all object on same
526 * alignment).
527 */
528 struct radeon_sa_manager {
529 wait_queue_head_t wq;
530 struct radeon_bo *bo;
531 struct list_head *hole;
532 struct list_head flist[RADEON_NUM_RINGS];
533 struct list_head olist;
534 unsigned size;
535 uint64_t gpu_addr;
536 void *cpu_ptr;
537 uint32_t domain;
538 uint32_t align;
539 };
540
541 struct radeon_sa_bo;
542
543 /* sub-allocation buffer */
544 struct radeon_sa_bo {
545 struct list_head olist;
546 struct list_head flist;
547 struct radeon_sa_manager *manager;
548 unsigned soffset;
549 unsigned eoffset;
550 struct radeon_fence *fence;
551 };
552
553 /*
554 * GEM objects.
555 */
556 struct radeon_gem {
557 struct mutex mutex;
558 struct list_head objects;
559 };
560
561 int radeon_gem_init(struct radeon_device *rdev);
562 void radeon_gem_fini(struct radeon_device *rdev);
563 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
564 int alignment, int initial_domain,
565 u32 flags, bool kernel,
566 struct drm_gem_object **obj);
567
568 int radeon_mode_dumb_create(struct drm_file *file_priv,
569 struct drm_device *dev,
570 struct drm_mode_create_dumb *args);
571 int radeon_mode_dumb_mmap(struct drm_file *filp,
572 struct drm_device *dev,
573 uint32_t handle, uint64_t *offset_p);
574
575 /*
576 * Semaphores.
577 */
578 struct radeon_semaphore {
579 struct radeon_sa_bo *sa_bo;
580 signed waiters;
581 uint64_t gpu_addr;
582 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
583 };
584
585 int radeon_semaphore_create(struct radeon_device *rdev,
586 struct radeon_semaphore **semaphore);
587 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
588 struct radeon_semaphore *semaphore);
589 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
590 struct radeon_semaphore *semaphore);
591 void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
592 struct radeon_fence *fence);
593 int radeon_semaphore_sync_resv(struct radeon_device *rdev,
594 struct radeon_semaphore *semaphore,
595 struct reservation_object *resv,
596 bool shared);
597 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
598 struct radeon_semaphore *semaphore,
599 int waiting_ring);
600 void radeon_semaphore_free(struct radeon_device *rdev,
601 struct radeon_semaphore **semaphore,
602 struct radeon_fence *fence);
603
604 /*
605 * GART structures, functions & helpers
606 */
607 struct radeon_mc;
608
609 #define RADEON_GPU_PAGE_SIZE 4096
610 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
611 #define RADEON_GPU_PAGE_SHIFT 12
612 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
613
614 #define RADEON_GART_PAGE_DUMMY 0
615 #define RADEON_GART_PAGE_VALID (1 << 0)
616 #define RADEON_GART_PAGE_READ (1 << 1)
617 #define RADEON_GART_PAGE_WRITE (1 << 2)
618 #define RADEON_GART_PAGE_SNOOP (1 << 3)
619
620 struct radeon_gart {
621 dma_addr_t table_addr;
622 struct radeon_bo *robj;
623 void *ptr;
624 unsigned num_gpu_pages;
625 unsigned num_cpu_pages;
626 unsigned table_size;
627 struct page **pages;
628 dma_addr_t *pages_addr;
629 bool ready;
630 };
631
632 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
633 void radeon_gart_table_ram_free(struct radeon_device *rdev);
634 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
635 void radeon_gart_table_vram_free(struct radeon_device *rdev);
636 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
637 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
638 int radeon_gart_init(struct radeon_device *rdev);
639 void radeon_gart_fini(struct radeon_device *rdev);
640 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
641 int pages);
642 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
643 int pages, struct page **pagelist,
644 dma_addr_t *dma_addr, uint32_t flags);
645
646
647 /*
648 * GPU MC structures, functions & helpers
649 */
650 struct radeon_mc {
651 resource_size_t aper_size;
652 resource_size_t aper_base;
653 resource_size_t agp_base;
654 /* for some chips with <= 32MB we need to lie
655 * about vram size near mc fb location */
656 u64 mc_vram_size;
657 u64 visible_vram_size;
658 u64 gtt_size;
659 u64 gtt_start;
660 u64 gtt_end;
661 u64 vram_start;
662 u64 vram_end;
663 unsigned vram_width;
664 u64 real_vram_size;
665 int vram_mtrr;
666 bool vram_is_ddr;
667 bool igp_sideport_enabled;
668 u64 gtt_base_align;
669 u64 mc_mask;
670 };
671
672 bool radeon_combios_sideport_present(struct radeon_device *rdev);
673 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
674
675 /*
676 * GPU scratch registers structures, functions & helpers
677 */
678 struct radeon_scratch {
679 unsigned num_reg;
680 uint32_t reg_base;
681 bool free[32];
682 uint32_t reg[32];
683 };
684
685 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
686 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
687
688 /*
689 * GPU doorbell structures, functions & helpers
690 */
691 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
692
693 struct radeon_doorbell {
694 /* doorbell mmio */
695 resource_size_t base;
696 resource_size_t size;
697 u32 __iomem *ptr;
698 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
699 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
700 };
701
702 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
703 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
704
705 /*
706 * IRQS.
707 */
708
709 struct radeon_flip_work {
710 struct work_struct flip_work;
711 struct work_struct unpin_work;
712 struct radeon_device *rdev;
713 int crtc_id;
714 uint64_t base;
715 struct drm_pending_vblank_event *event;
716 struct radeon_bo *old_rbo;
717 struct fence *fence;
718 };
719
720 struct r500_irq_stat_regs {
721 u32 disp_int;
722 u32 hdmi0_status;
723 };
724
725 struct r600_irq_stat_regs {
726 u32 disp_int;
727 u32 disp_int_cont;
728 u32 disp_int_cont2;
729 u32 d1grph_int;
730 u32 d2grph_int;
731 u32 hdmi0_status;
732 u32 hdmi1_status;
733 };
734
735 struct evergreen_irq_stat_regs {
736 u32 disp_int;
737 u32 disp_int_cont;
738 u32 disp_int_cont2;
739 u32 disp_int_cont3;
740 u32 disp_int_cont4;
741 u32 disp_int_cont5;
742 u32 d1grph_int;
743 u32 d2grph_int;
744 u32 d3grph_int;
745 u32 d4grph_int;
746 u32 d5grph_int;
747 u32 d6grph_int;
748 u32 afmt_status1;
749 u32 afmt_status2;
750 u32 afmt_status3;
751 u32 afmt_status4;
752 u32 afmt_status5;
753 u32 afmt_status6;
754 };
755
756 struct cik_irq_stat_regs {
757 u32 disp_int;
758 u32 disp_int_cont;
759 u32 disp_int_cont2;
760 u32 disp_int_cont3;
761 u32 disp_int_cont4;
762 u32 disp_int_cont5;
763 u32 disp_int_cont6;
764 u32 d1grph_int;
765 u32 d2grph_int;
766 u32 d3grph_int;
767 u32 d4grph_int;
768 u32 d5grph_int;
769 u32 d6grph_int;
770 };
771
772 union radeon_irq_stat_regs {
773 struct r500_irq_stat_regs r500;
774 struct r600_irq_stat_regs r600;
775 struct evergreen_irq_stat_regs evergreen;
776 struct cik_irq_stat_regs cik;
777 };
778
779 struct radeon_irq {
780 bool installed;
781 spinlock_t lock;
782 atomic_t ring_int[RADEON_NUM_RINGS];
783 bool crtc_vblank_int[RADEON_MAX_CRTCS];
784 atomic_t pflip[RADEON_MAX_CRTCS];
785 wait_queue_head_t vblank_queue;
786 bool hpd[RADEON_MAX_HPD_PINS];
787 bool afmt[RADEON_MAX_AFMT_BLOCKS];
788 union radeon_irq_stat_regs stat_regs;
789 bool dpm_thermal;
790 };
791
792 int radeon_irq_kms_init(struct radeon_device *rdev);
793 void radeon_irq_kms_fini(struct radeon_device *rdev);
794 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
795 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
796 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
797 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
798 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
799 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
800 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
801 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
802 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
803
804 /*
805 * CP & rings.
806 */
807
808 struct radeon_ib {
809 struct radeon_sa_bo *sa_bo;
810 uint32_t length_dw;
811 uint64_t gpu_addr;
812 uint32_t *ptr;
813 int ring;
814 struct radeon_fence *fence;
815 struct radeon_vm *vm;
816 bool is_const_ib;
817 struct radeon_semaphore *semaphore;
818 };
819
820 struct radeon_ring {
821 struct radeon_bo *ring_obj;
822 volatile uint32_t *ring;
823 unsigned rptr_offs;
824 unsigned rptr_save_reg;
825 u64 next_rptr_gpu_addr;
826 volatile u32 *next_rptr_cpu_addr;
827 unsigned wptr;
828 unsigned wptr_old;
829 unsigned ring_size;
830 unsigned ring_free_dw;
831 int count_dw;
832 atomic_t last_rptr;
833 atomic64_t last_activity;
834 uint64_t gpu_addr;
835 uint32_t align_mask;
836 uint32_t ptr_mask;
837 bool ready;
838 u32 nop;
839 u32 idx;
840 u64 last_semaphore_signal_addr;
841 u64 last_semaphore_wait_addr;
842 /* for CIK queues */
843 u32 me;
844 u32 pipe;
845 u32 queue;
846 struct radeon_bo *mqd_obj;
847 u32 doorbell_index;
848 unsigned wptr_offs;
849 };
850
851 struct radeon_mec {
852 struct radeon_bo *hpd_eop_obj;
853 u64 hpd_eop_gpu_addr;
854 u32 num_pipe;
855 u32 num_mec;
856 u32 num_queue;
857 };
858
859 /*
860 * VM
861 */
862
863 /* maximum number of VMIDs */
864 #define RADEON_NUM_VM 16
865
866 /* number of entries in page table */
867 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
868
869 /* PTBs (Page Table Blocks) need to be aligned to 32K */
870 #define RADEON_VM_PTB_ALIGN_SIZE 32768
871 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
872 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
873
874 #define R600_PTE_VALID (1 << 0)
875 #define R600_PTE_SYSTEM (1 << 1)
876 #define R600_PTE_SNOOPED (1 << 2)
877 #define R600_PTE_READABLE (1 << 5)
878 #define R600_PTE_WRITEABLE (1 << 6)
879
880 /* PTE (Page Table Entry) fragment field for different page sizes */
881 #define R600_PTE_FRAG_4KB (0 << 7)
882 #define R600_PTE_FRAG_64KB (4 << 7)
883 #define R600_PTE_FRAG_256KB (6 << 7)
884
885 /* flags needed to be set so we can copy directly from the GART table */
886 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
887 R600_PTE_SYSTEM | R600_PTE_VALID )
888
889 struct radeon_vm_pt {
890 struct radeon_bo *bo;
891 uint64_t addr;
892 };
893
894 struct radeon_vm {
895 struct rb_root va;
896 unsigned id;
897
898 /* BOs moved, but not yet updated in the PT */
899 struct list_head invalidated;
900
901 /* BOs freed, but not yet updated in the PT */
902 struct list_head freed;
903
904 /* contains the page directory */
905 struct radeon_bo *page_directory;
906 uint64_t pd_gpu_addr;
907 unsigned max_pde_used;
908
909 /* array of page tables, one for each page directory entry */
910 struct radeon_vm_pt *page_tables;
911
912 struct radeon_bo_va *ib_bo_va;
913
914 struct mutex mutex;
915 /* last fence for cs using this vm */
916 struct radeon_fence *fence;
917 /* last flush or NULL if we still need to flush */
918 struct radeon_fence *last_flush;
919 /* last use of vmid */
920 struct radeon_fence *last_id_use;
921 };
922
923 struct radeon_vm_manager {
924 struct radeon_fence *active[RADEON_NUM_VM];
925 uint32_t max_pfn;
926 /* number of VMIDs */
927 unsigned nvm;
928 /* vram base address for page table entry */
929 u64 vram_base_offset;
930 /* is vm enabled? */
931 bool enabled;
932 /* for hw to save the PD addr on suspend/resume */
933 uint32_t saved_table_addr[RADEON_NUM_VM];
934 };
935
936 /*
937 * file private structure
938 */
939 struct radeon_fpriv {
940 struct radeon_vm vm;
941 };
942
943 /*
944 * R6xx+ IH ring
945 */
946 struct r600_ih {
947 struct radeon_bo *ring_obj;
948 volatile uint32_t *ring;
949 unsigned rptr;
950 unsigned ring_size;
951 uint64_t gpu_addr;
952 uint32_t ptr_mask;
953 atomic_t lock;
954 bool enabled;
955 };
956
957 /*
958 * RLC stuff
959 */
960 #include "clearstate_defs.h"
961
962 struct radeon_rlc {
963 /* for power gating */
964 struct radeon_bo *save_restore_obj;
965 uint64_t save_restore_gpu_addr;
966 volatile uint32_t *sr_ptr;
967 const u32 *reg_list;
968 u32 reg_list_size;
969 /* for clear state */
970 struct radeon_bo *clear_state_obj;
971 uint64_t clear_state_gpu_addr;
972 volatile uint32_t *cs_ptr;
973 const struct cs_section_def *cs_data;
974 u32 clear_state_size;
975 /* for cp tables */
976 struct radeon_bo *cp_table_obj;
977 uint64_t cp_table_gpu_addr;
978 volatile uint32_t *cp_table_ptr;
979 u32 cp_table_size;
980 };
981
982 int radeon_ib_get(struct radeon_device *rdev, int ring,
983 struct radeon_ib *ib, struct radeon_vm *vm,
984 unsigned size);
985 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
986 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
987 struct radeon_ib *const_ib, bool hdp_flush);
988 int radeon_ib_pool_init(struct radeon_device *rdev);
989 void radeon_ib_pool_fini(struct radeon_device *rdev);
990 int radeon_ib_ring_tests(struct radeon_device *rdev);
991 /* Ring access between begin & end cannot sleep */
992 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
993 struct radeon_ring *ring);
994 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
995 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
996 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
997 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
998 bool hdp_flush);
999 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1000 bool hdp_flush);
1001 void radeon_ring_undo(struct radeon_ring *ring);
1002 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1003 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1004 void radeon_ring_lockup_update(struct radeon_device *rdev,
1005 struct radeon_ring *ring);
1006 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1007 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1008 uint32_t **data);
1009 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1010 unsigned size, uint32_t *data);
1011 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1012 unsigned rptr_offs, u32 nop);
1013 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1014
1015
1016 /* r600 async dma */
1017 void r600_dma_stop(struct radeon_device *rdev);
1018 int r600_dma_resume(struct radeon_device *rdev);
1019 void r600_dma_fini(struct radeon_device *rdev);
1020
1021 void cayman_dma_stop(struct radeon_device *rdev);
1022 int cayman_dma_resume(struct radeon_device *rdev);
1023 void cayman_dma_fini(struct radeon_device *rdev);
1024
1025 /*
1026 * CS.
1027 */
1028 struct radeon_cs_reloc {
1029 struct drm_gem_object *gobj;
1030 struct radeon_bo *robj;
1031 struct ttm_validate_buffer tv;
1032 uint64_t gpu_offset;
1033 unsigned prefered_domains;
1034 unsigned allowed_domains;
1035 uint32_t tiling_flags;
1036 uint32_t handle;
1037 };
1038
1039 struct radeon_cs_chunk {
1040 uint32_t chunk_id;
1041 uint32_t length_dw;
1042 uint32_t *kdata;
1043 void __user *user_ptr;
1044 };
1045
1046 struct radeon_cs_parser {
1047 struct device *dev;
1048 struct radeon_device *rdev;
1049 struct drm_file *filp;
1050 /* chunks */
1051 unsigned nchunks;
1052 struct radeon_cs_chunk *chunks;
1053 uint64_t *chunks_array;
1054 /* IB */
1055 unsigned idx;
1056 /* relocations */
1057 unsigned nrelocs;
1058 struct radeon_cs_reloc *relocs;
1059 struct radeon_cs_reloc **relocs_ptr;
1060 struct radeon_cs_reloc *vm_bos;
1061 struct list_head validated;
1062 unsigned dma_reloc_idx;
1063 /* indices of various chunks */
1064 int chunk_ib_idx;
1065 int chunk_relocs_idx;
1066 int chunk_flags_idx;
1067 int chunk_const_ib_idx;
1068 struct radeon_ib ib;
1069 struct radeon_ib const_ib;
1070 void *track;
1071 unsigned family;
1072 int parser_error;
1073 u32 cs_flags;
1074 u32 ring;
1075 s32 priority;
1076 struct ww_acquire_ctx ticket;
1077 };
1078
1079 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1080 {
1081 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1082
1083 if (ibc->kdata)
1084 return ibc->kdata[idx];
1085 return p->ib.ptr[idx];
1086 }
1087
1088
1089 struct radeon_cs_packet {
1090 unsigned idx;
1091 unsigned type;
1092 unsigned reg;
1093 unsigned opcode;
1094 int count;
1095 unsigned one_reg_wr;
1096 };
1097
1098 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1099 struct radeon_cs_packet *pkt,
1100 unsigned idx, unsigned reg);
1101 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1102 struct radeon_cs_packet *pkt);
1103
1104
1105 /*
1106 * AGP
1107 */
1108 int radeon_agp_init(struct radeon_device *rdev);
1109 void radeon_agp_resume(struct radeon_device *rdev);
1110 void radeon_agp_suspend(struct radeon_device *rdev);
1111 void radeon_agp_fini(struct radeon_device *rdev);
1112
1113
1114 /*
1115 * Writeback
1116 */
1117 struct radeon_wb {
1118 struct radeon_bo *wb_obj;
1119 volatile uint32_t *wb;
1120 uint64_t gpu_addr;
1121 bool enabled;
1122 bool use_event;
1123 };
1124
1125 #define RADEON_WB_SCRATCH_OFFSET 0
1126 #define RADEON_WB_RING0_NEXT_RPTR 256
1127 #define RADEON_WB_CP_RPTR_OFFSET 1024
1128 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1129 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1130 #define R600_WB_DMA_RPTR_OFFSET 1792
1131 #define R600_WB_IH_WPTR_OFFSET 2048
1132 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1133 #define R600_WB_EVENT_OFFSET 3072
1134 #define CIK_WB_CP1_WPTR_OFFSET 3328
1135 #define CIK_WB_CP2_WPTR_OFFSET 3584
1136 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1137 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1138
1139 /**
1140 * struct radeon_pm - power management datas
1141 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1142 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1143 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1144 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1145 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1146 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1147 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1148 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1149 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1150 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1151 * @needed_bandwidth: current bandwidth needs
1152 *
1153 * It keeps track of various data needed to take powermanagement decision.
1154 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1155 * Equation between gpu/memory clock and available bandwidth is hw dependent
1156 * (type of memory, bus size, efficiency, ...)
1157 */
1158
1159 enum radeon_pm_method {
1160 PM_METHOD_PROFILE,
1161 PM_METHOD_DYNPM,
1162 PM_METHOD_DPM,
1163 };
1164
1165 enum radeon_dynpm_state {
1166 DYNPM_STATE_DISABLED,
1167 DYNPM_STATE_MINIMUM,
1168 DYNPM_STATE_PAUSED,
1169 DYNPM_STATE_ACTIVE,
1170 DYNPM_STATE_SUSPENDED,
1171 };
1172 enum radeon_dynpm_action {
1173 DYNPM_ACTION_NONE,
1174 DYNPM_ACTION_MINIMUM,
1175 DYNPM_ACTION_DOWNCLOCK,
1176 DYNPM_ACTION_UPCLOCK,
1177 DYNPM_ACTION_DEFAULT
1178 };
1179
1180 enum radeon_voltage_type {
1181 VOLTAGE_NONE = 0,
1182 VOLTAGE_GPIO,
1183 VOLTAGE_VDDC,
1184 VOLTAGE_SW
1185 };
1186
1187 enum radeon_pm_state_type {
1188 /* not used for dpm */
1189 POWER_STATE_TYPE_DEFAULT,
1190 POWER_STATE_TYPE_POWERSAVE,
1191 /* user selectable states */
1192 POWER_STATE_TYPE_BATTERY,
1193 POWER_STATE_TYPE_BALANCED,
1194 POWER_STATE_TYPE_PERFORMANCE,
1195 /* internal states */
1196 POWER_STATE_TYPE_INTERNAL_UVD,
1197 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1198 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1199 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1200 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1201 POWER_STATE_TYPE_INTERNAL_BOOT,
1202 POWER_STATE_TYPE_INTERNAL_THERMAL,
1203 POWER_STATE_TYPE_INTERNAL_ACPI,
1204 POWER_STATE_TYPE_INTERNAL_ULV,
1205 POWER_STATE_TYPE_INTERNAL_3DPERF,
1206 };
1207
1208 enum radeon_pm_profile_type {
1209 PM_PROFILE_DEFAULT,
1210 PM_PROFILE_AUTO,
1211 PM_PROFILE_LOW,
1212 PM_PROFILE_MID,
1213 PM_PROFILE_HIGH,
1214 };
1215
1216 #define PM_PROFILE_DEFAULT_IDX 0
1217 #define PM_PROFILE_LOW_SH_IDX 1
1218 #define PM_PROFILE_MID_SH_IDX 2
1219 #define PM_PROFILE_HIGH_SH_IDX 3
1220 #define PM_PROFILE_LOW_MH_IDX 4
1221 #define PM_PROFILE_MID_MH_IDX 5
1222 #define PM_PROFILE_HIGH_MH_IDX 6
1223 #define PM_PROFILE_MAX 7
1224
1225 struct radeon_pm_profile {
1226 int dpms_off_ps_idx;
1227 int dpms_on_ps_idx;
1228 int dpms_off_cm_idx;
1229 int dpms_on_cm_idx;
1230 };
1231
1232 enum radeon_int_thermal_type {
1233 THERMAL_TYPE_NONE,
1234 THERMAL_TYPE_EXTERNAL,
1235 THERMAL_TYPE_EXTERNAL_GPIO,
1236 THERMAL_TYPE_RV6XX,
1237 THERMAL_TYPE_RV770,
1238 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1239 THERMAL_TYPE_EVERGREEN,
1240 THERMAL_TYPE_SUMO,
1241 THERMAL_TYPE_NI,
1242 THERMAL_TYPE_SI,
1243 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1244 THERMAL_TYPE_CI,
1245 THERMAL_TYPE_KV,
1246 };
1247
1248 struct radeon_voltage {
1249 enum radeon_voltage_type type;
1250 /* gpio voltage */
1251 struct radeon_gpio_rec gpio;
1252 u32 delay; /* delay in usec from voltage drop to sclk change */
1253 bool active_high; /* voltage drop is active when bit is high */
1254 /* VDDC voltage */
1255 u8 vddc_id; /* index into vddc voltage table */
1256 u8 vddci_id; /* index into vddci voltage table */
1257 bool vddci_enabled;
1258 /* r6xx+ sw */
1259 u16 voltage;
1260 /* evergreen+ vddci */
1261 u16 vddci;
1262 };
1263
1264 /* clock mode flags */
1265 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1266
1267 struct radeon_pm_clock_info {
1268 /* memory clock */
1269 u32 mclk;
1270 /* engine clock */
1271 u32 sclk;
1272 /* voltage info */
1273 struct radeon_voltage voltage;
1274 /* standardized clock flags */
1275 u32 flags;
1276 };
1277
1278 /* state flags */
1279 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1280
1281 struct radeon_power_state {
1282 enum radeon_pm_state_type type;
1283 struct radeon_pm_clock_info *clock_info;
1284 /* number of valid clock modes in this power state */
1285 int num_clock_modes;
1286 struct radeon_pm_clock_info *default_clock_mode;
1287 /* standardized state flags */
1288 u32 flags;
1289 u32 misc; /* vbios specific flags */
1290 u32 misc2; /* vbios specific flags */
1291 int pcie_lanes; /* pcie lanes */
1292 };
1293
1294 /*
1295 * Some modes are overclocked by very low value, accept them
1296 */
1297 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1298
1299 enum radeon_dpm_auto_throttle_src {
1300 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1301 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1302 };
1303
1304 enum radeon_dpm_event_src {
1305 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1306 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1307 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1308 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1309 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1310 };
1311
1312 #define RADEON_MAX_VCE_LEVELS 6
1313
1314 enum radeon_vce_level {
1315 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1316 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1317 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1318 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1319 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1320 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1321 };
1322
1323 struct radeon_ps {
1324 u32 caps; /* vbios flags */
1325 u32 class; /* vbios flags */
1326 u32 class2; /* vbios flags */
1327 /* UVD clocks */
1328 u32 vclk;
1329 u32 dclk;
1330 /* VCE clocks */
1331 u32 evclk;
1332 u32 ecclk;
1333 bool vce_active;
1334 enum radeon_vce_level vce_level;
1335 /* asic priv */
1336 void *ps_priv;
1337 };
1338
1339 struct radeon_dpm_thermal {
1340 /* thermal interrupt work */
1341 struct work_struct work;
1342 /* low temperature threshold */
1343 int min_temp;
1344 /* high temperature threshold */
1345 int max_temp;
1346 /* was interrupt low to high or high to low */
1347 bool high_to_low;
1348 };
1349
1350 enum radeon_clk_action
1351 {
1352 RADEON_SCLK_UP = 1,
1353 RADEON_SCLK_DOWN
1354 };
1355
1356 struct radeon_blacklist_clocks
1357 {
1358 u32 sclk;
1359 u32 mclk;
1360 enum radeon_clk_action action;
1361 };
1362
1363 struct radeon_clock_and_voltage_limits {
1364 u32 sclk;
1365 u32 mclk;
1366 u16 vddc;
1367 u16 vddci;
1368 };
1369
1370 struct radeon_clock_array {
1371 u32 count;
1372 u32 *values;
1373 };
1374
1375 struct radeon_clock_voltage_dependency_entry {
1376 u32 clk;
1377 u16 v;
1378 };
1379
1380 struct radeon_clock_voltage_dependency_table {
1381 u32 count;
1382 struct radeon_clock_voltage_dependency_entry *entries;
1383 };
1384
1385 union radeon_cac_leakage_entry {
1386 struct {
1387 u16 vddc;
1388 u32 leakage;
1389 };
1390 struct {
1391 u16 vddc1;
1392 u16 vddc2;
1393 u16 vddc3;
1394 };
1395 };
1396
1397 struct radeon_cac_leakage_table {
1398 u32 count;
1399 union radeon_cac_leakage_entry *entries;
1400 };
1401
1402 struct radeon_phase_shedding_limits_entry {
1403 u16 voltage;
1404 u32 sclk;
1405 u32 mclk;
1406 };
1407
1408 struct radeon_phase_shedding_limits_table {
1409 u32 count;
1410 struct radeon_phase_shedding_limits_entry *entries;
1411 };
1412
1413 struct radeon_uvd_clock_voltage_dependency_entry {
1414 u32 vclk;
1415 u32 dclk;
1416 u16 v;
1417 };
1418
1419 struct radeon_uvd_clock_voltage_dependency_table {
1420 u8 count;
1421 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1422 };
1423
1424 struct radeon_vce_clock_voltage_dependency_entry {
1425 u32 ecclk;
1426 u32 evclk;
1427 u16 v;
1428 };
1429
1430 struct radeon_vce_clock_voltage_dependency_table {
1431 u8 count;
1432 struct radeon_vce_clock_voltage_dependency_entry *entries;
1433 };
1434
1435 struct radeon_ppm_table {
1436 u8 ppm_design;
1437 u16 cpu_core_number;
1438 u32 platform_tdp;
1439 u32 small_ac_platform_tdp;
1440 u32 platform_tdc;
1441 u32 small_ac_platform_tdc;
1442 u32 apu_tdp;
1443 u32 dgpu_tdp;
1444 u32 dgpu_ulv_power;
1445 u32 tj_max;
1446 };
1447
1448 struct radeon_cac_tdp_table {
1449 u16 tdp;
1450 u16 configurable_tdp;
1451 u16 tdc;
1452 u16 battery_power_limit;
1453 u16 small_power_limit;
1454 u16 low_cac_leakage;
1455 u16 high_cac_leakage;
1456 u16 maximum_power_delivery_limit;
1457 };
1458
1459 struct radeon_dpm_dynamic_state {
1460 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1461 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1462 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1463 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1464 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1465 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1466 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1467 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1468 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1469 struct radeon_clock_array valid_sclk_values;
1470 struct radeon_clock_array valid_mclk_values;
1471 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1472 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1473 u32 mclk_sclk_ratio;
1474 u32 sclk_mclk_delta;
1475 u16 vddc_vddci_delta;
1476 u16 min_vddc_for_pcie_gen2;
1477 struct radeon_cac_leakage_table cac_leakage_table;
1478 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1479 struct radeon_ppm_table *ppm_table;
1480 struct radeon_cac_tdp_table *cac_tdp_table;
1481 };
1482
1483 struct radeon_dpm_fan {
1484 u16 t_min;
1485 u16 t_med;
1486 u16 t_high;
1487 u16 pwm_min;
1488 u16 pwm_med;
1489 u16 pwm_high;
1490 u8 t_hyst;
1491 u32 cycle_delay;
1492 u16 t_max;
1493 bool ucode_fan_control;
1494 };
1495
1496 enum radeon_pcie_gen {
1497 RADEON_PCIE_GEN1 = 0,
1498 RADEON_PCIE_GEN2 = 1,
1499 RADEON_PCIE_GEN3 = 2,
1500 RADEON_PCIE_GEN_INVALID = 0xffff
1501 };
1502
1503 enum radeon_dpm_forced_level {
1504 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1505 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1506 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1507 };
1508
1509 struct radeon_vce_state {
1510 /* vce clocks */
1511 u32 evclk;
1512 u32 ecclk;
1513 /* gpu clocks */
1514 u32 sclk;
1515 u32 mclk;
1516 u8 clk_idx;
1517 u8 pstate;
1518 };
1519
1520 struct radeon_dpm {
1521 struct radeon_ps *ps;
1522 /* number of valid power states */
1523 int num_ps;
1524 /* current power state that is active */
1525 struct radeon_ps *current_ps;
1526 /* requested power state */
1527 struct radeon_ps *requested_ps;
1528 /* boot up power state */
1529 struct radeon_ps *boot_ps;
1530 /* default uvd power state */
1531 struct radeon_ps *uvd_ps;
1532 /* vce requirements */
1533 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1534 enum radeon_vce_level vce_level;
1535 enum radeon_pm_state_type state;
1536 enum radeon_pm_state_type user_state;
1537 u32 platform_caps;
1538 u32 voltage_response_time;
1539 u32 backbias_response_time;
1540 void *priv;
1541 u32 new_active_crtcs;
1542 int new_active_crtc_count;
1543 u32 current_active_crtcs;
1544 int current_active_crtc_count;
1545 struct radeon_dpm_dynamic_state dyn_state;
1546 struct radeon_dpm_fan fan;
1547 u32 tdp_limit;
1548 u32 near_tdp_limit;
1549 u32 near_tdp_limit_adjusted;
1550 u32 sq_ramping_threshold;
1551 u32 cac_leakage;
1552 u16 tdp_od_limit;
1553 u32 tdp_adjustment;
1554 u16 load_line_slope;
1555 bool power_control;
1556 bool ac_power;
1557 /* special states active */
1558 bool thermal_active;
1559 bool uvd_active;
1560 bool vce_active;
1561 /* thermal handling */
1562 struct radeon_dpm_thermal thermal;
1563 /* forced levels */
1564 enum radeon_dpm_forced_level forced_level;
1565 /* track UVD streams */
1566 unsigned sd;
1567 unsigned hd;
1568 };
1569
1570 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1571 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1572
1573 struct radeon_pm {
1574 struct mutex mutex;
1575 /* write locked while reprogramming mclk */
1576 struct rw_semaphore mclk_lock;
1577 u32 active_crtcs;
1578 int active_crtc_count;
1579 int req_vblank;
1580 bool vblank_sync;
1581 fixed20_12 max_bandwidth;
1582 fixed20_12 igp_sideport_mclk;
1583 fixed20_12 igp_system_mclk;
1584 fixed20_12 igp_ht_link_clk;
1585 fixed20_12 igp_ht_link_width;
1586 fixed20_12 k8_bandwidth;
1587 fixed20_12 sideport_bandwidth;
1588 fixed20_12 ht_bandwidth;
1589 fixed20_12 core_bandwidth;
1590 fixed20_12 sclk;
1591 fixed20_12 mclk;
1592 fixed20_12 needed_bandwidth;
1593 struct radeon_power_state *power_state;
1594 /* number of valid power states */
1595 int num_power_states;
1596 int current_power_state_index;
1597 int current_clock_mode_index;
1598 int requested_power_state_index;
1599 int requested_clock_mode_index;
1600 int default_power_state_index;
1601 u32 current_sclk;
1602 u32 current_mclk;
1603 u16 current_vddc;
1604 u16 current_vddci;
1605 u32 default_sclk;
1606 u32 default_mclk;
1607 u16 default_vddc;
1608 u16 default_vddci;
1609 struct radeon_i2c_chan *i2c_bus;
1610 /* selected pm method */
1611 enum radeon_pm_method pm_method;
1612 /* dynpm power management */
1613 struct delayed_work dynpm_idle_work;
1614 enum radeon_dynpm_state dynpm_state;
1615 enum radeon_dynpm_action dynpm_planned_action;
1616 unsigned long dynpm_action_timeout;
1617 bool dynpm_can_upclock;
1618 bool dynpm_can_downclock;
1619 /* profile-based power management */
1620 enum radeon_pm_profile_type profile;
1621 int profile_index;
1622 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1623 /* internal thermal controller on rv6xx+ */
1624 enum radeon_int_thermal_type int_thermal_type;
1625 struct device *int_hwmon_dev;
1626 /* dpm */
1627 bool dpm_enabled;
1628 struct radeon_dpm dpm;
1629 };
1630
1631 int radeon_pm_get_type_index(struct radeon_device *rdev,
1632 enum radeon_pm_state_type ps_type,
1633 int instance);
1634 /*
1635 * UVD
1636 */
1637 #define RADEON_MAX_UVD_HANDLES 10
1638 #define RADEON_UVD_STACK_SIZE (1024*1024)
1639 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1640
1641 struct radeon_uvd {
1642 struct radeon_bo *vcpu_bo;
1643 void *cpu_addr;
1644 uint64_t gpu_addr;
1645 void *saved_bo;
1646 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1647 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1648 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1649 struct delayed_work idle_work;
1650 };
1651
1652 int radeon_uvd_init(struct radeon_device *rdev);
1653 void radeon_uvd_fini(struct radeon_device *rdev);
1654 int radeon_uvd_suspend(struct radeon_device *rdev);
1655 int radeon_uvd_resume(struct radeon_device *rdev);
1656 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1657 uint32_t handle, struct radeon_fence **fence);
1658 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1659 uint32_t handle, struct radeon_fence **fence);
1660 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1661 uint32_t allowed_domains);
1662 void radeon_uvd_free_handles(struct radeon_device *rdev,
1663 struct drm_file *filp);
1664 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1665 void radeon_uvd_note_usage(struct radeon_device *rdev);
1666 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1667 unsigned vclk, unsigned dclk,
1668 unsigned vco_min, unsigned vco_max,
1669 unsigned fb_factor, unsigned fb_mask,
1670 unsigned pd_min, unsigned pd_max,
1671 unsigned pd_even,
1672 unsigned *optimal_fb_div,
1673 unsigned *optimal_vclk_div,
1674 unsigned *optimal_dclk_div);
1675 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1676 unsigned cg_upll_func_cntl);
1677
1678 /*
1679 * VCE
1680 */
1681 #define RADEON_MAX_VCE_HANDLES 16
1682 #define RADEON_VCE_STACK_SIZE (1024*1024)
1683 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1684
1685 struct radeon_vce {
1686 struct radeon_bo *vcpu_bo;
1687 uint64_t gpu_addr;
1688 unsigned fw_version;
1689 unsigned fb_version;
1690 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1691 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1692 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1693 struct delayed_work idle_work;
1694 };
1695
1696 int radeon_vce_init(struct radeon_device *rdev);
1697 void radeon_vce_fini(struct radeon_device *rdev);
1698 int radeon_vce_suspend(struct radeon_device *rdev);
1699 int radeon_vce_resume(struct radeon_device *rdev);
1700 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1701 uint32_t handle, struct radeon_fence **fence);
1702 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1703 uint32_t handle, struct radeon_fence **fence);
1704 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1705 void radeon_vce_note_usage(struct radeon_device *rdev);
1706 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1707 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1708 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1709 struct radeon_ring *ring,
1710 struct radeon_semaphore *semaphore,
1711 bool emit_wait);
1712 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1713 void radeon_vce_fence_emit(struct radeon_device *rdev,
1714 struct radeon_fence *fence);
1715 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1716 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1717
1718 struct r600_audio_pin {
1719 int channels;
1720 int rate;
1721 int bits_per_sample;
1722 u8 status_bits;
1723 u8 category_code;
1724 u32 offset;
1725 bool connected;
1726 u32 id;
1727 };
1728
1729 struct r600_audio {
1730 bool enabled;
1731 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1732 int num_pins;
1733 };
1734
1735 /*
1736 * Benchmarking
1737 */
1738 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1739
1740
1741 /*
1742 * Testing
1743 */
1744 void radeon_test_moves(struct radeon_device *rdev);
1745 void radeon_test_ring_sync(struct radeon_device *rdev,
1746 struct radeon_ring *cpA,
1747 struct radeon_ring *cpB);
1748 void radeon_test_syncing(struct radeon_device *rdev);
1749
1750 /*
1751 * MMU Notifier
1752 */
1753 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1754 void radeon_mn_unregister(struct radeon_bo *bo);
1755
1756 /*
1757 * Debugfs
1758 */
1759 struct radeon_debugfs {
1760 struct drm_info_list *files;
1761 unsigned num_files;
1762 };
1763
1764 int radeon_debugfs_add_files(struct radeon_device *rdev,
1765 struct drm_info_list *files,
1766 unsigned nfiles);
1767 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1768
1769 /*
1770 * ASIC ring specific functions.
1771 */
1772 struct radeon_asic_ring {
1773 /* ring read/write ptr handling */
1774 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1775 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1776 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1777
1778 /* validating and patching of IBs */
1779 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1780 int (*cs_parse)(struct radeon_cs_parser *p);
1781
1782 /* command emmit functions */
1783 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1784 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1785 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1786 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1787 struct radeon_semaphore *semaphore, bool emit_wait);
1788 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1789
1790 /* testing functions */
1791 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1792 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1793 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1794
1795 /* deprecated */
1796 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1797 };
1798
1799 /*
1800 * ASIC specific functions.
1801 */
1802 struct radeon_asic {
1803 int (*init)(struct radeon_device *rdev);
1804 void (*fini)(struct radeon_device *rdev);
1805 int (*resume)(struct radeon_device *rdev);
1806 int (*suspend)(struct radeon_device *rdev);
1807 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1808 int (*asic_reset)(struct radeon_device *rdev);
1809 /* Flush the HDP cache via MMIO */
1810 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1811 /* check if 3D engine is idle */
1812 bool (*gui_idle)(struct radeon_device *rdev);
1813 /* wait for mc_idle */
1814 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1815 /* get the reference clock */
1816 u32 (*get_xclk)(struct radeon_device *rdev);
1817 /* get the gpu clock counter */
1818 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1819 /* gart */
1820 struct {
1821 void (*tlb_flush)(struct radeon_device *rdev);
1822 void (*set_page)(struct radeon_device *rdev, unsigned i,
1823 uint64_t addr, uint32_t flags);
1824 } gart;
1825 struct {
1826 int (*init)(struct radeon_device *rdev);
1827 void (*fini)(struct radeon_device *rdev);
1828 void (*copy_pages)(struct radeon_device *rdev,
1829 struct radeon_ib *ib,
1830 uint64_t pe, uint64_t src,
1831 unsigned count);
1832 void (*write_pages)(struct radeon_device *rdev,
1833 struct radeon_ib *ib,
1834 uint64_t pe,
1835 uint64_t addr, unsigned count,
1836 uint32_t incr, uint32_t flags);
1837 void (*set_pages)(struct radeon_device *rdev,
1838 struct radeon_ib *ib,
1839 uint64_t pe,
1840 uint64_t addr, unsigned count,
1841 uint32_t incr, uint32_t flags);
1842 void (*pad_ib)(struct radeon_ib *ib);
1843 } vm;
1844 /* ring specific callbacks */
1845 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1846 /* irqs */
1847 struct {
1848 int (*set)(struct radeon_device *rdev);
1849 int (*process)(struct radeon_device *rdev);
1850 } irq;
1851 /* displays */
1852 struct {
1853 /* display watermarks */
1854 void (*bandwidth_update)(struct radeon_device *rdev);
1855 /* get frame count */
1856 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1857 /* wait for vblank */
1858 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1859 /* set backlight level */
1860 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1861 /* get backlight level */
1862 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1863 /* audio callbacks */
1864 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1865 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1866 } display;
1867 /* copy functions for bo handling */
1868 struct {
1869 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1870 uint64_t src_offset,
1871 uint64_t dst_offset,
1872 unsigned num_gpu_pages,
1873 struct reservation_object *resv);
1874 u32 blit_ring_index;
1875 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1876 uint64_t src_offset,
1877 uint64_t dst_offset,
1878 unsigned num_gpu_pages,
1879 struct reservation_object *resv);
1880 u32 dma_ring_index;
1881 /* method used for bo copy */
1882 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1883 uint64_t src_offset,
1884 uint64_t dst_offset,
1885 unsigned num_gpu_pages,
1886 struct reservation_object *resv);
1887 /* ring used for bo copies */
1888 u32 copy_ring_index;
1889 } copy;
1890 /* surfaces */
1891 struct {
1892 int (*set_reg)(struct radeon_device *rdev, int reg,
1893 uint32_t tiling_flags, uint32_t pitch,
1894 uint32_t offset, uint32_t obj_size);
1895 void (*clear_reg)(struct radeon_device *rdev, int reg);
1896 } surface;
1897 /* hotplug detect */
1898 struct {
1899 void (*init)(struct radeon_device *rdev);
1900 void (*fini)(struct radeon_device *rdev);
1901 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1902 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1903 } hpd;
1904 /* static power management */
1905 struct {
1906 void (*misc)(struct radeon_device *rdev);
1907 void (*prepare)(struct radeon_device *rdev);
1908 void (*finish)(struct radeon_device *rdev);
1909 void (*init_profile)(struct radeon_device *rdev);
1910 void (*get_dynpm_state)(struct radeon_device *rdev);
1911 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1912 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1913 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1914 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1915 int (*get_pcie_lanes)(struct radeon_device *rdev);
1916 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1917 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1918 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1919 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1920 int (*get_temperature)(struct radeon_device *rdev);
1921 } pm;
1922 /* dynamic power management */
1923 struct {
1924 int (*init)(struct radeon_device *rdev);
1925 void (*setup_asic)(struct radeon_device *rdev);
1926 int (*enable)(struct radeon_device *rdev);
1927 int (*late_enable)(struct radeon_device *rdev);
1928 void (*disable)(struct radeon_device *rdev);
1929 int (*pre_set_power_state)(struct radeon_device *rdev);
1930 int (*set_power_state)(struct radeon_device *rdev);
1931 void (*post_set_power_state)(struct radeon_device *rdev);
1932 void (*display_configuration_changed)(struct radeon_device *rdev);
1933 void (*fini)(struct radeon_device *rdev);
1934 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1935 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1936 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1937 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1938 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1939 bool (*vblank_too_short)(struct radeon_device *rdev);
1940 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1941 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1942 } dpm;
1943 /* pageflipping */
1944 struct {
1945 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1946 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1947 } pflip;
1948 };
1949
1950 /*
1951 * Asic structures
1952 */
1953 struct r100_asic {
1954 const unsigned *reg_safe_bm;
1955 unsigned reg_safe_bm_size;
1956 u32 hdp_cntl;
1957 };
1958
1959 struct r300_asic {
1960 const unsigned *reg_safe_bm;
1961 unsigned reg_safe_bm_size;
1962 u32 resync_scratch;
1963 u32 hdp_cntl;
1964 };
1965
1966 struct r600_asic {
1967 unsigned max_pipes;
1968 unsigned max_tile_pipes;
1969 unsigned max_simds;
1970 unsigned max_backends;
1971 unsigned max_gprs;
1972 unsigned max_threads;
1973 unsigned max_stack_entries;
1974 unsigned max_hw_contexts;
1975 unsigned max_gs_threads;
1976 unsigned sx_max_export_size;
1977 unsigned sx_max_export_pos_size;
1978 unsigned sx_max_export_smx_size;
1979 unsigned sq_num_cf_insts;
1980 unsigned tiling_nbanks;
1981 unsigned tiling_npipes;
1982 unsigned tiling_group_size;
1983 unsigned tile_config;
1984 unsigned backend_map;
1985 unsigned active_simds;
1986 };
1987
1988 struct rv770_asic {
1989 unsigned max_pipes;
1990 unsigned max_tile_pipes;
1991 unsigned max_simds;
1992 unsigned max_backends;
1993 unsigned max_gprs;
1994 unsigned max_threads;
1995 unsigned max_stack_entries;
1996 unsigned max_hw_contexts;
1997 unsigned max_gs_threads;
1998 unsigned sx_max_export_size;
1999 unsigned sx_max_export_pos_size;
2000 unsigned sx_max_export_smx_size;
2001 unsigned sq_num_cf_insts;
2002 unsigned sx_num_of_sets;
2003 unsigned sc_prim_fifo_size;
2004 unsigned sc_hiz_tile_fifo_size;
2005 unsigned sc_earlyz_tile_fifo_fize;
2006 unsigned tiling_nbanks;
2007 unsigned tiling_npipes;
2008 unsigned tiling_group_size;
2009 unsigned tile_config;
2010 unsigned backend_map;
2011 unsigned active_simds;
2012 };
2013
2014 struct evergreen_asic {
2015 unsigned num_ses;
2016 unsigned max_pipes;
2017 unsigned max_tile_pipes;
2018 unsigned max_simds;
2019 unsigned max_backends;
2020 unsigned max_gprs;
2021 unsigned max_threads;
2022 unsigned max_stack_entries;
2023 unsigned max_hw_contexts;
2024 unsigned max_gs_threads;
2025 unsigned sx_max_export_size;
2026 unsigned sx_max_export_pos_size;
2027 unsigned sx_max_export_smx_size;
2028 unsigned sq_num_cf_insts;
2029 unsigned sx_num_of_sets;
2030 unsigned sc_prim_fifo_size;
2031 unsigned sc_hiz_tile_fifo_size;
2032 unsigned sc_earlyz_tile_fifo_size;
2033 unsigned tiling_nbanks;
2034 unsigned tiling_npipes;
2035 unsigned tiling_group_size;
2036 unsigned tile_config;
2037 unsigned backend_map;
2038 unsigned active_simds;
2039 };
2040
2041 struct cayman_asic {
2042 unsigned max_shader_engines;
2043 unsigned max_pipes_per_simd;
2044 unsigned max_tile_pipes;
2045 unsigned max_simds_per_se;
2046 unsigned max_backends_per_se;
2047 unsigned max_texture_channel_caches;
2048 unsigned max_gprs;
2049 unsigned max_threads;
2050 unsigned max_gs_threads;
2051 unsigned max_stack_entries;
2052 unsigned sx_num_of_sets;
2053 unsigned sx_max_export_size;
2054 unsigned sx_max_export_pos_size;
2055 unsigned sx_max_export_smx_size;
2056 unsigned max_hw_contexts;
2057 unsigned sq_num_cf_insts;
2058 unsigned sc_prim_fifo_size;
2059 unsigned sc_hiz_tile_fifo_size;
2060 unsigned sc_earlyz_tile_fifo_size;
2061
2062 unsigned num_shader_engines;
2063 unsigned num_shader_pipes_per_simd;
2064 unsigned num_tile_pipes;
2065 unsigned num_simds_per_se;
2066 unsigned num_backends_per_se;
2067 unsigned backend_disable_mask_per_asic;
2068 unsigned backend_map;
2069 unsigned num_texture_channel_caches;
2070 unsigned mem_max_burst_length_bytes;
2071 unsigned mem_row_size_in_kb;
2072 unsigned shader_engine_tile_size;
2073 unsigned num_gpus;
2074 unsigned multi_gpu_tile_size;
2075
2076 unsigned tile_config;
2077 unsigned active_simds;
2078 };
2079
2080 struct si_asic {
2081 unsigned max_shader_engines;
2082 unsigned max_tile_pipes;
2083 unsigned max_cu_per_sh;
2084 unsigned max_sh_per_se;
2085 unsigned max_backends_per_se;
2086 unsigned max_texture_channel_caches;
2087 unsigned max_gprs;
2088 unsigned max_gs_threads;
2089 unsigned max_hw_contexts;
2090 unsigned sc_prim_fifo_size_frontend;
2091 unsigned sc_prim_fifo_size_backend;
2092 unsigned sc_hiz_tile_fifo_size;
2093 unsigned sc_earlyz_tile_fifo_size;
2094
2095 unsigned num_tile_pipes;
2096 unsigned backend_enable_mask;
2097 unsigned backend_disable_mask_per_asic;
2098 unsigned backend_map;
2099 unsigned num_texture_channel_caches;
2100 unsigned mem_max_burst_length_bytes;
2101 unsigned mem_row_size_in_kb;
2102 unsigned shader_engine_tile_size;
2103 unsigned num_gpus;
2104 unsigned multi_gpu_tile_size;
2105
2106 unsigned tile_config;
2107 uint32_t tile_mode_array[32];
2108 uint32_t active_cus;
2109 };
2110
2111 struct cik_asic {
2112 unsigned max_shader_engines;
2113 unsigned max_tile_pipes;
2114 unsigned max_cu_per_sh;
2115 unsigned max_sh_per_se;
2116 unsigned max_backends_per_se;
2117 unsigned max_texture_channel_caches;
2118 unsigned max_gprs;
2119 unsigned max_gs_threads;
2120 unsigned max_hw_contexts;
2121 unsigned sc_prim_fifo_size_frontend;
2122 unsigned sc_prim_fifo_size_backend;
2123 unsigned sc_hiz_tile_fifo_size;
2124 unsigned sc_earlyz_tile_fifo_size;
2125
2126 unsigned num_tile_pipes;
2127 unsigned backend_enable_mask;
2128 unsigned backend_disable_mask_per_asic;
2129 unsigned backend_map;
2130 unsigned num_texture_channel_caches;
2131 unsigned mem_max_burst_length_bytes;
2132 unsigned mem_row_size_in_kb;
2133 unsigned shader_engine_tile_size;
2134 unsigned num_gpus;
2135 unsigned multi_gpu_tile_size;
2136
2137 unsigned tile_config;
2138 uint32_t tile_mode_array[32];
2139 uint32_t macrotile_mode_array[16];
2140 uint32_t active_cus;
2141 };
2142
2143 union radeon_asic_config {
2144 struct r300_asic r300;
2145 struct r100_asic r100;
2146 struct r600_asic r600;
2147 struct rv770_asic rv770;
2148 struct evergreen_asic evergreen;
2149 struct cayman_asic cayman;
2150 struct si_asic si;
2151 struct cik_asic cik;
2152 };
2153
2154 /*
2155 * asic initizalization from radeon_asic.c
2156 */
2157 void radeon_agp_disable(struct radeon_device *rdev);
2158 int radeon_asic_init(struct radeon_device *rdev);
2159
2160
2161 /*
2162 * IOCTL.
2163 */
2164 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2165 struct drm_file *filp);
2166 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2167 struct drm_file *filp);
2168 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2169 struct drm_file *filp);
2170 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2171 struct drm_file *file_priv);
2172 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2173 struct drm_file *file_priv);
2174 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2175 struct drm_file *file_priv);
2176 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2177 struct drm_file *file_priv);
2178 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2179 struct drm_file *filp);
2180 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2181 struct drm_file *filp);
2182 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2183 struct drm_file *filp);
2184 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2185 struct drm_file *filp);
2186 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2187 struct drm_file *filp);
2188 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2189 struct drm_file *filp);
2190 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2191 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2192 struct drm_file *filp);
2193 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2194 struct drm_file *filp);
2195
2196 /* VRAM scratch page for HDP bug, default vram page */
2197 struct r600_vram_scratch {
2198 struct radeon_bo *robj;
2199 volatile uint32_t *ptr;
2200 u64 gpu_addr;
2201 };
2202
2203 /*
2204 * ACPI
2205 */
2206 struct radeon_atif_notification_cfg {
2207 bool enabled;
2208 int command_code;
2209 };
2210
2211 struct radeon_atif_notifications {
2212 bool display_switch;
2213 bool expansion_mode_change;
2214 bool thermal_state;
2215 bool forced_power_state;
2216 bool system_power_state;
2217 bool display_conf_change;
2218 bool px_gfx_switch;
2219 bool brightness_change;
2220 bool dgpu_display_event;
2221 };
2222
2223 struct radeon_atif_functions {
2224 bool system_params;
2225 bool sbios_requests;
2226 bool select_active_disp;
2227 bool lid_state;
2228 bool get_tv_standard;
2229 bool set_tv_standard;
2230 bool get_panel_expansion_mode;
2231 bool set_panel_expansion_mode;
2232 bool temperature_change;
2233 bool graphics_device_types;
2234 };
2235
2236 struct radeon_atif {
2237 struct radeon_atif_notifications notifications;
2238 struct radeon_atif_functions functions;
2239 struct radeon_atif_notification_cfg notification_cfg;
2240 struct radeon_encoder *encoder_for_bl;
2241 };
2242
2243 struct radeon_atcs_functions {
2244 bool get_ext_state;
2245 bool pcie_perf_req;
2246 bool pcie_dev_rdy;
2247 bool pcie_bus_width;
2248 };
2249
2250 struct radeon_atcs {
2251 struct radeon_atcs_functions functions;
2252 };
2253
2254 /*
2255 * Core structure, functions and helpers.
2256 */
2257 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2258 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2259
2260 struct radeon_device {
2261 struct device *dev;
2262 struct drm_device *ddev;
2263 struct pci_dev *pdev;
2264 struct rw_semaphore exclusive_lock;
2265 /* ASIC */
2266 union radeon_asic_config config;
2267 enum radeon_family family;
2268 unsigned long flags;
2269 int usec_timeout;
2270 enum radeon_pll_errata pll_errata;
2271 int num_gb_pipes;
2272 int num_z_pipes;
2273 int disp_priority;
2274 /* BIOS */
2275 uint8_t *bios;
2276 bool is_atom_bios;
2277 uint16_t bios_header_start;
2278 struct radeon_bo *stollen_vga_memory;
2279 /* Register mmio */
2280 resource_size_t rmmio_base;
2281 resource_size_t rmmio_size;
2282 /* protects concurrent MM_INDEX/DATA based register access */
2283 spinlock_t mmio_idx_lock;
2284 /* protects concurrent SMC based register access */
2285 spinlock_t smc_idx_lock;
2286 /* protects concurrent PLL register access */
2287 spinlock_t pll_idx_lock;
2288 /* protects concurrent MC register access */
2289 spinlock_t mc_idx_lock;
2290 /* protects concurrent PCIE register access */
2291 spinlock_t pcie_idx_lock;
2292 /* protects concurrent PCIE_PORT register access */
2293 spinlock_t pciep_idx_lock;
2294 /* protects concurrent PIF register access */
2295 spinlock_t pif_idx_lock;
2296 /* protects concurrent CG register access */
2297 spinlock_t cg_idx_lock;
2298 /* protects concurrent UVD register access */
2299 spinlock_t uvd_idx_lock;
2300 /* protects concurrent RCU register access */
2301 spinlock_t rcu_idx_lock;
2302 /* protects concurrent DIDT register access */
2303 spinlock_t didt_idx_lock;
2304 /* protects concurrent ENDPOINT (audio) register access */
2305 spinlock_t end_idx_lock;
2306 void __iomem *rmmio;
2307 radeon_rreg_t mc_rreg;
2308 radeon_wreg_t mc_wreg;
2309 radeon_rreg_t pll_rreg;
2310 radeon_wreg_t pll_wreg;
2311 uint32_t pcie_reg_mask;
2312 radeon_rreg_t pciep_rreg;
2313 radeon_wreg_t pciep_wreg;
2314 /* io port */
2315 void __iomem *rio_mem;
2316 resource_size_t rio_mem_size;
2317 struct radeon_clock clock;
2318 struct radeon_mc mc;
2319 struct radeon_gart gart;
2320 struct radeon_mode_info mode_info;
2321 struct radeon_scratch scratch;
2322 struct radeon_doorbell doorbell;
2323 struct radeon_mman mman;
2324 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2325 wait_queue_head_t fence_queue;
2326 unsigned fence_context;
2327 struct mutex ring_lock;
2328 struct radeon_ring ring[RADEON_NUM_RINGS];
2329 bool ib_pool_ready;
2330 struct radeon_sa_manager ring_tmp_bo;
2331 struct radeon_irq irq;
2332 struct radeon_asic *asic;
2333 struct radeon_gem gem;
2334 struct radeon_pm pm;
2335 struct radeon_uvd uvd;
2336 struct radeon_vce vce;
2337 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2338 struct radeon_wb wb;
2339 struct radeon_dummy_page dummy_page;
2340 bool shutdown;
2341 bool suspend;
2342 bool need_dma32;
2343 bool accel_working;
2344 bool fastfb_working; /* IGP feature*/
2345 bool needs_reset, in_reset;
2346 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2347 const struct firmware *me_fw; /* all family ME firmware */
2348 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2349 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2350 const struct firmware *mc_fw; /* NI MC firmware */
2351 const struct firmware *ce_fw; /* SI CE firmware */
2352 const struct firmware *mec_fw; /* CIK MEC firmware */
2353 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2354 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2355 const struct firmware *smc_fw; /* SMC firmware */
2356 const struct firmware *uvd_fw; /* UVD firmware */
2357 const struct firmware *vce_fw; /* VCE firmware */
2358 bool new_fw;
2359 struct r600_vram_scratch vram_scratch;
2360 int msi_enabled; /* msi enabled */
2361 struct r600_ih ih; /* r6/700 interrupt ring */
2362 struct radeon_rlc rlc;
2363 struct radeon_mec mec;
2364 struct work_struct hotplug_work;
2365 struct work_struct audio_work;
2366 int num_crtc; /* number of crtcs */
2367 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2368 bool has_uvd;
2369 struct r600_audio audio; /* audio stuff */
2370 struct notifier_block acpi_nb;
2371 /* only one userspace can use Hyperz features or CMASK at a time */
2372 struct drm_file *hyperz_filp;
2373 struct drm_file *cmask_filp;
2374 /* i2c buses */
2375 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2376 /* debugfs */
2377 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2378 unsigned debugfs_count;
2379 /* virtual memory */
2380 struct radeon_vm_manager vm_manager;
2381 struct mutex gpu_clock_mutex;
2382 /* memory stats */
2383 atomic64_t vram_usage;
2384 atomic64_t gtt_usage;
2385 atomic64_t num_bytes_moved;
2386 /* ACPI interface */
2387 struct radeon_atif atif;
2388 struct radeon_atcs atcs;
2389 /* srbm instance registers */
2390 struct mutex srbm_mutex;
2391 /* clock, powergating flags */
2392 u32 cg_flags;
2393 u32 pg_flags;
2394
2395 struct dev_pm_domain vga_pm_domain;
2396 bool have_disp_power_ref;
2397 u32 px_quirk_flags;
2398
2399 /* tracking pinned memory */
2400 u64 vram_pin_size;
2401 u64 gart_pin_size;
2402
2403 struct mutex mn_lock;
2404 DECLARE_HASHTABLE(mn_hash, 7);
2405 };
2406
2407 bool radeon_is_px(struct drm_device *dev);
2408 int radeon_device_init(struct radeon_device *rdev,
2409 struct drm_device *ddev,
2410 struct pci_dev *pdev,
2411 uint32_t flags);
2412 void radeon_device_fini(struct radeon_device *rdev);
2413 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2414
2415 #define RADEON_MIN_MMIO_SIZE 0x10000
2416
2417 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2418 bool always_indirect)
2419 {
2420 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2421 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2422 return readl(((void __iomem *)rdev->rmmio) + reg);
2423 else {
2424 unsigned long flags;
2425 uint32_t ret;
2426
2427 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2428 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2429 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2430 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2431
2432 return ret;
2433 }
2434 }
2435
2436 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2437 bool always_indirect)
2438 {
2439 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2440 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2441 else {
2442 unsigned long flags;
2443
2444 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2445 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2446 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2447 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2448 }
2449 }
2450
2451 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2452 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2453
2454 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2455 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2456
2457 /*
2458 * Cast helper
2459 */
2460 extern const struct fence_ops radeon_fence_ops;
2461
2462 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2463 {
2464 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2465
2466 if (__f->base.ops == &radeon_fence_ops)
2467 return __f;
2468
2469 return NULL;
2470 }
2471
2472 /*
2473 * Registers read & write functions.
2474 */
2475 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2476 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2477 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2478 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2479 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2480 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2481 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2482 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2483 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2484 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2485 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2486 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2487 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2488 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2489 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2490 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2491 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2492 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2493 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2494 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2495 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2496 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2497 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2498 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2499 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2500 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2501 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2502 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2503 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2504 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2505 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2506 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2507 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2508 #define WREG32_P(reg, val, mask) \
2509 do { \
2510 uint32_t tmp_ = RREG32(reg); \
2511 tmp_ &= (mask); \
2512 tmp_ |= ((val) & ~(mask)); \
2513 WREG32(reg, tmp_); \
2514 } while (0)
2515 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2516 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2517 #define WREG32_PLL_P(reg, val, mask) \
2518 do { \
2519 uint32_t tmp_ = RREG32_PLL(reg); \
2520 tmp_ &= (mask); \
2521 tmp_ |= ((val) & ~(mask)); \
2522 WREG32_PLL(reg, tmp_); \
2523 } while (0)
2524 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2525 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2526 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2527
2528 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2529 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2530
2531 /*
2532 * Indirect registers accessor
2533 */
2534 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2535 {
2536 unsigned long flags;
2537 uint32_t r;
2538
2539 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2540 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2541 r = RREG32(RADEON_PCIE_DATA);
2542 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2543 return r;
2544 }
2545
2546 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2547 {
2548 unsigned long flags;
2549
2550 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2551 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2552 WREG32(RADEON_PCIE_DATA, (v));
2553 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2554 }
2555
2556 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2557 {
2558 unsigned long flags;
2559 u32 r;
2560
2561 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2562 WREG32(TN_SMC_IND_INDEX_0, (reg));
2563 r = RREG32(TN_SMC_IND_DATA_0);
2564 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2565 return r;
2566 }
2567
2568 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2569 {
2570 unsigned long flags;
2571
2572 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2573 WREG32(TN_SMC_IND_INDEX_0, (reg));
2574 WREG32(TN_SMC_IND_DATA_0, (v));
2575 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2576 }
2577
2578 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2579 {
2580 unsigned long flags;
2581 u32 r;
2582
2583 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2584 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2585 r = RREG32(R600_RCU_DATA);
2586 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2587 return r;
2588 }
2589
2590 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2591 {
2592 unsigned long flags;
2593
2594 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2595 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2596 WREG32(R600_RCU_DATA, (v));
2597 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2598 }
2599
2600 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2601 {
2602 unsigned long flags;
2603 u32 r;
2604
2605 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2606 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2607 r = RREG32(EVERGREEN_CG_IND_DATA);
2608 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2609 return r;
2610 }
2611
2612 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2613 {
2614 unsigned long flags;
2615
2616 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2617 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2618 WREG32(EVERGREEN_CG_IND_DATA, (v));
2619 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2620 }
2621
2622 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2623 {
2624 unsigned long flags;
2625 u32 r;
2626
2627 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2628 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2629 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2630 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2631 return r;
2632 }
2633
2634 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2635 {
2636 unsigned long flags;
2637
2638 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2639 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2640 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2641 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2642 }
2643
2644 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2645 {
2646 unsigned long flags;
2647 u32 r;
2648
2649 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2650 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2651 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2652 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2653 return r;
2654 }
2655
2656 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2657 {
2658 unsigned long flags;
2659
2660 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2661 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2662 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2663 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2664 }
2665
2666 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2667 {
2668 unsigned long flags;
2669 u32 r;
2670
2671 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2672 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2673 r = RREG32(R600_UVD_CTX_DATA);
2674 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2675 return r;
2676 }
2677
2678 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2679 {
2680 unsigned long flags;
2681
2682 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2683 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2684 WREG32(R600_UVD_CTX_DATA, (v));
2685 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2686 }
2687
2688
2689 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2690 {
2691 unsigned long flags;
2692 u32 r;
2693
2694 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2695 WREG32(CIK_DIDT_IND_INDEX, (reg));
2696 r = RREG32(CIK_DIDT_IND_DATA);
2697 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2698 return r;
2699 }
2700
2701 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2702 {
2703 unsigned long flags;
2704
2705 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2706 WREG32(CIK_DIDT_IND_INDEX, (reg));
2707 WREG32(CIK_DIDT_IND_DATA, (v));
2708 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2709 }
2710
2711 void r100_pll_errata_after_index(struct radeon_device *rdev);
2712
2713
2714 /*
2715 * ASICs helpers.
2716 */
2717 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2718 (rdev->pdev->device == 0x5969))
2719 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2720 (rdev->family == CHIP_RV200) || \
2721 (rdev->family == CHIP_RS100) || \
2722 (rdev->family == CHIP_RS200) || \
2723 (rdev->family == CHIP_RV250) || \
2724 (rdev->family == CHIP_RV280) || \
2725 (rdev->family == CHIP_RS300))
2726 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2727 (rdev->family == CHIP_RV350) || \
2728 (rdev->family == CHIP_R350) || \
2729 (rdev->family == CHIP_RV380) || \
2730 (rdev->family == CHIP_R420) || \
2731 (rdev->family == CHIP_R423) || \
2732 (rdev->family == CHIP_RV410) || \
2733 (rdev->family == CHIP_RS400) || \
2734 (rdev->family == CHIP_RS480))
2735 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2736 (rdev->ddev->pdev->device == 0x9443) || \
2737 (rdev->ddev->pdev->device == 0x944B) || \
2738 (rdev->ddev->pdev->device == 0x9506) || \
2739 (rdev->ddev->pdev->device == 0x9509) || \
2740 (rdev->ddev->pdev->device == 0x950F) || \
2741 (rdev->ddev->pdev->device == 0x689C) || \
2742 (rdev->ddev->pdev->device == 0x689D))
2743 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2744 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2745 (rdev->family == CHIP_RS690) || \
2746 (rdev->family == CHIP_RS740) || \
2747 (rdev->family >= CHIP_R600))
2748 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2749 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2750 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2751 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2752 (rdev->flags & RADEON_IS_IGP))
2753 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2754 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2755 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2756 (rdev->flags & RADEON_IS_IGP))
2757 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2758 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2759 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2760 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2761 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2762 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2763 (rdev->family == CHIP_MULLINS))
2764
2765 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2766 (rdev->ddev->pdev->device == 0x6850) || \
2767 (rdev->ddev->pdev->device == 0x6858) || \
2768 (rdev->ddev->pdev->device == 0x6859) || \
2769 (rdev->ddev->pdev->device == 0x6840) || \
2770 (rdev->ddev->pdev->device == 0x6841) || \
2771 (rdev->ddev->pdev->device == 0x6842) || \
2772 (rdev->ddev->pdev->device == 0x6843))
2773
2774 /*
2775 * BIOS helpers.
2776 */
2777 #define RBIOS8(i) (rdev->bios[i])
2778 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2779 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2780
2781 int radeon_combios_init(struct radeon_device *rdev);
2782 void radeon_combios_fini(struct radeon_device *rdev);
2783 int radeon_atombios_init(struct radeon_device *rdev);
2784 void radeon_atombios_fini(struct radeon_device *rdev);
2785
2786
2787 /*
2788 * RING helpers.
2789 */
2790
2791 /**
2792 * radeon_ring_write - write a value to the ring
2793 *
2794 * @ring: radeon_ring structure holding ring information
2795 * @v: dword (dw) value to write
2796 *
2797 * Write a value to the requested ring buffer (all asics).
2798 */
2799 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2800 {
2801 if (ring->count_dw <= 0)
2802 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2803
2804 ring->ring[ring->wptr++] = v;
2805 ring->wptr &= ring->ptr_mask;
2806 ring->count_dw--;
2807 ring->ring_free_dw--;
2808 }
2809
2810 /*
2811 * ASICs macro.
2812 */
2813 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2814 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2815 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2816 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2817 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2818 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2819 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2820 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2821 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2822 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2823 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2824 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2825 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2826 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2827 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2828 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2829 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2830 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2831 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2832 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2833 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2834 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2835 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2836 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2837 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2838 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2839 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2840 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2841 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2842 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2843 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2844 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2845 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2846 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2847 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2848 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2849 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2850 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2851 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2852 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2853 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2854 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2855 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2856 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2857 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2858 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2859 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2860 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2861 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2862 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2863 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2864 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2865 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2866 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2867 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2868 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2869 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2870 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2871 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2872 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2873 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2874 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2875 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2876 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2877 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2878 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2879 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2880 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2881 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2882 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2883 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2884 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2885 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2886 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2887 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2888 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2889 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2890 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2891 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2892 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2893 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2894 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2895 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2896 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2897 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2898 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2899 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2900
2901 /* Common functions */
2902 /* AGP */
2903 extern int radeon_gpu_reset(struct radeon_device *rdev);
2904 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2905 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2906 extern void radeon_agp_disable(struct radeon_device *rdev);
2907 extern int radeon_modeset_init(struct radeon_device *rdev);
2908 extern void radeon_modeset_fini(struct radeon_device *rdev);
2909 extern bool radeon_card_posted(struct radeon_device *rdev);
2910 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2911 extern void radeon_update_display_priority(struct radeon_device *rdev);
2912 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2913 extern void radeon_scratch_init(struct radeon_device *rdev);
2914 extern void radeon_wb_fini(struct radeon_device *rdev);
2915 extern int radeon_wb_init(struct radeon_device *rdev);
2916 extern void radeon_wb_disable(struct radeon_device *rdev);
2917 extern void radeon_surface_init(struct radeon_device *rdev);
2918 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2919 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2920 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2921 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2922 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2923 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2924 uint32_t flags);
2925 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2926 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2927 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2928 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2929 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2930 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2931 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2932 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2933 const u32 *registers,
2934 const u32 array_size);
2935
2936 /*
2937 * vm
2938 */
2939 int radeon_vm_manager_init(struct radeon_device *rdev);
2940 void radeon_vm_manager_fini(struct radeon_device *rdev);
2941 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2942 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2943 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2944 struct radeon_vm *vm,
2945 struct list_head *head);
2946 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2947 struct radeon_vm *vm, int ring);
2948 void radeon_vm_flush(struct radeon_device *rdev,
2949 struct radeon_vm *vm,
2950 int ring);
2951 void radeon_vm_fence(struct radeon_device *rdev,
2952 struct radeon_vm *vm,
2953 struct radeon_fence *fence);
2954 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2955 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2956 struct radeon_vm *vm);
2957 int radeon_vm_clear_freed(struct radeon_device *rdev,
2958 struct radeon_vm *vm);
2959 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2960 struct radeon_vm *vm);
2961 int radeon_vm_bo_update(struct radeon_device *rdev,
2962 struct radeon_bo_va *bo_va,
2963 struct ttm_mem_reg *mem);
2964 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2965 struct radeon_bo *bo);
2966 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2967 struct radeon_bo *bo);
2968 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2969 struct radeon_vm *vm,
2970 struct radeon_bo *bo);
2971 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2972 struct radeon_bo_va *bo_va,
2973 uint64_t offset,
2974 uint32_t flags);
2975 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2976 struct radeon_bo_va *bo_va);
2977
2978 /* audio */
2979 void r600_audio_update_hdmi(struct work_struct *work);
2980 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2981 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2982 void r600_audio_enable(struct radeon_device *rdev,
2983 struct r600_audio_pin *pin,
2984 u8 enable_mask);
2985 void dce6_audio_enable(struct radeon_device *rdev,
2986 struct r600_audio_pin *pin,
2987 u8 enable_mask);
2988
2989 /*
2990 * R600 vram scratch functions
2991 */
2992 int r600_vram_scratch_init(struct radeon_device *rdev);
2993 void r600_vram_scratch_fini(struct radeon_device *rdev);
2994
2995 /*
2996 * r600 cs checking helper
2997 */
2998 unsigned r600_mip_minify(unsigned size, unsigned level);
2999 bool r600_fmt_is_valid_color(u32 format);
3000 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3001 int r600_fmt_get_blocksize(u32 format);
3002 int r600_fmt_get_nblocksx(u32 format, u32 w);
3003 int r600_fmt_get_nblocksy(u32 format, u32 h);
3004
3005 /*
3006 * r600 functions used by radeon_encoder.c
3007 */
3008 struct radeon_hdmi_acr {
3009 u32 clock;
3010
3011 int n_32khz;
3012 int cts_32khz;
3013
3014 int n_44_1khz;
3015 int cts_44_1khz;
3016
3017 int n_48khz;
3018 int cts_48khz;
3019
3020 };
3021
3022 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3023
3024 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3025 u32 tiling_pipe_num,
3026 u32 max_rb_num,
3027 u32 total_max_rb_num,
3028 u32 enabled_rb_mask);
3029
3030 /*
3031 * evergreen functions used by radeon_encoder.c
3032 */
3033
3034 extern int ni_init_microcode(struct radeon_device *rdev);
3035 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3036
3037 /* radeon_acpi.c */
3038 #if defined(CONFIG_ACPI)
3039 extern int radeon_acpi_init(struct radeon_device *rdev);
3040 extern void radeon_acpi_fini(struct radeon_device *rdev);
3041 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3042 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3043 u8 perf_req, bool advertise);
3044 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3045 #else
3046 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3047 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3048 #endif
3049
3050 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3051 struct radeon_cs_packet *pkt,
3052 unsigned idx);
3053 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3054 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3055 struct radeon_cs_packet *pkt);
3056 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3057 struct radeon_cs_reloc **cs_reloc,
3058 int nomm);
3059 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3060 uint32_t *vline_start_end,
3061 uint32_t *vline_status);
3062
3063 #include "radeon_object.h"
3064
3065 #endif
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