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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
76
77 /*
78 * Modules parameters.
79 */
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
90 extern int radeon_tv;
91 extern int radeon_new_pll;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95
96 /*
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
98 * symbol;
99 */
100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
102 /* RADEON_IB_POOL_SIZE must be a power of 2 */
103 #define RADEON_IB_POOL_SIZE 16
104 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
105 #define RADEONFB_CONN_LIMIT 4
106 #define RADEON_BIOS_NUM_SCRATCH 8
107
108 /*
109 * Errata workarounds.
110 */
111 enum radeon_pll_errata {
112 CHIP_ERRATA_R300_CG = 0x00000001,
113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
114 CHIP_ERRATA_PLL_DELAY = 0x00000004
115 };
116
117
118 struct radeon_device;
119
120
121 /*
122 * BIOS.
123 */
124 #define ATRM_BIOS_PAGE 4096
125
126 #if defined(CONFIG_VGA_SWITCHEROO)
127 bool radeon_atrm_supported(struct pci_dev *pdev);
128 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
129 #else
130 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
131 {
132 return false;
133 }
134
135 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
136 return -EINVAL;
137 }
138 #endif
139 bool radeon_get_bios(struct radeon_device *rdev);
140
141
142 /*
143 * Dummy page
144 */
145 struct radeon_dummy_page {
146 struct page *page;
147 dma_addr_t addr;
148 };
149 int radeon_dummy_page_init(struct radeon_device *rdev);
150 void radeon_dummy_page_fini(struct radeon_device *rdev);
151
152
153 /*
154 * Clocks
155 */
156 struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll dcpll;
160 struct radeon_pll spll;
161 struct radeon_pll mpll;
162 /* 10 Khz units */
163 uint32_t default_mclk;
164 uint32_t default_sclk;
165 uint32_t default_dispclk;
166 uint32_t dp_extclk;
167 };
168
169 /*
170 * Power management
171 */
172 int radeon_pm_init(struct radeon_device *rdev);
173 void radeon_pm_fini(struct radeon_device *rdev);
174 void radeon_pm_compute_clocks(struct radeon_device *rdev);
175 void radeon_pm_suspend(struct radeon_device *rdev);
176 void radeon_pm_resume(struct radeon_device *rdev);
177 void radeon_combios_get_power_modes(struct radeon_device *rdev);
178 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
180 void rs690_pm_info(struct radeon_device *rdev);
181
182 /*
183 * Fences.
184 */
185 struct radeon_fence_driver {
186 uint32_t scratch_reg;
187 atomic_t seq;
188 uint32_t last_seq;
189 unsigned long last_jiffies;
190 unsigned long last_timeout;
191 wait_queue_head_t queue;
192 rwlock_t lock;
193 struct list_head created;
194 struct list_head emited;
195 struct list_head signaled;
196 bool initialized;
197 };
198
199 struct radeon_fence {
200 struct radeon_device *rdev;
201 struct kref kref;
202 struct list_head list;
203 /* protected by radeon_fence.lock */
204 uint32_t seq;
205 bool emited;
206 bool signaled;
207 };
208
209 int radeon_fence_driver_init(struct radeon_device *rdev);
210 void radeon_fence_driver_fini(struct radeon_device *rdev);
211 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
212 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
213 void radeon_fence_process(struct radeon_device *rdev);
214 bool radeon_fence_signaled(struct radeon_fence *fence);
215 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
216 int radeon_fence_wait_next(struct radeon_device *rdev);
217 int radeon_fence_wait_last(struct radeon_device *rdev);
218 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
219 void radeon_fence_unref(struct radeon_fence **fence);
220
221 /*
222 * Tiling registers
223 */
224 struct radeon_surface_reg {
225 struct radeon_bo *bo;
226 };
227
228 #define RADEON_GEM_MAX_SURFACES 8
229
230 /*
231 * TTM.
232 */
233 struct radeon_mman {
234 struct ttm_bo_global_ref bo_global_ref;
235 struct ttm_global_reference mem_global_ref;
236 struct ttm_bo_device bdev;
237 bool mem_global_referenced;
238 bool initialized;
239 };
240
241 struct radeon_bo {
242 /* Protected by gem.mutex */
243 struct list_head list;
244 /* Protected by tbo.reserved */
245 u32 placements[3];
246 struct ttm_placement placement;
247 struct ttm_buffer_object tbo;
248 struct ttm_bo_kmap_obj kmap;
249 unsigned pin_count;
250 void *kptr;
251 u32 tiling_flags;
252 u32 pitch;
253 int surface_reg;
254 /* Constant after initialization */
255 struct radeon_device *rdev;
256 struct drm_gem_object *gobj;
257 };
258
259 struct radeon_bo_list {
260 struct list_head list;
261 struct radeon_bo *bo;
262 uint64_t gpu_offset;
263 unsigned rdomain;
264 unsigned wdomain;
265 u32 tiling_flags;
266 bool reserved;
267 };
268
269 /*
270 * GEM objects.
271 */
272 struct radeon_gem {
273 struct mutex mutex;
274 struct list_head objects;
275 };
276
277 int radeon_gem_init(struct radeon_device *rdev);
278 void radeon_gem_fini(struct radeon_device *rdev);
279 int radeon_gem_object_create(struct radeon_device *rdev, int size,
280 int alignment, int initial_domain,
281 bool discardable, bool kernel,
282 struct drm_gem_object **obj);
283 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
284 uint64_t *gpu_addr);
285 void radeon_gem_object_unpin(struct drm_gem_object *obj);
286
287
288 /*
289 * GART structures, functions & helpers
290 */
291 struct radeon_mc;
292
293 struct radeon_gart_table_ram {
294 volatile uint32_t *ptr;
295 };
296
297 struct radeon_gart_table_vram {
298 struct radeon_bo *robj;
299 volatile uint32_t *ptr;
300 };
301
302 union radeon_gart_table {
303 struct radeon_gart_table_ram ram;
304 struct radeon_gart_table_vram vram;
305 };
306
307 #define RADEON_GPU_PAGE_SIZE 4096
308 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
309
310 struct radeon_gart {
311 dma_addr_t table_addr;
312 unsigned num_gpu_pages;
313 unsigned num_cpu_pages;
314 unsigned table_size;
315 union radeon_gart_table table;
316 struct page **pages;
317 dma_addr_t *pages_addr;
318 bool ready;
319 };
320
321 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
322 void radeon_gart_table_ram_free(struct radeon_device *rdev);
323 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
324 void radeon_gart_table_vram_free(struct radeon_device *rdev);
325 int radeon_gart_init(struct radeon_device *rdev);
326 void radeon_gart_fini(struct radeon_device *rdev);
327 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
328 int pages);
329 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
330 int pages, struct page **pagelist);
331
332
333 /*
334 * GPU MC structures, functions & helpers
335 */
336 struct radeon_mc {
337 resource_size_t aper_size;
338 resource_size_t aper_base;
339 resource_size_t agp_base;
340 /* for some chips with <= 32MB we need to lie
341 * about vram size near mc fb location */
342 u64 mc_vram_size;
343 u64 visible_vram_size;
344 u64 gtt_size;
345 u64 gtt_start;
346 u64 gtt_end;
347 u64 vram_start;
348 u64 vram_end;
349 unsigned vram_width;
350 u64 real_vram_size;
351 int vram_mtrr;
352 bool vram_is_ddr;
353 bool igp_sideport_enabled;
354 };
355
356 bool radeon_combios_sideport_present(struct radeon_device *rdev);
357 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
358
359 /*
360 * GPU scratch registers structures, functions & helpers
361 */
362 struct radeon_scratch {
363 unsigned num_reg;
364 bool free[32];
365 uint32_t reg[32];
366 };
367
368 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
369 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
370
371
372 /*
373 * IRQS.
374 */
375 struct radeon_irq {
376 bool installed;
377 bool sw_int;
378 /* FIXME: use a define max crtc rather than hardcode it */
379 bool crtc_vblank_int[6];
380 wait_queue_head_t vblank_queue;
381 /* FIXME: use defines for max hpd/dacs */
382 bool hpd[6];
383 bool gui_idle;
384 bool gui_idle_acked;
385 wait_queue_head_t idle_queue;
386 /* FIXME: use defines for max HDMI blocks */
387 bool hdmi[2];
388 spinlock_t sw_lock;
389 int sw_refcount;
390 };
391
392 int radeon_irq_kms_init(struct radeon_device *rdev);
393 void radeon_irq_kms_fini(struct radeon_device *rdev);
394 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
395 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
396
397 /*
398 * CP & ring.
399 */
400 struct radeon_ib {
401 struct list_head list;
402 unsigned idx;
403 uint64_t gpu_addr;
404 struct radeon_fence *fence;
405 uint32_t *ptr;
406 uint32_t length_dw;
407 bool free;
408 };
409
410 /*
411 * locking -
412 * mutex protects scheduled_ibs, ready, alloc_bm
413 */
414 struct radeon_ib_pool {
415 struct mutex mutex;
416 struct radeon_bo *robj;
417 struct list_head bogus_ib;
418 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
419 bool ready;
420 unsigned head_id;
421 };
422
423 struct radeon_cp {
424 struct radeon_bo *ring_obj;
425 volatile uint32_t *ring;
426 unsigned rptr;
427 unsigned wptr;
428 unsigned wptr_old;
429 unsigned ring_size;
430 unsigned ring_free_dw;
431 int count_dw;
432 uint64_t gpu_addr;
433 uint32_t align_mask;
434 uint32_t ptr_mask;
435 struct mutex mutex;
436 bool ready;
437 };
438
439 /*
440 * R6xx+ IH ring
441 */
442 struct r600_ih {
443 struct radeon_bo *ring_obj;
444 volatile uint32_t *ring;
445 unsigned rptr;
446 unsigned wptr;
447 unsigned wptr_old;
448 unsigned ring_size;
449 uint64_t gpu_addr;
450 uint32_t ptr_mask;
451 spinlock_t lock;
452 bool enabled;
453 };
454
455 struct r600_blit {
456 struct mutex mutex;
457 struct radeon_bo *shader_obj;
458 u64 shader_gpu_addr;
459 u32 vs_offset, ps_offset;
460 u32 state_offset;
461 u32 state_len;
462 u32 vb_used, vb_total;
463 struct radeon_ib *vb_ib;
464 };
465
466 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
467 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
468 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
469 int radeon_ib_pool_init(struct radeon_device *rdev);
470 void radeon_ib_pool_fini(struct radeon_device *rdev);
471 int radeon_ib_test(struct radeon_device *rdev);
472 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
473 /* Ring access between begin & end cannot sleep */
474 void radeon_ring_free_size(struct radeon_device *rdev);
475 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
476 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
477 void radeon_ring_commit(struct radeon_device *rdev);
478 void radeon_ring_unlock_commit(struct radeon_device *rdev);
479 void radeon_ring_unlock_undo(struct radeon_device *rdev);
480 int radeon_ring_test(struct radeon_device *rdev);
481 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
482 void radeon_ring_fini(struct radeon_device *rdev);
483
484
485 /*
486 * CS.
487 */
488 struct radeon_cs_reloc {
489 struct drm_gem_object *gobj;
490 struct radeon_bo *robj;
491 struct radeon_bo_list lobj;
492 uint32_t handle;
493 uint32_t flags;
494 };
495
496 struct radeon_cs_chunk {
497 uint32_t chunk_id;
498 uint32_t length_dw;
499 int kpage_idx[2];
500 uint32_t *kpage[2];
501 uint32_t *kdata;
502 void __user *user_ptr;
503 int last_copied_page;
504 int last_page_index;
505 };
506
507 struct radeon_cs_parser {
508 struct device *dev;
509 struct radeon_device *rdev;
510 struct drm_file *filp;
511 /* chunks */
512 unsigned nchunks;
513 struct radeon_cs_chunk *chunks;
514 uint64_t *chunks_array;
515 /* IB */
516 unsigned idx;
517 /* relocations */
518 unsigned nrelocs;
519 struct radeon_cs_reloc *relocs;
520 struct radeon_cs_reloc **relocs_ptr;
521 struct list_head validated;
522 /* indices of various chunks */
523 int chunk_ib_idx;
524 int chunk_relocs_idx;
525 struct radeon_ib *ib;
526 void *track;
527 unsigned family;
528 int parser_error;
529 };
530
531 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
532 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
533
534
535 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
536 {
537 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
538 u32 pg_idx, pg_offset;
539 u32 idx_value = 0;
540 int new_page;
541
542 pg_idx = (idx * 4) / PAGE_SIZE;
543 pg_offset = (idx * 4) % PAGE_SIZE;
544
545 if (ibc->kpage_idx[0] == pg_idx)
546 return ibc->kpage[0][pg_offset/4];
547 if (ibc->kpage_idx[1] == pg_idx)
548 return ibc->kpage[1][pg_offset/4];
549
550 new_page = radeon_cs_update_pages(p, pg_idx);
551 if (new_page < 0) {
552 p->parser_error = new_page;
553 return 0;
554 }
555
556 idx_value = ibc->kpage[new_page][pg_offset/4];
557 return idx_value;
558 }
559
560 struct radeon_cs_packet {
561 unsigned idx;
562 unsigned type;
563 unsigned reg;
564 unsigned opcode;
565 int count;
566 unsigned one_reg_wr;
567 };
568
569 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
570 struct radeon_cs_packet *pkt,
571 unsigned idx, unsigned reg);
572 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
573 struct radeon_cs_packet *pkt);
574
575
576 /*
577 * AGP
578 */
579 int radeon_agp_init(struct radeon_device *rdev);
580 void radeon_agp_resume(struct radeon_device *rdev);
581 void radeon_agp_suspend(struct radeon_device *rdev);
582 void radeon_agp_fini(struct radeon_device *rdev);
583
584
585 /*
586 * Writeback
587 */
588 struct radeon_wb {
589 struct radeon_bo *wb_obj;
590 volatile uint32_t *wb;
591 uint64_t gpu_addr;
592 };
593
594 /**
595 * struct radeon_pm - power management datas
596 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
597 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
598 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
599 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
600 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
601 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
602 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
603 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
604 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
605 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
606 * @needed_bandwidth: current bandwidth needs
607 *
608 * It keeps track of various data needed to take powermanagement decision.
609 * Bandwith need is used to determine minimun clock of the GPU and memory.
610 * Equation between gpu/memory clock and available bandwidth is hw dependent
611 * (type of memory, bus size, efficiency, ...)
612 */
613
614 enum radeon_pm_method {
615 PM_METHOD_PROFILE,
616 PM_METHOD_DYNPM,
617 };
618
619 enum radeon_dynpm_state {
620 DYNPM_STATE_DISABLED,
621 DYNPM_STATE_MINIMUM,
622 DYNPM_STATE_PAUSED,
623 DYNPM_STATE_ACTIVE,
624 DYNPM_STATE_SUSPENDED,
625 };
626 enum radeon_dynpm_action {
627 DYNPM_ACTION_NONE,
628 DYNPM_ACTION_MINIMUM,
629 DYNPM_ACTION_DOWNCLOCK,
630 DYNPM_ACTION_UPCLOCK,
631 DYNPM_ACTION_DEFAULT
632 };
633
634 enum radeon_voltage_type {
635 VOLTAGE_NONE = 0,
636 VOLTAGE_GPIO,
637 VOLTAGE_VDDC,
638 VOLTAGE_SW
639 };
640
641 enum radeon_pm_state_type {
642 POWER_STATE_TYPE_DEFAULT,
643 POWER_STATE_TYPE_POWERSAVE,
644 POWER_STATE_TYPE_BATTERY,
645 POWER_STATE_TYPE_BALANCED,
646 POWER_STATE_TYPE_PERFORMANCE,
647 };
648
649 enum radeon_pm_profile_type {
650 PM_PROFILE_DEFAULT,
651 PM_PROFILE_AUTO,
652 PM_PROFILE_LOW,
653 PM_PROFILE_MID,
654 PM_PROFILE_HIGH,
655 };
656
657 #define PM_PROFILE_DEFAULT_IDX 0
658 #define PM_PROFILE_LOW_SH_IDX 1
659 #define PM_PROFILE_MID_SH_IDX 2
660 #define PM_PROFILE_HIGH_SH_IDX 3
661 #define PM_PROFILE_LOW_MH_IDX 4
662 #define PM_PROFILE_MID_MH_IDX 5
663 #define PM_PROFILE_HIGH_MH_IDX 6
664 #define PM_PROFILE_MAX 7
665
666 struct radeon_pm_profile {
667 int dpms_off_ps_idx;
668 int dpms_on_ps_idx;
669 int dpms_off_cm_idx;
670 int dpms_on_cm_idx;
671 };
672
673 struct radeon_voltage {
674 enum radeon_voltage_type type;
675 /* gpio voltage */
676 struct radeon_gpio_rec gpio;
677 u32 delay; /* delay in usec from voltage drop to sclk change */
678 bool active_high; /* voltage drop is active when bit is high */
679 /* VDDC voltage */
680 u8 vddc_id; /* index into vddc voltage table */
681 u8 vddci_id; /* index into vddci voltage table */
682 bool vddci_enabled;
683 /* r6xx+ sw */
684 u32 voltage;
685 };
686
687 /* clock mode flags */
688 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
689
690 struct radeon_pm_clock_info {
691 /* memory clock */
692 u32 mclk;
693 /* engine clock */
694 u32 sclk;
695 /* voltage info */
696 struct radeon_voltage voltage;
697 /* standardized clock flags */
698 u32 flags;
699 };
700
701 /* state flags */
702 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
703
704 struct radeon_power_state {
705 enum radeon_pm_state_type type;
706 /* XXX: use a define for num clock modes */
707 struct radeon_pm_clock_info clock_info[8];
708 /* number of valid clock modes in this power state */
709 int num_clock_modes;
710 struct radeon_pm_clock_info *default_clock_mode;
711 /* standardized state flags */
712 u32 flags;
713 u32 misc; /* vbios specific flags */
714 u32 misc2; /* vbios specific flags */
715 int pcie_lanes; /* pcie lanes */
716 };
717
718 /*
719 * Some modes are overclocked by very low value, accept them
720 */
721 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
722
723 struct radeon_pm {
724 struct mutex mutex;
725 u32 active_crtcs;
726 int active_crtc_count;
727 int req_vblank;
728 bool vblank_sync;
729 bool gui_idle;
730 fixed20_12 max_bandwidth;
731 fixed20_12 igp_sideport_mclk;
732 fixed20_12 igp_system_mclk;
733 fixed20_12 igp_ht_link_clk;
734 fixed20_12 igp_ht_link_width;
735 fixed20_12 k8_bandwidth;
736 fixed20_12 sideport_bandwidth;
737 fixed20_12 ht_bandwidth;
738 fixed20_12 core_bandwidth;
739 fixed20_12 sclk;
740 fixed20_12 mclk;
741 fixed20_12 needed_bandwidth;
742 /* XXX: use a define for num power modes */
743 struct radeon_power_state power_state[8];
744 /* number of valid power states */
745 int num_power_states;
746 int current_power_state_index;
747 int current_clock_mode_index;
748 int requested_power_state_index;
749 int requested_clock_mode_index;
750 int default_power_state_index;
751 u32 current_sclk;
752 u32 current_mclk;
753 u32 current_vddc;
754 struct radeon_i2c_chan *i2c_bus;
755 /* selected pm method */
756 enum radeon_pm_method pm_method;
757 /* dynpm power management */
758 struct delayed_work dynpm_idle_work;
759 enum radeon_dynpm_state dynpm_state;
760 enum radeon_dynpm_action dynpm_planned_action;
761 unsigned long dynpm_action_timeout;
762 bool dynpm_can_upclock;
763 bool dynpm_can_downclock;
764 /* profile-based power management */
765 enum radeon_pm_profile_type profile;
766 int profile_index;
767 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
768 };
769
770
771 /*
772 * Benchmarking
773 */
774 void radeon_benchmark(struct radeon_device *rdev);
775
776
777 /*
778 * Testing
779 */
780 void radeon_test_moves(struct radeon_device *rdev);
781
782
783 /*
784 * Debugfs
785 */
786 int radeon_debugfs_add_files(struct radeon_device *rdev,
787 struct drm_info_list *files,
788 unsigned nfiles);
789 int radeon_debugfs_fence_init(struct radeon_device *rdev);
790
791
792 /*
793 * ASIC specific functions.
794 */
795 struct radeon_asic {
796 int (*init)(struct radeon_device *rdev);
797 void (*fini)(struct radeon_device *rdev);
798 int (*resume)(struct radeon_device *rdev);
799 int (*suspend)(struct radeon_device *rdev);
800 void (*vga_set_state)(struct radeon_device *rdev, bool state);
801 bool (*gpu_is_lockup)(struct radeon_device *rdev);
802 int (*asic_reset)(struct radeon_device *rdev);
803 void (*gart_tlb_flush)(struct radeon_device *rdev);
804 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
805 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
806 void (*cp_fini)(struct radeon_device *rdev);
807 void (*cp_disable)(struct radeon_device *rdev);
808 void (*cp_commit)(struct radeon_device *rdev);
809 void (*ring_start)(struct radeon_device *rdev);
810 int (*ring_test)(struct radeon_device *rdev);
811 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
812 int (*irq_set)(struct radeon_device *rdev);
813 int (*irq_process)(struct radeon_device *rdev);
814 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
815 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
816 int (*cs_parse)(struct radeon_cs_parser *p);
817 int (*copy_blit)(struct radeon_device *rdev,
818 uint64_t src_offset,
819 uint64_t dst_offset,
820 unsigned num_pages,
821 struct radeon_fence *fence);
822 int (*copy_dma)(struct radeon_device *rdev,
823 uint64_t src_offset,
824 uint64_t dst_offset,
825 unsigned num_pages,
826 struct radeon_fence *fence);
827 int (*copy)(struct radeon_device *rdev,
828 uint64_t src_offset,
829 uint64_t dst_offset,
830 unsigned num_pages,
831 struct radeon_fence *fence);
832 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
833 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
834 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
835 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
836 int (*get_pcie_lanes)(struct radeon_device *rdev);
837 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
838 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
839 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
840 uint32_t tiling_flags, uint32_t pitch,
841 uint32_t offset, uint32_t obj_size);
842 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
843 void (*bandwidth_update)(struct radeon_device *rdev);
844 void (*hpd_init)(struct radeon_device *rdev);
845 void (*hpd_fini)(struct radeon_device *rdev);
846 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
847 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
848 /* ioctl hw specific callback. Some hw might want to perform special
849 * operation on specific ioctl. For instance on wait idle some hw
850 * might want to perform and HDP flush through MMIO as it seems that
851 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
852 * through ring.
853 */
854 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
855 bool (*gui_idle)(struct radeon_device *rdev);
856 /* power management */
857 void (*pm_misc)(struct radeon_device *rdev);
858 void (*pm_prepare)(struct radeon_device *rdev);
859 void (*pm_finish)(struct radeon_device *rdev);
860 void (*pm_init_profile)(struct radeon_device *rdev);
861 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
862 };
863
864 /*
865 * Asic structures
866 */
867 struct r100_gpu_lockup {
868 unsigned long last_jiffies;
869 u32 last_cp_rptr;
870 };
871
872 struct r100_asic {
873 const unsigned *reg_safe_bm;
874 unsigned reg_safe_bm_size;
875 u32 hdp_cntl;
876 struct r100_gpu_lockup lockup;
877 };
878
879 struct r300_asic {
880 const unsigned *reg_safe_bm;
881 unsigned reg_safe_bm_size;
882 u32 resync_scratch;
883 u32 hdp_cntl;
884 struct r100_gpu_lockup lockup;
885 };
886
887 struct r600_asic {
888 unsigned max_pipes;
889 unsigned max_tile_pipes;
890 unsigned max_simds;
891 unsigned max_backends;
892 unsigned max_gprs;
893 unsigned max_threads;
894 unsigned max_stack_entries;
895 unsigned max_hw_contexts;
896 unsigned max_gs_threads;
897 unsigned sx_max_export_size;
898 unsigned sx_max_export_pos_size;
899 unsigned sx_max_export_smx_size;
900 unsigned sq_num_cf_insts;
901 unsigned tiling_nbanks;
902 unsigned tiling_npipes;
903 unsigned tiling_group_size;
904 struct r100_gpu_lockup lockup;
905 };
906
907 struct rv770_asic {
908 unsigned max_pipes;
909 unsigned max_tile_pipes;
910 unsigned max_simds;
911 unsigned max_backends;
912 unsigned max_gprs;
913 unsigned max_threads;
914 unsigned max_stack_entries;
915 unsigned max_hw_contexts;
916 unsigned max_gs_threads;
917 unsigned sx_max_export_size;
918 unsigned sx_max_export_pos_size;
919 unsigned sx_max_export_smx_size;
920 unsigned sq_num_cf_insts;
921 unsigned sx_num_of_sets;
922 unsigned sc_prim_fifo_size;
923 unsigned sc_hiz_tile_fifo_size;
924 unsigned sc_earlyz_tile_fifo_fize;
925 unsigned tiling_nbanks;
926 unsigned tiling_npipes;
927 unsigned tiling_group_size;
928 struct r100_gpu_lockup lockup;
929 };
930
931 struct evergreen_asic {
932 unsigned num_ses;
933 unsigned max_pipes;
934 unsigned max_tile_pipes;
935 unsigned max_simds;
936 unsigned max_backends;
937 unsigned max_gprs;
938 unsigned max_threads;
939 unsigned max_stack_entries;
940 unsigned max_hw_contexts;
941 unsigned max_gs_threads;
942 unsigned sx_max_export_size;
943 unsigned sx_max_export_pos_size;
944 unsigned sx_max_export_smx_size;
945 unsigned sq_num_cf_insts;
946 unsigned sx_num_of_sets;
947 unsigned sc_prim_fifo_size;
948 unsigned sc_hiz_tile_fifo_size;
949 unsigned sc_earlyz_tile_fifo_size;
950 unsigned tiling_nbanks;
951 unsigned tiling_npipes;
952 unsigned tiling_group_size;
953 };
954
955 union radeon_asic_config {
956 struct r300_asic r300;
957 struct r100_asic r100;
958 struct r600_asic r600;
959 struct rv770_asic rv770;
960 struct evergreen_asic evergreen;
961 };
962
963 /*
964 * asic initizalization from radeon_asic.c
965 */
966 void radeon_agp_disable(struct radeon_device *rdev);
967 int radeon_asic_init(struct radeon_device *rdev);
968
969
970 /*
971 * IOCTL.
972 */
973 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
974 struct drm_file *filp);
975 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
976 struct drm_file *filp);
977 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
978 struct drm_file *file_priv);
979 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
980 struct drm_file *file_priv);
981 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
982 struct drm_file *file_priv);
983 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
984 struct drm_file *file_priv);
985 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
986 struct drm_file *filp);
987 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
988 struct drm_file *filp);
989 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
990 struct drm_file *filp);
991 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *filp);
993 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
994 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
995 struct drm_file *filp);
996 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
997 struct drm_file *filp);
998
999
1000 /*
1001 * Core structure, functions and helpers.
1002 */
1003 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1004 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1005
1006 struct radeon_device {
1007 struct device *dev;
1008 struct drm_device *ddev;
1009 struct pci_dev *pdev;
1010 /* ASIC */
1011 union radeon_asic_config config;
1012 enum radeon_family family;
1013 unsigned long flags;
1014 int usec_timeout;
1015 enum radeon_pll_errata pll_errata;
1016 int num_gb_pipes;
1017 int num_z_pipes;
1018 int disp_priority;
1019 /* BIOS */
1020 uint8_t *bios;
1021 bool is_atom_bios;
1022 uint16_t bios_header_start;
1023 struct radeon_bo *stollen_vga_memory;
1024 /* Register mmio */
1025 resource_size_t rmmio_base;
1026 resource_size_t rmmio_size;
1027 void *rmmio;
1028 radeon_rreg_t mc_rreg;
1029 radeon_wreg_t mc_wreg;
1030 radeon_rreg_t pll_rreg;
1031 radeon_wreg_t pll_wreg;
1032 uint32_t pcie_reg_mask;
1033 radeon_rreg_t pciep_rreg;
1034 radeon_wreg_t pciep_wreg;
1035 struct radeon_clock clock;
1036 struct radeon_mc mc;
1037 struct radeon_gart gart;
1038 struct radeon_mode_info mode_info;
1039 struct radeon_scratch scratch;
1040 struct radeon_mman mman;
1041 struct radeon_fence_driver fence_drv;
1042 struct radeon_cp cp;
1043 struct radeon_ib_pool ib_pool;
1044 struct radeon_irq irq;
1045 struct radeon_asic *asic;
1046 struct radeon_gem gem;
1047 struct radeon_pm pm;
1048 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1049 struct mutex cs_mutex;
1050 struct radeon_wb wb;
1051 struct radeon_dummy_page dummy_page;
1052 bool gpu_lockup;
1053 bool shutdown;
1054 bool suspend;
1055 bool need_dma32;
1056 bool accel_working;
1057 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1058 const struct firmware *me_fw; /* all family ME firmware */
1059 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1060 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1061 struct r600_blit r600_blit;
1062 int msi_enabled; /* msi enabled */
1063 struct r600_ih ih; /* r6/700 interrupt ring */
1064 struct workqueue_struct *wq;
1065 struct work_struct hotplug_work;
1066 int num_crtc; /* number of crtcs */
1067 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1068 struct mutex vram_mutex;
1069
1070 /* audio stuff */
1071 struct timer_list audio_timer;
1072 int audio_channels;
1073 int audio_rate;
1074 int audio_bits_per_sample;
1075 uint8_t audio_status_bits;
1076 uint8_t audio_category_code;
1077
1078 bool powered_down;
1079 struct notifier_block acpi_nb;
1080 };
1081
1082 int radeon_device_init(struct radeon_device *rdev,
1083 struct drm_device *ddev,
1084 struct pci_dev *pdev,
1085 uint32_t flags);
1086 void radeon_device_fini(struct radeon_device *rdev);
1087 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1088
1089 /* r600 blit */
1090 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1091 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1092 void r600_kms_blit_copy(struct radeon_device *rdev,
1093 u64 src_gpu_addr, u64 dst_gpu_addr,
1094 int size_bytes);
1095
1096 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1097 {
1098 if (reg < rdev->rmmio_size)
1099 return readl(((void __iomem *)rdev->rmmio) + reg);
1100 else {
1101 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1102 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1103 }
1104 }
1105
1106 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1107 {
1108 if (reg < rdev->rmmio_size)
1109 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1110 else {
1111 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1112 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1113 }
1114 }
1115
1116 /*
1117 * Cast helper
1118 */
1119 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1120
1121 /*
1122 * Registers read & write functions.
1123 */
1124 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1125 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1126 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1127 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1128 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1129 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1130 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1131 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1132 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1133 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1134 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1135 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1136 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1137 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1138 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1139 #define WREG32_P(reg, val, mask) \
1140 do { \
1141 uint32_t tmp_ = RREG32(reg); \
1142 tmp_ &= (mask); \
1143 tmp_ |= ((val) & ~(mask)); \
1144 WREG32(reg, tmp_); \
1145 } while (0)
1146 #define WREG32_PLL_P(reg, val, mask) \
1147 do { \
1148 uint32_t tmp_ = RREG32_PLL(reg); \
1149 tmp_ &= (mask); \
1150 tmp_ |= ((val) & ~(mask)); \
1151 WREG32_PLL(reg, tmp_); \
1152 } while (0)
1153 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1154
1155 /*
1156 * Indirect registers accessor
1157 */
1158 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1159 {
1160 uint32_t r;
1161
1162 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1163 r = RREG32(RADEON_PCIE_DATA);
1164 return r;
1165 }
1166
1167 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1168 {
1169 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1170 WREG32(RADEON_PCIE_DATA, (v));
1171 }
1172
1173 void r100_pll_errata_after_index(struct radeon_device *rdev);
1174
1175
1176 /*
1177 * ASICs helpers.
1178 */
1179 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1180 (rdev->pdev->device == 0x5969))
1181 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1182 (rdev->family == CHIP_RV200) || \
1183 (rdev->family == CHIP_RS100) || \
1184 (rdev->family == CHIP_RS200) || \
1185 (rdev->family == CHIP_RV250) || \
1186 (rdev->family == CHIP_RV280) || \
1187 (rdev->family == CHIP_RS300))
1188 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1189 (rdev->family == CHIP_RV350) || \
1190 (rdev->family == CHIP_R350) || \
1191 (rdev->family == CHIP_RV380) || \
1192 (rdev->family == CHIP_R420) || \
1193 (rdev->family == CHIP_R423) || \
1194 (rdev->family == CHIP_RV410) || \
1195 (rdev->family == CHIP_RS400) || \
1196 (rdev->family == CHIP_RS480))
1197 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1198 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1199 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1200 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1201
1202 /*
1203 * BIOS helpers.
1204 */
1205 #define RBIOS8(i) (rdev->bios[i])
1206 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1207 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1208
1209 int radeon_combios_init(struct radeon_device *rdev);
1210 void radeon_combios_fini(struct radeon_device *rdev);
1211 int radeon_atombios_init(struct radeon_device *rdev);
1212 void radeon_atombios_fini(struct radeon_device *rdev);
1213
1214
1215 /*
1216 * RING helpers.
1217 */
1218 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1219 {
1220 #if DRM_DEBUG_CODE
1221 if (rdev->cp.count_dw <= 0) {
1222 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1223 }
1224 #endif
1225 rdev->cp.ring[rdev->cp.wptr++] = v;
1226 rdev->cp.wptr &= rdev->cp.ptr_mask;
1227 rdev->cp.count_dw--;
1228 rdev->cp.ring_free_dw--;
1229 }
1230
1231
1232 /*
1233 * ASICs macro.
1234 */
1235 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1236 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1237 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1238 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1239 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1240 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1241 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1242 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1243 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1244 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1245 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1246 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1247 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1248 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1249 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1250 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1251 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1252 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1253 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1254 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1255 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1256 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1257 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1258 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1259 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1260 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1261 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1262 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1263 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1264 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1265 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1266 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1267 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1268 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1269 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1270 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1271 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1272 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1273 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1274 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1275 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1276
1277 /* Common functions */
1278 /* AGP */
1279 extern int radeon_gpu_reset(struct radeon_device *rdev);
1280 extern void radeon_agp_disable(struct radeon_device *rdev);
1281 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1282 extern void radeon_gart_restore(struct radeon_device *rdev);
1283 extern int radeon_modeset_init(struct radeon_device *rdev);
1284 extern void radeon_modeset_fini(struct radeon_device *rdev);
1285 extern bool radeon_card_posted(struct radeon_device *rdev);
1286 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1287 extern void radeon_update_display_priority(struct radeon_device *rdev);
1288 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1289 extern int radeon_clocks_init(struct radeon_device *rdev);
1290 extern void radeon_clocks_fini(struct radeon_device *rdev);
1291 extern void radeon_scratch_init(struct radeon_device *rdev);
1292 extern void radeon_surface_init(struct radeon_device *rdev);
1293 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1294 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1295 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1296 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1297 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1298 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1299 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1300 extern int radeon_resume_kms(struct drm_device *dev);
1301 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1302
1303 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1304 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1305 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1306
1307 /* rv200,rv250,rv280 */
1308 extern void r200_set_safe_registers(struct radeon_device *rdev);
1309
1310 /* r300,r350,rv350,rv370,rv380 */
1311 extern void r300_set_reg_safe(struct radeon_device *rdev);
1312 extern void r300_mc_program(struct radeon_device *rdev);
1313 extern void r300_mc_init(struct radeon_device *rdev);
1314 extern void r300_clock_startup(struct radeon_device *rdev);
1315 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1316 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1317 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1318 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1319 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1320
1321 /* r420,r423,rv410 */
1322 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1323 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1324 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1325 extern void r420_pipes_init(struct radeon_device *rdev);
1326
1327 /* rv515 */
1328 struct rv515_mc_save {
1329 u32 d1vga_control;
1330 u32 d2vga_control;
1331 u32 vga_render_control;
1332 u32 vga_hdp_control;
1333 u32 d1crtc_control;
1334 u32 d2crtc_control;
1335 };
1336 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1337 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1338 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1339 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1340 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1341 extern void rv515_clock_startup(struct radeon_device *rdev);
1342 extern void rv515_debugfs(struct radeon_device *rdev);
1343 extern int rv515_suspend(struct radeon_device *rdev);
1344
1345 /* rs400 */
1346 extern int rs400_gart_init(struct radeon_device *rdev);
1347 extern int rs400_gart_enable(struct radeon_device *rdev);
1348 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1349 extern void rs400_gart_disable(struct radeon_device *rdev);
1350 extern void rs400_gart_fini(struct radeon_device *rdev);
1351
1352 /* rs600 */
1353 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1354 extern int rs600_irq_set(struct radeon_device *rdev);
1355 extern void rs600_irq_disable(struct radeon_device *rdev);
1356
1357 /* rs690, rs740 */
1358 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1359 struct drm_display_mode *mode1,
1360 struct drm_display_mode *mode2);
1361
1362 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1363 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1364 extern bool r600_card_posted(struct radeon_device *rdev);
1365 extern void r600_cp_stop(struct radeon_device *rdev);
1366 extern int r600_cp_start(struct radeon_device *rdev);
1367 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1368 extern int r600_cp_resume(struct radeon_device *rdev);
1369 extern void r600_cp_fini(struct radeon_device *rdev);
1370 extern int r600_count_pipe_bits(uint32_t val);
1371 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1372 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1373 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1374 extern int r600_ib_test(struct radeon_device *rdev);
1375 extern int r600_ring_test(struct radeon_device *rdev);
1376 extern void r600_wb_fini(struct radeon_device *rdev);
1377 extern int r600_wb_enable(struct radeon_device *rdev);
1378 extern void r600_wb_disable(struct radeon_device *rdev);
1379 extern void r600_scratch_init(struct radeon_device *rdev);
1380 extern int r600_blit_init(struct radeon_device *rdev);
1381 extern void r600_blit_fini(struct radeon_device *rdev);
1382 extern int r600_init_microcode(struct radeon_device *rdev);
1383 extern int r600_asic_reset(struct radeon_device *rdev);
1384 /* r600 irq */
1385 extern int r600_irq_init(struct radeon_device *rdev);
1386 extern void r600_irq_fini(struct radeon_device *rdev);
1387 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1388 extern int r600_irq_set(struct radeon_device *rdev);
1389 extern void r600_irq_suspend(struct radeon_device *rdev);
1390 extern void r600_disable_interrupts(struct radeon_device *rdev);
1391 extern void r600_rlc_stop(struct radeon_device *rdev);
1392 /* r600 audio */
1393 extern int r600_audio_init(struct radeon_device *rdev);
1394 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1395 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1396 extern int r600_audio_channels(struct radeon_device *rdev);
1397 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1398 extern int r600_audio_rate(struct radeon_device *rdev);
1399 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1400 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1401 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1402 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1403 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1404 extern void r600_audio_fini(struct radeon_device *rdev);
1405 extern void r600_hdmi_init(struct drm_encoder *encoder);
1406 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1407 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1408 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1409 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1410 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1411
1412 extern void r700_cp_stop(struct radeon_device *rdev);
1413 extern void r700_cp_fini(struct radeon_device *rdev);
1414 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1415 extern int evergreen_irq_set(struct radeon_device *rdev);
1416
1417 /* evergreen */
1418 struct evergreen_mc_save {
1419 u32 vga_control[6];
1420 u32 vga_render_control;
1421 u32 vga_hdp_control;
1422 u32 crtc_control[6];
1423 };
1424
1425 #include "radeon_object.h"
1426
1427 #endif
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