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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
76
77 /*
78 * Modules parameters.
79 */
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
90 extern int radeon_tv;
91 extern int radeon_new_pll;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95
96 /*
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
98 * symbol;
99 */
100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
102 /* RADEON_IB_POOL_SIZE must be a power of 2 */
103 #define RADEON_IB_POOL_SIZE 16
104 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
105 #define RADEONFB_CONN_LIMIT 4
106 #define RADEON_BIOS_NUM_SCRATCH 8
107
108 /*
109 * Errata workarounds.
110 */
111 enum radeon_pll_errata {
112 CHIP_ERRATA_R300_CG = 0x00000001,
113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
114 CHIP_ERRATA_PLL_DELAY = 0x00000004
115 };
116
117
118 struct radeon_device;
119
120
121 /*
122 * BIOS.
123 */
124 #define ATRM_BIOS_PAGE 4096
125
126 #if defined(CONFIG_VGA_SWITCHEROO)
127 bool radeon_atrm_supported(struct pci_dev *pdev);
128 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
129 #else
130 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
131 {
132 return false;
133 }
134
135 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
136 return -EINVAL;
137 }
138 #endif
139 bool radeon_get_bios(struct radeon_device *rdev);
140
141
142 /*
143 * Dummy page
144 */
145 struct radeon_dummy_page {
146 struct page *page;
147 dma_addr_t addr;
148 };
149 int radeon_dummy_page_init(struct radeon_device *rdev);
150 void radeon_dummy_page_fini(struct radeon_device *rdev);
151
152
153 /*
154 * Clocks
155 */
156 struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll dcpll;
160 struct radeon_pll spll;
161 struct radeon_pll mpll;
162 /* 10 Khz units */
163 uint32_t default_mclk;
164 uint32_t default_sclk;
165 uint32_t default_dispclk;
166 uint32_t dp_extclk;
167 };
168
169 /*
170 * Power management
171 */
172 int radeon_pm_init(struct radeon_device *rdev);
173 void radeon_pm_fini(struct radeon_device *rdev);
174 void radeon_pm_compute_clocks(struct radeon_device *rdev);
175 void radeon_pm_suspend(struct radeon_device *rdev);
176 void radeon_pm_resume(struct radeon_device *rdev);
177 void radeon_combios_get_power_modes(struct radeon_device *rdev);
178 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
180
181 /*
182 * Fences.
183 */
184 struct radeon_fence_driver {
185 uint32_t scratch_reg;
186 atomic_t seq;
187 uint32_t last_seq;
188 unsigned long last_jiffies;
189 unsigned long last_timeout;
190 wait_queue_head_t queue;
191 rwlock_t lock;
192 struct list_head created;
193 struct list_head emited;
194 struct list_head signaled;
195 bool initialized;
196 };
197
198 struct radeon_fence {
199 struct radeon_device *rdev;
200 struct kref kref;
201 struct list_head list;
202 /* protected by radeon_fence.lock */
203 uint32_t seq;
204 bool emited;
205 bool signaled;
206 };
207
208 int radeon_fence_driver_init(struct radeon_device *rdev);
209 void radeon_fence_driver_fini(struct radeon_device *rdev);
210 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
211 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
212 void radeon_fence_process(struct radeon_device *rdev);
213 bool radeon_fence_signaled(struct radeon_fence *fence);
214 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
215 int radeon_fence_wait_next(struct radeon_device *rdev);
216 int radeon_fence_wait_last(struct radeon_device *rdev);
217 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
218 void radeon_fence_unref(struct radeon_fence **fence);
219
220 /*
221 * Tiling registers
222 */
223 struct radeon_surface_reg {
224 struct radeon_bo *bo;
225 };
226
227 #define RADEON_GEM_MAX_SURFACES 8
228
229 /*
230 * TTM.
231 */
232 struct radeon_mman {
233 struct ttm_bo_global_ref bo_global_ref;
234 struct ttm_global_reference mem_global_ref;
235 struct ttm_bo_device bdev;
236 bool mem_global_referenced;
237 bool initialized;
238 };
239
240 struct radeon_bo {
241 /* Protected by gem.mutex */
242 struct list_head list;
243 /* Protected by tbo.reserved */
244 u32 placements[3];
245 struct ttm_placement placement;
246 struct ttm_buffer_object tbo;
247 struct ttm_bo_kmap_obj kmap;
248 unsigned pin_count;
249 void *kptr;
250 u32 tiling_flags;
251 u32 pitch;
252 int surface_reg;
253 /* Constant after initialization */
254 struct radeon_device *rdev;
255 struct drm_gem_object *gobj;
256 };
257
258 struct radeon_bo_list {
259 struct list_head list;
260 struct radeon_bo *bo;
261 uint64_t gpu_offset;
262 unsigned rdomain;
263 unsigned wdomain;
264 u32 tiling_flags;
265 bool reserved;
266 };
267
268 /*
269 * GEM objects.
270 */
271 struct radeon_gem {
272 struct mutex mutex;
273 struct list_head objects;
274 };
275
276 int radeon_gem_init(struct radeon_device *rdev);
277 void radeon_gem_fini(struct radeon_device *rdev);
278 int radeon_gem_object_create(struct radeon_device *rdev, int size,
279 int alignment, int initial_domain,
280 bool discardable, bool kernel,
281 struct drm_gem_object **obj);
282 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
283 uint64_t *gpu_addr);
284 void radeon_gem_object_unpin(struct drm_gem_object *obj);
285
286
287 /*
288 * GART structures, functions & helpers
289 */
290 struct radeon_mc;
291
292 struct radeon_gart_table_ram {
293 volatile uint32_t *ptr;
294 };
295
296 struct radeon_gart_table_vram {
297 struct radeon_bo *robj;
298 volatile uint32_t *ptr;
299 };
300
301 union radeon_gart_table {
302 struct radeon_gart_table_ram ram;
303 struct radeon_gart_table_vram vram;
304 };
305
306 #define RADEON_GPU_PAGE_SIZE 4096
307 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
308
309 struct radeon_gart {
310 dma_addr_t table_addr;
311 unsigned num_gpu_pages;
312 unsigned num_cpu_pages;
313 unsigned table_size;
314 union radeon_gart_table table;
315 struct page **pages;
316 dma_addr_t *pages_addr;
317 bool ready;
318 };
319
320 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
321 void radeon_gart_table_ram_free(struct radeon_device *rdev);
322 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
323 void radeon_gart_table_vram_free(struct radeon_device *rdev);
324 int radeon_gart_init(struct radeon_device *rdev);
325 void radeon_gart_fini(struct radeon_device *rdev);
326 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
327 int pages);
328 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
329 int pages, struct page **pagelist);
330
331
332 /*
333 * GPU MC structures, functions & helpers
334 */
335 struct radeon_mc {
336 resource_size_t aper_size;
337 resource_size_t aper_base;
338 resource_size_t agp_base;
339 /* for some chips with <= 32MB we need to lie
340 * about vram size near mc fb location */
341 u64 mc_vram_size;
342 u64 visible_vram_size;
343 u64 gtt_size;
344 u64 gtt_start;
345 u64 gtt_end;
346 u64 vram_start;
347 u64 vram_end;
348 unsigned vram_width;
349 u64 real_vram_size;
350 int vram_mtrr;
351 bool vram_is_ddr;
352 bool igp_sideport_enabled;
353 };
354
355 bool radeon_combios_sideport_present(struct radeon_device *rdev);
356 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
357
358 /*
359 * GPU scratch registers structures, functions & helpers
360 */
361 struct radeon_scratch {
362 unsigned num_reg;
363 bool free[32];
364 uint32_t reg[32];
365 };
366
367 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
368 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
369
370
371 /*
372 * IRQS.
373 */
374 struct radeon_irq {
375 bool installed;
376 bool sw_int;
377 /* FIXME: use a define max crtc rather than hardcode it */
378 bool crtc_vblank_int[6];
379 wait_queue_head_t vblank_queue;
380 /* FIXME: use defines for max hpd/dacs */
381 bool hpd[6];
382 bool gui_idle;
383 bool gui_idle_acked;
384 wait_queue_head_t idle_queue;
385 /* FIXME: use defines for max HDMI blocks */
386 bool hdmi[2];
387 spinlock_t sw_lock;
388 int sw_refcount;
389 };
390
391 int radeon_irq_kms_init(struct radeon_device *rdev);
392 void radeon_irq_kms_fini(struct radeon_device *rdev);
393 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
394 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
395
396 /*
397 * CP & ring.
398 */
399 struct radeon_ib {
400 struct list_head list;
401 unsigned idx;
402 uint64_t gpu_addr;
403 struct radeon_fence *fence;
404 uint32_t *ptr;
405 uint32_t length_dw;
406 bool free;
407 };
408
409 /*
410 * locking -
411 * mutex protects scheduled_ibs, ready, alloc_bm
412 */
413 struct radeon_ib_pool {
414 struct mutex mutex;
415 struct radeon_bo *robj;
416 struct list_head bogus_ib;
417 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
418 bool ready;
419 unsigned head_id;
420 };
421
422 struct radeon_cp {
423 struct radeon_bo *ring_obj;
424 volatile uint32_t *ring;
425 unsigned rptr;
426 unsigned wptr;
427 unsigned wptr_old;
428 unsigned ring_size;
429 unsigned ring_free_dw;
430 int count_dw;
431 uint64_t gpu_addr;
432 uint32_t align_mask;
433 uint32_t ptr_mask;
434 struct mutex mutex;
435 bool ready;
436 };
437
438 /*
439 * R6xx+ IH ring
440 */
441 struct r600_ih {
442 struct radeon_bo *ring_obj;
443 volatile uint32_t *ring;
444 unsigned rptr;
445 unsigned wptr;
446 unsigned wptr_old;
447 unsigned ring_size;
448 uint64_t gpu_addr;
449 uint32_t ptr_mask;
450 spinlock_t lock;
451 bool enabled;
452 };
453
454 struct r600_blit {
455 struct mutex mutex;
456 struct radeon_bo *shader_obj;
457 u64 shader_gpu_addr;
458 u32 vs_offset, ps_offset;
459 u32 state_offset;
460 u32 state_len;
461 u32 vb_used, vb_total;
462 struct radeon_ib *vb_ib;
463 };
464
465 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
466 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
467 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
468 int radeon_ib_pool_init(struct radeon_device *rdev);
469 void radeon_ib_pool_fini(struct radeon_device *rdev);
470 int radeon_ib_test(struct radeon_device *rdev);
471 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
472 /* Ring access between begin & end cannot sleep */
473 void radeon_ring_free_size(struct radeon_device *rdev);
474 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
475 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
476 void radeon_ring_commit(struct radeon_device *rdev);
477 void radeon_ring_unlock_commit(struct radeon_device *rdev);
478 void radeon_ring_unlock_undo(struct radeon_device *rdev);
479 int radeon_ring_test(struct radeon_device *rdev);
480 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
481 void radeon_ring_fini(struct radeon_device *rdev);
482
483
484 /*
485 * CS.
486 */
487 struct radeon_cs_reloc {
488 struct drm_gem_object *gobj;
489 struct radeon_bo *robj;
490 struct radeon_bo_list lobj;
491 uint32_t handle;
492 uint32_t flags;
493 };
494
495 struct radeon_cs_chunk {
496 uint32_t chunk_id;
497 uint32_t length_dw;
498 int kpage_idx[2];
499 uint32_t *kpage[2];
500 uint32_t *kdata;
501 void __user *user_ptr;
502 int last_copied_page;
503 int last_page_index;
504 };
505
506 struct radeon_cs_parser {
507 struct device *dev;
508 struct radeon_device *rdev;
509 struct drm_file *filp;
510 /* chunks */
511 unsigned nchunks;
512 struct radeon_cs_chunk *chunks;
513 uint64_t *chunks_array;
514 /* IB */
515 unsigned idx;
516 /* relocations */
517 unsigned nrelocs;
518 struct radeon_cs_reloc *relocs;
519 struct radeon_cs_reloc **relocs_ptr;
520 struct list_head validated;
521 /* indices of various chunks */
522 int chunk_ib_idx;
523 int chunk_relocs_idx;
524 struct radeon_ib *ib;
525 void *track;
526 unsigned family;
527 int parser_error;
528 };
529
530 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
531 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
532
533
534 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
535 {
536 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
537 u32 pg_idx, pg_offset;
538 u32 idx_value = 0;
539 int new_page;
540
541 pg_idx = (idx * 4) / PAGE_SIZE;
542 pg_offset = (idx * 4) % PAGE_SIZE;
543
544 if (ibc->kpage_idx[0] == pg_idx)
545 return ibc->kpage[0][pg_offset/4];
546 if (ibc->kpage_idx[1] == pg_idx)
547 return ibc->kpage[1][pg_offset/4];
548
549 new_page = radeon_cs_update_pages(p, pg_idx);
550 if (new_page < 0) {
551 p->parser_error = new_page;
552 return 0;
553 }
554
555 idx_value = ibc->kpage[new_page][pg_offset/4];
556 return idx_value;
557 }
558
559 struct radeon_cs_packet {
560 unsigned idx;
561 unsigned type;
562 unsigned reg;
563 unsigned opcode;
564 int count;
565 unsigned one_reg_wr;
566 };
567
568 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
569 struct radeon_cs_packet *pkt,
570 unsigned idx, unsigned reg);
571 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
572 struct radeon_cs_packet *pkt);
573
574
575 /*
576 * AGP
577 */
578 int radeon_agp_init(struct radeon_device *rdev);
579 void radeon_agp_resume(struct radeon_device *rdev);
580 void radeon_agp_suspend(struct radeon_device *rdev);
581 void radeon_agp_fini(struct radeon_device *rdev);
582
583
584 /*
585 * Writeback
586 */
587 struct radeon_wb {
588 struct radeon_bo *wb_obj;
589 volatile uint32_t *wb;
590 uint64_t gpu_addr;
591 };
592
593 /**
594 * struct radeon_pm - power management datas
595 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
596 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
597 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
598 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
599 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
600 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
601 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
602 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
603 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
604 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
605 * @needed_bandwidth: current bandwidth needs
606 *
607 * It keeps track of various data needed to take powermanagement decision.
608 * Bandwith need is used to determine minimun clock of the GPU and memory.
609 * Equation between gpu/memory clock and available bandwidth is hw dependent
610 * (type of memory, bus size, efficiency, ...)
611 */
612
613 enum radeon_pm_method {
614 PM_METHOD_PROFILE,
615 PM_METHOD_DYNPM,
616 };
617
618 enum radeon_dynpm_state {
619 DYNPM_STATE_DISABLED,
620 DYNPM_STATE_MINIMUM,
621 DYNPM_STATE_PAUSED,
622 DYNPM_STATE_ACTIVE
623 };
624 enum radeon_dynpm_action {
625 DYNPM_ACTION_NONE,
626 DYNPM_ACTION_MINIMUM,
627 DYNPM_ACTION_DOWNCLOCK,
628 DYNPM_ACTION_UPCLOCK,
629 DYNPM_ACTION_DEFAULT
630 };
631
632 enum radeon_voltage_type {
633 VOLTAGE_NONE = 0,
634 VOLTAGE_GPIO,
635 VOLTAGE_VDDC,
636 VOLTAGE_SW
637 };
638
639 enum radeon_pm_state_type {
640 POWER_STATE_TYPE_DEFAULT,
641 POWER_STATE_TYPE_POWERSAVE,
642 POWER_STATE_TYPE_BATTERY,
643 POWER_STATE_TYPE_BALANCED,
644 POWER_STATE_TYPE_PERFORMANCE,
645 };
646
647 enum radeon_pm_profile_type {
648 PM_PROFILE_DEFAULT,
649 PM_PROFILE_AUTO,
650 PM_PROFILE_LOW,
651 PM_PROFILE_MID,
652 PM_PROFILE_HIGH,
653 };
654
655 #define PM_PROFILE_DEFAULT_IDX 0
656 #define PM_PROFILE_LOW_SH_IDX 1
657 #define PM_PROFILE_MID_SH_IDX 2
658 #define PM_PROFILE_HIGH_SH_IDX 3
659 #define PM_PROFILE_LOW_MH_IDX 4
660 #define PM_PROFILE_MID_MH_IDX 5
661 #define PM_PROFILE_HIGH_MH_IDX 6
662 #define PM_PROFILE_MAX 7
663
664 struct radeon_pm_profile {
665 int dpms_off_ps_idx;
666 int dpms_on_ps_idx;
667 int dpms_off_cm_idx;
668 int dpms_on_cm_idx;
669 };
670
671 struct radeon_voltage {
672 enum radeon_voltage_type type;
673 /* gpio voltage */
674 struct radeon_gpio_rec gpio;
675 u32 delay; /* delay in usec from voltage drop to sclk change */
676 bool active_high; /* voltage drop is active when bit is high */
677 /* VDDC voltage */
678 u8 vddc_id; /* index into vddc voltage table */
679 u8 vddci_id; /* index into vddci voltage table */
680 bool vddci_enabled;
681 /* r6xx+ sw */
682 u32 voltage;
683 };
684
685 /* clock mode flags */
686 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
687
688 struct radeon_pm_clock_info {
689 /* memory clock */
690 u32 mclk;
691 /* engine clock */
692 u32 sclk;
693 /* voltage info */
694 struct radeon_voltage voltage;
695 /* standardized clock flags */
696 u32 flags;
697 };
698
699 /* state flags */
700 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
701
702 struct radeon_power_state {
703 enum radeon_pm_state_type type;
704 /* XXX: use a define for num clock modes */
705 struct radeon_pm_clock_info clock_info[8];
706 /* number of valid clock modes in this power state */
707 int num_clock_modes;
708 struct radeon_pm_clock_info *default_clock_mode;
709 /* standardized state flags */
710 u32 flags;
711 u32 misc; /* vbios specific flags */
712 u32 misc2; /* vbios specific flags */
713 int pcie_lanes; /* pcie lanes */
714 };
715
716 /*
717 * Some modes are overclocked by very low value, accept them
718 */
719 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
720
721 struct radeon_pm {
722 struct mutex mutex;
723 u32 active_crtcs;
724 int active_crtc_count;
725 int req_vblank;
726 bool vblank_sync;
727 bool gui_idle;
728 fixed20_12 max_bandwidth;
729 fixed20_12 igp_sideport_mclk;
730 fixed20_12 igp_system_mclk;
731 fixed20_12 igp_ht_link_clk;
732 fixed20_12 igp_ht_link_width;
733 fixed20_12 k8_bandwidth;
734 fixed20_12 sideport_bandwidth;
735 fixed20_12 ht_bandwidth;
736 fixed20_12 core_bandwidth;
737 fixed20_12 sclk;
738 fixed20_12 mclk;
739 fixed20_12 needed_bandwidth;
740 /* XXX: use a define for num power modes */
741 struct radeon_power_state power_state[8];
742 /* number of valid power states */
743 int num_power_states;
744 int current_power_state_index;
745 int current_clock_mode_index;
746 int requested_power_state_index;
747 int requested_clock_mode_index;
748 int default_power_state_index;
749 u32 current_sclk;
750 u32 current_mclk;
751 u32 current_vddc;
752 struct radeon_i2c_chan *i2c_bus;
753 /* selected pm method */
754 enum radeon_pm_method pm_method;
755 /* dynpm power management */
756 struct delayed_work dynpm_idle_work;
757 enum radeon_dynpm_state dynpm_state;
758 enum radeon_dynpm_action dynpm_planned_action;
759 unsigned long dynpm_action_timeout;
760 bool dynpm_can_upclock;
761 bool dynpm_can_downclock;
762 /* profile-based power management */
763 enum radeon_pm_profile_type profile;
764 int profile_index;
765 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
766 };
767
768
769 /*
770 * Benchmarking
771 */
772 void radeon_benchmark(struct radeon_device *rdev);
773
774
775 /*
776 * Testing
777 */
778 void radeon_test_moves(struct radeon_device *rdev);
779
780
781 /*
782 * Debugfs
783 */
784 int radeon_debugfs_add_files(struct radeon_device *rdev,
785 struct drm_info_list *files,
786 unsigned nfiles);
787 int radeon_debugfs_fence_init(struct radeon_device *rdev);
788
789
790 /*
791 * ASIC specific functions.
792 */
793 struct radeon_asic {
794 int (*init)(struct radeon_device *rdev);
795 void (*fini)(struct radeon_device *rdev);
796 int (*resume)(struct radeon_device *rdev);
797 int (*suspend)(struct radeon_device *rdev);
798 void (*vga_set_state)(struct radeon_device *rdev, bool state);
799 bool (*gpu_is_lockup)(struct radeon_device *rdev);
800 int (*asic_reset)(struct radeon_device *rdev);
801 void (*gart_tlb_flush)(struct radeon_device *rdev);
802 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
803 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
804 void (*cp_fini)(struct radeon_device *rdev);
805 void (*cp_disable)(struct radeon_device *rdev);
806 void (*cp_commit)(struct radeon_device *rdev);
807 void (*ring_start)(struct radeon_device *rdev);
808 int (*ring_test)(struct radeon_device *rdev);
809 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
810 int (*irq_set)(struct radeon_device *rdev);
811 int (*irq_process)(struct radeon_device *rdev);
812 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
813 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
814 int (*cs_parse)(struct radeon_cs_parser *p);
815 int (*copy_blit)(struct radeon_device *rdev,
816 uint64_t src_offset,
817 uint64_t dst_offset,
818 unsigned num_pages,
819 struct radeon_fence *fence);
820 int (*copy_dma)(struct radeon_device *rdev,
821 uint64_t src_offset,
822 uint64_t dst_offset,
823 unsigned num_pages,
824 struct radeon_fence *fence);
825 int (*copy)(struct radeon_device *rdev,
826 uint64_t src_offset,
827 uint64_t dst_offset,
828 unsigned num_pages,
829 struct radeon_fence *fence);
830 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
831 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
832 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
833 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
834 int (*get_pcie_lanes)(struct radeon_device *rdev);
835 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
836 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
837 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
838 uint32_t tiling_flags, uint32_t pitch,
839 uint32_t offset, uint32_t obj_size);
840 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
841 void (*bandwidth_update)(struct radeon_device *rdev);
842 void (*hpd_init)(struct radeon_device *rdev);
843 void (*hpd_fini)(struct radeon_device *rdev);
844 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
845 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
846 /* ioctl hw specific callback. Some hw might want to perform special
847 * operation on specific ioctl. For instance on wait idle some hw
848 * might want to perform and HDP flush through MMIO as it seems that
849 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
850 * through ring.
851 */
852 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
853 bool (*gui_idle)(struct radeon_device *rdev);
854 /* power management */
855 void (*pm_misc)(struct radeon_device *rdev);
856 void (*pm_prepare)(struct radeon_device *rdev);
857 void (*pm_finish)(struct radeon_device *rdev);
858 void (*pm_init_profile)(struct radeon_device *rdev);
859 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
860 };
861
862 /*
863 * Asic structures
864 */
865 struct r100_gpu_lockup {
866 unsigned long last_jiffies;
867 u32 last_cp_rptr;
868 };
869
870 struct r100_asic {
871 const unsigned *reg_safe_bm;
872 unsigned reg_safe_bm_size;
873 u32 hdp_cntl;
874 struct r100_gpu_lockup lockup;
875 };
876
877 struct r300_asic {
878 const unsigned *reg_safe_bm;
879 unsigned reg_safe_bm_size;
880 u32 resync_scratch;
881 u32 hdp_cntl;
882 struct r100_gpu_lockup lockup;
883 };
884
885 struct r600_asic {
886 unsigned max_pipes;
887 unsigned max_tile_pipes;
888 unsigned max_simds;
889 unsigned max_backends;
890 unsigned max_gprs;
891 unsigned max_threads;
892 unsigned max_stack_entries;
893 unsigned max_hw_contexts;
894 unsigned max_gs_threads;
895 unsigned sx_max_export_size;
896 unsigned sx_max_export_pos_size;
897 unsigned sx_max_export_smx_size;
898 unsigned sq_num_cf_insts;
899 unsigned tiling_nbanks;
900 unsigned tiling_npipes;
901 unsigned tiling_group_size;
902 struct r100_gpu_lockup lockup;
903 };
904
905 struct rv770_asic {
906 unsigned max_pipes;
907 unsigned max_tile_pipes;
908 unsigned max_simds;
909 unsigned max_backends;
910 unsigned max_gprs;
911 unsigned max_threads;
912 unsigned max_stack_entries;
913 unsigned max_hw_contexts;
914 unsigned max_gs_threads;
915 unsigned sx_max_export_size;
916 unsigned sx_max_export_pos_size;
917 unsigned sx_max_export_smx_size;
918 unsigned sq_num_cf_insts;
919 unsigned sx_num_of_sets;
920 unsigned sc_prim_fifo_size;
921 unsigned sc_hiz_tile_fifo_size;
922 unsigned sc_earlyz_tile_fifo_fize;
923 unsigned tiling_nbanks;
924 unsigned tiling_npipes;
925 unsigned tiling_group_size;
926 struct r100_gpu_lockup lockup;
927 };
928
929 struct evergreen_asic {
930 unsigned num_ses;
931 unsigned max_pipes;
932 unsigned max_tile_pipes;
933 unsigned max_simds;
934 unsigned max_backends;
935 unsigned max_gprs;
936 unsigned max_threads;
937 unsigned max_stack_entries;
938 unsigned max_hw_contexts;
939 unsigned max_gs_threads;
940 unsigned sx_max_export_size;
941 unsigned sx_max_export_pos_size;
942 unsigned sx_max_export_smx_size;
943 unsigned sq_num_cf_insts;
944 unsigned sx_num_of_sets;
945 unsigned sc_prim_fifo_size;
946 unsigned sc_hiz_tile_fifo_size;
947 unsigned sc_earlyz_tile_fifo_size;
948 unsigned tiling_nbanks;
949 unsigned tiling_npipes;
950 unsigned tiling_group_size;
951 };
952
953 union radeon_asic_config {
954 struct r300_asic r300;
955 struct r100_asic r100;
956 struct r600_asic r600;
957 struct rv770_asic rv770;
958 struct evergreen_asic evergreen;
959 };
960
961 /*
962 * asic initizalization from radeon_asic.c
963 */
964 void radeon_agp_disable(struct radeon_device *rdev);
965 int radeon_asic_init(struct radeon_device *rdev);
966
967
968 /*
969 * IOCTL.
970 */
971 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
972 struct drm_file *filp);
973 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
974 struct drm_file *filp);
975 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
976 struct drm_file *file_priv);
977 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
978 struct drm_file *file_priv);
979 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
980 struct drm_file *file_priv);
981 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
982 struct drm_file *file_priv);
983 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
984 struct drm_file *filp);
985 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
986 struct drm_file *filp);
987 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
988 struct drm_file *filp);
989 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
990 struct drm_file *filp);
991 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
992 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
993 struct drm_file *filp);
994 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
995 struct drm_file *filp);
996
997
998 /*
999 * Core structure, functions and helpers.
1000 */
1001 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1002 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1003
1004 struct radeon_device {
1005 struct device *dev;
1006 struct drm_device *ddev;
1007 struct pci_dev *pdev;
1008 /* ASIC */
1009 union radeon_asic_config config;
1010 enum radeon_family family;
1011 unsigned long flags;
1012 int usec_timeout;
1013 enum radeon_pll_errata pll_errata;
1014 int num_gb_pipes;
1015 int num_z_pipes;
1016 int disp_priority;
1017 /* BIOS */
1018 uint8_t *bios;
1019 bool is_atom_bios;
1020 uint16_t bios_header_start;
1021 struct radeon_bo *stollen_vga_memory;
1022 /* Register mmio */
1023 resource_size_t rmmio_base;
1024 resource_size_t rmmio_size;
1025 void *rmmio;
1026 radeon_rreg_t mc_rreg;
1027 radeon_wreg_t mc_wreg;
1028 radeon_rreg_t pll_rreg;
1029 radeon_wreg_t pll_wreg;
1030 uint32_t pcie_reg_mask;
1031 radeon_rreg_t pciep_rreg;
1032 radeon_wreg_t pciep_wreg;
1033 struct radeon_clock clock;
1034 struct radeon_mc mc;
1035 struct radeon_gart gart;
1036 struct radeon_mode_info mode_info;
1037 struct radeon_scratch scratch;
1038 struct radeon_mman mman;
1039 struct radeon_fence_driver fence_drv;
1040 struct radeon_cp cp;
1041 struct radeon_ib_pool ib_pool;
1042 struct radeon_irq irq;
1043 struct radeon_asic *asic;
1044 struct radeon_gem gem;
1045 struct radeon_pm pm;
1046 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1047 struct mutex cs_mutex;
1048 struct radeon_wb wb;
1049 struct radeon_dummy_page dummy_page;
1050 bool gpu_lockup;
1051 bool shutdown;
1052 bool suspend;
1053 bool need_dma32;
1054 bool accel_working;
1055 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1056 const struct firmware *me_fw; /* all family ME firmware */
1057 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1058 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1059 struct r600_blit r600_blit;
1060 int msi_enabled; /* msi enabled */
1061 struct r600_ih ih; /* r6/700 interrupt ring */
1062 struct workqueue_struct *wq;
1063 struct work_struct hotplug_work;
1064 int num_crtc; /* number of crtcs */
1065 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1066 struct mutex vram_mutex;
1067
1068 /* audio stuff */
1069 struct timer_list audio_timer;
1070 int audio_channels;
1071 int audio_rate;
1072 int audio_bits_per_sample;
1073 uint8_t audio_status_bits;
1074 uint8_t audio_category_code;
1075
1076 bool powered_down;
1077 struct notifier_block acpi_nb;
1078 };
1079
1080 int radeon_device_init(struct radeon_device *rdev,
1081 struct drm_device *ddev,
1082 struct pci_dev *pdev,
1083 uint32_t flags);
1084 void radeon_device_fini(struct radeon_device *rdev);
1085 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1086
1087 /* r600 blit */
1088 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1089 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1090 void r600_kms_blit_copy(struct radeon_device *rdev,
1091 u64 src_gpu_addr, u64 dst_gpu_addr,
1092 int size_bytes);
1093
1094 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1095 {
1096 if (reg < rdev->rmmio_size)
1097 return readl(((void __iomem *)rdev->rmmio) + reg);
1098 else {
1099 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1100 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1101 }
1102 }
1103
1104 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1105 {
1106 if (reg < rdev->rmmio_size)
1107 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1108 else {
1109 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1110 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1111 }
1112 }
1113
1114 /*
1115 * Cast helper
1116 */
1117 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1118
1119 /*
1120 * Registers read & write functions.
1121 */
1122 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1123 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1124 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1125 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1126 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1127 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1128 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1129 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1130 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1131 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1132 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1133 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1134 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1135 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1136 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1137 #define WREG32_P(reg, val, mask) \
1138 do { \
1139 uint32_t tmp_ = RREG32(reg); \
1140 tmp_ &= (mask); \
1141 tmp_ |= ((val) & ~(mask)); \
1142 WREG32(reg, tmp_); \
1143 } while (0)
1144 #define WREG32_PLL_P(reg, val, mask) \
1145 do { \
1146 uint32_t tmp_ = RREG32_PLL(reg); \
1147 tmp_ &= (mask); \
1148 tmp_ |= ((val) & ~(mask)); \
1149 WREG32_PLL(reg, tmp_); \
1150 } while (0)
1151 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1152
1153 /*
1154 * Indirect registers accessor
1155 */
1156 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1157 {
1158 uint32_t r;
1159
1160 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1161 r = RREG32(RADEON_PCIE_DATA);
1162 return r;
1163 }
1164
1165 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1166 {
1167 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1168 WREG32(RADEON_PCIE_DATA, (v));
1169 }
1170
1171 void r100_pll_errata_after_index(struct radeon_device *rdev);
1172
1173
1174 /*
1175 * ASICs helpers.
1176 */
1177 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1178 (rdev->pdev->device == 0x5969))
1179 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1180 (rdev->family == CHIP_RV200) || \
1181 (rdev->family == CHIP_RS100) || \
1182 (rdev->family == CHIP_RS200) || \
1183 (rdev->family == CHIP_RV250) || \
1184 (rdev->family == CHIP_RV280) || \
1185 (rdev->family == CHIP_RS300))
1186 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1187 (rdev->family == CHIP_RV350) || \
1188 (rdev->family == CHIP_R350) || \
1189 (rdev->family == CHIP_RV380) || \
1190 (rdev->family == CHIP_R420) || \
1191 (rdev->family == CHIP_R423) || \
1192 (rdev->family == CHIP_RV410) || \
1193 (rdev->family == CHIP_RS400) || \
1194 (rdev->family == CHIP_RS480))
1195 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1196 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1197 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1198 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1199
1200 /*
1201 * BIOS helpers.
1202 */
1203 #define RBIOS8(i) (rdev->bios[i])
1204 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1205 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1206
1207 int radeon_combios_init(struct radeon_device *rdev);
1208 void radeon_combios_fini(struct radeon_device *rdev);
1209 int radeon_atombios_init(struct radeon_device *rdev);
1210 void radeon_atombios_fini(struct radeon_device *rdev);
1211
1212
1213 /*
1214 * RING helpers.
1215 */
1216 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1217 {
1218 #if DRM_DEBUG_CODE
1219 if (rdev->cp.count_dw <= 0) {
1220 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1221 }
1222 #endif
1223 rdev->cp.ring[rdev->cp.wptr++] = v;
1224 rdev->cp.wptr &= rdev->cp.ptr_mask;
1225 rdev->cp.count_dw--;
1226 rdev->cp.ring_free_dw--;
1227 }
1228
1229
1230 /*
1231 * ASICs macro.
1232 */
1233 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1234 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1235 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1236 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1237 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1238 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1239 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1240 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1241 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1242 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1243 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1244 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1245 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1246 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1247 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1248 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1249 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1250 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1251 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1252 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1253 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1254 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1255 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1256 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1257 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1258 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1259 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1260 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1261 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1262 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1263 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1264 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1265 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1266 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1267 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1268 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1269 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1270 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1271 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1272 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1273 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1274
1275 /* Common functions */
1276 /* AGP */
1277 extern int radeon_gpu_reset(struct radeon_device *rdev);
1278 extern void radeon_agp_disable(struct radeon_device *rdev);
1279 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1280 extern void radeon_gart_restore(struct radeon_device *rdev);
1281 extern int radeon_modeset_init(struct radeon_device *rdev);
1282 extern void radeon_modeset_fini(struct radeon_device *rdev);
1283 extern bool radeon_card_posted(struct radeon_device *rdev);
1284 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1285 extern void radeon_update_display_priority(struct radeon_device *rdev);
1286 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1287 extern int radeon_clocks_init(struct radeon_device *rdev);
1288 extern void radeon_clocks_fini(struct radeon_device *rdev);
1289 extern void radeon_scratch_init(struct radeon_device *rdev);
1290 extern void radeon_surface_init(struct radeon_device *rdev);
1291 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1292 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1293 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1294 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1295 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1296 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1297 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1298 extern int radeon_resume_kms(struct drm_device *dev);
1299 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1300
1301 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1302 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1303 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1304
1305 /* rv200,rv250,rv280 */
1306 extern void r200_set_safe_registers(struct radeon_device *rdev);
1307
1308 /* r300,r350,rv350,rv370,rv380 */
1309 extern void r300_set_reg_safe(struct radeon_device *rdev);
1310 extern void r300_mc_program(struct radeon_device *rdev);
1311 extern void r300_mc_init(struct radeon_device *rdev);
1312 extern void r300_clock_startup(struct radeon_device *rdev);
1313 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1314 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1315 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1316 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1317 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1318
1319 /* r420,r423,rv410 */
1320 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1321 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1322 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1323 extern void r420_pipes_init(struct radeon_device *rdev);
1324
1325 /* rv515 */
1326 struct rv515_mc_save {
1327 u32 d1vga_control;
1328 u32 d2vga_control;
1329 u32 vga_render_control;
1330 u32 vga_hdp_control;
1331 u32 d1crtc_control;
1332 u32 d2crtc_control;
1333 };
1334 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1335 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1336 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1337 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1338 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1339 extern void rv515_clock_startup(struct radeon_device *rdev);
1340 extern void rv515_debugfs(struct radeon_device *rdev);
1341 extern int rv515_suspend(struct radeon_device *rdev);
1342
1343 /* rs400 */
1344 extern int rs400_gart_init(struct radeon_device *rdev);
1345 extern int rs400_gart_enable(struct radeon_device *rdev);
1346 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1347 extern void rs400_gart_disable(struct radeon_device *rdev);
1348 extern void rs400_gart_fini(struct radeon_device *rdev);
1349
1350 /* rs600 */
1351 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1352 extern int rs600_irq_set(struct radeon_device *rdev);
1353 extern void rs600_irq_disable(struct radeon_device *rdev);
1354
1355 /* rs690, rs740 */
1356 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1357 struct drm_display_mode *mode1,
1358 struct drm_display_mode *mode2);
1359
1360 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1361 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1362 extern bool r600_card_posted(struct radeon_device *rdev);
1363 extern void r600_cp_stop(struct radeon_device *rdev);
1364 extern int r600_cp_start(struct radeon_device *rdev);
1365 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1366 extern int r600_cp_resume(struct radeon_device *rdev);
1367 extern void r600_cp_fini(struct radeon_device *rdev);
1368 extern int r600_count_pipe_bits(uint32_t val);
1369 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1370 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1371 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1372 extern int r600_ib_test(struct radeon_device *rdev);
1373 extern int r600_ring_test(struct radeon_device *rdev);
1374 extern void r600_wb_fini(struct radeon_device *rdev);
1375 extern int r600_wb_enable(struct radeon_device *rdev);
1376 extern void r600_wb_disable(struct radeon_device *rdev);
1377 extern void r600_scratch_init(struct radeon_device *rdev);
1378 extern int r600_blit_init(struct radeon_device *rdev);
1379 extern void r600_blit_fini(struct radeon_device *rdev);
1380 extern int r600_init_microcode(struct radeon_device *rdev);
1381 extern int r600_asic_reset(struct radeon_device *rdev);
1382 /* r600 irq */
1383 extern int r600_irq_init(struct radeon_device *rdev);
1384 extern void r600_irq_fini(struct radeon_device *rdev);
1385 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1386 extern int r600_irq_set(struct radeon_device *rdev);
1387 extern void r600_irq_suspend(struct radeon_device *rdev);
1388 extern void r600_disable_interrupts(struct radeon_device *rdev);
1389 extern void r600_rlc_stop(struct radeon_device *rdev);
1390 /* r600 audio */
1391 extern int r600_audio_init(struct radeon_device *rdev);
1392 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1393 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1394 extern int r600_audio_channels(struct radeon_device *rdev);
1395 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1396 extern int r600_audio_rate(struct radeon_device *rdev);
1397 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1398 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1399 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1400 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1401 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1402 extern void r600_audio_fini(struct radeon_device *rdev);
1403 extern void r600_hdmi_init(struct drm_encoder *encoder);
1404 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1405 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1406 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1407 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1408 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1409
1410 extern void r700_cp_stop(struct radeon_device *rdev);
1411 extern void r700_cp_fini(struct radeon_device *rdev);
1412 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1413 extern int evergreen_irq_set(struct radeon_device *rdev);
1414
1415 /* evergreen */
1416 struct evergreen_mc_save {
1417 u32 vga_control[6];
1418 u32 vga_render_control;
1419 u32 vga_hdp_control;
1420 u32 crtc_control[6];
1421 };
1422
1423 #include "radeon_object.h"
1424
1425 #endif
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