]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/gpu/drm/radeon/radeon.h
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
76
77 /*
78 * Modules parameters.
79 */
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
90 extern int radeon_tv;
91 extern int radeon_new_pll;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95
96 /*
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
98 * symbol;
99 */
100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
102 /* RADEON_IB_POOL_SIZE must be a power of 2 */
103 #define RADEON_IB_POOL_SIZE 16
104 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
105 #define RADEONFB_CONN_LIMIT 4
106 #define RADEON_BIOS_NUM_SCRATCH 8
107
108 /*
109 * Errata workarounds.
110 */
111 enum radeon_pll_errata {
112 CHIP_ERRATA_R300_CG = 0x00000001,
113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
114 CHIP_ERRATA_PLL_DELAY = 0x00000004
115 };
116
117
118 struct radeon_device;
119
120
121 /*
122 * BIOS.
123 */
124 #define ATRM_BIOS_PAGE 4096
125
126 #if defined(CONFIG_VGA_SWITCHEROO)
127 bool radeon_atrm_supported(struct pci_dev *pdev);
128 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
129 #else
130 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
131 {
132 return false;
133 }
134
135 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
136 return -EINVAL;
137 }
138 #endif
139 bool radeon_get_bios(struct radeon_device *rdev);
140
141
142 /*
143 * Dummy page
144 */
145 struct radeon_dummy_page {
146 struct page *page;
147 dma_addr_t addr;
148 };
149 int radeon_dummy_page_init(struct radeon_device *rdev);
150 void radeon_dummy_page_fini(struct radeon_device *rdev);
151
152
153 /*
154 * Clocks
155 */
156 struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll dcpll;
160 struct radeon_pll spll;
161 struct radeon_pll mpll;
162 /* 10 Khz units */
163 uint32_t default_mclk;
164 uint32_t default_sclk;
165 uint32_t default_dispclk;
166 uint32_t dp_extclk;
167 };
168
169 /*
170 * Power management
171 */
172 int radeon_pm_init(struct radeon_device *rdev);
173 void radeon_pm_fini(struct radeon_device *rdev);
174 void radeon_pm_compute_clocks(struct radeon_device *rdev);
175 void radeon_pm_suspend(struct radeon_device *rdev);
176 void radeon_pm_resume(struct radeon_device *rdev);
177 void radeon_combios_get_power_modes(struct radeon_device *rdev);
178 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
180 void rs690_pm_info(struct radeon_device *rdev);
181
182 /*
183 * Fences.
184 */
185 struct radeon_fence_driver {
186 uint32_t scratch_reg;
187 atomic_t seq;
188 uint32_t last_seq;
189 unsigned long last_jiffies;
190 unsigned long last_timeout;
191 wait_queue_head_t queue;
192 rwlock_t lock;
193 struct list_head created;
194 struct list_head emited;
195 struct list_head signaled;
196 bool initialized;
197 };
198
199 struct radeon_fence {
200 struct radeon_device *rdev;
201 struct kref kref;
202 struct list_head list;
203 /* protected by radeon_fence.lock */
204 uint32_t seq;
205 bool emited;
206 bool signaled;
207 };
208
209 int radeon_fence_driver_init(struct radeon_device *rdev);
210 void radeon_fence_driver_fini(struct radeon_device *rdev);
211 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
212 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
213 void radeon_fence_process(struct radeon_device *rdev);
214 bool radeon_fence_signaled(struct radeon_fence *fence);
215 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
216 int radeon_fence_wait_next(struct radeon_device *rdev);
217 int radeon_fence_wait_last(struct radeon_device *rdev);
218 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
219 void radeon_fence_unref(struct radeon_fence **fence);
220
221 /*
222 * Tiling registers
223 */
224 struct radeon_surface_reg {
225 struct radeon_bo *bo;
226 };
227
228 #define RADEON_GEM_MAX_SURFACES 8
229
230 /*
231 * TTM.
232 */
233 struct radeon_mman {
234 struct ttm_bo_global_ref bo_global_ref;
235 struct ttm_global_reference mem_global_ref;
236 struct ttm_bo_device bdev;
237 bool mem_global_referenced;
238 bool initialized;
239 };
240
241 struct radeon_bo {
242 /* Protected by gem.mutex */
243 struct list_head list;
244 /* Protected by tbo.reserved */
245 u32 placements[3];
246 struct ttm_placement placement;
247 struct ttm_buffer_object tbo;
248 struct ttm_bo_kmap_obj kmap;
249 unsigned pin_count;
250 void *kptr;
251 u32 tiling_flags;
252 u32 pitch;
253 int surface_reg;
254 /* Constant after initialization */
255 struct radeon_device *rdev;
256 struct drm_gem_object *gobj;
257 };
258
259 struct radeon_bo_list {
260 struct list_head list;
261 struct radeon_bo *bo;
262 uint64_t gpu_offset;
263 unsigned rdomain;
264 unsigned wdomain;
265 u32 tiling_flags;
266 bool reserved;
267 };
268
269 /*
270 * GEM objects.
271 */
272 struct radeon_gem {
273 struct mutex mutex;
274 struct list_head objects;
275 };
276
277 int radeon_gem_init(struct radeon_device *rdev);
278 void radeon_gem_fini(struct radeon_device *rdev);
279 int radeon_gem_object_create(struct radeon_device *rdev, int size,
280 int alignment, int initial_domain,
281 bool discardable, bool kernel,
282 struct drm_gem_object **obj);
283 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
284 uint64_t *gpu_addr);
285 void radeon_gem_object_unpin(struct drm_gem_object *obj);
286
287
288 /*
289 * GART structures, functions & helpers
290 */
291 struct radeon_mc;
292
293 struct radeon_gart_table_ram {
294 volatile uint32_t *ptr;
295 };
296
297 struct radeon_gart_table_vram {
298 struct radeon_bo *robj;
299 volatile uint32_t *ptr;
300 };
301
302 union radeon_gart_table {
303 struct radeon_gart_table_ram ram;
304 struct radeon_gart_table_vram vram;
305 };
306
307 #define RADEON_GPU_PAGE_SIZE 4096
308 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
309
310 struct radeon_gart {
311 dma_addr_t table_addr;
312 unsigned num_gpu_pages;
313 unsigned num_cpu_pages;
314 unsigned table_size;
315 union radeon_gart_table table;
316 struct page **pages;
317 dma_addr_t *pages_addr;
318 bool ready;
319 };
320
321 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
322 void radeon_gart_table_ram_free(struct radeon_device *rdev);
323 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
324 void radeon_gart_table_vram_free(struct radeon_device *rdev);
325 int radeon_gart_init(struct radeon_device *rdev);
326 void radeon_gart_fini(struct radeon_device *rdev);
327 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
328 int pages);
329 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
330 int pages, struct page **pagelist);
331
332
333 /*
334 * GPU MC structures, functions & helpers
335 */
336 struct radeon_mc {
337 resource_size_t aper_size;
338 resource_size_t aper_base;
339 resource_size_t agp_base;
340 /* for some chips with <= 32MB we need to lie
341 * about vram size near mc fb location */
342 u64 mc_vram_size;
343 u64 visible_vram_size;
344 u64 gtt_size;
345 u64 gtt_start;
346 u64 gtt_end;
347 u64 vram_start;
348 u64 vram_end;
349 unsigned vram_width;
350 u64 real_vram_size;
351 int vram_mtrr;
352 bool vram_is_ddr;
353 bool igp_sideport_enabled;
354 u64 gtt_base_align;
355 };
356
357 bool radeon_combios_sideport_present(struct radeon_device *rdev);
358 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
359
360 /*
361 * GPU scratch registers structures, functions & helpers
362 */
363 struct radeon_scratch {
364 unsigned num_reg;
365 bool free[32];
366 uint32_t reg[32];
367 };
368
369 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
370 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
371
372
373 /*
374 * IRQS.
375 */
376 struct radeon_irq {
377 bool installed;
378 bool sw_int;
379 /* FIXME: use a define max crtc rather than hardcode it */
380 bool crtc_vblank_int[6];
381 wait_queue_head_t vblank_queue;
382 /* FIXME: use defines for max hpd/dacs */
383 bool hpd[6];
384 bool gui_idle;
385 bool gui_idle_acked;
386 wait_queue_head_t idle_queue;
387 /* FIXME: use defines for max HDMI blocks */
388 bool hdmi[2];
389 spinlock_t sw_lock;
390 int sw_refcount;
391 };
392
393 int radeon_irq_kms_init(struct radeon_device *rdev);
394 void radeon_irq_kms_fini(struct radeon_device *rdev);
395 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
396 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
397
398 /*
399 * CP & ring.
400 */
401 struct radeon_ib {
402 struct list_head list;
403 unsigned idx;
404 uint64_t gpu_addr;
405 struct radeon_fence *fence;
406 uint32_t *ptr;
407 uint32_t length_dw;
408 bool free;
409 };
410
411 /*
412 * locking -
413 * mutex protects scheduled_ibs, ready, alloc_bm
414 */
415 struct radeon_ib_pool {
416 struct mutex mutex;
417 struct radeon_bo *robj;
418 struct list_head bogus_ib;
419 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
420 bool ready;
421 unsigned head_id;
422 };
423
424 struct radeon_cp {
425 struct radeon_bo *ring_obj;
426 volatile uint32_t *ring;
427 unsigned rptr;
428 unsigned wptr;
429 unsigned wptr_old;
430 unsigned ring_size;
431 unsigned ring_free_dw;
432 int count_dw;
433 uint64_t gpu_addr;
434 uint32_t align_mask;
435 uint32_t ptr_mask;
436 struct mutex mutex;
437 bool ready;
438 };
439
440 /*
441 * R6xx+ IH ring
442 */
443 struct r600_ih {
444 struct radeon_bo *ring_obj;
445 volatile uint32_t *ring;
446 unsigned rptr;
447 unsigned wptr;
448 unsigned wptr_old;
449 unsigned ring_size;
450 uint64_t gpu_addr;
451 uint32_t ptr_mask;
452 spinlock_t lock;
453 bool enabled;
454 };
455
456 struct r600_blit {
457 struct mutex mutex;
458 struct radeon_bo *shader_obj;
459 u64 shader_gpu_addr;
460 u32 vs_offset, ps_offset;
461 u32 state_offset;
462 u32 state_len;
463 u32 vb_used, vb_total;
464 struct radeon_ib *vb_ib;
465 };
466
467 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
468 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
469 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
470 int radeon_ib_pool_init(struct radeon_device *rdev);
471 void radeon_ib_pool_fini(struct radeon_device *rdev);
472 int radeon_ib_test(struct radeon_device *rdev);
473 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
474 /* Ring access between begin & end cannot sleep */
475 void radeon_ring_free_size(struct radeon_device *rdev);
476 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
477 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
478 void radeon_ring_commit(struct radeon_device *rdev);
479 void radeon_ring_unlock_commit(struct radeon_device *rdev);
480 void radeon_ring_unlock_undo(struct radeon_device *rdev);
481 int radeon_ring_test(struct radeon_device *rdev);
482 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
483 void radeon_ring_fini(struct radeon_device *rdev);
484
485
486 /*
487 * CS.
488 */
489 struct radeon_cs_reloc {
490 struct drm_gem_object *gobj;
491 struct radeon_bo *robj;
492 struct radeon_bo_list lobj;
493 uint32_t handle;
494 uint32_t flags;
495 };
496
497 struct radeon_cs_chunk {
498 uint32_t chunk_id;
499 uint32_t length_dw;
500 int kpage_idx[2];
501 uint32_t *kpage[2];
502 uint32_t *kdata;
503 void __user *user_ptr;
504 int last_copied_page;
505 int last_page_index;
506 };
507
508 struct radeon_cs_parser {
509 struct device *dev;
510 struct radeon_device *rdev;
511 struct drm_file *filp;
512 /* chunks */
513 unsigned nchunks;
514 struct radeon_cs_chunk *chunks;
515 uint64_t *chunks_array;
516 /* IB */
517 unsigned idx;
518 /* relocations */
519 unsigned nrelocs;
520 struct radeon_cs_reloc *relocs;
521 struct radeon_cs_reloc **relocs_ptr;
522 struct list_head validated;
523 /* indices of various chunks */
524 int chunk_ib_idx;
525 int chunk_relocs_idx;
526 struct radeon_ib *ib;
527 void *track;
528 unsigned family;
529 int parser_error;
530 };
531
532 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
533 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
534
535
536 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
537 {
538 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
539 u32 pg_idx, pg_offset;
540 u32 idx_value = 0;
541 int new_page;
542
543 pg_idx = (idx * 4) / PAGE_SIZE;
544 pg_offset = (idx * 4) % PAGE_SIZE;
545
546 if (ibc->kpage_idx[0] == pg_idx)
547 return ibc->kpage[0][pg_offset/4];
548 if (ibc->kpage_idx[1] == pg_idx)
549 return ibc->kpage[1][pg_offset/4];
550
551 new_page = radeon_cs_update_pages(p, pg_idx);
552 if (new_page < 0) {
553 p->parser_error = new_page;
554 return 0;
555 }
556
557 idx_value = ibc->kpage[new_page][pg_offset/4];
558 return idx_value;
559 }
560
561 struct radeon_cs_packet {
562 unsigned idx;
563 unsigned type;
564 unsigned reg;
565 unsigned opcode;
566 int count;
567 unsigned one_reg_wr;
568 };
569
570 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
571 struct radeon_cs_packet *pkt,
572 unsigned idx, unsigned reg);
573 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
574 struct radeon_cs_packet *pkt);
575
576
577 /*
578 * AGP
579 */
580 int radeon_agp_init(struct radeon_device *rdev);
581 void radeon_agp_resume(struct radeon_device *rdev);
582 void radeon_agp_suspend(struct radeon_device *rdev);
583 void radeon_agp_fini(struct radeon_device *rdev);
584
585
586 /*
587 * Writeback
588 */
589 struct radeon_wb {
590 struct radeon_bo *wb_obj;
591 volatile uint32_t *wb;
592 uint64_t gpu_addr;
593 };
594
595 /**
596 * struct radeon_pm - power management datas
597 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
598 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
599 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
600 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
601 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
602 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
603 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
604 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
605 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
606 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
607 * @needed_bandwidth: current bandwidth needs
608 *
609 * It keeps track of various data needed to take powermanagement decision.
610 * Bandwith need is used to determine minimun clock of the GPU and memory.
611 * Equation between gpu/memory clock and available bandwidth is hw dependent
612 * (type of memory, bus size, efficiency, ...)
613 */
614
615 enum radeon_pm_method {
616 PM_METHOD_PROFILE,
617 PM_METHOD_DYNPM,
618 };
619
620 enum radeon_dynpm_state {
621 DYNPM_STATE_DISABLED,
622 DYNPM_STATE_MINIMUM,
623 DYNPM_STATE_PAUSED,
624 DYNPM_STATE_ACTIVE,
625 DYNPM_STATE_SUSPENDED,
626 };
627 enum radeon_dynpm_action {
628 DYNPM_ACTION_NONE,
629 DYNPM_ACTION_MINIMUM,
630 DYNPM_ACTION_DOWNCLOCK,
631 DYNPM_ACTION_UPCLOCK,
632 DYNPM_ACTION_DEFAULT
633 };
634
635 enum radeon_voltage_type {
636 VOLTAGE_NONE = 0,
637 VOLTAGE_GPIO,
638 VOLTAGE_VDDC,
639 VOLTAGE_SW
640 };
641
642 enum radeon_pm_state_type {
643 POWER_STATE_TYPE_DEFAULT,
644 POWER_STATE_TYPE_POWERSAVE,
645 POWER_STATE_TYPE_BATTERY,
646 POWER_STATE_TYPE_BALANCED,
647 POWER_STATE_TYPE_PERFORMANCE,
648 };
649
650 enum radeon_pm_profile_type {
651 PM_PROFILE_DEFAULT,
652 PM_PROFILE_AUTO,
653 PM_PROFILE_LOW,
654 PM_PROFILE_MID,
655 PM_PROFILE_HIGH,
656 };
657
658 #define PM_PROFILE_DEFAULT_IDX 0
659 #define PM_PROFILE_LOW_SH_IDX 1
660 #define PM_PROFILE_MID_SH_IDX 2
661 #define PM_PROFILE_HIGH_SH_IDX 3
662 #define PM_PROFILE_LOW_MH_IDX 4
663 #define PM_PROFILE_MID_MH_IDX 5
664 #define PM_PROFILE_HIGH_MH_IDX 6
665 #define PM_PROFILE_MAX 7
666
667 struct radeon_pm_profile {
668 int dpms_off_ps_idx;
669 int dpms_on_ps_idx;
670 int dpms_off_cm_idx;
671 int dpms_on_cm_idx;
672 };
673
674 struct radeon_voltage {
675 enum radeon_voltage_type type;
676 /* gpio voltage */
677 struct radeon_gpio_rec gpio;
678 u32 delay; /* delay in usec from voltage drop to sclk change */
679 bool active_high; /* voltage drop is active when bit is high */
680 /* VDDC voltage */
681 u8 vddc_id; /* index into vddc voltage table */
682 u8 vddci_id; /* index into vddci voltage table */
683 bool vddci_enabled;
684 /* r6xx+ sw */
685 u32 voltage;
686 };
687
688 /* clock mode flags */
689 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
690
691 struct radeon_pm_clock_info {
692 /* memory clock */
693 u32 mclk;
694 /* engine clock */
695 u32 sclk;
696 /* voltage info */
697 struct radeon_voltage voltage;
698 /* standardized clock flags */
699 u32 flags;
700 };
701
702 /* state flags */
703 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
704
705 struct radeon_power_state {
706 enum radeon_pm_state_type type;
707 /* XXX: use a define for num clock modes */
708 struct radeon_pm_clock_info clock_info[8];
709 /* number of valid clock modes in this power state */
710 int num_clock_modes;
711 struct radeon_pm_clock_info *default_clock_mode;
712 /* standardized state flags */
713 u32 flags;
714 u32 misc; /* vbios specific flags */
715 u32 misc2; /* vbios specific flags */
716 int pcie_lanes; /* pcie lanes */
717 };
718
719 /*
720 * Some modes are overclocked by very low value, accept them
721 */
722 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
723
724 struct radeon_pm {
725 struct mutex mutex;
726 u32 active_crtcs;
727 int active_crtc_count;
728 int req_vblank;
729 bool vblank_sync;
730 bool gui_idle;
731 fixed20_12 max_bandwidth;
732 fixed20_12 igp_sideport_mclk;
733 fixed20_12 igp_system_mclk;
734 fixed20_12 igp_ht_link_clk;
735 fixed20_12 igp_ht_link_width;
736 fixed20_12 k8_bandwidth;
737 fixed20_12 sideport_bandwidth;
738 fixed20_12 ht_bandwidth;
739 fixed20_12 core_bandwidth;
740 fixed20_12 sclk;
741 fixed20_12 mclk;
742 fixed20_12 needed_bandwidth;
743 /* XXX: use a define for num power modes */
744 struct radeon_power_state power_state[8];
745 /* number of valid power states */
746 int num_power_states;
747 int current_power_state_index;
748 int current_clock_mode_index;
749 int requested_power_state_index;
750 int requested_clock_mode_index;
751 int default_power_state_index;
752 u32 current_sclk;
753 u32 current_mclk;
754 u32 current_vddc;
755 struct radeon_i2c_chan *i2c_bus;
756 /* selected pm method */
757 enum radeon_pm_method pm_method;
758 /* dynpm power management */
759 struct delayed_work dynpm_idle_work;
760 enum radeon_dynpm_state dynpm_state;
761 enum radeon_dynpm_action dynpm_planned_action;
762 unsigned long dynpm_action_timeout;
763 bool dynpm_can_upclock;
764 bool dynpm_can_downclock;
765 /* profile-based power management */
766 enum radeon_pm_profile_type profile;
767 int profile_index;
768 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
769 };
770
771
772 /*
773 * Benchmarking
774 */
775 void radeon_benchmark(struct radeon_device *rdev);
776
777
778 /*
779 * Testing
780 */
781 void radeon_test_moves(struct radeon_device *rdev);
782
783
784 /*
785 * Debugfs
786 */
787 int radeon_debugfs_add_files(struct radeon_device *rdev,
788 struct drm_info_list *files,
789 unsigned nfiles);
790 int radeon_debugfs_fence_init(struct radeon_device *rdev);
791
792
793 /*
794 * ASIC specific functions.
795 */
796 struct radeon_asic {
797 int (*init)(struct radeon_device *rdev);
798 void (*fini)(struct radeon_device *rdev);
799 int (*resume)(struct radeon_device *rdev);
800 int (*suspend)(struct radeon_device *rdev);
801 void (*vga_set_state)(struct radeon_device *rdev, bool state);
802 bool (*gpu_is_lockup)(struct radeon_device *rdev);
803 int (*asic_reset)(struct radeon_device *rdev);
804 void (*gart_tlb_flush)(struct radeon_device *rdev);
805 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
806 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
807 void (*cp_fini)(struct radeon_device *rdev);
808 void (*cp_disable)(struct radeon_device *rdev);
809 void (*cp_commit)(struct radeon_device *rdev);
810 void (*ring_start)(struct radeon_device *rdev);
811 int (*ring_test)(struct radeon_device *rdev);
812 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
813 int (*irq_set)(struct radeon_device *rdev);
814 int (*irq_process)(struct radeon_device *rdev);
815 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
816 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
817 int (*cs_parse)(struct radeon_cs_parser *p);
818 int (*copy_blit)(struct radeon_device *rdev,
819 uint64_t src_offset,
820 uint64_t dst_offset,
821 unsigned num_pages,
822 struct radeon_fence *fence);
823 int (*copy_dma)(struct radeon_device *rdev,
824 uint64_t src_offset,
825 uint64_t dst_offset,
826 unsigned num_pages,
827 struct radeon_fence *fence);
828 int (*copy)(struct radeon_device *rdev,
829 uint64_t src_offset,
830 uint64_t dst_offset,
831 unsigned num_pages,
832 struct radeon_fence *fence);
833 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
834 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
835 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
836 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
837 int (*get_pcie_lanes)(struct radeon_device *rdev);
838 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
839 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
840 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
841 uint32_t tiling_flags, uint32_t pitch,
842 uint32_t offset, uint32_t obj_size);
843 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
844 void (*bandwidth_update)(struct radeon_device *rdev);
845 void (*hpd_init)(struct radeon_device *rdev);
846 void (*hpd_fini)(struct radeon_device *rdev);
847 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
848 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
849 /* ioctl hw specific callback. Some hw might want to perform special
850 * operation on specific ioctl. For instance on wait idle some hw
851 * might want to perform and HDP flush through MMIO as it seems that
852 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
853 * through ring.
854 */
855 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
856 bool (*gui_idle)(struct radeon_device *rdev);
857 /* power management */
858 void (*pm_misc)(struct radeon_device *rdev);
859 void (*pm_prepare)(struct radeon_device *rdev);
860 void (*pm_finish)(struct radeon_device *rdev);
861 void (*pm_init_profile)(struct radeon_device *rdev);
862 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
863 };
864
865 /*
866 * Asic structures
867 */
868 struct r100_gpu_lockup {
869 unsigned long last_jiffies;
870 u32 last_cp_rptr;
871 };
872
873 struct r100_asic {
874 const unsigned *reg_safe_bm;
875 unsigned reg_safe_bm_size;
876 u32 hdp_cntl;
877 struct r100_gpu_lockup lockup;
878 };
879
880 struct r300_asic {
881 const unsigned *reg_safe_bm;
882 unsigned reg_safe_bm_size;
883 u32 resync_scratch;
884 u32 hdp_cntl;
885 struct r100_gpu_lockup lockup;
886 };
887
888 struct r600_asic {
889 unsigned max_pipes;
890 unsigned max_tile_pipes;
891 unsigned max_simds;
892 unsigned max_backends;
893 unsigned max_gprs;
894 unsigned max_threads;
895 unsigned max_stack_entries;
896 unsigned max_hw_contexts;
897 unsigned max_gs_threads;
898 unsigned sx_max_export_size;
899 unsigned sx_max_export_pos_size;
900 unsigned sx_max_export_smx_size;
901 unsigned sq_num_cf_insts;
902 unsigned tiling_nbanks;
903 unsigned tiling_npipes;
904 unsigned tiling_group_size;
905 struct r100_gpu_lockup lockup;
906 };
907
908 struct rv770_asic {
909 unsigned max_pipes;
910 unsigned max_tile_pipes;
911 unsigned max_simds;
912 unsigned max_backends;
913 unsigned max_gprs;
914 unsigned max_threads;
915 unsigned max_stack_entries;
916 unsigned max_hw_contexts;
917 unsigned max_gs_threads;
918 unsigned sx_max_export_size;
919 unsigned sx_max_export_pos_size;
920 unsigned sx_max_export_smx_size;
921 unsigned sq_num_cf_insts;
922 unsigned sx_num_of_sets;
923 unsigned sc_prim_fifo_size;
924 unsigned sc_hiz_tile_fifo_size;
925 unsigned sc_earlyz_tile_fifo_fize;
926 unsigned tiling_nbanks;
927 unsigned tiling_npipes;
928 unsigned tiling_group_size;
929 struct r100_gpu_lockup lockup;
930 };
931
932 struct evergreen_asic {
933 unsigned num_ses;
934 unsigned max_pipes;
935 unsigned max_tile_pipes;
936 unsigned max_simds;
937 unsigned max_backends;
938 unsigned max_gprs;
939 unsigned max_threads;
940 unsigned max_stack_entries;
941 unsigned max_hw_contexts;
942 unsigned max_gs_threads;
943 unsigned sx_max_export_size;
944 unsigned sx_max_export_pos_size;
945 unsigned sx_max_export_smx_size;
946 unsigned sq_num_cf_insts;
947 unsigned sx_num_of_sets;
948 unsigned sc_prim_fifo_size;
949 unsigned sc_hiz_tile_fifo_size;
950 unsigned sc_earlyz_tile_fifo_size;
951 unsigned tiling_nbanks;
952 unsigned tiling_npipes;
953 unsigned tiling_group_size;
954 };
955
956 union radeon_asic_config {
957 struct r300_asic r300;
958 struct r100_asic r100;
959 struct r600_asic r600;
960 struct rv770_asic rv770;
961 struct evergreen_asic evergreen;
962 };
963
964 /*
965 * asic initizalization from radeon_asic.c
966 */
967 void radeon_agp_disable(struct radeon_device *rdev);
968 int radeon_asic_init(struct radeon_device *rdev);
969
970
971 /*
972 * IOCTL.
973 */
974 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
975 struct drm_file *filp);
976 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *filp);
978 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv);
980 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv);
982 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
983 struct drm_file *file_priv);
984 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
985 struct drm_file *file_priv);
986 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
987 struct drm_file *filp);
988 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
989 struct drm_file *filp);
990 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
991 struct drm_file *filp);
992 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
993 struct drm_file *filp);
994 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
995 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *filp);
997 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
998 struct drm_file *filp);
999
1000
1001 /*
1002 * Core structure, functions and helpers.
1003 */
1004 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1005 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1006
1007 struct radeon_device {
1008 struct device *dev;
1009 struct drm_device *ddev;
1010 struct pci_dev *pdev;
1011 /* ASIC */
1012 union radeon_asic_config config;
1013 enum radeon_family family;
1014 unsigned long flags;
1015 int usec_timeout;
1016 enum radeon_pll_errata pll_errata;
1017 int num_gb_pipes;
1018 int num_z_pipes;
1019 int disp_priority;
1020 /* BIOS */
1021 uint8_t *bios;
1022 bool is_atom_bios;
1023 uint16_t bios_header_start;
1024 struct radeon_bo *stollen_vga_memory;
1025 /* Register mmio */
1026 resource_size_t rmmio_base;
1027 resource_size_t rmmio_size;
1028 void *rmmio;
1029 radeon_rreg_t mc_rreg;
1030 radeon_wreg_t mc_wreg;
1031 radeon_rreg_t pll_rreg;
1032 radeon_wreg_t pll_wreg;
1033 uint32_t pcie_reg_mask;
1034 radeon_rreg_t pciep_rreg;
1035 radeon_wreg_t pciep_wreg;
1036 struct radeon_clock clock;
1037 struct radeon_mc mc;
1038 struct radeon_gart gart;
1039 struct radeon_mode_info mode_info;
1040 struct radeon_scratch scratch;
1041 struct radeon_mman mman;
1042 struct radeon_fence_driver fence_drv;
1043 struct radeon_cp cp;
1044 struct radeon_ib_pool ib_pool;
1045 struct radeon_irq irq;
1046 struct radeon_asic *asic;
1047 struct radeon_gem gem;
1048 struct radeon_pm pm;
1049 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1050 struct mutex cs_mutex;
1051 struct radeon_wb wb;
1052 struct radeon_dummy_page dummy_page;
1053 bool gpu_lockup;
1054 bool shutdown;
1055 bool suspend;
1056 bool need_dma32;
1057 bool accel_working;
1058 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1059 const struct firmware *me_fw; /* all family ME firmware */
1060 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1061 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1062 struct r600_blit r600_blit;
1063 int msi_enabled; /* msi enabled */
1064 struct r600_ih ih; /* r6/700 interrupt ring */
1065 struct workqueue_struct *wq;
1066 struct work_struct hotplug_work;
1067 int num_crtc; /* number of crtcs */
1068 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1069 struct mutex vram_mutex;
1070
1071 /* audio stuff */
1072 struct timer_list audio_timer;
1073 int audio_channels;
1074 int audio_rate;
1075 int audio_bits_per_sample;
1076 uint8_t audio_status_bits;
1077 uint8_t audio_category_code;
1078
1079 bool powered_down;
1080 struct notifier_block acpi_nb;
1081 };
1082
1083 int radeon_device_init(struct radeon_device *rdev,
1084 struct drm_device *ddev,
1085 struct pci_dev *pdev,
1086 uint32_t flags);
1087 void radeon_device_fini(struct radeon_device *rdev);
1088 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1089
1090 /* r600 blit */
1091 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1092 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1093 void r600_kms_blit_copy(struct radeon_device *rdev,
1094 u64 src_gpu_addr, u64 dst_gpu_addr,
1095 int size_bytes);
1096
1097 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1098 {
1099 if (reg < rdev->rmmio_size)
1100 return readl(((void __iomem *)rdev->rmmio) + reg);
1101 else {
1102 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1103 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1104 }
1105 }
1106
1107 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1108 {
1109 if (reg < rdev->rmmio_size)
1110 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1111 else {
1112 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1113 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1114 }
1115 }
1116
1117 /*
1118 * Cast helper
1119 */
1120 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1121
1122 /*
1123 * Registers read & write functions.
1124 */
1125 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1126 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1127 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1128 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1129 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1130 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1131 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1132 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1133 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1134 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1135 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1136 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1137 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1138 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1139 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1140 #define WREG32_P(reg, val, mask) \
1141 do { \
1142 uint32_t tmp_ = RREG32(reg); \
1143 tmp_ &= (mask); \
1144 tmp_ |= ((val) & ~(mask)); \
1145 WREG32(reg, tmp_); \
1146 } while (0)
1147 #define WREG32_PLL_P(reg, val, mask) \
1148 do { \
1149 uint32_t tmp_ = RREG32_PLL(reg); \
1150 tmp_ &= (mask); \
1151 tmp_ |= ((val) & ~(mask)); \
1152 WREG32_PLL(reg, tmp_); \
1153 } while (0)
1154 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1155
1156 /*
1157 * Indirect registers accessor
1158 */
1159 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1160 {
1161 uint32_t r;
1162
1163 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1164 r = RREG32(RADEON_PCIE_DATA);
1165 return r;
1166 }
1167
1168 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1169 {
1170 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1171 WREG32(RADEON_PCIE_DATA, (v));
1172 }
1173
1174 void r100_pll_errata_after_index(struct radeon_device *rdev);
1175
1176
1177 /*
1178 * ASICs helpers.
1179 */
1180 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1181 (rdev->pdev->device == 0x5969))
1182 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1183 (rdev->family == CHIP_RV200) || \
1184 (rdev->family == CHIP_RS100) || \
1185 (rdev->family == CHIP_RS200) || \
1186 (rdev->family == CHIP_RV250) || \
1187 (rdev->family == CHIP_RV280) || \
1188 (rdev->family == CHIP_RS300))
1189 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1190 (rdev->family == CHIP_RV350) || \
1191 (rdev->family == CHIP_R350) || \
1192 (rdev->family == CHIP_RV380) || \
1193 (rdev->family == CHIP_R420) || \
1194 (rdev->family == CHIP_R423) || \
1195 (rdev->family == CHIP_RV410) || \
1196 (rdev->family == CHIP_RS400) || \
1197 (rdev->family == CHIP_RS480))
1198 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1199 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1200 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1201 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1202
1203 /*
1204 * BIOS helpers.
1205 */
1206 #define RBIOS8(i) (rdev->bios[i])
1207 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1208 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1209
1210 int radeon_combios_init(struct radeon_device *rdev);
1211 void radeon_combios_fini(struct radeon_device *rdev);
1212 int radeon_atombios_init(struct radeon_device *rdev);
1213 void radeon_atombios_fini(struct radeon_device *rdev);
1214
1215
1216 /*
1217 * RING helpers.
1218 */
1219 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1220 {
1221 #if DRM_DEBUG_CODE
1222 if (rdev->cp.count_dw <= 0) {
1223 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1224 }
1225 #endif
1226 rdev->cp.ring[rdev->cp.wptr++] = v;
1227 rdev->cp.wptr &= rdev->cp.ptr_mask;
1228 rdev->cp.count_dw--;
1229 rdev->cp.ring_free_dw--;
1230 }
1231
1232
1233 /*
1234 * ASICs macro.
1235 */
1236 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1237 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1238 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1239 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1240 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1241 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1242 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1243 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1244 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1245 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1246 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1247 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1248 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1249 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1250 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1251 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1252 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1253 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1254 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1255 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1256 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1257 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1258 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1259 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1260 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1261 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1262 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1263 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1264 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1265 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1266 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1267 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1268 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1269 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1270 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1271 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1272 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1273 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1274 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1275 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1276 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1277
1278 /* Common functions */
1279 /* AGP */
1280 extern int radeon_gpu_reset(struct radeon_device *rdev);
1281 extern void radeon_agp_disable(struct radeon_device *rdev);
1282 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1283 extern void radeon_gart_restore(struct radeon_device *rdev);
1284 extern int radeon_modeset_init(struct radeon_device *rdev);
1285 extern void radeon_modeset_fini(struct radeon_device *rdev);
1286 extern bool radeon_card_posted(struct radeon_device *rdev);
1287 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1288 extern void radeon_update_display_priority(struct radeon_device *rdev);
1289 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1290 extern int radeon_clocks_init(struct radeon_device *rdev);
1291 extern void radeon_clocks_fini(struct radeon_device *rdev);
1292 extern void radeon_scratch_init(struct radeon_device *rdev);
1293 extern void radeon_surface_init(struct radeon_device *rdev);
1294 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1295 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1296 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1297 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1298 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1299 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1300 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1301 extern int radeon_resume_kms(struct drm_device *dev);
1302 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1303
1304 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1305 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1306 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1307
1308 /* rv200,rv250,rv280 */
1309 extern void r200_set_safe_registers(struct radeon_device *rdev);
1310
1311 /* r300,r350,rv350,rv370,rv380 */
1312 extern void r300_set_reg_safe(struct radeon_device *rdev);
1313 extern void r300_mc_program(struct radeon_device *rdev);
1314 extern void r300_mc_init(struct radeon_device *rdev);
1315 extern void r300_clock_startup(struct radeon_device *rdev);
1316 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1317 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1318 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1319 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1320 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1321
1322 /* r420,r423,rv410 */
1323 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1324 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1325 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1326 extern void r420_pipes_init(struct radeon_device *rdev);
1327
1328 /* rv515 */
1329 struct rv515_mc_save {
1330 u32 d1vga_control;
1331 u32 d2vga_control;
1332 u32 vga_render_control;
1333 u32 vga_hdp_control;
1334 u32 d1crtc_control;
1335 u32 d2crtc_control;
1336 };
1337 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1338 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1339 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1340 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1341 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1342 extern void rv515_clock_startup(struct radeon_device *rdev);
1343 extern void rv515_debugfs(struct radeon_device *rdev);
1344 extern int rv515_suspend(struct radeon_device *rdev);
1345
1346 /* rs400 */
1347 extern int rs400_gart_init(struct radeon_device *rdev);
1348 extern int rs400_gart_enable(struct radeon_device *rdev);
1349 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1350 extern void rs400_gart_disable(struct radeon_device *rdev);
1351 extern void rs400_gart_fini(struct radeon_device *rdev);
1352
1353 /* rs600 */
1354 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1355 extern int rs600_irq_set(struct radeon_device *rdev);
1356 extern void rs600_irq_disable(struct radeon_device *rdev);
1357
1358 /* rs690, rs740 */
1359 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1360 struct drm_display_mode *mode1,
1361 struct drm_display_mode *mode2);
1362
1363 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1364 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1365 extern bool r600_card_posted(struct radeon_device *rdev);
1366 extern void r600_cp_stop(struct radeon_device *rdev);
1367 extern int r600_cp_start(struct radeon_device *rdev);
1368 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1369 extern int r600_cp_resume(struct radeon_device *rdev);
1370 extern void r600_cp_fini(struct radeon_device *rdev);
1371 extern int r600_count_pipe_bits(uint32_t val);
1372 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1373 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1374 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1375 extern int r600_ib_test(struct radeon_device *rdev);
1376 extern int r600_ring_test(struct radeon_device *rdev);
1377 extern void r600_wb_fini(struct radeon_device *rdev);
1378 extern int r600_wb_enable(struct radeon_device *rdev);
1379 extern void r600_wb_disable(struct radeon_device *rdev);
1380 extern void r600_scratch_init(struct radeon_device *rdev);
1381 extern int r600_blit_init(struct radeon_device *rdev);
1382 extern void r600_blit_fini(struct radeon_device *rdev);
1383 extern int r600_init_microcode(struct radeon_device *rdev);
1384 extern int r600_asic_reset(struct radeon_device *rdev);
1385 /* r600 irq */
1386 extern int r600_irq_init(struct radeon_device *rdev);
1387 extern void r600_irq_fini(struct radeon_device *rdev);
1388 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1389 extern int r600_irq_set(struct radeon_device *rdev);
1390 extern void r600_irq_suspend(struct radeon_device *rdev);
1391 extern void r600_disable_interrupts(struct radeon_device *rdev);
1392 extern void r600_rlc_stop(struct radeon_device *rdev);
1393 /* r600 audio */
1394 extern int r600_audio_init(struct radeon_device *rdev);
1395 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1396 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1397 extern int r600_audio_channels(struct radeon_device *rdev);
1398 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1399 extern int r600_audio_rate(struct radeon_device *rdev);
1400 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1401 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1402 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1403 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1404 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1405 extern void r600_audio_fini(struct radeon_device *rdev);
1406 extern void r600_hdmi_init(struct drm_encoder *encoder);
1407 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1408 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1409 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1410 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1411 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1412
1413 extern void r700_cp_stop(struct radeon_device *rdev);
1414 extern void r700_cp_fini(struct radeon_device *rdev);
1415 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1416 extern int evergreen_irq_set(struct radeon_device *rdev);
1417
1418 /* evergreen */
1419 struct evergreen_mc_save {
1420 u32 vga_control[6];
1421 u32 vga_render_control;
1422 u32 vga_hdp_control;
1423 u32 crtc_control[6];
1424 };
1425
1426 #include "radeon_object.h"
1427
1428 #endif
Ubuntu Artful kernel mirror