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drm/ttm: Fix up io_mem_reserve / io_mem_free calling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
76
77 /*
78 * Modules parameters.
79 */
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
90 extern int radeon_tv;
91 extern int radeon_audio;
92 extern int radeon_disp_priority;
93 extern int radeon_hw_i2c;
94
95 /*
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
97 * symbol;
98 */
99 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
101 /* RADEON_IB_POOL_SIZE must be a power of 2 */
102 #define RADEON_IB_POOL_SIZE 16
103 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
104 #define RADEONFB_CONN_LIMIT 4
105 #define RADEON_BIOS_NUM_SCRATCH 8
106
107 /*
108 * Errata workarounds.
109 */
110 enum radeon_pll_errata {
111 CHIP_ERRATA_R300_CG = 0x00000001,
112 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
113 CHIP_ERRATA_PLL_DELAY = 0x00000004
114 };
115
116
117 struct radeon_device;
118
119
120 /*
121 * BIOS.
122 */
123 #define ATRM_BIOS_PAGE 4096
124
125 #if defined(CONFIG_VGA_SWITCHEROO)
126 bool radeon_atrm_supported(struct pci_dev *pdev);
127 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
128 #else
129 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
130 {
131 return false;
132 }
133
134 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
135 return -EINVAL;
136 }
137 #endif
138 bool radeon_get_bios(struct radeon_device *rdev);
139
140
141 /*
142 * Dummy page
143 */
144 struct radeon_dummy_page {
145 struct page *page;
146 dma_addr_t addr;
147 };
148 int radeon_dummy_page_init(struct radeon_device *rdev);
149 void radeon_dummy_page_fini(struct radeon_device *rdev);
150
151
152 /*
153 * Clocks
154 */
155 struct radeon_clock {
156 struct radeon_pll p1pll;
157 struct radeon_pll p2pll;
158 struct radeon_pll dcpll;
159 struct radeon_pll spll;
160 struct radeon_pll mpll;
161 /* 10 Khz units */
162 uint32_t default_mclk;
163 uint32_t default_sclk;
164 uint32_t default_dispclk;
165 uint32_t dp_extclk;
166 };
167
168 /*
169 * Power management
170 */
171 int radeon_pm_init(struct radeon_device *rdev);
172 void radeon_pm_fini(struct radeon_device *rdev);
173 void radeon_pm_compute_clocks(struct radeon_device *rdev);
174 void radeon_pm_suspend(struct radeon_device *rdev);
175 void radeon_pm_resume(struct radeon_device *rdev);
176 void radeon_combios_get_power_modes(struct radeon_device *rdev);
177 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
178 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
179 void rs690_pm_info(struct radeon_device *rdev);
180 extern u32 rv6xx_get_temp(struct radeon_device *rdev);
181 extern u32 rv770_get_temp(struct radeon_device *rdev);
182 extern u32 evergreen_get_temp(struct radeon_device *rdev);
183
184 /*
185 * Fences.
186 */
187 struct radeon_fence_driver {
188 uint32_t scratch_reg;
189 atomic_t seq;
190 uint32_t last_seq;
191 unsigned long last_jiffies;
192 unsigned long last_timeout;
193 wait_queue_head_t queue;
194 rwlock_t lock;
195 struct list_head created;
196 struct list_head emited;
197 struct list_head signaled;
198 bool initialized;
199 };
200
201 struct radeon_fence {
202 struct radeon_device *rdev;
203 struct kref kref;
204 struct list_head list;
205 /* protected by radeon_fence.lock */
206 uint32_t seq;
207 bool emited;
208 bool signaled;
209 };
210
211 int radeon_fence_driver_init(struct radeon_device *rdev);
212 void radeon_fence_driver_fini(struct radeon_device *rdev);
213 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
214 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
215 void radeon_fence_process(struct radeon_device *rdev);
216 bool radeon_fence_signaled(struct radeon_fence *fence);
217 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
218 int radeon_fence_wait_next(struct radeon_device *rdev);
219 int radeon_fence_wait_last(struct radeon_device *rdev);
220 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
221 void radeon_fence_unref(struct radeon_fence **fence);
222
223 /*
224 * Tiling registers
225 */
226 struct radeon_surface_reg {
227 struct radeon_bo *bo;
228 };
229
230 #define RADEON_GEM_MAX_SURFACES 8
231
232 /*
233 * TTM.
234 */
235 struct radeon_mman {
236 struct ttm_bo_global_ref bo_global_ref;
237 struct drm_global_reference mem_global_ref;
238 struct ttm_bo_device bdev;
239 bool mem_global_referenced;
240 bool initialized;
241 };
242
243 struct radeon_bo {
244 /* Protected by gem.mutex */
245 struct list_head list;
246 /* Protected by tbo.reserved */
247 u32 placements[3];
248 struct ttm_placement placement;
249 struct ttm_buffer_object tbo;
250 struct ttm_bo_kmap_obj kmap;
251 unsigned pin_count;
252 void *kptr;
253 u32 tiling_flags;
254 u32 pitch;
255 int surface_reg;
256 /* Constant after initialization */
257 struct radeon_device *rdev;
258 struct drm_gem_object *gobj;
259 };
260
261 struct radeon_bo_list {
262 struct list_head list;
263 struct radeon_bo *bo;
264 uint64_t gpu_offset;
265 unsigned rdomain;
266 unsigned wdomain;
267 u32 tiling_flags;
268 bool reserved;
269 };
270
271 /*
272 * GEM objects.
273 */
274 struct radeon_gem {
275 struct mutex mutex;
276 struct list_head objects;
277 };
278
279 int radeon_gem_init(struct radeon_device *rdev);
280 void radeon_gem_fini(struct radeon_device *rdev);
281 int radeon_gem_object_create(struct radeon_device *rdev, int size,
282 int alignment, int initial_domain,
283 bool discardable, bool kernel,
284 struct drm_gem_object **obj);
285 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
286 uint64_t *gpu_addr);
287 void radeon_gem_object_unpin(struct drm_gem_object *obj);
288
289
290 /*
291 * GART structures, functions & helpers
292 */
293 struct radeon_mc;
294
295 struct radeon_gart_table_ram {
296 volatile uint32_t *ptr;
297 };
298
299 struct radeon_gart_table_vram {
300 struct radeon_bo *robj;
301 volatile uint32_t *ptr;
302 };
303
304 union radeon_gart_table {
305 struct radeon_gart_table_ram ram;
306 struct radeon_gart_table_vram vram;
307 };
308
309 #define RADEON_GPU_PAGE_SIZE 4096
310 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
311
312 struct radeon_gart {
313 dma_addr_t table_addr;
314 unsigned num_gpu_pages;
315 unsigned num_cpu_pages;
316 unsigned table_size;
317 union radeon_gart_table table;
318 struct page **pages;
319 dma_addr_t *pages_addr;
320 bool ready;
321 };
322
323 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
324 void radeon_gart_table_ram_free(struct radeon_device *rdev);
325 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
326 void radeon_gart_table_vram_free(struct radeon_device *rdev);
327 int radeon_gart_init(struct radeon_device *rdev);
328 void radeon_gart_fini(struct radeon_device *rdev);
329 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
330 int pages);
331 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
332 int pages, struct page **pagelist);
333
334
335 /*
336 * GPU MC structures, functions & helpers
337 */
338 struct radeon_mc {
339 resource_size_t aper_size;
340 resource_size_t aper_base;
341 resource_size_t agp_base;
342 /* for some chips with <= 32MB we need to lie
343 * about vram size near mc fb location */
344 u64 mc_vram_size;
345 u64 visible_vram_size;
346 u64 active_vram_size;
347 u64 gtt_size;
348 u64 gtt_start;
349 u64 gtt_end;
350 u64 vram_start;
351 u64 vram_end;
352 unsigned vram_width;
353 u64 real_vram_size;
354 int vram_mtrr;
355 bool vram_is_ddr;
356 bool igp_sideport_enabled;
357 u64 gtt_base_align;
358 };
359
360 bool radeon_combios_sideport_present(struct radeon_device *rdev);
361 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
362
363 /*
364 * GPU scratch registers structures, functions & helpers
365 */
366 struct radeon_scratch {
367 unsigned num_reg;
368 uint32_t reg_base;
369 bool free[32];
370 uint32_t reg[32];
371 };
372
373 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
374 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
375
376
377 /*
378 * IRQS.
379 */
380 struct radeon_irq {
381 bool installed;
382 bool sw_int;
383 /* FIXME: use a define max crtc rather than hardcode it */
384 bool crtc_vblank_int[6];
385 wait_queue_head_t vblank_queue;
386 /* FIXME: use defines for max hpd/dacs */
387 bool hpd[6];
388 bool gui_idle;
389 bool gui_idle_acked;
390 wait_queue_head_t idle_queue;
391 /* FIXME: use defines for max HDMI blocks */
392 bool hdmi[2];
393 spinlock_t sw_lock;
394 int sw_refcount;
395 };
396
397 int radeon_irq_kms_init(struct radeon_device *rdev);
398 void radeon_irq_kms_fini(struct radeon_device *rdev);
399 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
400 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
401
402 /*
403 * CP & ring.
404 */
405 struct radeon_ib {
406 struct list_head list;
407 unsigned idx;
408 uint64_t gpu_addr;
409 struct radeon_fence *fence;
410 uint32_t *ptr;
411 uint32_t length_dw;
412 bool free;
413 };
414
415 /*
416 * locking -
417 * mutex protects scheduled_ibs, ready, alloc_bm
418 */
419 struct radeon_ib_pool {
420 struct mutex mutex;
421 struct radeon_bo *robj;
422 struct list_head bogus_ib;
423 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
424 bool ready;
425 unsigned head_id;
426 };
427
428 struct radeon_cp {
429 struct radeon_bo *ring_obj;
430 volatile uint32_t *ring;
431 unsigned rptr;
432 unsigned wptr;
433 unsigned wptr_old;
434 unsigned ring_size;
435 unsigned ring_free_dw;
436 int count_dw;
437 uint64_t gpu_addr;
438 uint32_t align_mask;
439 uint32_t ptr_mask;
440 struct mutex mutex;
441 bool ready;
442 };
443
444 /*
445 * R6xx+ IH ring
446 */
447 struct r600_ih {
448 struct radeon_bo *ring_obj;
449 volatile uint32_t *ring;
450 unsigned rptr;
451 unsigned wptr;
452 unsigned wptr_old;
453 unsigned ring_size;
454 uint64_t gpu_addr;
455 uint32_t ptr_mask;
456 spinlock_t lock;
457 bool enabled;
458 };
459
460 struct r600_blit {
461 struct mutex mutex;
462 struct radeon_bo *shader_obj;
463 u64 shader_gpu_addr;
464 u32 vs_offset, ps_offset;
465 u32 state_offset;
466 u32 state_len;
467 u32 vb_used, vb_total;
468 struct radeon_ib *vb_ib;
469 };
470
471 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
472 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
473 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
474 int radeon_ib_pool_init(struct radeon_device *rdev);
475 void radeon_ib_pool_fini(struct radeon_device *rdev);
476 int radeon_ib_test(struct radeon_device *rdev);
477 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
478 /* Ring access between begin & end cannot sleep */
479 void radeon_ring_free_size(struct radeon_device *rdev);
480 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
481 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
482 void radeon_ring_commit(struct radeon_device *rdev);
483 void radeon_ring_unlock_commit(struct radeon_device *rdev);
484 void radeon_ring_unlock_undo(struct radeon_device *rdev);
485 int radeon_ring_test(struct radeon_device *rdev);
486 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
487 void radeon_ring_fini(struct radeon_device *rdev);
488
489
490 /*
491 * CS.
492 */
493 struct radeon_cs_reloc {
494 struct drm_gem_object *gobj;
495 struct radeon_bo *robj;
496 struct radeon_bo_list lobj;
497 uint32_t handle;
498 uint32_t flags;
499 };
500
501 struct radeon_cs_chunk {
502 uint32_t chunk_id;
503 uint32_t length_dw;
504 int kpage_idx[2];
505 uint32_t *kpage[2];
506 uint32_t *kdata;
507 void __user *user_ptr;
508 int last_copied_page;
509 int last_page_index;
510 };
511
512 struct radeon_cs_parser {
513 struct device *dev;
514 struct radeon_device *rdev;
515 struct drm_file *filp;
516 /* chunks */
517 unsigned nchunks;
518 struct radeon_cs_chunk *chunks;
519 uint64_t *chunks_array;
520 /* IB */
521 unsigned idx;
522 /* relocations */
523 unsigned nrelocs;
524 struct radeon_cs_reloc *relocs;
525 struct radeon_cs_reloc **relocs_ptr;
526 struct list_head validated;
527 /* indices of various chunks */
528 int chunk_ib_idx;
529 int chunk_relocs_idx;
530 struct radeon_ib *ib;
531 void *track;
532 unsigned family;
533 int parser_error;
534 };
535
536 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
537 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
538
539
540 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
541 {
542 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
543 u32 pg_idx, pg_offset;
544 u32 idx_value = 0;
545 int new_page;
546
547 pg_idx = (idx * 4) / PAGE_SIZE;
548 pg_offset = (idx * 4) % PAGE_SIZE;
549
550 if (ibc->kpage_idx[0] == pg_idx)
551 return ibc->kpage[0][pg_offset/4];
552 if (ibc->kpage_idx[1] == pg_idx)
553 return ibc->kpage[1][pg_offset/4];
554
555 new_page = radeon_cs_update_pages(p, pg_idx);
556 if (new_page < 0) {
557 p->parser_error = new_page;
558 return 0;
559 }
560
561 idx_value = ibc->kpage[new_page][pg_offset/4];
562 return idx_value;
563 }
564
565 struct radeon_cs_packet {
566 unsigned idx;
567 unsigned type;
568 unsigned reg;
569 unsigned opcode;
570 int count;
571 unsigned one_reg_wr;
572 };
573
574 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
575 struct radeon_cs_packet *pkt,
576 unsigned idx, unsigned reg);
577 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
578 struct radeon_cs_packet *pkt);
579
580
581 /*
582 * AGP
583 */
584 int radeon_agp_init(struct radeon_device *rdev);
585 void radeon_agp_resume(struct radeon_device *rdev);
586 void radeon_agp_suspend(struct radeon_device *rdev);
587 void radeon_agp_fini(struct radeon_device *rdev);
588
589
590 /*
591 * Writeback
592 */
593 struct radeon_wb {
594 struct radeon_bo *wb_obj;
595 volatile uint32_t *wb;
596 uint64_t gpu_addr;
597 bool enabled;
598 bool use_event;
599 };
600
601 #define RADEON_WB_SCRATCH_OFFSET 0
602 #define RADEON_WB_CP_RPTR_OFFSET 1024
603 #define R600_WB_IH_WPTR_OFFSET 2048
604 #define R600_WB_EVENT_OFFSET 3072
605
606 /**
607 * struct radeon_pm - power management datas
608 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
609 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
610 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
611 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
612 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
613 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
614 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
615 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
616 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
617 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
618 * @needed_bandwidth: current bandwidth needs
619 *
620 * It keeps track of various data needed to take powermanagement decision.
621 * Bandwith need is used to determine minimun clock of the GPU and memory.
622 * Equation between gpu/memory clock and available bandwidth is hw dependent
623 * (type of memory, bus size, efficiency, ...)
624 */
625
626 enum radeon_pm_method {
627 PM_METHOD_PROFILE,
628 PM_METHOD_DYNPM,
629 };
630
631 enum radeon_dynpm_state {
632 DYNPM_STATE_DISABLED,
633 DYNPM_STATE_MINIMUM,
634 DYNPM_STATE_PAUSED,
635 DYNPM_STATE_ACTIVE,
636 DYNPM_STATE_SUSPENDED,
637 };
638 enum radeon_dynpm_action {
639 DYNPM_ACTION_NONE,
640 DYNPM_ACTION_MINIMUM,
641 DYNPM_ACTION_DOWNCLOCK,
642 DYNPM_ACTION_UPCLOCK,
643 DYNPM_ACTION_DEFAULT
644 };
645
646 enum radeon_voltage_type {
647 VOLTAGE_NONE = 0,
648 VOLTAGE_GPIO,
649 VOLTAGE_VDDC,
650 VOLTAGE_SW
651 };
652
653 enum radeon_pm_state_type {
654 POWER_STATE_TYPE_DEFAULT,
655 POWER_STATE_TYPE_POWERSAVE,
656 POWER_STATE_TYPE_BATTERY,
657 POWER_STATE_TYPE_BALANCED,
658 POWER_STATE_TYPE_PERFORMANCE,
659 };
660
661 enum radeon_pm_profile_type {
662 PM_PROFILE_DEFAULT,
663 PM_PROFILE_AUTO,
664 PM_PROFILE_LOW,
665 PM_PROFILE_MID,
666 PM_PROFILE_HIGH,
667 };
668
669 #define PM_PROFILE_DEFAULT_IDX 0
670 #define PM_PROFILE_LOW_SH_IDX 1
671 #define PM_PROFILE_MID_SH_IDX 2
672 #define PM_PROFILE_HIGH_SH_IDX 3
673 #define PM_PROFILE_LOW_MH_IDX 4
674 #define PM_PROFILE_MID_MH_IDX 5
675 #define PM_PROFILE_HIGH_MH_IDX 6
676 #define PM_PROFILE_MAX 7
677
678 struct radeon_pm_profile {
679 int dpms_off_ps_idx;
680 int dpms_on_ps_idx;
681 int dpms_off_cm_idx;
682 int dpms_on_cm_idx;
683 };
684
685 enum radeon_int_thermal_type {
686 THERMAL_TYPE_NONE,
687 THERMAL_TYPE_RV6XX,
688 THERMAL_TYPE_RV770,
689 THERMAL_TYPE_EVERGREEN,
690 };
691
692 struct radeon_voltage {
693 enum radeon_voltage_type type;
694 /* gpio voltage */
695 struct radeon_gpio_rec gpio;
696 u32 delay; /* delay in usec from voltage drop to sclk change */
697 bool active_high; /* voltage drop is active when bit is high */
698 /* VDDC voltage */
699 u8 vddc_id; /* index into vddc voltage table */
700 u8 vddci_id; /* index into vddci voltage table */
701 bool vddci_enabled;
702 /* r6xx+ sw */
703 u32 voltage;
704 };
705
706 /* clock mode flags */
707 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
708
709 struct radeon_pm_clock_info {
710 /* memory clock */
711 u32 mclk;
712 /* engine clock */
713 u32 sclk;
714 /* voltage info */
715 struct radeon_voltage voltage;
716 /* standardized clock flags */
717 u32 flags;
718 };
719
720 /* state flags */
721 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
722
723 struct radeon_power_state {
724 enum radeon_pm_state_type type;
725 /* XXX: use a define for num clock modes */
726 struct radeon_pm_clock_info clock_info[8];
727 /* number of valid clock modes in this power state */
728 int num_clock_modes;
729 struct radeon_pm_clock_info *default_clock_mode;
730 /* standardized state flags */
731 u32 flags;
732 u32 misc; /* vbios specific flags */
733 u32 misc2; /* vbios specific flags */
734 int pcie_lanes; /* pcie lanes */
735 };
736
737 /*
738 * Some modes are overclocked by very low value, accept them
739 */
740 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
741
742 struct radeon_pm {
743 struct mutex mutex;
744 u32 active_crtcs;
745 int active_crtc_count;
746 int req_vblank;
747 bool vblank_sync;
748 bool gui_idle;
749 fixed20_12 max_bandwidth;
750 fixed20_12 igp_sideport_mclk;
751 fixed20_12 igp_system_mclk;
752 fixed20_12 igp_ht_link_clk;
753 fixed20_12 igp_ht_link_width;
754 fixed20_12 k8_bandwidth;
755 fixed20_12 sideport_bandwidth;
756 fixed20_12 ht_bandwidth;
757 fixed20_12 core_bandwidth;
758 fixed20_12 sclk;
759 fixed20_12 mclk;
760 fixed20_12 needed_bandwidth;
761 /* XXX: use a define for num power modes */
762 struct radeon_power_state power_state[8];
763 /* number of valid power states */
764 int num_power_states;
765 int current_power_state_index;
766 int current_clock_mode_index;
767 int requested_power_state_index;
768 int requested_clock_mode_index;
769 int default_power_state_index;
770 u32 current_sclk;
771 u32 current_mclk;
772 u32 current_vddc;
773 struct radeon_i2c_chan *i2c_bus;
774 /* selected pm method */
775 enum radeon_pm_method pm_method;
776 /* dynpm power management */
777 struct delayed_work dynpm_idle_work;
778 enum radeon_dynpm_state dynpm_state;
779 enum radeon_dynpm_action dynpm_planned_action;
780 unsigned long dynpm_action_timeout;
781 bool dynpm_can_upclock;
782 bool dynpm_can_downclock;
783 /* profile-based power management */
784 enum radeon_pm_profile_type profile;
785 int profile_index;
786 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
787 /* internal thermal controller on rv6xx+ */
788 enum radeon_int_thermal_type int_thermal_type;
789 struct device *int_hwmon_dev;
790 };
791
792
793 /*
794 * Benchmarking
795 */
796 void radeon_benchmark(struct radeon_device *rdev);
797
798
799 /*
800 * Testing
801 */
802 void radeon_test_moves(struct radeon_device *rdev);
803
804
805 /*
806 * Debugfs
807 */
808 int radeon_debugfs_add_files(struct radeon_device *rdev,
809 struct drm_info_list *files,
810 unsigned nfiles);
811 int radeon_debugfs_fence_init(struct radeon_device *rdev);
812
813
814 /*
815 * ASIC specific functions.
816 */
817 struct radeon_asic {
818 int (*init)(struct radeon_device *rdev);
819 void (*fini)(struct radeon_device *rdev);
820 int (*resume)(struct radeon_device *rdev);
821 int (*suspend)(struct radeon_device *rdev);
822 void (*vga_set_state)(struct radeon_device *rdev, bool state);
823 bool (*gpu_is_lockup)(struct radeon_device *rdev);
824 int (*asic_reset)(struct radeon_device *rdev);
825 void (*gart_tlb_flush)(struct radeon_device *rdev);
826 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
827 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
828 void (*cp_fini)(struct radeon_device *rdev);
829 void (*cp_disable)(struct radeon_device *rdev);
830 void (*cp_commit)(struct radeon_device *rdev);
831 void (*ring_start)(struct radeon_device *rdev);
832 int (*ring_test)(struct radeon_device *rdev);
833 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
834 int (*irq_set)(struct radeon_device *rdev);
835 int (*irq_process)(struct radeon_device *rdev);
836 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
837 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
838 int (*cs_parse)(struct radeon_cs_parser *p);
839 int (*copy_blit)(struct radeon_device *rdev,
840 uint64_t src_offset,
841 uint64_t dst_offset,
842 unsigned num_pages,
843 struct radeon_fence *fence);
844 int (*copy_dma)(struct radeon_device *rdev,
845 uint64_t src_offset,
846 uint64_t dst_offset,
847 unsigned num_pages,
848 struct radeon_fence *fence);
849 int (*copy)(struct radeon_device *rdev,
850 uint64_t src_offset,
851 uint64_t dst_offset,
852 unsigned num_pages,
853 struct radeon_fence *fence);
854 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
855 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
856 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
857 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
858 int (*get_pcie_lanes)(struct radeon_device *rdev);
859 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
860 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
861 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
862 uint32_t tiling_flags, uint32_t pitch,
863 uint32_t offset, uint32_t obj_size);
864 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
865 void (*bandwidth_update)(struct radeon_device *rdev);
866 void (*hpd_init)(struct radeon_device *rdev);
867 void (*hpd_fini)(struct radeon_device *rdev);
868 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
869 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
870 /* ioctl hw specific callback. Some hw might want to perform special
871 * operation on specific ioctl. For instance on wait idle some hw
872 * might want to perform and HDP flush through MMIO as it seems that
873 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
874 * through ring.
875 */
876 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
877 bool (*gui_idle)(struct radeon_device *rdev);
878 /* power management */
879 void (*pm_misc)(struct radeon_device *rdev);
880 void (*pm_prepare)(struct radeon_device *rdev);
881 void (*pm_finish)(struct radeon_device *rdev);
882 void (*pm_init_profile)(struct radeon_device *rdev);
883 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
884 };
885
886 /*
887 * Asic structures
888 */
889 struct r100_gpu_lockup {
890 unsigned long last_jiffies;
891 u32 last_cp_rptr;
892 };
893
894 struct r100_asic {
895 const unsigned *reg_safe_bm;
896 unsigned reg_safe_bm_size;
897 u32 hdp_cntl;
898 struct r100_gpu_lockup lockup;
899 };
900
901 struct r300_asic {
902 const unsigned *reg_safe_bm;
903 unsigned reg_safe_bm_size;
904 u32 resync_scratch;
905 u32 hdp_cntl;
906 struct r100_gpu_lockup lockup;
907 };
908
909 struct r600_asic {
910 unsigned max_pipes;
911 unsigned max_tile_pipes;
912 unsigned max_simds;
913 unsigned max_backends;
914 unsigned max_gprs;
915 unsigned max_threads;
916 unsigned max_stack_entries;
917 unsigned max_hw_contexts;
918 unsigned max_gs_threads;
919 unsigned sx_max_export_size;
920 unsigned sx_max_export_pos_size;
921 unsigned sx_max_export_smx_size;
922 unsigned sq_num_cf_insts;
923 unsigned tiling_nbanks;
924 unsigned tiling_npipes;
925 unsigned tiling_group_size;
926 unsigned tile_config;
927 struct r100_gpu_lockup lockup;
928 };
929
930 struct rv770_asic {
931 unsigned max_pipes;
932 unsigned max_tile_pipes;
933 unsigned max_simds;
934 unsigned max_backends;
935 unsigned max_gprs;
936 unsigned max_threads;
937 unsigned max_stack_entries;
938 unsigned max_hw_contexts;
939 unsigned max_gs_threads;
940 unsigned sx_max_export_size;
941 unsigned sx_max_export_pos_size;
942 unsigned sx_max_export_smx_size;
943 unsigned sq_num_cf_insts;
944 unsigned sx_num_of_sets;
945 unsigned sc_prim_fifo_size;
946 unsigned sc_hiz_tile_fifo_size;
947 unsigned sc_earlyz_tile_fifo_fize;
948 unsigned tiling_nbanks;
949 unsigned tiling_npipes;
950 unsigned tiling_group_size;
951 unsigned tile_config;
952 struct r100_gpu_lockup lockup;
953 };
954
955 struct evergreen_asic {
956 unsigned num_ses;
957 unsigned max_pipes;
958 unsigned max_tile_pipes;
959 unsigned max_simds;
960 unsigned max_backends;
961 unsigned max_gprs;
962 unsigned max_threads;
963 unsigned max_stack_entries;
964 unsigned max_hw_contexts;
965 unsigned max_gs_threads;
966 unsigned sx_max_export_size;
967 unsigned sx_max_export_pos_size;
968 unsigned sx_max_export_smx_size;
969 unsigned sq_num_cf_insts;
970 unsigned sx_num_of_sets;
971 unsigned sc_prim_fifo_size;
972 unsigned sc_hiz_tile_fifo_size;
973 unsigned sc_earlyz_tile_fifo_size;
974 unsigned tiling_nbanks;
975 unsigned tiling_npipes;
976 unsigned tiling_group_size;
977 unsigned tile_config;
978 };
979
980 union radeon_asic_config {
981 struct r300_asic r300;
982 struct r100_asic r100;
983 struct r600_asic r600;
984 struct rv770_asic rv770;
985 struct evergreen_asic evergreen;
986 };
987
988 /*
989 * asic initizalization from radeon_asic.c
990 */
991 void radeon_agp_disable(struct radeon_device *rdev);
992 int radeon_asic_init(struct radeon_device *rdev);
993
994
995 /*
996 * IOCTL.
997 */
998 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
999 struct drm_file *filp);
1000 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1001 struct drm_file *filp);
1002 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1003 struct drm_file *file_priv);
1004 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1005 struct drm_file *file_priv);
1006 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1007 struct drm_file *file_priv);
1008 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv);
1010 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1011 struct drm_file *filp);
1012 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1013 struct drm_file *filp);
1014 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1015 struct drm_file *filp);
1016 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1017 struct drm_file *filp);
1018 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1019 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1020 struct drm_file *filp);
1021 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1022 struct drm_file *filp);
1023
1024 /* VRAM scratch page for HDP bug */
1025 struct r700_vram_scratch {
1026 struct radeon_bo *robj;
1027 volatile uint32_t *ptr;
1028 };
1029
1030 /*
1031 * Core structure, functions and helpers.
1032 */
1033 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1034 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1035
1036 struct radeon_device {
1037 struct device *dev;
1038 struct drm_device *ddev;
1039 struct pci_dev *pdev;
1040 /* ASIC */
1041 union radeon_asic_config config;
1042 enum radeon_family family;
1043 unsigned long flags;
1044 int usec_timeout;
1045 enum radeon_pll_errata pll_errata;
1046 int num_gb_pipes;
1047 int num_z_pipes;
1048 int disp_priority;
1049 /* BIOS */
1050 uint8_t *bios;
1051 bool is_atom_bios;
1052 uint16_t bios_header_start;
1053 struct radeon_bo *stollen_vga_memory;
1054 /* Register mmio */
1055 resource_size_t rmmio_base;
1056 resource_size_t rmmio_size;
1057 void *rmmio;
1058 radeon_rreg_t mc_rreg;
1059 radeon_wreg_t mc_wreg;
1060 radeon_rreg_t pll_rreg;
1061 radeon_wreg_t pll_wreg;
1062 uint32_t pcie_reg_mask;
1063 radeon_rreg_t pciep_rreg;
1064 radeon_wreg_t pciep_wreg;
1065 /* io port */
1066 void __iomem *rio_mem;
1067 resource_size_t rio_mem_size;
1068 struct radeon_clock clock;
1069 struct radeon_mc mc;
1070 struct radeon_gart gart;
1071 struct radeon_mode_info mode_info;
1072 struct radeon_scratch scratch;
1073 struct radeon_mman mman;
1074 struct radeon_fence_driver fence_drv;
1075 struct radeon_cp cp;
1076 struct radeon_ib_pool ib_pool;
1077 struct radeon_irq irq;
1078 struct radeon_asic *asic;
1079 struct radeon_gem gem;
1080 struct radeon_pm pm;
1081 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1082 struct mutex cs_mutex;
1083 struct radeon_wb wb;
1084 struct radeon_dummy_page dummy_page;
1085 bool gpu_lockup;
1086 bool shutdown;
1087 bool suspend;
1088 bool need_dma32;
1089 bool accel_working;
1090 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1091 const struct firmware *me_fw; /* all family ME firmware */
1092 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1093 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1094 struct r600_blit r600_blit;
1095 struct r700_vram_scratch vram_scratch;
1096 int msi_enabled; /* msi enabled */
1097 struct r600_ih ih; /* r6/700 interrupt ring */
1098 struct workqueue_struct *wq;
1099 struct work_struct hotplug_work;
1100 int num_crtc; /* number of crtcs */
1101 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1102 struct mutex vram_mutex;
1103
1104 /* audio stuff */
1105 bool audio_enabled;
1106 struct timer_list audio_timer;
1107 int audio_channels;
1108 int audio_rate;
1109 int audio_bits_per_sample;
1110 uint8_t audio_status_bits;
1111 uint8_t audio_category_code;
1112
1113 bool powered_down;
1114 struct notifier_block acpi_nb;
1115 /* only one userspace can use Hyperz features at a time */
1116 struct drm_file *hyperz_filp;
1117 /* i2c buses */
1118 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1119 };
1120
1121 int radeon_device_init(struct radeon_device *rdev,
1122 struct drm_device *ddev,
1123 struct pci_dev *pdev,
1124 uint32_t flags);
1125 void radeon_device_fini(struct radeon_device *rdev);
1126 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1127
1128 /* r600 blit */
1129 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1130 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1131 void r600_kms_blit_copy(struct radeon_device *rdev,
1132 u64 src_gpu_addr, u64 dst_gpu_addr,
1133 int size_bytes);
1134 /* evergreen blit */
1135 int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1136 void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1137 void evergreen_kms_blit_copy(struct radeon_device *rdev,
1138 u64 src_gpu_addr, u64 dst_gpu_addr,
1139 int size_bytes);
1140
1141 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1142 {
1143 if (reg < rdev->rmmio_size)
1144 return readl(((void __iomem *)rdev->rmmio) + reg);
1145 else {
1146 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1147 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1148 }
1149 }
1150
1151 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1152 {
1153 if (reg < rdev->rmmio_size)
1154 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1155 else {
1156 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1157 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1158 }
1159 }
1160
1161 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1162 {
1163 if (reg < rdev->rio_mem_size)
1164 return ioread32(rdev->rio_mem + reg);
1165 else {
1166 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1167 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1168 }
1169 }
1170
1171 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1172 {
1173 if (reg < rdev->rio_mem_size)
1174 iowrite32(v, rdev->rio_mem + reg);
1175 else {
1176 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1177 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1178 }
1179 }
1180
1181 /*
1182 * Cast helper
1183 */
1184 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1185
1186 /*
1187 * Registers read & write functions.
1188 */
1189 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1190 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1191 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1192 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1193 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1194 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1195 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1196 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1197 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1198 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1199 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1200 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1201 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1202 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1203 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1204 #define WREG32_P(reg, val, mask) \
1205 do { \
1206 uint32_t tmp_ = RREG32(reg); \
1207 tmp_ &= (mask); \
1208 tmp_ |= ((val) & ~(mask)); \
1209 WREG32(reg, tmp_); \
1210 } while (0)
1211 #define WREG32_PLL_P(reg, val, mask) \
1212 do { \
1213 uint32_t tmp_ = RREG32_PLL(reg); \
1214 tmp_ &= (mask); \
1215 tmp_ |= ((val) & ~(mask)); \
1216 WREG32_PLL(reg, tmp_); \
1217 } while (0)
1218 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1219 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1220 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1221
1222 /*
1223 * Indirect registers accessor
1224 */
1225 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1226 {
1227 uint32_t r;
1228
1229 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1230 r = RREG32(RADEON_PCIE_DATA);
1231 return r;
1232 }
1233
1234 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1235 {
1236 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1237 WREG32(RADEON_PCIE_DATA, (v));
1238 }
1239
1240 void r100_pll_errata_after_index(struct radeon_device *rdev);
1241
1242
1243 /*
1244 * ASICs helpers.
1245 */
1246 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1247 (rdev->pdev->device == 0x5969))
1248 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1249 (rdev->family == CHIP_RV200) || \
1250 (rdev->family == CHIP_RS100) || \
1251 (rdev->family == CHIP_RS200) || \
1252 (rdev->family == CHIP_RV250) || \
1253 (rdev->family == CHIP_RV280) || \
1254 (rdev->family == CHIP_RS300))
1255 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1256 (rdev->family == CHIP_RV350) || \
1257 (rdev->family == CHIP_R350) || \
1258 (rdev->family == CHIP_RV380) || \
1259 (rdev->family == CHIP_R420) || \
1260 (rdev->family == CHIP_R423) || \
1261 (rdev->family == CHIP_RV410) || \
1262 (rdev->family == CHIP_RS400) || \
1263 (rdev->family == CHIP_RS480))
1264 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1265 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1266 (rdev->family == CHIP_RS690) || \
1267 (rdev->family == CHIP_RS740) || \
1268 (rdev->family >= CHIP_R600))
1269 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1270 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1271 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1272
1273 /*
1274 * BIOS helpers.
1275 */
1276 #define RBIOS8(i) (rdev->bios[i])
1277 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1278 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1279
1280 int radeon_combios_init(struct radeon_device *rdev);
1281 void radeon_combios_fini(struct radeon_device *rdev);
1282 int radeon_atombios_init(struct radeon_device *rdev);
1283 void radeon_atombios_fini(struct radeon_device *rdev);
1284
1285
1286 /*
1287 * RING helpers.
1288 */
1289 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1290 {
1291 #if DRM_DEBUG_CODE
1292 if (rdev->cp.count_dw <= 0) {
1293 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1294 }
1295 #endif
1296 rdev->cp.ring[rdev->cp.wptr++] = v;
1297 rdev->cp.wptr &= rdev->cp.ptr_mask;
1298 rdev->cp.count_dw--;
1299 rdev->cp.ring_free_dw--;
1300 }
1301
1302
1303 /*
1304 * ASICs macro.
1305 */
1306 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1307 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1308 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1309 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1310 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1311 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1312 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1313 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1314 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1315 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1316 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1317 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1318 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1319 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1320 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1321 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1322 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1323 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1324 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1325 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1326 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1327 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1328 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1329 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1330 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1331 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1332 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1333 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1334 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1335 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1336 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1337 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1338 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1339 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1340 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1341 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1342 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1343 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1344 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1345 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1346 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1347
1348 /* Common functions */
1349 /* AGP */
1350 extern int radeon_gpu_reset(struct radeon_device *rdev);
1351 extern void radeon_agp_disable(struct radeon_device *rdev);
1352 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1353 extern void radeon_gart_restore(struct radeon_device *rdev);
1354 extern int radeon_modeset_init(struct radeon_device *rdev);
1355 extern void radeon_modeset_fini(struct radeon_device *rdev);
1356 extern bool radeon_card_posted(struct radeon_device *rdev);
1357 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1358 extern void radeon_update_display_priority(struct radeon_device *rdev);
1359 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1360 extern void radeon_scratch_init(struct radeon_device *rdev);
1361 extern void radeon_wb_fini(struct radeon_device *rdev);
1362 extern int radeon_wb_init(struct radeon_device *rdev);
1363 extern void radeon_wb_disable(struct radeon_device *rdev);
1364 extern void radeon_surface_init(struct radeon_device *rdev);
1365 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1366 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1367 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1368 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1369 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1370 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1371 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1372 extern int radeon_resume_kms(struct drm_device *dev);
1373 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1374
1375 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1376 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1377 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1378
1379 /* rv200,rv250,rv280 */
1380 extern void r200_set_safe_registers(struct radeon_device *rdev);
1381
1382 /* r300,r350,rv350,rv370,rv380 */
1383 extern void r300_set_reg_safe(struct radeon_device *rdev);
1384 extern void r300_mc_program(struct radeon_device *rdev);
1385 extern void r300_mc_init(struct radeon_device *rdev);
1386 extern void r300_clock_startup(struct radeon_device *rdev);
1387 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1388 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1389 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1390 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1391 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1392
1393 /* r420,r423,rv410 */
1394 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1395 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1396 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1397 extern void r420_pipes_init(struct radeon_device *rdev);
1398
1399 /* rv515 */
1400 struct rv515_mc_save {
1401 u32 d1vga_control;
1402 u32 d2vga_control;
1403 u32 vga_render_control;
1404 u32 vga_hdp_control;
1405 u32 d1crtc_control;
1406 u32 d2crtc_control;
1407 };
1408 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1409 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1410 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1411 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1412 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1413 extern void rv515_clock_startup(struct radeon_device *rdev);
1414 extern void rv515_debugfs(struct radeon_device *rdev);
1415 extern int rv515_suspend(struct radeon_device *rdev);
1416
1417 /* rs400 */
1418 extern int rs400_gart_init(struct radeon_device *rdev);
1419 extern int rs400_gart_enable(struct radeon_device *rdev);
1420 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1421 extern void rs400_gart_disable(struct radeon_device *rdev);
1422 extern void rs400_gart_fini(struct radeon_device *rdev);
1423
1424 /* rs600 */
1425 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1426 extern int rs600_irq_set(struct radeon_device *rdev);
1427 extern void rs600_irq_disable(struct radeon_device *rdev);
1428
1429 /* rs690, rs740 */
1430 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1431 struct drm_display_mode *mode1,
1432 struct drm_display_mode *mode2);
1433
1434 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1435 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1436 extern bool r600_card_posted(struct radeon_device *rdev);
1437 extern void r600_cp_stop(struct radeon_device *rdev);
1438 extern int r600_cp_start(struct radeon_device *rdev);
1439 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1440 extern int r600_cp_resume(struct radeon_device *rdev);
1441 extern void r600_cp_fini(struct radeon_device *rdev);
1442 extern int r600_count_pipe_bits(uint32_t val);
1443 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1444 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1445 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1446 extern int r600_ib_test(struct radeon_device *rdev);
1447 extern int r600_ring_test(struct radeon_device *rdev);
1448 extern void r600_scratch_init(struct radeon_device *rdev);
1449 extern int r600_blit_init(struct radeon_device *rdev);
1450 extern void r600_blit_fini(struct radeon_device *rdev);
1451 extern int r600_init_microcode(struct radeon_device *rdev);
1452 extern int r600_asic_reset(struct radeon_device *rdev);
1453 /* r600 irq */
1454 extern int r600_irq_init(struct radeon_device *rdev);
1455 extern void r600_irq_fini(struct radeon_device *rdev);
1456 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1457 extern int r600_irq_set(struct radeon_device *rdev);
1458 extern void r600_irq_suspend(struct radeon_device *rdev);
1459 extern void r600_disable_interrupts(struct radeon_device *rdev);
1460 extern void r600_rlc_stop(struct radeon_device *rdev);
1461 /* r600 audio */
1462 extern int r600_audio_init(struct radeon_device *rdev);
1463 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1464 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1465 extern int r600_audio_channels(struct radeon_device *rdev);
1466 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1467 extern int r600_audio_rate(struct radeon_device *rdev);
1468 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1469 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1470 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1471 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1472 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1473 extern void r600_audio_fini(struct radeon_device *rdev);
1474 extern void r600_hdmi_init(struct drm_encoder *encoder);
1475 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1476 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1477 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1478 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1479 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1480
1481 extern void r700_cp_stop(struct radeon_device *rdev);
1482 extern void r700_cp_fini(struct radeon_device *rdev);
1483 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1484 extern int evergreen_irq_set(struct radeon_device *rdev);
1485 extern int evergreen_blit_init(struct radeon_device *rdev);
1486 extern void evergreen_blit_fini(struct radeon_device *rdev);
1487
1488 /* radeon_acpi.c */
1489 #if defined(CONFIG_ACPI)
1490 extern int radeon_acpi_init(struct radeon_device *rdev);
1491 #else
1492 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1493 #endif
1494
1495 /* evergreen */
1496 struct evergreen_mc_save {
1497 u32 vga_control[6];
1498 u32 vga_render_control;
1499 u32 vga_hdp_control;
1500 u32 crtc_control[6];
1501 };
1502
1503 #include "radeon_object.h"
1504
1505 #endif
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