2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
43 static uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
50 static void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
57 static void radeon_register_accessor_init(struct radeon_device
*rdev
)
59 rdev
->mc_rreg
= &radeon_invalid_rreg
;
60 rdev
->mc_wreg
= &radeon_invalid_wreg
;
61 rdev
->pll_rreg
= &radeon_invalid_rreg
;
62 rdev
->pll_wreg
= &radeon_invalid_wreg
;
63 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
64 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
66 /* Don't change order as we are overridding accessor. */
67 if (rdev
->family
< CHIP_RV515
) {
68 rdev
->pcie_reg_mask
= 0xff;
70 rdev
->pcie_reg_mask
= 0x7ff;
72 /* FIXME: not sure here */
73 if (rdev
->family
<= CHIP_R580
) {
74 rdev
->pll_rreg
= &r100_pll_rreg
;
75 rdev
->pll_wreg
= &r100_pll_wreg
;
77 if (rdev
->family
>= CHIP_R420
) {
78 rdev
->mc_rreg
= &r420_mc_rreg
;
79 rdev
->mc_wreg
= &r420_mc_wreg
;
81 if (rdev
->family
>= CHIP_RV515
) {
82 rdev
->mc_rreg
= &rv515_mc_rreg
;
83 rdev
->mc_wreg
= &rv515_mc_wreg
;
85 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
86 rdev
->mc_rreg
= &rs400_mc_rreg
;
87 rdev
->mc_wreg
= &rs400_mc_wreg
;
89 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
90 rdev
->mc_rreg
= &rs690_mc_rreg
;
91 rdev
->mc_wreg
= &rs690_mc_wreg
;
93 if (rdev
->family
== CHIP_RS600
) {
94 rdev
->mc_rreg
= &rs600_mc_rreg
;
95 rdev
->mc_wreg
= &rs600_mc_wreg
;
97 if (rdev
->family
>= CHIP_R600
) {
98 rdev
->pciep_rreg
= &r600_pciep_rreg
;
99 rdev
->pciep_wreg
= &r600_pciep_wreg
;
104 /* helper to disable agp */
105 void radeon_agp_disable(struct radeon_device
*rdev
)
107 rdev
->flags
&= ~RADEON_IS_AGP
;
108 if (rdev
->family
>= CHIP_R600
) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev
->flags
|= RADEON_IS_PCIE
;
111 } else if (rdev
->family
>= CHIP_RV515
||
112 rdev
->family
== CHIP_RV380
||
113 rdev
->family
== CHIP_RV410
||
114 rdev
->family
== CHIP_R423
) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev
->flags
|= RADEON_IS_PCIE
;
117 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
118 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev
->flags
|= RADEON_IS_PCI
;
122 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
123 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
125 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
131 static struct radeon_asic r100_asic
= {
134 .suspend
= &r100_suspend
,
135 .resume
= &r100_resume
,
136 .vga_set_state
= &r100_vga_set_state
,
137 .gpu_is_lockup
= &r100_gpu_is_lockup
,
138 .asic_reset
= &r100_asic_reset
,
139 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
140 .gart_set_page
= &r100_pci_gart_set_page
,
141 .ring_start
= &r100_ring_start
,
142 .ring_test
= &r100_ring_test
,
144 [RADEON_RING_TYPE_GFX_INDEX
] = {
145 .ib_execute
= &r100_ring_ib_execute
,
146 .emit_fence
= &r100_fence_ring_emit
,
147 .emit_semaphore
= &r100_semaphore_ring_emit
,
148 .cs_parse
= &r100_cs_parse
,
152 .set
= &r100_irq_set
,
153 .process
= &r100_irq_process
,
155 .get_vblank_counter
= &r100_get_vblank_counter
,
157 .blit
= &r100_copy_blit
,
158 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
160 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
161 .copy
= &r100_copy_blit
,
162 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
164 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
165 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
166 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
167 .set_memory_clock
= NULL
,
168 .get_pcie_lanes
= NULL
,
169 .set_pcie_lanes
= NULL
,
170 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
171 .set_surface_reg
= r100_set_surface_reg
,
172 .clear_surface_reg
= r100_clear_surface_reg
,
173 .bandwidth_update
= &r100_bandwidth_update
,
175 .init
= &r100_hpd_init
,
176 .fini
= &r100_hpd_fini
,
177 .sense
= &r100_hpd_sense
,
178 .set_polarity
= &r100_hpd_set_polarity
,
180 .ioctl_wait_idle
= NULL
,
181 .gui_idle
= &r100_gui_idle
,
183 .misc
= &r100_pm_misc
,
184 .prepare
= &r100_pm_prepare
,
185 .finish
= &r100_pm_finish
,
186 .init_profile
= &r100_pm_init_profile
,
187 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
190 .pre_page_flip
= &r100_pre_page_flip
,
191 .page_flip
= &r100_page_flip
,
192 .post_page_flip
= &r100_post_page_flip
,
194 .wait_for_vblank
= &r100_wait_for_vblank
,
195 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
198 static struct radeon_asic r200_asic
= {
201 .suspend
= &r100_suspend
,
202 .resume
= &r100_resume
,
203 .vga_set_state
= &r100_vga_set_state
,
204 .gpu_is_lockup
= &r100_gpu_is_lockup
,
205 .asic_reset
= &r100_asic_reset
,
206 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
207 .gart_set_page
= &r100_pci_gart_set_page
,
208 .ring_start
= &r100_ring_start
,
209 .ring_test
= &r100_ring_test
,
211 [RADEON_RING_TYPE_GFX_INDEX
] = {
212 .ib_execute
= &r100_ring_ib_execute
,
213 .emit_fence
= &r100_fence_ring_emit
,
214 .emit_semaphore
= &r100_semaphore_ring_emit
,
215 .cs_parse
= &r100_cs_parse
,
219 .set
= &r100_irq_set
,
220 .process
= &r100_irq_process
,
222 .get_vblank_counter
= &r100_get_vblank_counter
,
224 .blit
= &r100_copy_blit
,
225 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
226 .dma
= &r200_copy_dma
,
227 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
228 .copy
= &r100_copy_blit
,
229 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
231 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
232 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
233 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
234 .set_memory_clock
= NULL
,
235 .set_pcie_lanes
= NULL
,
236 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
237 .set_surface_reg
= r100_set_surface_reg
,
238 .clear_surface_reg
= r100_clear_surface_reg
,
239 .bandwidth_update
= &r100_bandwidth_update
,
241 .init
= &r100_hpd_init
,
242 .fini
= &r100_hpd_fini
,
243 .sense
= &r100_hpd_sense
,
244 .set_polarity
= &r100_hpd_set_polarity
,
246 .ioctl_wait_idle
= NULL
,
247 .gui_idle
= &r100_gui_idle
,
249 .misc
= &r100_pm_misc
,
250 .prepare
= &r100_pm_prepare
,
251 .finish
= &r100_pm_finish
,
252 .init_profile
= &r100_pm_init_profile
,
253 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
256 .pre_page_flip
= &r100_pre_page_flip
,
257 .page_flip
= &r100_page_flip
,
258 .post_page_flip
= &r100_post_page_flip
,
260 .wait_for_vblank
= &r100_wait_for_vblank
,
261 .mc_wait_for_idle
= &r100_mc_wait_for_idle
,
264 static struct radeon_asic r300_asic
= {
267 .suspend
= &r300_suspend
,
268 .resume
= &r300_resume
,
269 .vga_set_state
= &r100_vga_set_state
,
270 .gpu_is_lockup
= &r300_gpu_is_lockup
,
271 .asic_reset
= &r300_asic_reset
,
272 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
273 .gart_set_page
= &r100_pci_gart_set_page
,
274 .ring_start
= &r300_ring_start
,
275 .ring_test
= &r100_ring_test
,
277 [RADEON_RING_TYPE_GFX_INDEX
] = {
278 .ib_execute
= &r100_ring_ib_execute
,
279 .emit_fence
= &r300_fence_ring_emit
,
280 .emit_semaphore
= &r100_semaphore_ring_emit
,
281 .cs_parse
= &r300_cs_parse
,
285 .set
= &r100_irq_set
,
286 .process
= &r100_irq_process
,
288 .get_vblank_counter
= &r100_get_vblank_counter
,
290 .blit
= &r100_copy_blit
,
291 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
292 .dma
= &r200_copy_dma
,
293 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
294 .copy
= &r100_copy_blit
,
295 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
297 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
298 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
299 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
300 .set_memory_clock
= NULL
,
301 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
302 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
303 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
304 .set_surface_reg
= r100_set_surface_reg
,
305 .clear_surface_reg
= r100_clear_surface_reg
,
306 .bandwidth_update
= &r100_bandwidth_update
,
308 .init
= &r100_hpd_init
,
309 .fini
= &r100_hpd_fini
,
310 .sense
= &r100_hpd_sense
,
311 .set_polarity
= &r100_hpd_set_polarity
,
313 .ioctl_wait_idle
= NULL
,
314 .gui_idle
= &r100_gui_idle
,
316 .misc
= &r100_pm_misc
,
317 .prepare
= &r100_pm_prepare
,
318 .finish
= &r100_pm_finish
,
319 .init_profile
= &r100_pm_init_profile
,
320 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
323 .pre_page_flip
= &r100_pre_page_flip
,
324 .page_flip
= &r100_page_flip
,
325 .post_page_flip
= &r100_post_page_flip
,
327 .wait_for_vblank
= &r100_wait_for_vblank
,
328 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
331 static struct radeon_asic r300_asic_pcie
= {
334 .suspend
= &r300_suspend
,
335 .resume
= &r300_resume
,
336 .vga_set_state
= &r100_vga_set_state
,
337 .gpu_is_lockup
= &r300_gpu_is_lockup
,
338 .asic_reset
= &r300_asic_reset
,
339 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
340 .gart_set_page
= &rv370_pcie_gart_set_page
,
341 .ring_start
= &r300_ring_start
,
342 .ring_test
= &r100_ring_test
,
344 [RADEON_RING_TYPE_GFX_INDEX
] = {
345 .ib_execute
= &r100_ring_ib_execute
,
346 .emit_fence
= &r300_fence_ring_emit
,
347 .emit_semaphore
= &r100_semaphore_ring_emit
,
348 .cs_parse
= &r300_cs_parse
,
352 .set
= &r100_irq_set
,
353 .process
= &r100_irq_process
,
355 .get_vblank_counter
= &r100_get_vblank_counter
,
357 .blit
= &r100_copy_blit
,
358 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
359 .dma
= &r200_copy_dma
,
360 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
361 .copy
= &r100_copy_blit
,
362 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
364 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
365 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
366 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
367 .set_memory_clock
= NULL
,
368 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
369 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
370 .set_surface_reg
= r100_set_surface_reg
,
371 .clear_surface_reg
= r100_clear_surface_reg
,
372 .bandwidth_update
= &r100_bandwidth_update
,
374 .init
= &r100_hpd_init
,
375 .fini
= &r100_hpd_fini
,
376 .sense
= &r100_hpd_sense
,
377 .set_polarity
= &r100_hpd_set_polarity
,
379 .ioctl_wait_idle
= NULL
,
380 .gui_idle
= &r100_gui_idle
,
382 .misc
= &r100_pm_misc
,
383 .prepare
= &r100_pm_prepare
,
384 .finish
= &r100_pm_finish
,
385 .init_profile
= &r100_pm_init_profile
,
386 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
389 .pre_page_flip
= &r100_pre_page_flip
,
390 .page_flip
= &r100_page_flip
,
391 .post_page_flip
= &r100_post_page_flip
,
393 .wait_for_vblank
= &r100_wait_for_vblank
,
394 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
397 static struct radeon_asic r420_asic
= {
400 .suspend
= &r420_suspend
,
401 .resume
= &r420_resume
,
402 .vga_set_state
= &r100_vga_set_state
,
403 .gpu_is_lockup
= &r300_gpu_is_lockup
,
404 .asic_reset
= &r300_asic_reset
,
405 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
406 .gart_set_page
= &rv370_pcie_gart_set_page
,
407 .ring_start
= &r300_ring_start
,
408 .ring_test
= &r100_ring_test
,
410 [RADEON_RING_TYPE_GFX_INDEX
] = {
411 .ib_execute
= &r100_ring_ib_execute
,
412 .emit_fence
= &r300_fence_ring_emit
,
413 .emit_semaphore
= &r100_semaphore_ring_emit
,
414 .cs_parse
= &r300_cs_parse
,
418 .set
= &r100_irq_set
,
419 .process
= &r100_irq_process
,
421 .get_vblank_counter
= &r100_get_vblank_counter
,
423 .blit
= &r100_copy_blit
,
424 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
425 .dma
= &r200_copy_dma
,
426 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
427 .copy
= &r100_copy_blit
,
428 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
430 .get_engine_clock
= &radeon_atom_get_engine_clock
,
431 .set_engine_clock
= &radeon_atom_set_engine_clock
,
432 .get_memory_clock
= &radeon_atom_get_memory_clock
,
433 .set_memory_clock
= &radeon_atom_set_memory_clock
,
434 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
435 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
436 .set_clock_gating
= &radeon_atom_set_clock_gating
,
437 .set_surface_reg
= r100_set_surface_reg
,
438 .clear_surface_reg
= r100_clear_surface_reg
,
439 .bandwidth_update
= &r100_bandwidth_update
,
441 .init
= &r100_hpd_init
,
442 .fini
= &r100_hpd_fini
,
443 .sense
= &r100_hpd_sense
,
444 .set_polarity
= &r100_hpd_set_polarity
,
446 .ioctl_wait_idle
= NULL
,
447 .gui_idle
= &r100_gui_idle
,
449 .misc
= &r100_pm_misc
,
450 .prepare
= &r100_pm_prepare
,
451 .finish
= &r100_pm_finish
,
452 .init_profile
= &r420_pm_init_profile
,
453 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
456 .pre_page_flip
= &r100_pre_page_flip
,
457 .page_flip
= &r100_page_flip
,
458 .post_page_flip
= &r100_post_page_flip
,
460 .wait_for_vblank
= &r100_wait_for_vblank
,
461 .mc_wait_for_idle
= &r300_mc_wait_for_idle
,
464 static struct radeon_asic rs400_asic
= {
467 .suspend
= &rs400_suspend
,
468 .resume
= &rs400_resume
,
469 .vga_set_state
= &r100_vga_set_state
,
470 .gpu_is_lockup
= &r300_gpu_is_lockup
,
471 .asic_reset
= &r300_asic_reset
,
472 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
473 .gart_set_page
= &rs400_gart_set_page
,
474 .ring_start
= &r300_ring_start
,
475 .ring_test
= &r100_ring_test
,
477 [RADEON_RING_TYPE_GFX_INDEX
] = {
478 .ib_execute
= &r100_ring_ib_execute
,
479 .emit_fence
= &r300_fence_ring_emit
,
480 .emit_semaphore
= &r100_semaphore_ring_emit
,
481 .cs_parse
= &r300_cs_parse
,
485 .set
= &r100_irq_set
,
486 .process
= &r100_irq_process
,
488 .get_vblank_counter
= &r100_get_vblank_counter
,
490 .blit
= &r100_copy_blit
,
491 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
492 .dma
= &r200_copy_dma
,
493 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
494 .copy
= &r100_copy_blit
,
495 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
497 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
498 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
499 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
500 .set_memory_clock
= NULL
,
501 .get_pcie_lanes
= NULL
,
502 .set_pcie_lanes
= NULL
,
503 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
504 .set_surface_reg
= r100_set_surface_reg
,
505 .clear_surface_reg
= r100_clear_surface_reg
,
506 .bandwidth_update
= &r100_bandwidth_update
,
508 .init
= &r100_hpd_init
,
509 .fini
= &r100_hpd_fini
,
510 .sense
= &r100_hpd_sense
,
511 .set_polarity
= &r100_hpd_set_polarity
,
513 .ioctl_wait_idle
= NULL
,
514 .gui_idle
= &r100_gui_idle
,
516 .misc
= &r100_pm_misc
,
517 .prepare
= &r100_pm_prepare
,
518 .finish
= &r100_pm_finish
,
519 .init_profile
= &r100_pm_init_profile
,
520 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
523 .pre_page_flip
= &r100_pre_page_flip
,
524 .page_flip
= &r100_page_flip
,
525 .post_page_flip
= &r100_post_page_flip
,
527 .wait_for_vblank
= &r100_wait_for_vblank
,
528 .mc_wait_for_idle
= &rs400_mc_wait_for_idle
,
531 static struct radeon_asic rs600_asic
= {
534 .suspend
= &rs600_suspend
,
535 .resume
= &rs600_resume
,
536 .vga_set_state
= &r100_vga_set_state
,
537 .gpu_is_lockup
= &r300_gpu_is_lockup
,
538 .asic_reset
= &rs600_asic_reset
,
539 .gart_tlb_flush
= &rs600_gart_tlb_flush
,
540 .gart_set_page
= &rs600_gart_set_page
,
541 .ring_start
= &r300_ring_start
,
542 .ring_test
= &r100_ring_test
,
544 [RADEON_RING_TYPE_GFX_INDEX
] = {
545 .ib_execute
= &r100_ring_ib_execute
,
546 .emit_fence
= &r300_fence_ring_emit
,
547 .emit_semaphore
= &r100_semaphore_ring_emit
,
548 .cs_parse
= &r300_cs_parse
,
552 .set
= &rs600_irq_set
,
553 .process
= &rs600_irq_process
,
555 .get_vblank_counter
= &rs600_get_vblank_counter
,
557 .blit
= &r100_copy_blit
,
558 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
559 .dma
= &r200_copy_dma
,
560 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
561 .copy
= &r100_copy_blit
,
562 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
564 .get_engine_clock
= &radeon_atom_get_engine_clock
,
565 .set_engine_clock
= &radeon_atom_set_engine_clock
,
566 .get_memory_clock
= &radeon_atom_get_memory_clock
,
567 .set_memory_clock
= &radeon_atom_set_memory_clock
,
568 .get_pcie_lanes
= NULL
,
569 .set_pcie_lanes
= NULL
,
570 .set_clock_gating
= &radeon_atom_set_clock_gating
,
571 .set_surface_reg
= r100_set_surface_reg
,
572 .clear_surface_reg
= r100_clear_surface_reg
,
573 .bandwidth_update
= &rs600_bandwidth_update
,
575 .init
= &rs600_hpd_init
,
576 .fini
= &rs600_hpd_fini
,
577 .sense
= &rs600_hpd_sense
,
578 .set_polarity
= &rs600_hpd_set_polarity
,
580 .ioctl_wait_idle
= NULL
,
581 .gui_idle
= &r100_gui_idle
,
583 .misc
= &rs600_pm_misc
,
584 .prepare
= &rs600_pm_prepare
,
585 .finish
= &rs600_pm_finish
,
586 .init_profile
= &r420_pm_init_profile
,
587 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
590 .pre_page_flip
= &rs600_pre_page_flip
,
591 .page_flip
= &rs600_page_flip
,
592 .post_page_flip
= &rs600_post_page_flip
,
594 .wait_for_vblank
= &avivo_wait_for_vblank
,
595 .mc_wait_for_idle
= &rs600_mc_wait_for_idle
,
598 static struct radeon_asic rs690_asic
= {
601 .suspend
= &rs690_suspend
,
602 .resume
= &rs690_resume
,
603 .vga_set_state
= &r100_vga_set_state
,
604 .gpu_is_lockup
= &r300_gpu_is_lockup
,
605 .asic_reset
= &rs600_asic_reset
,
606 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
607 .gart_set_page
= &rs400_gart_set_page
,
608 .ring_start
= &r300_ring_start
,
609 .ring_test
= &r100_ring_test
,
611 [RADEON_RING_TYPE_GFX_INDEX
] = {
612 .ib_execute
= &r100_ring_ib_execute
,
613 .emit_fence
= &r300_fence_ring_emit
,
614 .emit_semaphore
= &r100_semaphore_ring_emit
,
615 .cs_parse
= &r300_cs_parse
,
619 .set
= &rs600_irq_set
,
620 .process
= &rs600_irq_process
,
622 .get_vblank_counter
= &rs600_get_vblank_counter
,
624 .blit
= &r100_copy_blit
,
625 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
626 .dma
= &r200_copy_dma
,
627 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
628 .copy
= &r200_copy_dma
,
629 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
631 .get_engine_clock
= &radeon_atom_get_engine_clock
,
632 .set_engine_clock
= &radeon_atom_set_engine_clock
,
633 .get_memory_clock
= &radeon_atom_get_memory_clock
,
634 .set_memory_clock
= &radeon_atom_set_memory_clock
,
635 .get_pcie_lanes
= NULL
,
636 .set_pcie_lanes
= NULL
,
637 .set_clock_gating
= &radeon_atom_set_clock_gating
,
638 .set_surface_reg
= r100_set_surface_reg
,
639 .clear_surface_reg
= r100_clear_surface_reg
,
640 .bandwidth_update
= &rs690_bandwidth_update
,
642 .init
= &rs600_hpd_init
,
643 .fini
= &rs600_hpd_fini
,
644 .sense
= &rs600_hpd_sense
,
645 .set_polarity
= &rs600_hpd_set_polarity
,
647 .ioctl_wait_idle
= NULL
,
648 .gui_idle
= &r100_gui_idle
,
650 .misc
= &rs600_pm_misc
,
651 .prepare
= &rs600_pm_prepare
,
652 .finish
= &rs600_pm_finish
,
653 .init_profile
= &r420_pm_init_profile
,
654 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
657 .pre_page_flip
= &rs600_pre_page_flip
,
658 .page_flip
= &rs600_page_flip
,
659 .post_page_flip
= &rs600_post_page_flip
,
661 .wait_for_vblank
= &avivo_wait_for_vblank
,
662 .mc_wait_for_idle
= &rs690_mc_wait_for_idle
,
665 static struct radeon_asic rv515_asic
= {
668 .suspend
= &rv515_suspend
,
669 .resume
= &rv515_resume
,
670 .vga_set_state
= &r100_vga_set_state
,
671 .gpu_is_lockup
= &r300_gpu_is_lockup
,
672 .asic_reset
= &rs600_asic_reset
,
673 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
674 .gart_set_page
= &rv370_pcie_gart_set_page
,
675 .ring_start
= &rv515_ring_start
,
676 .ring_test
= &r100_ring_test
,
678 [RADEON_RING_TYPE_GFX_INDEX
] = {
679 .ib_execute
= &r100_ring_ib_execute
,
680 .emit_fence
= &r300_fence_ring_emit
,
681 .emit_semaphore
= &r100_semaphore_ring_emit
,
682 .cs_parse
= &r300_cs_parse
,
686 .set
= &rs600_irq_set
,
687 .process
= &rs600_irq_process
,
689 .get_vblank_counter
= &rs600_get_vblank_counter
,
691 .blit
= &r100_copy_blit
,
692 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
693 .dma
= &r200_copy_dma
,
694 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
695 .copy
= &r100_copy_blit
,
696 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
698 .get_engine_clock
= &radeon_atom_get_engine_clock
,
699 .set_engine_clock
= &radeon_atom_set_engine_clock
,
700 .get_memory_clock
= &radeon_atom_get_memory_clock
,
701 .set_memory_clock
= &radeon_atom_set_memory_clock
,
702 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
703 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
704 .set_clock_gating
= &radeon_atom_set_clock_gating
,
705 .set_surface_reg
= r100_set_surface_reg
,
706 .clear_surface_reg
= r100_clear_surface_reg
,
707 .bandwidth_update
= &rv515_bandwidth_update
,
709 .init
= &rs600_hpd_init
,
710 .fini
= &rs600_hpd_fini
,
711 .sense
= &rs600_hpd_sense
,
712 .set_polarity
= &rs600_hpd_set_polarity
,
714 .ioctl_wait_idle
= NULL
,
715 .gui_idle
= &r100_gui_idle
,
717 .misc
= &rs600_pm_misc
,
718 .prepare
= &rs600_pm_prepare
,
719 .finish
= &rs600_pm_finish
,
720 .init_profile
= &r420_pm_init_profile
,
721 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
724 .pre_page_flip
= &rs600_pre_page_flip
,
725 .page_flip
= &rs600_page_flip
,
726 .post_page_flip
= &rs600_post_page_flip
,
728 .wait_for_vblank
= &avivo_wait_for_vblank
,
729 .mc_wait_for_idle
= &rv515_mc_wait_for_idle
,
732 static struct radeon_asic r520_asic
= {
735 .suspend
= &rv515_suspend
,
736 .resume
= &r520_resume
,
737 .vga_set_state
= &r100_vga_set_state
,
738 .gpu_is_lockup
= &r300_gpu_is_lockup
,
739 .asic_reset
= &rs600_asic_reset
,
740 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
741 .gart_set_page
= &rv370_pcie_gart_set_page
,
742 .ring_start
= &rv515_ring_start
,
743 .ring_test
= &r100_ring_test
,
745 [RADEON_RING_TYPE_GFX_INDEX
] = {
746 .ib_execute
= &r100_ring_ib_execute
,
747 .emit_fence
= &r300_fence_ring_emit
,
748 .emit_semaphore
= &r100_semaphore_ring_emit
,
749 .cs_parse
= &r300_cs_parse
,
753 .set
= &rs600_irq_set
,
754 .process
= &rs600_irq_process
,
756 .get_vblank_counter
= &rs600_get_vblank_counter
,
758 .blit
= &r100_copy_blit
,
759 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
760 .dma
= &r200_copy_dma
,
761 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
762 .copy
= &r100_copy_blit
,
763 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
765 .get_engine_clock
= &radeon_atom_get_engine_clock
,
766 .set_engine_clock
= &radeon_atom_set_engine_clock
,
767 .get_memory_clock
= &radeon_atom_get_memory_clock
,
768 .set_memory_clock
= &radeon_atom_set_memory_clock
,
769 .get_pcie_lanes
= &rv370_get_pcie_lanes
,
770 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
771 .set_clock_gating
= &radeon_atom_set_clock_gating
,
772 .set_surface_reg
= r100_set_surface_reg
,
773 .clear_surface_reg
= r100_clear_surface_reg
,
774 .bandwidth_update
= &rv515_bandwidth_update
,
776 .init
= &rs600_hpd_init
,
777 .fini
= &rs600_hpd_fini
,
778 .sense
= &rs600_hpd_sense
,
779 .set_polarity
= &rs600_hpd_set_polarity
,
781 .ioctl_wait_idle
= NULL
,
782 .gui_idle
= &r100_gui_idle
,
784 .misc
= &rs600_pm_misc
,
785 .prepare
= &rs600_pm_prepare
,
786 .finish
= &rs600_pm_finish
,
787 .init_profile
= &r420_pm_init_profile
,
788 .get_dynpm_state
= &r100_pm_get_dynpm_state
,
791 .pre_page_flip
= &rs600_pre_page_flip
,
792 .page_flip
= &rs600_page_flip
,
793 .post_page_flip
= &rs600_post_page_flip
,
795 .wait_for_vblank
= &avivo_wait_for_vblank
,
796 .mc_wait_for_idle
= &r520_mc_wait_for_idle
,
799 static struct radeon_asic r600_asic
= {
802 .suspend
= &r600_suspend
,
803 .resume
= &r600_resume
,
804 .vga_set_state
= &r600_vga_set_state
,
805 .gpu_is_lockup
= &r600_gpu_is_lockup
,
806 .asic_reset
= &r600_asic_reset
,
807 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
808 .gart_set_page
= &rs600_gart_set_page
,
809 .ring_test
= &r600_ring_test
,
811 [RADEON_RING_TYPE_GFX_INDEX
] = {
812 .ib_execute
= &r600_ring_ib_execute
,
813 .emit_fence
= &r600_fence_ring_emit
,
814 .emit_semaphore
= &r600_semaphore_ring_emit
,
815 .cs_parse
= &r600_cs_parse
,
819 .set
= &r600_irq_set
,
820 .process
= &r600_irq_process
,
822 .get_vblank_counter
= &rs600_get_vblank_counter
,
824 .blit
= &r600_copy_blit
,
825 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
827 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
828 .copy
= &r600_copy_blit
,
829 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
831 .get_engine_clock
= &radeon_atom_get_engine_clock
,
832 .set_engine_clock
= &radeon_atom_set_engine_clock
,
833 .get_memory_clock
= &radeon_atom_get_memory_clock
,
834 .set_memory_clock
= &radeon_atom_set_memory_clock
,
835 .get_pcie_lanes
= &r600_get_pcie_lanes
,
836 .set_pcie_lanes
= &r600_set_pcie_lanes
,
837 .set_clock_gating
= NULL
,
838 .set_surface_reg
= r600_set_surface_reg
,
839 .clear_surface_reg
= r600_clear_surface_reg
,
840 .bandwidth_update
= &rv515_bandwidth_update
,
842 .init
= &r600_hpd_init
,
843 .fini
= &r600_hpd_fini
,
844 .sense
= &r600_hpd_sense
,
845 .set_polarity
= &r600_hpd_set_polarity
,
847 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
848 .gui_idle
= &r600_gui_idle
,
850 .misc
= &r600_pm_misc
,
851 .prepare
= &rs600_pm_prepare
,
852 .finish
= &rs600_pm_finish
,
853 .init_profile
= &r600_pm_init_profile
,
854 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
857 .pre_page_flip
= &rs600_pre_page_flip
,
858 .page_flip
= &rs600_page_flip
,
859 .post_page_flip
= &rs600_post_page_flip
,
861 .wait_for_vblank
= &avivo_wait_for_vblank
,
862 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
865 static struct radeon_asic rs780_asic
= {
868 .suspend
= &r600_suspend
,
869 .resume
= &r600_resume
,
870 .gpu_is_lockup
= &r600_gpu_is_lockup
,
871 .vga_set_state
= &r600_vga_set_state
,
872 .asic_reset
= &r600_asic_reset
,
873 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
874 .gart_set_page
= &rs600_gart_set_page
,
875 .ring_test
= &r600_ring_test
,
877 [RADEON_RING_TYPE_GFX_INDEX
] = {
878 .ib_execute
= &r600_ring_ib_execute
,
879 .emit_fence
= &r600_fence_ring_emit
,
880 .emit_semaphore
= &r600_semaphore_ring_emit
,
881 .cs_parse
= &r600_cs_parse
,
885 .set
= &r600_irq_set
,
886 .process
= &r600_irq_process
,
888 .get_vblank_counter
= &rs600_get_vblank_counter
,
890 .blit
= &r600_copy_blit
,
891 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
893 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
894 .copy
= &r600_copy_blit
,
895 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
897 .get_engine_clock
= &radeon_atom_get_engine_clock
,
898 .set_engine_clock
= &radeon_atom_set_engine_clock
,
899 .get_memory_clock
= NULL
,
900 .set_memory_clock
= NULL
,
901 .get_pcie_lanes
= NULL
,
902 .set_pcie_lanes
= NULL
,
903 .set_clock_gating
= NULL
,
904 .set_surface_reg
= r600_set_surface_reg
,
905 .clear_surface_reg
= r600_clear_surface_reg
,
906 .bandwidth_update
= &rs690_bandwidth_update
,
908 .init
= &r600_hpd_init
,
909 .fini
= &r600_hpd_fini
,
910 .sense
= &r600_hpd_sense
,
911 .set_polarity
= &r600_hpd_set_polarity
,
913 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
914 .gui_idle
= &r600_gui_idle
,
916 .misc
= &r600_pm_misc
,
917 .prepare
= &rs600_pm_prepare
,
918 .finish
= &rs600_pm_finish
,
919 .init_profile
= &rs780_pm_init_profile
,
920 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
923 .pre_page_flip
= &rs600_pre_page_flip
,
924 .page_flip
= &rs600_page_flip
,
925 .post_page_flip
= &rs600_post_page_flip
,
927 .wait_for_vblank
= &avivo_wait_for_vblank
,
928 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
931 static struct radeon_asic rv770_asic
= {
934 .suspend
= &rv770_suspend
,
935 .resume
= &rv770_resume
,
936 .asic_reset
= &r600_asic_reset
,
937 .gpu_is_lockup
= &r600_gpu_is_lockup
,
938 .vga_set_state
= &r600_vga_set_state
,
939 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
940 .gart_set_page
= &rs600_gart_set_page
,
941 .ring_test
= &r600_ring_test
,
943 [RADEON_RING_TYPE_GFX_INDEX
] = {
944 .ib_execute
= &r600_ring_ib_execute
,
945 .emit_fence
= &r600_fence_ring_emit
,
946 .emit_semaphore
= &r600_semaphore_ring_emit
,
947 .cs_parse
= &r600_cs_parse
,
951 .set
= &r600_irq_set
,
952 .process
= &r600_irq_process
,
954 .get_vblank_counter
= &rs600_get_vblank_counter
,
956 .blit
= &r600_copy_blit
,
957 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
959 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
960 .copy
= &r600_copy_blit
,
961 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
963 .get_engine_clock
= &radeon_atom_get_engine_clock
,
964 .set_engine_clock
= &radeon_atom_set_engine_clock
,
965 .get_memory_clock
= &radeon_atom_get_memory_clock
,
966 .set_memory_clock
= &radeon_atom_set_memory_clock
,
967 .get_pcie_lanes
= &r600_get_pcie_lanes
,
968 .set_pcie_lanes
= &r600_set_pcie_lanes
,
969 .set_clock_gating
= &radeon_atom_set_clock_gating
,
970 .set_surface_reg
= r600_set_surface_reg
,
971 .clear_surface_reg
= r600_clear_surface_reg
,
972 .bandwidth_update
= &rv515_bandwidth_update
,
974 .init
= &r600_hpd_init
,
975 .fini
= &r600_hpd_fini
,
976 .sense
= &r600_hpd_sense
,
977 .set_polarity
= &r600_hpd_set_polarity
,
979 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
980 .gui_idle
= &r600_gui_idle
,
982 .misc
= &rv770_pm_misc
,
983 .prepare
= &rs600_pm_prepare
,
984 .finish
= &rs600_pm_finish
,
985 .init_profile
= &r600_pm_init_profile
,
986 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
989 .pre_page_flip
= &rs600_pre_page_flip
,
990 .page_flip
= &rv770_page_flip
,
991 .post_page_flip
= &rs600_post_page_flip
,
993 .wait_for_vblank
= &avivo_wait_for_vblank
,
994 .mc_wait_for_idle
= &r600_mc_wait_for_idle
,
997 static struct radeon_asic evergreen_asic
= {
998 .init
= &evergreen_init
,
999 .fini
= &evergreen_fini
,
1000 .suspend
= &evergreen_suspend
,
1001 .resume
= &evergreen_resume
,
1002 .gpu_is_lockup
= &evergreen_gpu_is_lockup
,
1003 .asic_reset
= &evergreen_asic_reset
,
1004 .vga_set_state
= &r600_vga_set_state
,
1005 .gart_tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1006 .gart_set_page
= &rs600_gart_set_page
,
1007 .ring_test
= &r600_ring_test
,
1009 [RADEON_RING_TYPE_GFX_INDEX
] = {
1010 .ib_execute
= &evergreen_ring_ib_execute
,
1011 .emit_fence
= &r600_fence_ring_emit
,
1012 .emit_semaphore
= &r600_semaphore_ring_emit
,
1013 .cs_parse
= &evergreen_cs_parse
,
1017 .set
= &evergreen_irq_set
,
1018 .process
= &evergreen_irq_process
,
1020 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1022 .blit
= &r600_copy_blit
,
1023 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1025 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1026 .copy
= &r600_copy_blit
,
1027 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1029 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1030 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1031 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1032 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1033 .get_pcie_lanes
= &r600_get_pcie_lanes
,
1034 .set_pcie_lanes
= &r600_set_pcie_lanes
,
1035 .set_clock_gating
= NULL
,
1036 .set_surface_reg
= r600_set_surface_reg
,
1037 .clear_surface_reg
= r600_clear_surface_reg
,
1038 .bandwidth_update
= &evergreen_bandwidth_update
,
1040 .init
= &evergreen_hpd_init
,
1041 .fini
= &evergreen_hpd_fini
,
1042 .sense
= &evergreen_hpd_sense
,
1043 .set_polarity
= &evergreen_hpd_set_polarity
,
1045 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1046 .gui_idle
= &r600_gui_idle
,
1048 .misc
= &evergreen_pm_misc
,
1049 .prepare
= &evergreen_pm_prepare
,
1050 .finish
= &evergreen_pm_finish
,
1051 .init_profile
= &r600_pm_init_profile
,
1052 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1055 .pre_page_flip
= &evergreen_pre_page_flip
,
1056 .page_flip
= &evergreen_page_flip
,
1057 .post_page_flip
= &evergreen_post_page_flip
,
1059 .wait_for_vblank
= &dce4_wait_for_vblank
,
1060 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1063 static struct radeon_asic sumo_asic
= {
1064 .init
= &evergreen_init
,
1065 .fini
= &evergreen_fini
,
1066 .suspend
= &evergreen_suspend
,
1067 .resume
= &evergreen_resume
,
1068 .gpu_is_lockup
= &evergreen_gpu_is_lockup
,
1069 .asic_reset
= &evergreen_asic_reset
,
1070 .vga_set_state
= &r600_vga_set_state
,
1071 .gart_tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1072 .gart_set_page
= &rs600_gart_set_page
,
1073 .ring_test
= &r600_ring_test
,
1075 [RADEON_RING_TYPE_GFX_INDEX
] = {
1076 .ib_execute
= &evergreen_ring_ib_execute
,
1077 .emit_fence
= &r600_fence_ring_emit
,
1078 .emit_semaphore
= &r600_semaphore_ring_emit
,
1079 .cs_parse
= &evergreen_cs_parse
,
1083 .set
= &evergreen_irq_set
,
1084 .process
= &evergreen_irq_process
,
1086 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1088 .blit
= &r600_copy_blit
,
1089 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1091 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1092 .copy
= &r600_copy_blit
,
1093 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1095 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1096 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1097 .get_memory_clock
= NULL
,
1098 .set_memory_clock
= NULL
,
1099 .get_pcie_lanes
= NULL
,
1100 .set_pcie_lanes
= NULL
,
1101 .set_clock_gating
= NULL
,
1102 .set_surface_reg
= r600_set_surface_reg
,
1103 .clear_surface_reg
= r600_clear_surface_reg
,
1104 .bandwidth_update
= &evergreen_bandwidth_update
,
1106 .init
= &evergreen_hpd_init
,
1107 .fini
= &evergreen_hpd_fini
,
1108 .sense
= &evergreen_hpd_sense
,
1109 .set_polarity
= &evergreen_hpd_set_polarity
,
1111 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1112 .gui_idle
= &r600_gui_idle
,
1114 .misc
= &evergreen_pm_misc
,
1115 .prepare
= &evergreen_pm_prepare
,
1116 .finish
= &evergreen_pm_finish
,
1117 .init_profile
= &sumo_pm_init_profile
,
1118 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1121 .pre_page_flip
= &evergreen_pre_page_flip
,
1122 .page_flip
= &evergreen_page_flip
,
1123 .post_page_flip
= &evergreen_post_page_flip
,
1125 .wait_for_vblank
= &dce4_wait_for_vblank
,
1126 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1129 static struct radeon_asic btc_asic
= {
1130 .init
= &evergreen_init
,
1131 .fini
= &evergreen_fini
,
1132 .suspend
= &evergreen_suspend
,
1133 .resume
= &evergreen_resume
,
1134 .gpu_is_lockup
= &evergreen_gpu_is_lockup
,
1135 .asic_reset
= &evergreen_asic_reset
,
1136 .vga_set_state
= &r600_vga_set_state
,
1137 .gart_tlb_flush
= &evergreen_pcie_gart_tlb_flush
,
1138 .gart_set_page
= &rs600_gart_set_page
,
1139 .ring_test
= &r600_ring_test
,
1141 [RADEON_RING_TYPE_GFX_INDEX
] = {
1142 .ib_execute
= &evergreen_ring_ib_execute
,
1143 .emit_fence
= &r600_fence_ring_emit
,
1144 .emit_semaphore
= &r600_semaphore_ring_emit
,
1145 .cs_parse
= &evergreen_cs_parse
,
1149 .set
= &evergreen_irq_set
,
1150 .process
= &evergreen_irq_process
,
1152 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1154 .blit
= &r600_copy_blit
,
1155 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1157 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1158 .copy
= &r600_copy_blit
,
1159 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1161 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1162 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1163 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1164 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1165 .get_pcie_lanes
= NULL
,
1166 .set_pcie_lanes
= NULL
,
1167 .set_clock_gating
= NULL
,
1168 .set_surface_reg
= r600_set_surface_reg
,
1169 .clear_surface_reg
= r600_clear_surface_reg
,
1170 .bandwidth_update
= &evergreen_bandwidth_update
,
1172 .init
= &evergreen_hpd_init
,
1173 .fini
= &evergreen_hpd_fini
,
1174 .sense
= &evergreen_hpd_sense
,
1175 .set_polarity
= &evergreen_hpd_set_polarity
,
1177 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1178 .gui_idle
= &r600_gui_idle
,
1180 .misc
= &evergreen_pm_misc
,
1181 .prepare
= &evergreen_pm_prepare
,
1182 .finish
= &evergreen_pm_finish
,
1183 .init_profile
= &r600_pm_init_profile
,
1184 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1187 .pre_page_flip
= &evergreen_pre_page_flip
,
1188 .page_flip
= &evergreen_page_flip
,
1189 .post_page_flip
= &evergreen_post_page_flip
,
1191 .wait_for_vblank
= &dce4_wait_for_vblank
,
1192 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1195 static const struct radeon_vm_funcs cayman_vm_funcs
= {
1196 .init
= &cayman_vm_init
,
1197 .fini
= &cayman_vm_fini
,
1198 .bind
= &cayman_vm_bind
,
1199 .unbind
= &cayman_vm_unbind
,
1200 .tlb_flush
= &cayman_vm_tlb_flush
,
1201 .page_flags
= &cayman_vm_page_flags
,
1202 .set_page
= &cayman_vm_set_page
,
1205 static struct radeon_asic cayman_asic
= {
1206 .init
= &cayman_init
,
1207 .fini
= &cayman_fini
,
1208 .suspend
= &cayman_suspend
,
1209 .resume
= &cayman_resume
,
1210 .gpu_is_lockup
= &cayman_gpu_is_lockup
,
1211 .asic_reset
= &cayman_asic_reset
,
1212 .vga_set_state
= &r600_vga_set_state
,
1213 .gart_tlb_flush
= &cayman_pcie_gart_tlb_flush
,
1214 .gart_set_page
= &rs600_gart_set_page
,
1215 .ring_test
= &r600_ring_test
,
1217 [RADEON_RING_TYPE_GFX_INDEX
] = {
1218 .ib_execute
= &cayman_ring_ib_execute
,
1219 .ib_parse
= &evergreen_ib_parse
,
1220 .emit_fence
= &cayman_fence_ring_emit
,
1221 .emit_semaphore
= &r600_semaphore_ring_emit
,
1222 .cs_parse
= &evergreen_cs_parse
,
1224 [CAYMAN_RING_TYPE_CP1_INDEX
] = {
1225 .ib_execute
= &cayman_ring_ib_execute
,
1226 .ib_parse
= &evergreen_ib_parse
,
1227 .emit_fence
= &cayman_fence_ring_emit
,
1228 .emit_semaphore
= &r600_semaphore_ring_emit
,
1229 .cs_parse
= &evergreen_cs_parse
,
1231 [CAYMAN_RING_TYPE_CP2_INDEX
] = {
1232 .ib_execute
= &cayman_ring_ib_execute
,
1233 .ib_parse
= &evergreen_ib_parse
,
1234 .emit_fence
= &cayman_fence_ring_emit
,
1235 .emit_semaphore
= &r600_semaphore_ring_emit
,
1236 .cs_parse
= &evergreen_cs_parse
,
1240 .set
= &evergreen_irq_set
,
1241 .process
= &evergreen_irq_process
,
1243 .get_vblank_counter
= &evergreen_get_vblank_counter
,
1245 .blit
= &r600_copy_blit
,
1246 .blit_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1248 .dma_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1249 .copy
= &r600_copy_blit
,
1250 .copy_ring_index
= RADEON_RING_TYPE_GFX_INDEX
,
1252 .get_engine_clock
= &radeon_atom_get_engine_clock
,
1253 .set_engine_clock
= &radeon_atom_set_engine_clock
,
1254 .get_memory_clock
= &radeon_atom_get_memory_clock
,
1255 .set_memory_clock
= &radeon_atom_set_memory_clock
,
1256 .get_pcie_lanes
= NULL
,
1257 .set_pcie_lanes
= NULL
,
1258 .set_clock_gating
= NULL
,
1259 .set_surface_reg
= r600_set_surface_reg
,
1260 .clear_surface_reg
= r600_clear_surface_reg
,
1261 .bandwidth_update
= &evergreen_bandwidth_update
,
1263 .init
= &evergreen_hpd_init
,
1264 .fini
= &evergreen_hpd_fini
,
1265 .sense
= &evergreen_hpd_sense
,
1266 .set_polarity
= &evergreen_hpd_set_polarity
,
1268 .ioctl_wait_idle
= r600_ioctl_wait_idle
,
1269 .gui_idle
= &r600_gui_idle
,
1271 .misc
= &evergreen_pm_misc
,
1272 .prepare
= &evergreen_pm_prepare
,
1273 .finish
= &evergreen_pm_finish
,
1274 .init_profile
= &r600_pm_init_profile
,
1275 .get_dynpm_state
= &r600_pm_get_dynpm_state
,
1278 .pre_page_flip
= &evergreen_pre_page_flip
,
1279 .page_flip
= &evergreen_page_flip
,
1280 .post_page_flip
= &evergreen_post_page_flip
,
1282 .wait_for_vblank
= &dce4_wait_for_vblank
,
1283 .mc_wait_for_idle
= &evergreen_mc_wait_for_idle
,
1286 int radeon_asic_init(struct radeon_device
*rdev
)
1288 radeon_register_accessor_init(rdev
);
1290 /* set the number of crtcs */
1291 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
1296 switch (rdev
->family
) {
1302 rdev
->asic
= &r100_asic
;
1308 rdev
->asic
= &r200_asic
;
1314 if (rdev
->flags
& RADEON_IS_PCIE
)
1315 rdev
->asic
= &r300_asic_pcie
;
1317 rdev
->asic
= &r300_asic
;
1322 rdev
->asic
= &r420_asic
;
1324 if (rdev
->bios
== NULL
) {
1325 rdev
->asic
->get_engine_clock
= &radeon_legacy_get_engine_clock
;
1326 rdev
->asic
->set_engine_clock
= &radeon_legacy_set_engine_clock
;
1327 rdev
->asic
->get_memory_clock
= &radeon_legacy_get_memory_clock
;
1328 rdev
->asic
->set_memory_clock
= NULL
;
1333 rdev
->asic
= &rs400_asic
;
1336 rdev
->asic
= &rs600_asic
;
1340 rdev
->asic
= &rs690_asic
;
1343 rdev
->asic
= &rv515_asic
;
1350 rdev
->asic
= &r520_asic
;
1358 rdev
->asic
= &r600_asic
;
1362 rdev
->asic
= &rs780_asic
;
1368 rdev
->asic
= &rv770_asic
;
1376 if (rdev
->family
== CHIP_CEDAR
)
1380 rdev
->asic
= &evergreen_asic
;
1385 rdev
->asic
= &sumo_asic
;
1391 if (rdev
->family
== CHIP_CAICOS
)
1395 rdev
->asic
= &btc_asic
;
1398 rdev
->asic
= &cayman_asic
;
1401 rdev
->vm_manager
.funcs
= &cayman_vm_funcs
;
1404 /* FIXME: not supported yet */
1408 if (rdev
->flags
& RADEON_IS_IGP
) {
1409 rdev
->asic
->get_memory_clock
= NULL
;
1410 rdev
->asic
->set_memory_clock
= NULL
;