2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device
*rdev
);
35 void radeon_legacy_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device
*rdev
);
37 void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
39 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
);
40 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
41 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
);
42 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
, uint32_t mem_clock
);
43 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
46 * r100,rv100,rs100,rv200,rs200
56 int r100_init(struct radeon_device
*rdev
);
57 void r100_fini(struct radeon_device
*rdev
);
58 int r100_suspend(struct radeon_device
*rdev
);
59 int r100_resume(struct radeon_device
*rdev
);
60 void r100_vga_set_state(struct radeon_device
*rdev
, bool state
);
61 bool r100_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
62 int r100_asic_reset(struct radeon_device
*rdev
);
63 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
64 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
);
65 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
66 void r100_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
67 int r100_irq_set(struct radeon_device
*rdev
);
68 int r100_irq_process(struct radeon_device
*rdev
);
69 void r100_fence_ring_emit(struct radeon_device
*rdev
,
70 struct radeon_fence
*fence
);
71 void r100_semaphore_ring_emit(struct radeon_device
*rdev
,
72 struct radeon_ring
*cp
,
73 struct radeon_semaphore
*semaphore
,
75 int r100_cs_parse(struct radeon_cs_parser
*p
);
76 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
77 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
);
78 int r100_copy_blit(struct radeon_device
*rdev
,
81 unsigned num_gpu_pages
,
82 struct radeon_fence
*fence
);
83 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
84 uint32_t tiling_flags
, uint32_t pitch
,
85 uint32_t offset
, uint32_t obj_size
);
86 void r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
87 void r100_bandwidth_update(struct radeon_device
*rdev
);
88 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
89 int r100_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
90 void r100_hpd_init(struct radeon_device
*rdev
);
91 void r100_hpd_fini(struct radeon_device
*rdev
);
92 bool r100_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
93 void r100_hpd_set_polarity(struct radeon_device
*rdev
,
94 enum radeon_hpd_id hpd
);
95 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
);
96 int r100_debugfs_cp_init(struct radeon_device
*rdev
);
97 void r100_cp_disable(struct radeon_device
*rdev
);
98 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
);
99 void r100_cp_fini(struct radeon_device
*rdev
);
100 int r100_pci_gart_init(struct radeon_device
*rdev
);
101 void r100_pci_gart_fini(struct radeon_device
*rdev
);
102 int r100_pci_gart_enable(struct radeon_device
*rdev
);
103 void r100_pci_gart_disable(struct radeon_device
*rdev
);
104 int r100_debugfs_mc_info_init(struct radeon_device
*rdev
);
105 int r100_gui_wait_for_idle(struct radeon_device
*rdev
);
106 void r100_gpu_lockup_update(struct r100_gpu_lockup
*lockup
,
107 struct radeon_ring
*cp
);
108 bool r100_gpu_cp_is_lockup(struct radeon_device
*rdev
,
109 struct r100_gpu_lockup
*lockup
,
110 struct radeon_ring
*cp
);
111 void r100_ib_fini(struct radeon_device
*rdev
);
112 int r100_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
113 void r100_irq_disable(struct radeon_device
*rdev
);
114 void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
115 void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
);
116 void r100_vram_init_sizes(struct radeon_device
*rdev
);
117 int r100_cp_reset(struct radeon_device
*rdev
);
118 void r100_vga_render_disable(struct radeon_device
*rdev
);
119 void r100_restore_sanity(struct radeon_device
*rdev
);
120 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
121 struct radeon_cs_packet
*pkt
,
122 struct radeon_bo
*robj
);
123 int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
124 struct radeon_cs_packet
*pkt
,
125 const unsigned *auth
, unsigned n
,
126 radeon_packet0_check_t check
);
127 int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
128 struct radeon_cs_packet
*pkt
,
130 void r100_enable_bm(struct radeon_device
*rdev
);
131 void r100_set_common_regs(struct radeon_device
*rdev
);
132 void r100_bm_disable(struct radeon_device
*rdev
);
133 extern bool r100_gui_idle(struct radeon_device
*rdev
);
134 extern void r100_pm_misc(struct radeon_device
*rdev
);
135 extern void r100_pm_prepare(struct radeon_device
*rdev
);
136 extern void r100_pm_finish(struct radeon_device
*rdev
);
137 extern void r100_pm_init_profile(struct radeon_device
*rdev
);
138 extern void r100_pm_get_dynpm_state(struct radeon_device
*rdev
);
139 extern void r100_pre_page_flip(struct radeon_device
*rdev
, int crtc
);
140 extern u32
r100_page_flip(struct radeon_device
*rdev
, int crtc
, u64 crtc_base
);
141 extern void r100_post_page_flip(struct radeon_device
*rdev
, int crtc
);
142 extern void r100_wait_for_vblank(struct radeon_device
*rdev
, int crtc
);
143 extern int r100_mc_wait_for_idle(struct radeon_device
*rdev
);
146 * r200,rv250,rs300,rv280
148 extern int r200_copy_dma(struct radeon_device
*rdev
,
151 unsigned num_gpu_pages
,
152 struct radeon_fence
*fence
);
153 void r200_set_safe_registers(struct radeon_device
*rdev
);
156 * r300,r350,rv350,rv380
158 extern int r300_init(struct radeon_device
*rdev
);
159 extern void r300_fini(struct radeon_device
*rdev
);
160 extern int r300_suspend(struct radeon_device
*rdev
);
161 extern int r300_resume(struct radeon_device
*rdev
);
162 extern bool r300_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
163 extern int r300_asic_reset(struct radeon_device
*rdev
);
164 extern void r300_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
165 extern void r300_fence_ring_emit(struct radeon_device
*rdev
,
166 struct radeon_fence
*fence
);
167 extern int r300_cs_parse(struct radeon_cs_parser
*p
);
168 extern void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
169 extern int rv370_pcie_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
170 extern void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
);
171 extern int rv370_get_pcie_lanes(struct radeon_device
*rdev
);
172 extern void r300_set_reg_safe(struct radeon_device
*rdev
);
173 extern void r300_mc_program(struct radeon_device
*rdev
);
174 extern void r300_mc_init(struct radeon_device
*rdev
);
175 extern void r300_clock_startup(struct radeon_device
*rdev
);
176 extern int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
177 extern int rv370_pcie_gart_init(struct radeon_device
*rdev
);
178 extern void rv370_pcie_gart_fini(struct radeon_device
*rdev
);
179 extern int rv370_pcie_gart_enable(struct radeon_device
*rdev
);
180 extern void rv370_pcie_gart_disable(struct radeon_device
*rdev
);
181 extern int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
186 extern int r420_init(struct radeon_device
*rdev
);
187 extern void r420_fini(struct radeon_device
*rdev
);
188 extern int r420_suspend(struct radeon_device
*rdev
);
189 extern int r420_resume(struct radeon_device
*rdev
);
190 extern void r420_pm_init_profile(struct radeon_device
*rdev
);
191 extern u32
r420_mc_rreg(struct radeon_device
*rdev
, u32 reg
);
192 extern void r420_mc_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
);
193 extern int r420_debugfs_pipes_info_init(struct radeon_device
*rdev
);
194 extern void r420_pipes_init(struct radeon_device
*rdev
);
199 extern int rs400_init(struct radeon_device
*rdev
);
200 extern void rs400_fini(struct radeon_device
*rdev
);
201 extern int rs400_suspend(struct radeon_device
*rdev
);
202 extern int rs400_resume(struct radeon_device
*rdev
);
203 void rs400_gart_tlb_flush(struct radeon_device
*rdev
);
204 int rs400_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
205 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
206 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
207 int rs400_gart_init(struct radeon_device
*rdev
);
208 int rs400_gart_enable(struct radeon_device
*rdev
);
209 void rs400_gart_adjust_size(struct radeon_device
*rdev
);
210 void rs400_gart_disable(struct radeon_device
*rdev
);
211 void rs400_gart_fini(struct radeon_device
*rdev
);
212 extern int rs400_mc_wait_for_idle(struct radeon_device
*rdev
);
217 extern int rs600_asic_reset(struct radeon_device
*rdev
);
218 extern int rs600_init(struct radeon_device
*rdev
);
219 extern void rs600_fini(struct radeon_device
*rdev
);
220 extern int rs600_suspend(struct radeon_device
*rdev
);
221 extern int rs600_resume(struct radeon_device
*rdev
);
222 int rs600_irq_set(struct radeon_device
*rdev
);
223 int rs600_irq_process(struct radeon_device
*rdev
);
224 void rs600_irq_disable(struct radeon_device
*rdev
);
225 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
226 void rs600_gart_tlb_flush(struct radeon_device
*rdev
);
227 int rs600_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
228 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
229 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
230 void rs600_bandwidth_update(struct radeon_device
*rdev
);
231 void rs600_hpd_init(struct radeon_device
*rdev
);
232 void rs600_hpd_fini(struct radeon_device
*rdev
);
233 bool rs600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
234 void rs600_hpd_set_polarity(struct radeon_device
*rdev
,
235 enum radeon_hpd_id hpd
);
236 extern void rs600_pm_misc(struct radeon_device
*rdev
);
237 extern void rs600_pm_prepare(struct radeon_device
*rdev
);
238 extern void rs600_pm_finish(struct radeon_device
*rdev
);
239 extern void rs600_pre_page_flip(struct radeon_device
*rdev
, int crtc
);
240 extern u32
rs600_page_flip(struct radeon_device
*rdev
, int crtc
, u64 crtc_base
);
241 extern void rs600_post_page_flip(struct radeon_device
*rdev
, int crtc
);
242 void rs600_set_safe_registers(struct radeon_device
*rdev
);
243 extern void avivo_wait_for_vblank(struct radeon_device
*rdev
, int crtc
);
244 extern int rs600_mc_wait_for_idle(struct radeon_device
*rdev
);
249 int rs690_init(struct radeon_device
*rdev
);
250 void rs690_fini(struct radeon_device
*rdev
);
251 int rs690_resume(struct radeon_device
*rdev
);
252 int rs690_suspend(struct radeon_device
*rdev
);
253 uint32_t rs690_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
254 void rs690_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
255 void rs690_bandwidth_update(struct radeon_device
*rdev
);
256 void rs690_line_buffer_adjust(struct radeon_device
*rdev
,
257 struct drm_display_mode
*mode1
,
258 struct drm_display_mode
*mode2
);
259 extern int rs690_mc_wait_for_idle(struct radeon_device
*rdev
);
264 struct rv515_mc_save
{
267 u32 vga_render_control
;
272 int rv515_init(struct radeon_device
*rdev
);
273 void rv515_fini(struct radeon_device
*rdev
);
274 uint32_t rv515_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
275 void rv515_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
276 void rv515_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
277 void rv515_bandwidth_update(struct radeon_device
*rdev
);
278 int rv515_resume(struct radeon_device
*rdev
);
279 int rv515_suspend(struct radeon_device
*rdev
);
280 void rv515_bandwidth_avivo_update(struct radeon_device
*rdev
);
281 void rv515_vga_render_disable(struct radeon_device
*rdev
);
282 void rv515_set_safe_registers(struct radeon_device
*rdev
);
283 void rv515_mc_stop(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
284 void rv515_mc_resume(struct radeon_device
*rdev
, struct rv515_mc_save
*save
);
285 void rv515_clock_startup(struct radeon_device
*rdev
);
286 void rv515_debugfs(struct radeon_device
*rdev
);
287 int rv515_mc_wait_for_idle(struct radeon_device
*rdev
);
290 * r520,rv530,rv560,rv570,r580
292 int r520_init(struct radeon_device
*rdev
);
293 int r520_resume(struct radeon_device
*rdev
);
294 int r520_mc_wait_for_idle(struct radeon_device
*rdev
);
297 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
299 int r600_init(struct radeon_device
*rdev
);
300 void r600_fini(struct radeon_device
*rdev
);
301 int r600_suspend(struct radeon_device
*rdev
);
302 int r600_resume(struct radeon_device
*rdev
);
303 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
);
304 int r600_wb_init(struct radeon_device
*rdev
);
305 void r600_wb_fini(struct radeon_device
*rdev
);
306 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
307 uint32_t r600_pciep_rreg(struct radeon_device
*rdev
, uint32_t reg
);
308 void r600_pciep_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
309 int r600_cs_parse(struct radeon_cs_parser
*p
);
310 void r600_fence_ring_emit(struct radeon_device
*rdev
,
311 struct radeon_fence
*fence
);
312 void r600_semaphore_ring_emit(struct radeon_device
*rdev
,
313 struct radeon_ring
*cp
,
314 struct radeon_semaphore
*semaphore
,
316 bool r600_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
317 int r600_asic_reset(struct radeon_device
*rdev
);
318 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
319 uint32_t tiling_flags
, uint32_t pitch
,
320 uint32_t offset
, uint32_t obj_size
);
321 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
322 int r600_ib_test(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
323 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
324 int r600_ring_test(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
325 int r600_copy_blit(struct radeon_device
*rdev
,
326 uint64_t src_offset
, uint64_t dst_offset
,
327 unsigned num_gpu_pages
, struct radeon_fence
*fence
);
328 void r600_hpd_init(struct radeon_device
*rdev
);
329 void r600_hpd_fini(struct radeon_device
*rdev
);
330 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
331 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
332 enum radeon_hpd_id hpd
);
333 extern void r600_ioctl_wait_idle(struct radeon_device
*rdev
, struct radeon_bo
*bo
);
334 extern bool r600_gui_idle(struct radeon_device
*rdev
);
335 extern void r600_pm_misc(struct radeon_device
*rdev
);
336 extern void r600_pm_init_profile(struct radeon_device
*rdev
);
337 extern void rs780_pm_init_profile(struct radeon_device
*rdev
);
338 extern void r600_pm_get_dynpm_state(struct radeon_device
*rdev
);
339 extern void r600_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
);
340 extern int r600_get_pcie_lanes(struct radeon_device
*rdev
);
341 bool r600_card_posted(struct radeon_device
*rdev
);
342 void r600_cp_stop(struct radeon_device
*rdev
);
343 int r600_cp_start(struct radeon_device
*rdev
);
344 void r600_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*cp
, unsigned ring_size
);
345 int r600_cp_resume(struct radeon_device
*rdev
);
346 void r600_cp_fini(struct radeon_device
*rdev
);
347 int r600_count_pipe_bits(uint32_t val
);
348 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
349 int r600_pcie_gart_init(struct radeon_device
*rdev
);
350 void r600_scratch_init(struct radeon_device
*rdev
);
351 int r600_blit_init(struct radeon_device
*rdev
);
352 void r600_blit_fini(struct radeon_device
*rdev
);
353 int r600_init_microcode(struct radeon_device
*rdev
);
355 int r600_irq_process(struct radeon_device
*rdev
);
356 int r600_irq_init(struct radeon_device
*rdev
);
357 void r600_irq_fini(struct radeon_device
*rdev
);
358 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
);
359 int r600_irq_set(struct radeon_device
*rdev
);
360 void r600_irq_suspend(struct radeon_device
*rdev
);
361 void r600_disable_interrupts(struct radeon_device
*rdev
);
362 void r600_rlc_stop(struct radeon_device
*rdev
);
364 int r600_audio_init(struct radeon_device
*rdev
);
365 int r600_audio_tmds_index(struct drm_encoder
*encoder
);
366 void r600_audio_set_clock(struct drm_encoder
*encoder
, int clock
);
367 int r600_audio_channels(struct radeon_device
*rdev
);
368 int r600_audio_bits_per_sample(struct radeon_device
*rdev
);
369 int r600_audio_rate(struct radeon_device
*rdev
);
370 uint8_t r600_audio_status_bits(struct radeon_device
*rdev
);
371 uint8_t r600_audio_category_code(struct radeon_device
*rdev
);
372 void r600_audio_schedule_polling(struct radeon_device
*rdev
);
373 void r600_audio_enable_polling(struct drm_encoder
*encoder
);
374 void r600_audio_disable_polling(struct drm_encoder
*encoder
);
375 void r600_audio_fini(struct radeon_device
*rdev
);
376 void r600_hdmi_init(struct drm_encoder
*encoder
);
377 int r600_hdmi_buffer_status_changed(struct drm_encoder
*encoder
);
378 void r600_hdmi_update_audio_settings(struct drm_encoder
*encoder
);
380 int r600_blit_prepare_copy(struct radeon_device
*rdev
, unsigned num_gpu_pages
);
381 void r600_blit_done_copy(struct radeon_device
*rdev
, struct radeon_fence
*fence
);
382 void r600_kms_blit_copy(struct radeon_device
*rdev
,
383 u64 src_gpu_addr
, u64 dst_gpu_addr
,
384 unsigned num_gpu_pages
);
385 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
388 * rv770,rv730,rv710,rv740
390 int rv770_init(struct radeon_device
*rdev
);
391 void rv770_fini(struct radeon_device
*rdev
);
392 int rv770_suspend(struct radeon_device
*rdev
);
393 int rv770_resume(struct radeon_device
*rdev
);
394 void rv770_pm_misc(struct radeon_device
*rdev
);
395 u32
rv770_page_flip(struct radeon_device
*rdev
, int crtc
, u64 crtc_base
);
396 void r700_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
);
397 void r700_cp_stop(struct radeon_device
*rdev
);
398 void r700_cp_fini(struct radeon_device
*rdev
);
403 struct evergreen_mc_save
{
405 u32 vga_render_control
;
409 void evergreen_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
410 int evergreen_init(struct radeon_device
*rdev
);
411 void evergreen_fini(struct radeon_device
*rdev
);
412 int evergreen_suspend(struct radeon_device
*rdev
);
413 int evergreen_resume(struct radeon_device
*rdev
);
414 bool evergreen_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
415 int evergreen_asic_reset(struct radeon_device
*rdev
);
416 void evergreen_bandwidth_update(struct radeon_device
*rdev
);
417 void evergreen_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
418 void evergreen_hpd_init(struct radeon_device
*rdev
);
419 void evergreen_hpd_fini(struct radeon_device
*rdev
);
420 bool evergreen_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
421 void evergreen_hpd_set_polarity(struct radeon_device
*rdev
,
422 enum radeon_hpd_id hpd
);
423 u32
evergreen_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
424 int evergreen_irq_set(struct radeon_device
*rdev
);
425 int evergreen_irq_process(struct radeon_device
*rdev
);
426 extern int evergreen_cs_parse(struct radeon_cs_parser
*p
);
427 extern void evergreen_pm_misc(struct radeon_device
*rdev
);
428 extern void evergreen_pm_prepare(struct radeon_device
*rdev
);
429 extern void evergreen_pm_finish(struct radeon_device
*rdev
);
430 extern void sumo_pm_init_profile(struct radeon_device
*rdev
);
431 extern void evergreen_pre_page_flip(struct radeon_device
*rdev
, int crtc
);
432 extern u32
evergreen_page_flip(struct radeon_device
*rdev
, int crtc
, u64 crtc_base
);
433 extern void evergreen_post_page_flip(struct radeon_device
*rdev
, int crtc
);
434 extern void dce4_wait_for_vblank(struct radeon_device
*rdev
, int crtc
);
435 void evergreen_disable_interrupt_state(struct radeon_device
*rdev
);
436 int evergreen_blit_init(struct radeon_device
*rdev
);
437 int evergreen_mc_wait_for_idle(struct radeon_device
*rdev
);
442 void cayman_fence_ring_emit(struct radeon_device
*rdev
,
443 struct radeon_fence
*fence
);
444 void cayman_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
445 int cayman_init(struct radeon_device
*rdev
);
446 void cayman_fini(struct radeon_device
*rdev
);
447 int cayman_suspend(struct radeon_device
*rdev
);
448 int cayman_resume(struct radeon_device
*rdev
);
449 bool cayman_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
450 int cayman_asic_reset(struct radeon_device
*rdev
);
451 void cayman_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
452 int cayman_vm_init(struct radeon_device
*rdev
);
453 void cayman_vm_fini(struct radeon_device
*rdev
);
454 int cayman_vm_bind(struct radeon_device
*rdev
, struct radeon_vm
*vm
, int id
);
455 void cayman_vm_unbind(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
456 void cayman_vm_tlb_flush(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
457 uint32_t cayman_vm_page_flags(struct radeon_device
*rdev
,
458 struct radeon_vm
*vm
,
460 void cayman_vm_set_page(struct radeon_device
*rdev
, struct radeon_vm
*vm
,
461 unsigned pfn
, uint64_t addr
, uint32_t flags
);
462 int evergreen_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
465 void dce6_bandwidth_update(struct radeon_device
*rdev
);
470 void si_fence_ring_emit(struct radeon_device
*rdev
,
471 struct radeon_fence
*fence
);
472 void si_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
473 int si_init(struct radeon_device
*rdev
);
474 void si_fini(struct radeon_device
*rdev
);
475 int si_suspend(struct radeon_device
*rdev
);
476 int si_resume(struct radeon_device
*rdev
);
477 bool si_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*cp
);
478 int si_asic_reset(struct radeon_device
*rdev
);
479 void si_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
480 int si_irq_set(struct radeon_device
*rdev
);
481 int si_irq_process(struct radeon_device
*rdev
);
482 int si_vm_init(struct radeon_device
*rdev
);
483 void si_vm_fini(struct radeon_device
*rdev
);
484 int si_vm_bind(struct radeon_device
*rdev
, struct radeon_vm
*vm
, int id
);
485 void si_vm_unbind(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
486 void si_vm_tlb_flush(struct radeon_device
*rdev
, struct radeon_vm
*vm
);
487 int si_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
);