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drm/radeon/kms: add atom helper functions for dpm (v3)
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_atombios.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63 };
64
65 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
66 ATOM_GPIO_I2C_ASSIGMENT *gpio,
67 u8 index)
68 {
69 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
70 if ((rdev->family == CHIP_R420) ||
71 (rdev->family == CHIP_R423) ||
72 (rdev->family == CHIP_RV410)) {
73 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
74 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
75 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
76 gpio->ucClkMaskShift = 0x19;
77 gpio->ucDataMaskShift = 0x18;
78 }
79 }
80
81 /* some evergreen boards have bad data for this entry */
82 if (ASIC_IS_DCE4(rdev)) {
83 if ((index == 7) &&
84 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
85 (gpio->sucI2cId.ucAccess == 0)) {
86 gpio->sucI2cId.ucAccess = 0x97;
87 gpio->ucDataMaskShift = 8;
88 gpio->ucDataEnShift = 8;
89 gpio->ucDataY_Shift = 8;
90 gpio->ucDataA_Shift = 8;
91 }
92 }
93
94 /* some DCE3 boards have bad data for this entry */
95 if (ASIC_IS_DCE3(rdev)) {
96 if ((index == 4) &&
97 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
98 (gpio->sucI2cId.ucAccess == 0x94))
99 gpio->sucI2cId.ucAccess = 0x14;
100 }
101 }
102
103 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
104 {
105 struct radeon_i2c_bus_rec i2c;
106
107 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
108
109 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
110 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
111 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
112 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
113 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
114 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
115 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
116 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
117 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
118 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
119 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
120 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
121 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
122 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
123 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
124 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
125
126 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
127 i2c.hw_capable = true;
128 else
129 i2c.hw_capable = false;
130
131 if (gpio->sucI2cId.ucAccess == 0xa0)
132 i2c.mm_i2c = true;
133 else
134 i2c.mm_i2c = false;
135
136 i2c.i2c_id = gpio->sucI2cId.ucAccess;
137
138 if (i2c.mask_clk_reg)
139 i2c.valid = true;
140 else
141 i2c.valid = false;
142
143 return i2c;
144 }
145
146 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
147 uint8_t id)
148 {
149 struct atom_context *ctx = rdev->mode_info.atom_context;
150 ATOM_GPIO_I2C_ASSIGMENT *gpio;
151 struct radeon_i2c_bus_rec i2c;
152 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
153 struct _ATOM_GPIO_I2C_INFO *i2c_info;
154 uint16_t data_offset, size;
155 int i, num_indices;
156
157 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
158 i2c.valid = false;
159
160 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
161 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
162
163 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
164 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
165
166 for (i = 0; i < num_indices; i++) {
167 gpio = &i2c_info->asGPIO_Info[i];
168
169 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
170
171 if (gpio->sucI2cId.ucAccess == id) {
172 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
173 break;
174 }
175 }
176 }
177
178 return i2c;
179 }
180
181 void radeon_atombios_i2c_init(struct radeon_device *rdev)
182 {
183 struct atom_context *ctx = rdev->mode_info.atom_context;
184 ATOM_GPIO_I2C_ASSIGMENT *gpio;
185 struct radeon_i2c_bus_rec i2c;
186 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
187 struct _ATOM_GPIO_I2C_INFO *i2c_info;
188 uint16_t data_offset, size;
189 int i, num_indices;
190 char stmp[32];
191
192 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
193 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
194
195 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
196 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
197
198 for (i = 0; i < num_indices; i++) {
199 gpio = &i2c_info->asGPIO_Info[i];
200
201 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
202
203 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
204
205 if (i2c.valid) {
206 sprintf(stmp, "0x%x", i2c.i2c_id);
207 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
208 }
209 }
210 }
211 }
212
213 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
214 u8 id)
215 {
216 struct atom_context *ctx = rdev->mode_info.atom_context;
217 struct radeon_gpio_rec gpio;
218 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
219 struct _ATOM_GPIO_PIN_LUT *gpio_info;
220 ATOM_GPIO_PIN_ASSIGNMENT *pin;
221 u16 data_offset, size;
222 int i, num_indices;
223
224 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
225 gpio.valid = false;
226
227 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
228 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
229
230 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
231 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
232
233 for (i = 0; i < num_indices; i++) {
234 pin = &gpio_info->asGPIO_Pin[i];
235 if (id == pin->ucGPIO_ID) {
236 gpio.id = pin->ucGPIO_ID;
237 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
238 gpio.mask = (1 << pin->ucGpioPinBitShift);
239 gpio.valid = true;
240 break;
241 }
242 }
243 }
244
245 return gpio;
246 }
247
248 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
249 struct radeon_gpio_rec *gpio)
250 {
251 struct radeon_hpd hpd;
252 u32 reg;
253
254 memset(&hpd, 0, sizeof(struct radeon_hpd));
255
256 if (ASIC_IS_DCE6(rdev))
257 reg = SI_DC_GPIO_HPD_A;
258 else if (ASIC_IS_DCE4(rdev))
259 reg = EVERGREEN_DC_GPIO_HPD_A;
260 else
261 reg = AVIVO_DC_GPIO_HPD_A;
262
263 hpd.gpio = *gpio;
264 if (gpio->reg == reg) {
265 switch(gpio->mask) {
266 case (1 << 0):
267 hpd.hpd = RADEON_HPD_1;
268 break;
269 case (1 << 8):
270 hpd.hpd = RADEON_HPD_2;
271 break;
272 case (1 << 16):
273 hpd.hpd = RADEON_HPD_3;
274 break;
275 case (1 << 24):
276 hpd.hpd = RADEON_HPD_4;
277 break;
278 case (1 << 26):
279 hpd.hpd = RADEON_HPD_5;
280 break;
281 case (1 << 28):
282 hpd.hpd = RADEON_HPD_6;
283 break;
284 default:
285 hpd.hpd = RADEON_HPD_NONE;
286 break;
287 }
288 } else
289 hpd.hpd = RADEON_HPD_NONE;
290 return hpd;
291 }
292
293 static bool radeon_atom_apply_quirks(struct drm_device *dev,
294 uint32_t supported_device,
295 int *connector_type,
296 struct radeon_i2c_bus_rec *i2c_bus,
297 uint16_t *line_mux,
298 struct radeon_hpd *hpd)
299 {
300
301 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
302 if ((dev->pdev->device == 0x791e) &&
303 (dev->pdev->subsystem_vendor == 0x1043) &&
304 (dev->pdev->subsystem_device == 0x826d)) {
305 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
306 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
307 *connector_type = DRM_MODE_CONNECTOR_DVID;
308 }
309
310 /* Asrock RS600 board lists the DVI port as HDMI */
311 if ((dev->pdev->device == 0x7941) &&
312 (dev->pdev->subsystem_vendor == 0x1849) &&
313 (dev->pdev->subsystem_device == 0x7941)) {
314 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
315 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
316 *connector_type = DRM_MODE_CONNECTOR_DVID;
317 }
318
319 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
320 if ((dev->pdev->device == 0x796e) &&
321 (dev->pdev->subsystem_vendor == 0x1462) &&
322 (dev->pdev->subsystem_device == 0x7302)) {
323 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
324 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
325 return false;
326 }
327
328 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
329 if ((dev->pdev->device == 0x7941) &&
330 (dev->pdev->subsystem_vendor == 0x147b) &&
331 (dev->pdev->subsystem_device == 0x2412)) {
332 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
333 return false;
334 }
335
336 /* Falcon NW laptop lists vga ddc line for LVDS */
337 if ((dev->pdev->device == 0x5653) &&
338 (dev->pdev->subsystem_vendor == 0x1462) &&
339 (dev->pdev->subsystem_device == 0x0291)) {
340 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
341 i2c_bus->valid = false;
342 *line_mux = 53;
343 }
344 }
345
346 /* HIS X1300 is DVI+VGA, not DVI+DVI */
347 if ((dev->pdev->device == 0x7146) &&
348 (dev->pdev->subsystem_vendor == 0x17af) &&
349 (dev->pdev->subsystem_device == 0x2058)) {
350 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
351 return false;
352 }
353
354 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
355 if ((dev->pdev->device == 0x7142) &&
356 (dev->pdev->subsystem_vendor == 0x1458) &&
357 (dev->pdev->subsystem_device == 0x2134)) {
358 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
359 return false;
360 }
361
362
363 /* Funky macbooks */
364 if ((dev->pdev->device == 0x71C5) &&
365 (dev->pdev->subsystem_vendor == 0x106b) &&
366 (dev->pdev->subsystem_device == 0x0080)) {
367 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
368 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
369 return false;
370 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
371 *line_mux = 0x90;
372 }
373
374 /* mac rv630, rv730, others */
375 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
376 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
377 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
378 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
379 }
380
381 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
382 if ((dev->pdev->device == 0x9598) &&
383 (dev->pdev->subsystem_vendor == 0x1043) &&
384 (dev->pdev->subsystem_device == 0x01da)) {
385 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
386 *connector_type = DRM_MODE_CONNECTOR_DVII;
387 }
388 }
389
390 /* ASUS HD 3600 board lists the DVI port as HDMI */
391 if ((dev->pdev->device == 0x9598) &&
392 (dev->pdev->subsystem_vendor == 0x1043) &&
393 (dev->pdev->subsystem_device == 0x01e4)) {
394 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
395 *connector_type = DRM_MODE_CONNECTOR_DVII;
396 }
397 }
398
399 /* ASUS HD 3450 board lists the DVI port as HDMI */
400 if ((dev->pdev->device == 0x95C5) &&
401 (dev->pdev->subsystem_vendor == 0x1043) &&
402 (dev->pdev->subsystem_device == 0x01e2)) {
403 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
404 *connector_type = DRM_MODE_CONNECTOR_DVII;
405 }
406 }
407
408 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
409 * HDMI + VGA reporting as HDMI
410 */
411 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
412 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
413 *connector_type = DRM_MODE_CONNECTOR_VGA;
414 *line_mux = 0;
415 }
416 }
417
418 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
419 * on the laptop and a DVI port on the docking station and
420 * both share the same encoder, hpd pin, and ddc line.
421 * So while the bios table is technically correct,
422 * we drop the DVI port here since xrandr has no concept of
423 * encoders and will try and drive both connectors
424 * with different crtcs which isn't possible on the hardware
425 * side and leaves no crtcs for LVDS or VGA.
426 */
427 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
428 (dev->pdev->subsystem_vendor == 0x1025) &&
429 (dev->pdev->subsystem_device == 0x013c)) {
430 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
431 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
432 /* actually it's a DVI-D port not DVI-I */
433 *connector_type = DRM_MODE_CONNECTOR_DVID;
434 return false;
435 }
436 }
437
438 /* XFX Pine Group device rv730 reports no VGA DDC lines
439 * even though they are wired up to record 0x93
440 */
441 if ((dev->pdev->device == 0x9498) &&
442 (dev->pdev->subsystem_vendor == 0x1682) &&
443 (dev->pdev->subsystem_device == 0x2452) &&
444 (i2c_bus->valid == false) &&
445 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
446 struct radeon_device *rdev = dev->dev_private;
447 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
448 }
449
450 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
451 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
452 (dev->pdev->subsystem_vendor == 0x1734) &&
453 (dev->pdev->subsystem_device == 0x11bd)) {
454 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
455 *connector_type = DRM_MODE_CONNECTOR_DVII;
456 *line_mux = 0x3103;
457 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
458 *connector_type = DRM_MODE_CONNECTOR_DVII;
459 }
460 }
461
462
463 return true;
464 }
465
466 const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483 };
484
485 const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500 };
501
502 const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
525 };
526
527 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528 {
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
533 u16 size, data_offset;
534 u8 frev, crev;
535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
537 ATOM_OBJECT_TABLE *router_obj;
538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
540 int i, j, k, path_size, device_support;
541 int connector_type;
542 u16 igp_lane_info, conn_id, connector_object_id;
543 struct radeon_i2c_bus_rec ddc_bus;
544 struct radeon_router router;
545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
576
577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
593 continue;
594
595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
635 } else
636 continue;
637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
647 connector_object_id = con_obj_id;
648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
653 router.ddc_valid = false;
654 router.cd_valid = false;
655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
657
658 grph_obj_id =
659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
661 grph_obj_num =
662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
664 grph_obj_type =
665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
677
678 while (record->ucRecordSize > 0 &&
679 record->ucRecordType > 0 &&
680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
681 switch (record->ucRecordType) {
682 case ATOM_ENCODER_CAP_RECORD_TYPE:
683 cap_record =(ATOM_ENCODER_CAP_RECORD *)
684 record;
685 caps = le16_to_cpu(cap_record->usEncoderCap);
686 break;
687 }
688 record = (ATOM_COMMON_RECORD_HEADER *)
689 ((char *)record + record->ucRecordSize);
690 }
691 radeon_add_atom_encoder(dev,
692 encoder_obj,
693 le16_to_cpu
694 (path->
695 usDeviceTag),
696 caps);
697 }
698 }
699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
704 (ctx->bios + data_offset +
705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
706 ATOM_I2C_RECORD *i2c_record;
707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
712 (ctx->bios + data_offset +
713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
718 enum_id++) {
719 if (le16_to_cpu(path->usConnObjectId) ==
720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
721 break;
722 }
723
724 while (record->ucRecordSize > 0 &&
725 record->ucRecordType > 0 &&
726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
727 switch (record->ucRecordType) {
728 case ATOM_I2C_RECORD_TYPE:
729 i2c_record =
730 (ATOM_I2C_RECORD *)
731 record;
732 i2c_config =
733 (ATOM_I2C_ID_CONFIG_ACCESS *)
734 &i2c_record->sucI2cId;
735 router.i2c_info =
736 radeon_lookup_i2c_gpio(rdev,
737 i2c_config->
738 ucAccess);
739 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
740 break;
741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
743 record;
744 router.ddc_valid = true;
745 router.ddc_mux_type = ddc_path->ucMuxType;
746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
748 break;
749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
751 record;
752 router.cd_valid = true;
753 router.cd_mux_type = cd_path->ucMuxType;
754 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
755 router.cd_mux_state = cd_path->ucMuxState[enum_id];
756 break;
757 }
758 record = (ATOM_COMMON_RECORD_HEADER *)
759 ((char *)record + record->ucRecordSize);
760 }
761 }
762 }
763 }
764 }
765
766 /* look up gpio for ddc, hpd */
767 ddc_bus.valid = false;
768 hpd.hpd = RADEON_HPD_NONE;
769 if ((le16_to_cpu(path->usDeviceTag) &
770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
772 if (le16_to_cpu(path->usConnObjectId) ==
773 le16_to_cpu(con_obj->asObjects[j].
774 usObjectID)) {
775 ATOM_COMMON_RECORD_HEADER
776 *record =
777 (ATOM_COMMON_RECORD_HEADER
778 *)
779 (ctx->bios + data_offset +
780 le16_to_cpu(con_obj->
781 asObjects[j].
782 usRecordOffset));
783 ATOM_I2C_RECORD *i2c_record;
784 ATOM_HPD_INT_RECORD *hpd_record;
785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
786
787 while (record->ucRecordSize > 0 &&
788 record->ucRecordType > 0 &&
789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
790 switch (record->ucRecordType) {
791 case ATOM_I2C_RECORD_TYPE:
792 i2c_record =
793 (ATOM_I2C_RECORD *)
794 record;
795 i2c_config =
796 (ATOM_I2C_ID_CONFIG_ACCESS *)
797 &i2c_record->sucI2cId;
798 ddc_bus = radeon_lookup_i2c_gpio(rdev,
799 i2c_config->
800 ucAccess);
801 break;
802 case ATOM_HPD_INT_RECORD_TYPE:
803 hpd_record =
804 (ATOM_HPD_INT_RECORD *)
805 record;
806 gpio = radeon_lookup_gpio(rdev,
807 hpd_record->ucHPDIntGPIOID);
808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
809 hpd.plugged_state = hpd_record->ucPlugged_PinState;
810 break;
811 }
812 record =
813 (ATOM_COMMON_RECORD_HEADER
814 *) ((char *)record
815 +
816 record->
817 ucRecordSize);
818 }
819 break;
820 }
821 }
822 }
823
824 /* needed for aux chan transactions */
825 ddc_bus.hpd = hpd.hpd;
826
827 conn_id = le16_to_cpu(path->usConnObjectId);
828
829 if (!radeon_atom_apply_quirks
830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
831 &ddc_bus, &conn_id, &hpd))
832 continue;
833
834 radeon_add_atom_connector(dev,
835 conn_id,
836 le16_to_cpu(path->
837 usDeviceTag),
838 connector_type, &ddc_bus,
839 igp_lane_info,
840 connector_object_id,
841 &hpd,
842 &router);
843
844 }
845 }
846
847 radeon_link_encoder_connector(dev);
848
849 return true;
850 }
851
852 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855 {
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
873
874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892 }
893
894 struct bios_connector {
895 bool valid;
896 uint16_t line_mux;
897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
900 struct radeon_hpd hpd;
901 };
902
903 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906 {
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
916 int i, j, max_device;
917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
919 struct radeon_router router;
920
921 router.ddc_valid = false;
922 router.cd_valid = false;
923
924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
931 return false;
932 }
933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
955 DRM_DEBUG_KMS("Skipping Component Video\n");
956 continue;
957 }
958
959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
1029 radeon_get_encoder_enum(dev,
1030 (1 << i),
1031 dac),
1032 (1 << i),
1033 0);
1034 else
1035 radeon_add_legacy_encoder(dev,
1036 radeon_get_encoder_enum(dev,
1037 (1 << i),
1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
1043 for (i = 0; i < max_device; i++) {
1044 if (bios_connectors[i].valid) {
1045 for (j = 0; j < max_device; j++) {
1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
1072 bios_connectors[j].valid = false;
1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
1081 for (i = 0; i < max_device; i++) {
1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
1093 0,
1094 connector_object_id,
1095 &bios_connectors[i].hpd,
1096 &router);
1097 }
1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
1102 kfree(bios_connectors);
1103 return true;
1104 }
1105
1106 union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
1113 };
1114
1115 bool radeon_atom_get_clock_info(struct drm_device *dev)
1116 {
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1241 else
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1243 }
1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1246 }
1247 *dcpll = *p1pll;
1248
1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1250 if (rdev->clock.max_pixel_clock == 0)
1251 rdev->clock.max_pixel_clock = 40000;
1252
1253 /* not technically a clock, but... */
1254 rdev->mode_info.firmware_flags =
1255 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1256
1257 return true;
1258 }
1259
1260 return false;
1261 }
1262
1263 union igp_info {
1264 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1265 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1266 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1267 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1268 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1269 };
1270
1271 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1272 {
1273 struct radeon_mode_info *mode_info = &rdev->mode_info;
1274 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1275 union igp_info *igp_info;
1276 u8 frev, crev;
1277 u16 data_offset;
1278
1279 /* sideport is AMD only */
1280 if (rdev->family == CHIP_RS600)
1281 return false;
1282
1283 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1284 &frev, &crev, &data_offset)) {
1285 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1286 data_offset);
1287 switch (crev) {
1288 case 1:
1289 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1290 return true;
1291 break;
1292 case 2:
1293 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1294 return true;
1295 break;
1296 default:
1297 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1298 break;
1299 }
1300 }
1301 return false;
1302 }
1303
1304 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1305 struct radeon_encoder_int_tmds *tmds)
1306 {
1307 struct drm_device *dev = encoder->base.dev;
1308 struct radeon_device *rdev = dev->dev_private;
1309 struct radeon_mode_info *mode_info = &rdev->mode_info;
1310 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1311 uint16_t data_offset;
1312 struct _ATOM_TMDS_INFO *tmds_info;
1313 uint8_t frev, crev;
1314 uint16_t maxfreq;
1315 int i;
1316
1317 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1318 &frev, &crev, &data_offset)) {
1319 tmds_info =
1320 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1321 data_offset);
1322
1323 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1324 for (i = 0; i < 4; i++) {
1325 tmds->tmds_pll[i].freq =
1326 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1327 tmds->tmds_pll[i].value =
1328 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1329 tmds->tmds_pll[i].value |=
1330 (tmds_info->asMiscInfo[i].
1331 ucPLL_VCO_Gain & 0x3f) << 6;
1332 tmds->tmds_pll[i].value |=
1333 (tmds_info->asMiscInfo[i].
1334 ucPLL_DutyCycle & 0xf) << 12;
1335 tmds->tmds_pll[i].value |=
1336 (tmds_info->asMiscInfo[i].
1337 ucPLL_VoltageSwing & 0xf) << 16;
1338
1339 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1340 tmds->tmds_pll[i].freq,
1341 tmds->tmds_pll[i].value);
1342
1343 if (maxfreq == tmds->tmds_pll[i].freq) {
1344 tmds->tmds_pll[i].freq = 0xffffffff;
1345 break;
1346 }
1347 }
1348 return true;
1349 }
1350 return false;
1351 }
1352
1353 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1354 struct radeon_atom_ss *ss,
1355 int id)
1356 {
1357 struct radeon_mode_info *mode_info = &rdev->mode_info;
1358 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1359 uint16_t data_offset, size;
1360 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1361 uint8_t frev, crev;
1362 int i, num_indices;
1363
1364 memset(ss, 0, sizeof(struct radeon_atom_ss));
1365 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1366 &frev, &crev, &data_offset)) {
1367 ss_info =
1368 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1369
1370 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1371 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1372
1373 for (i = 0; i < num_indices; i++) {
1374 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1375 ss->percentage =
1376 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1377 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1378 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1379 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1380 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1381 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1382 return true;
1383 }
1384 }
1385 }
1386 return false;
1387 }
1388
1389 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1390 struct radeon_atom_ss *ss,
1391 int id)
1392 {
1393 struct radeon_mode_info *mode_info = &rdev->mode_info;
1394 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1395 u16 data_offset, size;
1396 union igp_info *igp_info;
1397 u8 frev, crev;
1398 u16 percentage = 0, rate = 0;
1399
1400 /* get any igp specific overrides */
1401 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1402 &frev, &crev, &data_offset)) {
1403 igp_info = (union igp_info *)
1404 (mode_info->atom_context->bios + data_offset);
1405 switch (crev) {
1406 case 6:
1407 switch (id) {
1408 case ASIC_INTERNAL_SS_ON_TMDS:
1409 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1410 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1411 break;
1412 case ASIC_INTERNAL_SS_ON_HDMI:
1413 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1414 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1415 break;
1416 case ASIC_INTERNAL_SS_ON_LVDS:
1417 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1418 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1419 break;
1420 }
1421 break;
1422 case 7:
1423 switch (id) {
1424 case ASIC_INTERNAL_SS_ON_TMDS:
1425 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1426 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1427 break;
1428 case ASIC_INTERNAL_SS_ON_HDMI:
1429 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1430 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1431 break;
1432 case ASIC_INTERNAL_SS_ON_LVDS:
1433 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1434 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1435 break;
1436 }
1437 break;
1438 case 8:
1439 switch (id) {
1440 case ASIC_INTERNAL_SS_ON_TMDS:
1441 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1442 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1443 break;
1444 case ASIC_INTERNAL_SS_ON_HDMI:
1445 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1446 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1447 break;
1448 case ASIC_INTERNAL_SS_ON_LVDS:
1449 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1450 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1451 break;
1452 }
1453 break;
1454 default:
1455 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1456 break;
1457 }
1458 if (percentage)
1459 ss->percentage = percentage;
1460 if (rate)
1461 ss->rate = rate;
1462 }
1463 }
1464
1465 union asic_ss_info {
1466 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1467 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1468 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1469 };
1470
1471 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1472 struct radeon_atom_ss *ss,
1473 int id, u32 clock)
1474 {
1475 struct radeon_mode_info *mode_info = &rdev->mode_info;
1476 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1477 uint16_t data_offset, size;
1478 union asic_ss_info *ss_info;
1479 uint8_t frev, crev;
1480 int i, num_indices;
1481
1482 memset(ss, 0, sizeof(struct radeon_atom_ss));
1483 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1484 &frev, &crev, &data_offset)) {
1485
1486 ss_info =
1487 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1488
1489 switch (frev) {
1490 case 1:
1491 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1492 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1493
1494 for (i = 0; i < num_indices; i++) {
1495 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1496 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1497 ss->percentage =
1498 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1499 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1500 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1501 return true;
1502 }
1503 }
1504 break;
1505 case 2:
1506 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1507 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1508 for (i = 0; i < num_indices; i++) {
1509 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1510 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1511 ss->percentage =
1512 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1513 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1514 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1515 if ((crev == 2) &&
1516 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1517 (id == ASIC_INTERNAL_MEMORY_SS)))
1518 ss->rate /= 100;
1519 return true;
1520 }
1521 }
1522 break;
1523 case 3:
1524 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1525 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1526 for (i = 0; i < num_indices; i++) {
1527 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1528 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1529 ss->percentage =
1530 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1531 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1532 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1533 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1534 (id == ASIC_INTERNAL_MEMORY_SS))
1535 ss->rate /= 100;
1536 if (rdev->flags & RADEON_IS_IGP)
1537 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1538 return true;
1539 }
1540 }
1541 break;
1542 default:
1543 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1544 break;
1545 }
1546
1547 }
1548 return false;
1549 }
1550
1551 union lvds_info {
1552 struct _ATOM_LVDS_INFO info;
1553 struct _ATOM_LVDS_INFO_V12 info_12;
1554 };
1555
1556 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1557 radeon_encoder
1558 *encoder)
1559 {
1560 struct drm_device *dev = encoder->base.dev;
1561 struct radeon_device *rdev = dev->dev_private;
1562 struct radeon_mode_info *mode_info = &rdev->mode_info;
1563 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1564 uint16_t data_offset, misc;
1565 union lvds_info *lvds_info;
1566 uint8_t frev, crev;
1567 struct radeon_encoder_atom_dig *lvds = NULL;
1568 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1569
1570 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1571 &frev, &crev, &data_offset)) {
1572 lvds_info =
1573 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1574 lvds =
1575 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1576
1577 if (!lvds)
1578 return NULL;
1579
1580 lvds->native_mode.clock =
1581 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1582 lvds->native_mode.hdisplay =
1583 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1584 lvds->native_mode.vdisplay =
1585 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1586 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1587 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1588 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1589 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1590 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1591 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1592 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1593 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1594 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1595 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1596 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1597 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1598 lvds->panel_pwr_delay =
1599 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1600 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1601
1602 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1603 if (misc & ATOM_VSYNC_POLARITY)
1604 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1605 if (misc & ATOM_HSYNC_POLARITY)
1606 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1607 if (misc & ATOM_COMPOSITESYNC)
1608 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1609 if (misc & ATOM_INTERLACE)
1610 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1611 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1612 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1613
1614 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1615 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1616
1617 /* set crtc values */
1618 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1619
1620 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1621
1622 encoder->native_mode = lvds->native_mode;
1623
1624 if (encoder_enum == 2)
1625 lvds->linkb = true;
1626 else
1627 lvds->linkb = false;
1628
1629 /* parse the lcd record table */
1630 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1631 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1632 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1633 bool bad_record = false;
1634 u8 *record;
1635
1636 if ((frev == 1) && (crev < 2))
1637 /* absolute */
1638 record = (u8 *)(mode_info->atom_context->bios +
1639 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1640 else
1641 /* relative */
1642 record = (u8 *)(mode_info->atom_context->bios +
1643 data_offset +
1644 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1645 while (*record != ATOM_RECORD_END_TYPE) {
1646 switch (*record) {
1647 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1648 record += sizeof(ATOM_PATCH_RECORD_MODE);
1649 break;
1650 case LCD_RTS_RECORD_TYPE:
1651 record += sizeof(ATOM_LCD_RTS_RECORD);
1652 break;
1653 case LCD_CAP_RECORD_TYPE:
1654 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1655 break;
1656 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1657 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1658 if (fake_edid_record->ucFakeEDIDLength) {
1659 struct edid *edid;
1660 int edid_size =
1661 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1662 edid = kmalloc(edid_size, GFP_KERNEL);
1663 if (edid) {
1664 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1665 fake_edid_record->ucFakeEDIDLength);
1666
1667 if (drm_edid_is_valid(edid)) {
1668 rdev->mode_info.bios_hardcoded_edid = edid;
1669 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1670 } else
1671 kfree(edid);
1672 }
1673 }
1674 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1675 break;
1676 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1677 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1678 lvds->native_mode.width_mm = panel_res_record->usHSize;
1679 lvds->native_mode.height_mm = panel_res_record->usVSize;
1680 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1681 break;
1682 default:
1683 DRM_ERROR("Bad LCD record %d\n", *record);
1684 bad_record = true;
1685 break;
1686 }
1687 if (bad_record)
1688 break;
1689 }
1690 }
1691 }
1692 return lvds;
1693 }
1694
1695 struct radeon_encoder_primary_dac *
1696 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1697 {
1698 struct drm_device *dev = encoder->base.dev;
1699 struct radeon_device *rdev = dev->dev_private;
1700 struct radeon_mode_info *mode_info = &rdev->mode_info;
1701 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1702 uint16_t data_offset;
1703 struct _COMPASSIONATE_DATA *dac_info;
1704 uint8_t frev, crev;
1705 uint8_t bg, dac;
1706 struct radeon_encoder_primary_dac *p_dac = NULL;
1707
1708 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1709 &frev, &crev, &data_offset)) {
1710 dac_info = (struct _COMPASSIONATE_DATA *)
1711 (mode_info->atom_context->bios + data_offset);
1712
1713 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1714
1715 if (!p_dac)
1716 return NULL;
1717
1718 bg = dac_info->ucDAC1_BG_Adjustment;
1719 dac = dac_info->ucDAC1_DAC_Adjustment;
1720 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1721
1722 }
1723 return p_dac;
1724 }
1725
1726 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1727 struct drm_display_mode *mode)
1728 {
1729 struct radeon_mode_info *mode_info = &rdev->mode_info;
1730 ATOM_ANALOG_TV_INFO *tv_info;
1731 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1732 ATOM_DTD_FORMAT *dtd_timings;
1733 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1734 u8 frev, crev;
1735 u16 data_offset, misc;
1736
1737 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1738 &frev, &crev, &data_offset))
1739 return false;
1740
1741 switch (crev) {
1742 case 1:
1743 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1744 if (index >= MAX_SUPPORTED_TV_TIMING)
1745 return false;
1746
1747 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1748 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1749 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1750 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1751 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1752
1753 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1754 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1755 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1756 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1757 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1758
1759 mode->flags = 0;
1760 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1761 if (misc & ATOM_VSYNC_POLARITY)
1762 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1763 if (misc & ATOM_HSYNC_POLARITY)
1764 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1765 if (misc & ATOM_COMPOSITESYNC)
1766 mode->flags |= DRM_MODE_FLAG_CSYNC;
1767 if (misc & ATOM_INTERLACE)
1768 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1769 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1770 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1771
1772 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1773
1774 if (index == 1) {
1775 /* PAL timings appear to have wrong values for totals */
1776 mode->crtc_htotal -= 1;
1777 mode->crtc_vtotal -= 1;
1778 }
1779 break;
1780 case 2:
1781 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1782 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1783 return false;
1784
1785 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1786 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1787 le16_to_cpu(dtd_timings->usHBlanking_Time);
1788 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1789 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1790 le16_to_cpu(dtd_timings->usHSyncOffset);
1791 mode->crtc_hsync_end = mode->crtc_hsync_start +
1792 le16_to_cpu(dtd_timings->usHSyncWidth);
1793
1794 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1795 le16_to_cpu(dtd_timings->usVBlanking_Time);
1796 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1797 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1798 le16_to_cpu(dtd_timings->usVSyncOffset);
1799 mode->crtc_vsync_end = mode->crtc_vsync_start +
1800 le16_to_cpu(dtd_timings->usVSyncWidth);
1801
1802 mode->flags = 0;
1803 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1804 if (misc & ATOM_VSYNC_POLARITY)
1805 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1806 if (misc & ATOM_HSYNC_POLARITY)
1807 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1808 if (misc & ATOM_COMPOSITESYNC)
1809 mode->flags |= DRM_MODE_FLAG_CSYNC;
1810 if (misc & ATOM_INTERLACE)
1811 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1812 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1813 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1814
1815 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1816 break;
1817 }
1818 return true;
1819 }
1820
1821 enum radeon_tv_std
1822 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1823 {
1824 struct radeon_mode_info *mode_info = &rdev->mode_info;
1825 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1826 uint16_t data_offset;
1827 uint8_t frev, crev;
1828 struct _ATOM_ANALOG_TV_INFO *tv_info;
1829 enum radeon_tv_std tv_std = TV_STD_NTSC;
1830
1831 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1832 &frev, &crev, &data_offset)) {
1833
1834 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1835 (mode_info->atom_context->bios + data_offset);
1836
1837 switch (tv_info->ucTV_BootUpDefaultStandard) {
1838 case ATOM_TV_NTSC:
1839 tv_std = TV_STD_NTSC;
1840 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1841 break;
1842 case ATOM_TV_NTSCJ:
1843 tv_std = TV_STD_NTSC_J;
1844 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1845 break;
1846 case ATOM_TV_PAL:
1847 tv_std = TV_STD_PAL;
1848 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1849 break;
1850 case ATOM_TV_PALM:
1851 tv_std = TV_STD_PAL_M;
1852 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1853 break;
1854 case ATOM_TV_PALN:
1855 tv_std = TV_STD_PAL_N;
1856 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1857 break;
1858 case ATOM_TV_PALCN:
1859 tv_std = TV_STD_PAL_CN;
1860 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1861 break;
1862 case ATOM_TV_PAL60:
1863 tv_std = TV_STD_PAL_60;
1864 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1865 break;
1866 case ATOM_TV_SECAM:
1867 tv_std = TV_STD_SECAM;
1868 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1869 break;
1870 default:
1871 tv_std = TV_STD_NTSC;
1872 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1873 break;
1874 }
1875 }
1876 return tv_std;
1877 }
1878
1879 struct radeon_encoder_tv_dac *
1880 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1881 {
1882 struct drm_device *dev = encoder->base.dev;
1883 struct radeon_device *rdev = dev->dev_private;
1884 struct radeon_mode_info *mode_info = &rdev->mode_info;
1885 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1886 uint16_t data_offset;
1887 struct _COMPASSIONATE_DATA *dac_info;
1888 uint8_t frev, crev;
1889 uint8_t bg, dac;
1890 struct radeon_encoder_tv_dac *tv_dac = NULL;
1891
1892 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1893 &frev, &crev, &data_offset)) {
1894
1895 dac_info = (struct _COMPASSIONATE_DATA *)
1896 (mode_info->atom_context->bios + data_offset);
1897
1898 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1899
1900 if (!tv_dac)
1901 return NULL;
1902
1903 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1904 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1905 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1906
1907 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1908 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1909 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1910
1911 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1912 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1913 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1914
1915 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1916 }
1917 return tv_dac;
1918 }
1919
1920 static const char *thermal_controller_names[] = {
1921 "NONE",
1922 "lm63",
1923 "adm1032",
1924 "adm1030",
1925 "max6649",
1926 "lm64",
1927 "f75375",
1928 "asc7xxx",
1929 };
1930
1931 static const char *pp_lib_thermal_controller_names[] = {
1932 "NONE",
1933 "lm63",
1934 "adm1032",
1935 "adm1030",
1936 "max6649",
1937 "lm64",
1938 "f75375",
1939 "RV6xx",
1940 "RV770",
1941 "adt7473",
1942 "NONE",
1943 "External GPIO",
1944 "Evergreen",
1945 "emc2103",
1946 "Sumo",
1947 "Northern Islands",
1948 "Southern Islands",
1949 "lm96163",
1950 "Sea Islands",
1951 };
1952
1953 union power_info {
1954 struct _ATOM_POWERPLAY_INFO info;
1955 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1956 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1957 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1958 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1959 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1960 };
1961
1962 union pplib_clock_info {
1963 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1964 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1965 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1966 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1967 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1968 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
1969 };
1970
1971 union pplib_power_state {
1972 struct _ATOM_PPLIB_STATE v1;
1973 struct _ATOM_PPLIB_STATE_V2 v2;
1974 };
1975
1976 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1977 int state_index,
1978 u32 misc, u32 misc2)
1979 {
1980 rdev->pm.power_state[state_index].misc = misc;
1981 rdev->pm.power_state[state_index].misc2 = misc2;
1982 /* order matters! */
1983 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1984 rdev->pm.power_state[state_index].type =
1985 POWER_STATE_TYPE_POWERSAVE;
1986 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1987 rdev->pm.power_state[state_index].type =
1988 POWER_STATE_TYPE_BATTERY;
1989 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1990 rdev->pm.power_state[state_index].type =
1991 POWER_STATE_TYPE_BATTERY;
1992 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1993 rdev->pm.power_state[state_index].type =
1994 POWER_STATE_TYPE_BALANCED;
1995 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1996 rdev->pm.power_state[state_index].type =
1997 POWER_STATE_TYPE_PERFORMANCE;
1998 rdev->pm.power_state[state_index].flags &=
1999 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2000 }
2001 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2002 rdev->pm.power_state[state_index].type =
2003 POWER_STATE_TYPE_BALANCED;
2004 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2005 rdev->pm.power_state[state_index].type =
2006 POWER_STATE_TYPE_DEFAULT;
2007 rdev->pm.default_power_state_index = state_index;
2008 rdev->pm.power_state[state_index].default_clock_mode =
2009 &rdev->pm.power_state[state_index].clock_info[0];
2010 } else if (state_index == 0) {
2011 rdev->pm.power_state[state_index].clock_info[0].flags |=
2012 RADEON_PM_MODE_NO_DISPLAY;
2013 }
2014 }
2015
2016 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2017 {
2018 struct radeon_mode_info *mode_info = &rdev->mode_info;
2019 u32 misc, misc2 = 0;
2020 int num_modes = 0, i;
2021 int state_index = 0;
2022 struct radeon_i2c_bus_rec i2c_bus;
2023 union power_info *power_info;
2024 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2025 u16 data_offset;
2026 u8 frev, crev;
2027
2028 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2029 &frev, &crev, &data_offset))
2030 return state_index;
2031 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2032
2033 /* add the i2c bus for thermal/fan chip */
2034 if ((power_info->info.ucOverdriveThermalController > 0) &&
2035 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2036 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2037 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2038 power_info->info.ucOverdriveControllerAddress >> 1);
2039 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2040 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2041 if (rdev->pm.i2c_bus) {
2042 struct i2c_board_info info = { };
2043 const char *name = thermal_controller_names[power_info->info.
2044 ucOverdriveThermalController];
2045 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2046 strlcpy(info.type, name, sizeof(info.type));
2047 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2048 }
2049 }
2050 num_modes = power_info->info.ucNumOfPowerModeEntries;
2051 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2052 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2053 if (num_modes == 0)
2054 return state_index;
2055 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2056 if (!rdev->pm.power_state)
2057 return state_index;
2058 /* last mode is usually default, array is low to high */
2059 for (i = 0; i < num_modes; i++) {
2060 rdev->pm.power_state[state_index].clock_info =
2061 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2062 if (!rdev->pm.power_state[state_index].clock_info)
2063 return state_index;
2064 rdev->pm.power_state[state_index].num_clock_modes = 1;
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2066 switch (frev) {
2067 case 1:
2068 rdev->pm.power_state[state_index].clock_info[0].mclk =
2069 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2070 rdev->pm.power_state[state_index].clock_info[0].sclk =
2071 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2072 /* skip invalid modes */
2073 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2074 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2075 continue;
2076 rdev->pm.power_state[state_index].pcie_lanes =
2077 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2078 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2079 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2080 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2081 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2082 VOLTAGE_GPIO;
2083 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2084 radeon_lookup_gpio(rdev,
2085 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2086 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2087 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2088 true;
2089 else
2090 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2091 false;
2092 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2093 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2094 VOLTAGE_VDDC;
2095 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2096 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2097 }
2098 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2099 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2100 state_index++;
2101 break;
2102 case 2:
2103 rdev->pm.power_state[state_index].clock_info[0].mclk =
2104 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2105 rdev->pm.power_state[state_index].clock_info[0].sclk =
2106 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2107 /* skip invalid modes */
2108 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2109 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2110 continue;
2111 rdev->pm.power_state[state_index].pcie_lanes =
2112 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2113 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2114 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2115 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2116 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2117 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2118 VOLTAGE_GPIO;
2119 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2120 radeon_lookup_gpio(rdev,
2121 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2122 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2123 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2124 true;
2125 else
2126 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2127 false;
2128 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2129 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2130 VOLTAGE_VDDC;
2131 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2132 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2133 }
2134 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2135 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2136 state_index++;
2137 break;
2138 case 3:
2139 rdev->pm.power_state[state_index].clock_info[0].mclk =
2140 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2141 rdev->pm.power_state[state_index].clock_info[0].sclk =
2142 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2143 /* skip invalid modes */
2144 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2145 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2146 continue;
2147 rdev->pm.power_state[state_index].pcie_lanes =
2148 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2149 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2150 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2151 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2152 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2153 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2154 VOLTAGE_GPIO;
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2156 radeon_lookup_gpio(rdev,
2157 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2158 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2159 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2160 true;
2161 else
2162 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2163 false;
2164 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2165 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2166 VOLTAGE_VDDC;
2167 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2168 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2169 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2170 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2171 true;
2172 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2173 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2174 }
2175 }
2176 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2177 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2178 state_index++;
2179 break;
2180 }
2181 }
2182 /* last mode is usually default */
2183 if (rdev->pm.default_power_state_index == -1) {
2184 rdev->pm.power_state[state_index - 1].type =
2185 POWER_STATE_TYPE_DEFAULT;
2186 rdev->pm.default_power_state_index = state_index - 1;
2187 rdev->pm.power_state[state_index - 1].default_clock_mode =
2188 &rdev->pm.power_state[state_index - 1].clock_info[0];
2189 rdev->pm.power_state[state_index].flags &=
2190 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2191 rdev->pm.power_state[state_index].misc = 0;
2192 rdev->pm.power_state[state_index].misc2 = 0;
2193 }
2194 return state_index;
2195 }
2196
2197 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2198 ATOM_PPLIB_THERMALCONTROLLER *controller)
2199 {
2200 struct radeon_i2c_bus_rec i2c_bus;
2201
2202 /* add the i2c bus for thermal/fan chip */
2203 if (controller->ucType > 0) {
2204 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2205 DRM_INFO("Internal thermal controller %s fan control\n",
2206 (controller->ucFanParameters &
2207 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2208 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2209 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2210 DRM_INFO("Internal thermal controller %s fan control\n",
2211 (controller->ucFanParameters &
2212 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2213 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2214 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2215 DRM_INFO("Internal thermal controller %s fan control\n",
2216 (controller->ucFanParameters &
2217 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2218 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2219 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2220 DRM_INFO("Internal thermal controller %s fan control\n",
2221 (controller->ucFanParameters &
2222 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2223 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2224 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2225 DRM_INFO("Internal thermal controller %s fan control\n",
2226 (controller->ucFanParameters &
2227 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2228 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2229 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2230 DRM_INFO("Internal thermal controller %s fan control\n",
2231 (controller->ucFanParameters &
2232 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2233 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2234 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2235 DRM_INFO("Internal thermal controller %s fan control\n",
2236 (controller->ucFanParameters &
2237 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2238 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2239 } else if ((controller->ucType ==
2240 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2241 (controller->ucType ==
2242 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2243 (controller->ucType ==
2244 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2245 DRM_INFO("Special thermal controller config\n");
2246 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2247 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2248 pp_lib_thermal_controller_names[controller->ucType],
2249 controller->ucI2cAddress >> 1,
2250 (controller->ucFanParameters &
2251 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2252 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2253 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2254 if (rdev->pm.i2c_bus) {
2255 struct i2c_board_info info = { };
2256 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2257 info.addr = controller->ucI2cAddress >> 1;
2258 strlcpy(info.type, name, sizeof(info.type));
2259 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2260 }
2261 } else {
2262 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2263 controller->ucType,
2264 controller->ucI2cAddress >> 1,
2265 (controller->ucFanParameters &
2266 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2267 }
2268 }
2269 }
2270
2271 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2272 u16 *vddc, u16 *vddci)
2273 {
2274 struct radeon_mode_info *mode_info = &rdev->mode_info;
2275 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2276 u8 frev, crev;
2277 u16 data_offset;
2278 union firmware_info *firmware_info;
2279
2280 *vddc = 0;
2281 *vddci = 0;
2282
2283 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2284 &frev, &crev, &data_offset)) {
2285 firmware_info =
2286 (union firmware_info *)(mode_info->atom_context->bios +
2287 data_offset);
2288 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2289 if ((frev == 2) && (crev >= 2))
2290 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2291 }
2292 }
2293
2294 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2295 int state_index, int mode_index,
2296 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2297 {
2298 int j;
2299 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2300 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2301 u16 vddc, vddci;
2302
2303 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2304
2305 rdev->pm.power_state[state_index].misc = misc;
2306 rdev->pm.power_state[state_index].misc2 = misc2;
2307 rdev->pm.power_state[state_index].pcie_lanes =
2308 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2309 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2310 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2311 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2312 rdev->pm.power_state[state_index].type =
2313 POWER_STATE_TYPE_BATTERY;
2314 break;
2315 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2316 rdev->pm.power_state[state_index].type =
2317 POWER_STATE_TYPE_BALANCED;
2318 break;
2319 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2320 rdev->pm.power_state[state_index].type =
2321 POWER_STATE_TYPE_PERFORMANCE;
2322 break;
2323 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2324 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2325 rdev->pm.power_state[state_index].type =
2326 POWER_STATE_TYPE_PERFORMANCE;
2327 break;
2328 }
2329 rdev->pm.power_state[state_index].flags = 0;
2330 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2331 rdev->pm.power_state[state_index].flags |=
2332 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2333 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2334 rdev->pm.power_state[state_index].type =
2335 POWER_STATE_TYPE_DEFAULT;
2336 rdev->pm.default_power_state_index = state_index;
2337 rdev->pm.power_state[state_index].default_clock_mode =
2338 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2339 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2340 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2341 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2342 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2343 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2344 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2345 } else {
2346 u16 max_vddci = 0;
2347
2348 if (ASIC_IS_DCE4(rdev))
2349 radeon_atom_get_max_voltage(rdev,
2350 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2351 &max_vddci);
2352 /* patch the table values with the default sclk/mclk from firmware info */
2353 for (j = 0; j < mode_index; j++) {
2354 rdev->pm.power_state[state_index].clock_info[j].mclk =
2355 rdev->clock.default_mclk;
2356 rdev->pm.power_state[state_index].clock_info[j].sclk =
2357 rdev->clock.default_sclk;
2358 if (vddc)
2359 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2360 vddc;
2361 if (max_vddci)
2362 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2363 max_vddci;
2364 }
2365 }
2366 }
2367 }
2368
2369 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2370 int state_index, int mode_index,
2371 union pplib_clock_info *clock_info)
2372 {
2373 u32 sclk, mclk;
2374 u16 vddc;
2375
2376 if (rdev->flags & RADEON_IS_IGP) {
2377 if (rdev->family >= CHIP_PALM) {
2378 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2379 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2380 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2381 } else {
2382 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2383 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2384 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2385 }
2386 } else if (rdev->family >= CHIP_BONAIRE) {
2387 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2388 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2389 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2390 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2391 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2392 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2393 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2394 VOLTAGE_NONE;
2395 } else if (rdev->family >= CHIP_TAHITI) {
2396 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2397 sclk |= clock_info->si.ucEngineClockHigh << 16;
2398 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2399 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2400 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2401 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2402 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2403 VOLTAGE_SW;
2404 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2405 le16_to_cpu(clock_info->si.usVDDC);
2406 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2407 le16_to_cpu(clock_info->si.usVDDCI);
2408 } else if (rdev->family >= CHIP_CEDAR) {
2409 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2410 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2411 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2412 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2413 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2414 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2415 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2416 VOLTAGE_SW;
2417 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2418 le16_to_cpu(clock_info->evergreen.usVDDC);
2419 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2420 le16_to_cpu(clock_info->evergreen.usVDDCI);
2421 } else {
2422 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2423 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2424 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2425 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2426 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2427 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2428 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2429 VOLTAGE_SW;
2430 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2431 le16_to_cpu(clock_info->r600.usVDDC);
2432 }
2433
2434 /* patch up vddc if necessary */
2435 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2436 case ATOM_VIRTUAL_VOLTAGE_ID0:
2437 case ATOM_VIRTUAL_VOLTAGE_ID1:
2438 case ATOM_VIRTUAL_VOLTAGE_ID2:
2439 case ATOM_VIRTUAL_VOLTAGE_ID3:
2440 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2441 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2442 &vddc) == 0)
2443 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2444 break;
2445 default:
2446 break;
2447 }
2448
2449 if (rdev->flags & RADEON_IS_IGP) {
2450 /* skip invalid modes */
2451 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2452 return false;
2453 } else {
2454 /* skip invalid modes */
2455 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2456 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2457 return false;
2458 }
2459 return true;
2460 }
2461
2462 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2463 {
2464 struct radeon_mode_info *mode_info = &rdev->mode_info;
2465 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2466 union pplib_power_state *power_state;
2467 int i, j;
2468 int state_index = 0, mode_index = 0;
2469 union pplib_clock_info *clock_info;
2470 bool valid;
2471 union power_info *power_info;
2472 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2473 u16 data_offset;
2474 u8 frev, crev;
2475
2476 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2477 &frev, &crev, &data_offset))
2478 return state_index;
2479 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2480
2481 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2482 if (power_info->pplib.ucNumStates == 0)
2483 return state_index;
2484 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2485 power_info->pplib.ucNumStates, GFP_KERNEL);
2486 if (!rdev->pm.power_state)
2487 return state_index;
2488 /* first mode is usually default, followed by low to high */
2489 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2490 mode_index = 0;
2491 power_state = (union pplib_power_state *)
2492 (mode_info->atom_context->bios + data_offset +
2493 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2494 i * power_info->pplib.ucStateEntrySize);
2495 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2496 (mode_info->atom_context->bios + data_offset +
2497 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2498 (power_state->v1.ucNonClockStateIndex *
2499 power_info->pplib.ucNonClockSize));
2500 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2501 ((power_info->pplib.ucStateEntrySize - 1) ?
2502 (power_info->pplib.ucStateEntrySize - 1) : 1),
2503 GFP_KERNEL);
2504 if (!rdev->pm.power_state[i].clock_info)
2505 return state_index;
2506 if (power_info->pplib.ucStateEntrySize - 1) {
2507 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2508 clock_info = (union pplib_clock_info *)
2509 (mode_info->atom_context->bios + data_offset +
2510 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2511 (power_state->v1.ucClockStateIndices[j] *
2512 power_info->pplib.ucClockInfoSize));
2513 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2514 state_index, mode_index,
2515 clock_info);
2516 if (valid)
2517 mode_index++;
2518 }
2519 } else {
2520 rdev->pm.power_state[state_index].clock_info[0].mclk =
2521 rdev->clock.default_mclk;
2522 rdev->pm.power_state[state_index].clock_info[0].sclk =
2523 rdev->clock.default_sclk;
2524 mode_index++;
2525 }
2526 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2527 if (mode_index) {
2528 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2529 non_clock_info);
2530 state_index++;
2531 }
2532 }
2533 /* if multiple clock modes, mark the lowest as no display */
2534 for (i = 0; i < state_index; i++) {
2535 if (rdev->pm.power_state[i].num_clock_modes > 1)
2536 rdev->pm.power_state[i].clock_info[0].flags |=
2537 RADEON_PM_MODE_NO_DISPLAY;
2538 }
2539 /* first mode is usually default */
2540 if (rdev->pm.default_power_state_index == -1) {
2541 rdev->pm.power_state[0].type =
2542 POWER_STATE_TYPE_DEFAULT;
2543 rdev->pm.default_power_state_index = 0;
2544 rdev->pm.power_state[0].default_clock_mode =
2545 &rdev->pm.power_state[0].clock_info[0];
2546 }
2547 return state_index;
2548 }
2549
2550 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2551 {
2552 struct radeon_mode_info *mode_info = &rdev->mode_info;
2553 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2554 union pplib_power_state *power_state;
2555 int i, j, non_clock_array_index, clock_array_index;
2556 int state_index = 0, mode_index = 0;
2557 union pplib_clock_info *clock_info;
2558 struct _StateArray *state_array;
2559 struct _ClockInfoArray *clock_info_array;
2560 struct _NonClockInfoArray *non_clock_info_array;
2561 bool valid;
2562 union power_info *power_info;
2563 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2564 u16 data_offset;
2565 u8 frev, crev;
2566 u8 *power_state_offset;
2567
2568 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2569 &frev, &crev, &data_offset))
2570 return state_index;
2571 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2572
2573 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2574 state_array = (struct _StateArray *)
2575 (mode_info->atom_context->bios + data_offset +
2576 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2577 clock_info_array = (struct _ClockInfoArray *)
2578 (mode_info->atom_context->bios + data_offset +
2579 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2580 non_clock_info_array = (struct _NonClockInfoArray *)
2581 (mode_info->atom_context->bios + data_offset +
2582 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2583 if (state_array->ucNumEntries == 0)
2584 return state_index;
2585 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2586 state_array->ucNumEntries, GFP_KERNEL);
2587 if (!rdev->pm.power_state)
2588 return state_index;
2589 power_state_offset = (u8 *)state_array->states;
2590 for (i = 0; i < state_array->ucNumEntries; i++) {
2591 mode_index = 0;
2592 power_state = (union pplib_power_state *)power_state_offset;
2593 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2594 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2595 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2596 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2597 (power_state->v2.ucNumDPMLevels ?
2598 power_state->v2.ucNumDPMLevels : 1),
2599 GFP_KERNEL);
2600 if (!rdev->pm.power_state[i].clock_info)
2601 return state_index;
2602 if (power_state->v2.ucNumDPMLevels) {
2603 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2604 clock_array_index = power_state->v2.clockInfoIndex[j];
2605 clock_info = (union pplib_clock_info *)
2606 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2607 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2608 state_index, mode_index,
2609 clock_info);
2610 if (valid)
2611 mode_index++;
2612 }
2613 } else {
2614 rdev->pm.power_state[state_index].clock_info[0].mclk =
2615 rdev->clock.default_mclk;
2616 rdev->pm.power_state[state_index].clock_info[0].sclk =
2617 rdev->clock.default_sclk;
2618 mode_index++;
2619 }
2620 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2621 if (mode_index) {
2622 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2623 non_clock_info);
2624 state_index++;
2625 }
2626 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2627 }
2628 /* if multiple clock modes, mark the lowest as no display */
2629 for (i = 0; i < state_index; i++) {
2630 if (rdev->pm.power_state[i].num_clock_modes > 1)
2631 rdev->pm.power_state[i].clock_info[0].flags |=
2632 RADEON_PM_MODE_NO_DISPLAY;
2633 }
2634 /* first mode is usually default */
2635 if (rdev->pm.default_power_state_index == -1) {
2636 rdev->pm.power_state[0].type =
2637 POWER_STATE_TYPE_DEFAULT;
2638 rdev->pm.default_power_state_index = 0;
2639 rdev->pm.power_state[0].default_clock_mode =
2640 &rdev->pm.power_state[0].clock_info[0];
2641 }
2642 return state_index;
2643 }
2644
2645 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2646 {
2647 struct radeon_mode_info *mode_info = &rdev->mode_info;
2648 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2649 u16 data_offset;
2650 u8 frev, crev;
2651 int state_index = 0;
2652
2653 rdev->pm.default_power_state_index = -1;
2654
2655 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2656 &frev, &crev, &data_offset)) {
2657 switch (frev) {
2658 case 1:
2659 case 2:
2660 case 3:
2661 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2662 break;
2663 case 4:
2664 case 5:
2665 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2666 break;
2667 case 6:
2668 state_index = radeon_atombios_parse_power_table_6(rdev);
2669 break;
2670 default:
2671 break;
2672 }
2673 }
2674
2675 if (state_index == 0) {
2676 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2677 if (rdev->pm.power_state) {
2678 rdev->pm.power_state[0].clock_info =
2679 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2680 if (rdev->pm.power_state[0].clock_info) {
2681 /* add the default mode */
2682 rdev->pm.power_state[state_index].type =
2683 POWER_STATE_TYPE_DEFAULT;
2684 rdev->pm.power_state[state_index].num_clock_modes = 1;
2685 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2686 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2687 rdev->pm.power_state[state_index].default_clock_mode =
2688 &rdev->pm.power_state[state_index].clock_info[0];
2689 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2690 rdev->pm.power_state[state_index].pcie_lanes = 16;
2691 rdev->pm.default_power_state_index = state_index;
2692 rdev->pm.power_state[state_index].flags = 0;
2693 state_index++;
2694 }
2695 }
2696 }
2697
2698 rdev->pm.num_power_states = state_index;
2699
2700 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2701 rdev->pm.current_clock_mode_index = 0;
2702 if (rdev->pm.default_power_state_index >= 0)
2703 rdev->pm.current_vddc =
2704 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2705 else
2706 rdev->pm.current_vddc = 0;
2707 }
2708
2709 union get_clock_dividers {
2710 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2711 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2712 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2713 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2714 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2715 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2716 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2717 };
2718
2719 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2720 u8 clock_type,
2721 u32 clock,
2722 bool strobe_mode,
2723 struct atom_clock_dividers *dividers)
2724 {
2725 union get_clock_dividers args;
2726 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2727 u8 frev, crev;
2728
2729 memset(&args, 0, sizeof(args));
2730 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2731
2732 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2733 return -EINVAL;
2734
2735 switch (crev) {
2736 case 1:
2737 /* r4xx, r5xx */
2738 args.v1.ucAction = clock_type;
2739 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2740
2741 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2742
2743 dividers->post_div = args.v1.ucPostDiv;
2744 dividers->fb_div = args.v1.ucFbDiv;
2745 dividers->enable_post_div = true;
2746 break;
2747 case 2:
2748 case 3:
2749 case 5:
2750 /* r6xx, r7xx, evergreen, ni, si */
2751 if (rdev->family <= CHIP_RV770) {
2752 args.v2.ucAction = clock_type;
2753 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2754
2755 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2756
2757 dividers->post_div = args.v2.ucPostDiv;
2758 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2759 dividers->ref_div = args.v2.ucAction;
2760 if (rdev->family == CHIP_RV770) {
2761 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2762 true : false;
2763 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2764 } else
2765 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2766 } else {
2767 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2768 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2769
2770 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2771
2772 dividers->post_div = args.v3.ucPostDiv;
2773 dividers->enable_post_div = (args.v3.ucCntlFlag &
2774 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2775 dividers->enable_dithen = (args.v3.ucCntlFlag &
2776 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2777 dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2778 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2779 dividers->ref_div = args.v3.ucRefDiv;
2780 dividers->vco_mode = (args.v3.ucCntlFlag &
2781 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2782 } else {
2783 /* for SI we use ComputeMemoryClockParam for memory plls */
2784 if (rdev->family >= CHIP_TAHITI)
2785 return -EINVAL;
2786 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2787 if (strobe_mode)
2788 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2789
2790 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2791
2792 dividers->post_div = args.v5.ucPostDiv;
2793 dividers->enable_post_div = (args.v5.ucCntlFlag &
2794 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2795 dividers->enable_dithen = (args.v5.ucCntlFlag &
2796 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2797 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2798 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2799 dividers->ref_div = args.v5.ucRefDiv;
2800 dividers->vco_mode = (args.v5.ucCntlFlag &
2801 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2802 }
2803 }
2804 break;
2805 case 4:
2806 /* fusion */
2807 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2808
2809 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2810
2811 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2812 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2813 break;
2814 case 6:
2815 /* CI */
2816 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2817 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2818 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2819
2820 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2821
2822 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2823 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2824 dividers->ref_div = args.v6_out.ucPllRefDiv;
2825 dividers->post_div = args.v6_out.ucPllPostDiv;
2826 dividers->flags = args.v6_out.ucPllCntlFlag;
2827 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2828 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2829 break;
2830 default:
2831 return -EINVAL;
2832 }
2833 return 0;
2834 }
2835
2836 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2837 {
2838 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2839 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2840
2841 args.ucEnable = enable;
2842
2843 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2844 }
2845
2846 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2847 {
2848 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2849 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2850
2851 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2852 return le32_to_cpu(args.ulReturnEngineClock);
2853 }
2854
2855 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2856 {
2857 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2858 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2859
2860 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2861 return le32_to_cpu(args.ulReturnMemoryClock);
2862 }
2863
2864 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2865 uint32_t eng_clock)
2866 {
2867 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2868 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2869
2870 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2871
2872 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2873 }
2874
2875 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2876 uint32_t mem_clock)
2877 {
2878 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2879 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2880
2881 if (rdev->flags & RADEON_IS_IGP)
2882 return;
2883
2884 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2885
2886 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2887 }
2888
2889 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
2890 u32 eng_clock, u32 mem_clock)
2891 {
2892 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2893 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2894 u32 tmp;
2895
2896 memset(&args, 0, sizeof(args));
2897
2898 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
2899 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
2900
2901 args.ulTargetEngineClock = cpu_to_le32(tmp);
2902 if (mem_clock)
2903 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
2904
2905 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2906 }
2907
2908 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
2909 u32 mem_clock)
2910 {
2911 u32 args;
2912 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2913
2914 args = cpu_to_le32(mem_clock); /* 10 khz */
2915
2916 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2917 }
2918
2919 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
2920 u32 mem_clock)
2921 {
2922 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2923 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2924 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
2925
2926 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
2927
2928 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2929 }
2930
2931 union set_voltage {
2932 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2933 struct _SET_VOLTAGE_PARAMETERS v1;
2934 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2935 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2936 };
2937
2938 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2939 {
2940 union set_voltage args;
2941 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2942 u8 frev, crev, volt_index = voltage_level;
2943
2944 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2945 return;
2946
2947 /* 0xff01 is a flag rather then an actual voltage */
2948 if (voltage_level == 0xff01)
2949 return;
2950
2951 switch (crev) {
2952 case 1:
2953 args.v1.ucVoltageType = voltage_type;
2954 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2955 args.v1.ucVoltageIndex = volt_index;
2956 break;
2957 case 2:
2958 args.v2.ucVoltageType = voltage_type;
2959 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2960 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2961 break;
2962 case 3:
2963 args.v3.ucVoltageType = voltage_type;
2964 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2965 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2966 break;
2967 default:
2968 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2969 return;
2970 }
2971
2972 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2973 }
2974
2975 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2976 u16 voltage_id, u16 *voltage)
2977 {
2978 union set_voltage args;
2979 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2980 u8 frev, crev;
2981
2982 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2983 return -EINVAL;
2984
2985 switch (crev) {
2986 case 1:
2987 return -EINVAL;
2988 case 2:
2989 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2990 args.v2.ucVoltageMode = 0;
2991 args.v2.usVoltageLevel = 0;
2992
2993 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2994
2995 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2996 break;
2997 case 3:
2998 args.v3.ucVoltageType = voltage_type;
2999 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3000 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3001
3002 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3003
3004 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3005 break;
3006 default:
3007 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3008 return -EINVAL;
3009 }
3010
3011 return 0;
3012 }
3013
3014 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3015 u16 voltage_level, u8 voltage_type,
3016 u32 *gpio_value, u32 *gpio_mask)
3017 {
3018 union set_voltage args;
3019 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3020 u8 frev, crev;
3021
3022 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3023 return -EINVAL;
3024
3025 switch (crev) {
3026 case 1:
3027 return -EINVAL;
3028 case 2:
3029 args.v2.ucVoltageType = voltage_type;
3030 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3031 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3032
3033 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3034
3035 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3036
3037 args.v2.ucVoltageType = voltage_type;
3038 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3039 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3040
3041 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3042
3043 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3044 break;
3045 default:
3046 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3047 return -EINVAL;
3048 }
3049
3050 return 0;
3051 }
3052
3053 union voltage_object_info {
3054 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3055 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3056 };
3057
3058 bool
3059 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, u8 voltage_type)
3060 {
3061 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3062 u8 frev, crev;
3063 u16 data_offset, size;
3064 int num_indices, i;
3065 union voltage_object_info *voltage_info;
3066
3067 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3068 &frev, &crev, &data_offset)) {
3069 voltage_info = (union voltage_object_info *)
3070 (rdev->mode_info.atom_context->bios + data_offset);
3071
3072 switch (crev) {
3073 case 1:
3074 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3075 sizeof(ATOM_VOLTAGE_OBJECT);
3076
3077 for (i = 0; i < num_indices; i++) {
3078 if ((voltage_info->v1.asVoltageObj[i].ucVoltageType == voltage_type) &&
3079 (voltage_info->v1.asVoltageObj[i].asControl.ucVoltageControlId ==
3080 VOLTAGE_CONTROLLED_BY_GPIO))
3081 return true;
3082 }
3083 break;
3084 case 2:
3085 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3086 sizeof(ATOM_VOLTAGE_OBJECT_INFO_V2);
3087
3088 for (i = 0; i < num_indices; i++) {
3089 if ((voltage_info->v2.asVoltageObj[i].ucVoltageType == voltage_type) &&
3090 (voltage_info->v2.asVoltageObj[i].asControl.ucVoltageControlId ==
3091 VOLTAGE_CONTROLLED_BY_GPIO))
3092 return true;
3093 }
3094 break;
3095 default:
3096 DRM_ERROR("unknown voltage object table\n");
3097 return false;
3098 }
3099
3100 }
3101 return false;
3102 }
3103
3104 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3105 u8 voltage_type, u16 *max_voltage)
3106 {
3107 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3108 u8 frev, crev;
3109 u16 data_offset, size;
3110 int num_indices, i;
3111 union voltage_object_info *voltage_info;
3112
3113 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3114 &frev, &crev, &data_offset)) {
3115 voltage_info = (union voltage_object_info *)
3116 (rdev->mode_info.atom_context->bios + data_offset);
3117
3118 switch (crev) {
3119 case 1:
3120 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3121 sizeof(ATOM_VOLTAGE_OBJECT);
3122
3123 for (i = 0; i < num_indices; i++) {
3124 if (voltage_info->v1.asVoltageObj[i].ucVoltageType == voltage_type) {
3125 ATOM_VOLTAGE_FORMULA *formula =
3126 &voltage_info->v1.asVoltageObj[i].asFormula;
3127 if (formula->ucFlag & 1)
3128 *max_voltage =
3129 le16_to_cpu(formula->usVoltageBaseLevel) +
3130 formula->ucNumOfVoltageEntries / 2 *
3131 le16_to_cpu(formula->usVoltageStep);
3132 else
3133 *max_voltage =
3134 le16_to_cpu(formula->usVoltageBaseLevel) +
3135 (formula->ucNumOfVoltageEntries - 1) *
3136 le16_to_cpu(formula->usVoltageStep);
3137 return 0;
3138 }
3139 }
3140 break;
3141 case 2:
3142 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3143 sizeof(ATOM_VOLTAGE_OBJECT_INFO_V2);
3144
3145 for (i = 0; i < num_indices; i++) {
3146 if (voltage_info->v2.asVoltageObj[i].ucVoltageType == voltage_type) {
3147 ATOM_VOLTAGE_FORMULA_V2 *formula =
3148 &voltage_info->v2.asVoltageObj[i].asFormula;
3149 if (formula->ucNumOfVoltageEntries) {
3150 *max_voltage =
3151 le16_to_cpu(formula->asVIDAdjustEntries[
3152 formula->ucNumOfVoltageEntries - 1
3153 ].usVoltageValue);
3154 return 0;
3155 }
3156 }
3157 }
3158 break;
3159 default:
3160 DRM_ERROR("unknown voltage object table\n");
3161 return -EINVAL;
3162 }
3163
3164 }
3165 return -EINVAL;
3166 }
3167
3168 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3169 u8 voltage_type, u16 *min_voltage)
3170 {
3171 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3172 u8 frev, crev;
3173 u16 data_offset, size;
3174 int num_indices, i;
3175 union voltage_object_info *voltage_info;
3176
3177 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3178 &frev, &crev, &data_offset)) {
3179 voltage_info = (union voltage_object_info *)
3180 (rdev->mode_info.atom_context->bios + data_offset);
3181
3182 switch (crev) {
3183 case 1:
3184 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3185 sizeof(ATOM_VOLTAGE_OBJECT);
3186
3187 for (i = 0; i < num_indices; i++) {
3188 if (voltage_info->v1.asVoltageObj[i].ucVoltageType == voltage_type) {
3189 ATOM_VOLTAGE_FORMULA *formula =
3190 &voltage_info->v1.asVoltageObj[i].asFormula;
3191 *min_voltage =
3192 le16_to_cpu(formula->usVoltageBaseLevel);
3193 return 0;
3194 }
3195 }
3196 break;
3197 case 2:
3198 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3199 sizeof(ATOM_VOLTAGE_OBJECT_INFO_V2);
3200
3201 for (i = 0; i < num_indices; i++) {
3202 if (voltage_info->v2.asVoltageObj[i].ucVoltageType == voltage_type) {
3203 ATOM_VOLTAGE_FORMULA_V2 *formula =
3204 &voltage_info->v2.asVoltageObj[i].asFormula;
3205 if (formula->ucNumOfVoltageEntries) {
3206 *min_voltage =
3207 le16_to_cpu(formula->asVIDAdjustEntries[
3208 0
3209 ].usVoltageValue);
3210 return 0;
3211 }
3212 }
3213 }
3214 break;
3215 default:
3216 DRM_ERROR("unknown voltage object table\n");
3217 return -EINVAL;
3218 }
3219
3220 }
3221 return -EINVAL;
3222 }
3223
3224 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3225 u8 voltage_type, u16 *voltage_step)
3226 {
3227 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3228 u8 frev, crev;
3229 u16 data_offset, size;
3230 int num_indices, i;
3231 union voltage_object_info *voltage_info;
3232
3233 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3234 &frev, &crev, &data_offset)) {
3235 voltage_info = (union voltage_object_info *)
3236 (rdev->mode_info.atom_context->bios + data_offset);
3237
3238 switch (crev) {
3239 case 1:
3240 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3241 sizeof(ATOM_VOLTAGE_OBJECT);
3242
3243 for (i = 0; i < num_indices; i++) {
3244 if (voltage_info->v1.asVoltageObj[i].ucVoltageType == voltage_type) {
3245 ATOM_VOLTAGE_FORMULA *formula =
3246 &voltage_info->v1.asVoltageObj[i].asFormula;
3247 if (formula->ucFlag & 1)
3248 *voltage_step =
3249 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3250 else
3251 *voltage_step =
3252 le16_to_cpu(formula->usVoltageStep);
3253 return 0;
3254 }
3255 }
3256 break;
3257 case 2:
3258 return -EINVAL;
3259 default:
3260 DRM_ERROR("unknown voltage object table\n");
3261 return -EINVAL;
3262 }
3263
3264 }
3265 return -EINVAL;
3266 }
3267
3268 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3269 u8 voltage_type,
3270 u16 nominal_voltage,
3271 u16 *true_voltage)
3272 {
3273 u16 min_voltage, max_voltage, voltage_step;
3274
3275 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3276 return -EINVAL;
3277 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3278 return -EINVAL;
3279 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3280 return -EINVAL;
3281
3282 if (nominal_voltage <= min_voltage)
3283 *true_voltage = min_voltage;
3284 else if (nominal_voltage >= max_voltage)
3285 *true_voltage = max_voltage;
3286 else
3287 *true_voltage = min_voltage +
3288 ((nominal_voltage - min_voltage) / voltage_step) *
3289 voltage_step;
3290
3291 return 0;
3292 }
3293
3294 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3295 u8 voltage_type,
3296 struct atom_voltage_table *voltage_table)
3297 {
3298 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3299 u8 frev, crev;
3300 u16 data_offset, size;
3301 int num_indices, i, j, ret;
3302 union voltage_object_info *voltage_info;
3303
3304 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3305 &frev, &crev, &data_offset)) {
3306 voltage_info = (union voltage_object_info *)
3307 (rdev->mode_info.atom_context->bios + data_offset);
3308
3309 switch (crev) {
3310 case 1:
3311 DRM_ERROR("old table version %d, %d\n", frev, crev);
3312 return -EINVAL;
3313 case 2:
3314 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
3315 sizeof(ATOM_VOLTAGE_OBJECT_INFO_V2);
3316
3317 for (i = 0; i < num_indices; i++) {
3318 if (voltage_info->v2.asVoltageObj[i].ucVoltageType == voltage_type) {
3319 ATOM_VOLTAGE_FORMULA_V2 *formula =
3320 &voltage_info->v2.asVoltageObj[i].asFormula;
3321 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3322 return -EINVAL;
3323 for (j = 0; j < formula->ucNumOfVoltageEntries; j++) {
3324 voltage_table->entries[j].value =
3325 le16_to_cpu(formula->asVIDAdjustEntries[j].usVoltageValue);
3326 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3327 voltage_table->entries[j].value,
3328 voltage_type,
3329 &voltage_table->entries[j].smio_low,
3330 &voltage_table->mask_low);
3331 if (ret)
3332 return ret;
3333 }
3334 voltage_table->count = formula->ucNumOfVoltageEntries;
3335 return 0;
3336 }
3337 }
3338 break;
3339 default:
3340 DRM_ERROR("unknown voltage object table\n");
3341 return -EINVAL;
3342 }
3343
3344 }
3345 return -EINVAL;
3346 }
3347
3348 union vram_info {
3349 struct _ATOM_VRAM_INFO_V3 v1_3;
3350 struct _ATOM_VRAM_INFO_V4 v1_4;
3351 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3352 };
3353
3354 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3355 u8 module_index, struct atom_memory_info *mem_info)
3356 {
3357 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3358 u8 frev, crev, i;
3359 u16 data_offset, size;
3360 union vram_info *vram_info;
3361 u8 *p;
3362
3363 memset(mem_info, 0, sizeof(struct atom_memory_info));
3364
3365 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3366 &frev, &crev, &data_offset)) {
3367 vram_info = (union vram_info *)
3368 (rdev->mode_info.atom_context->bios + data_offset);
3369 switch (frev) {
3370 case 1:
3371 switch (crev) {
3372 case 3:
3373 /* r6xx */
3374 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3375 ATOM_VRAM_MODULE_V3 *vram_module =
3376 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3377 p = (u8 *)vram_info->v1_3.aVramInfo;
3378
3379 for (i = 0; i < module_index; i++) {
3380 vram_module = (ATOM_VRAM_MODULE_V3 *)p;
3381 if (le16_to_cpu(vram_module->usSize) == 0)
3382 return -EINVAL;
3383 p += le16_to_cpu(vram_module->usSize);
3384 }
3385 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3386 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3387 } else
3388 return -EINVAL;
3389 break;
3390 case 4:
3391 /* r7xx, evergreen */
3392 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3393 ATOM_VRAM_MODULE_V4 *vram_module =
3394 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3395 p = (u8 *)vram_info->v1_4.aVramInfo;
3396
3397 for (i = 0; i < module_index; i++) {
3398 vram_module = (ATOM_VRAM_MODULE_V4 *)p;
3399 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3400 return -EINVAL;
3401 p += le16_to_cpu(vram_module->usModuleSize);
3402 }
3403 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3404 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3405 } else
3406 return -EINVAL;
3407 break;
3408 default:
3409 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3410 return -EINVAL;
3411 }
3412 break;
3413 case 2:
3414 switch (crev) {
3415 case 1:
3416 /* ni */
3417 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3418 ATOM_VRAM_MODULE_V7 *vram_module =
3419 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3420 p = (u8 *)vram_info->v2_1.aVramInfo;
3421
3422 for (i = 0; i < module_index; i++) {
3423 vram_module = (ATOM_VRAM_MODULE_V7 *)p;
3424 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3425 return -EINVAL;
3426 p += le16_to_cpu(vram_module->usModuleSize);
3427 }
3428 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3429 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3430 } else
3431 return -EINVAL;
3432 break;
3433 default:
3434 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3435 return -EINVAL;
3436 }
3437 break;
3438 default:
3439 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3440 return -EINVAL;
3441 }
3442 return 0;
3443 }
3444 return -EINVAL;
3445 }
3446
3447 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3448 bool gddr5, u8 module_index,
3449 struct atom_memory_clock_range_table *mclk_range_table)
3450 {
3451 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3452 u8 frev, crev, i;
3453 u16 data_offset, size;
3454 union vram_info *vram_info;
3455 u32 mem_timing_size = gddr5 ?
3456 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3457 u8 *p;
3458
3459 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3460
3461 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3462 &frev, &crev, &data_offset)) {
3463 vram_info = (union vram_info *)
3464 (rdev->mode_info.atom_context->bios + data_offset);
3465 switch (frev) {
3466 case 1:
3467 switch (crev) {
3468 case 3:
3469 DRM_ERROR("old table version %d, %d\n", frev, crev);
3470 return -EINVAL;
3471 case 4:
3472 /* r7xx, evergreen */
3473 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3474 ATOM_VRAM_MODULE_V4 *vram_module =
3475 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3476 ATOM_MEMORY_TIMING_FORMAT *format;
3477 p = (u8 *)vram_info->v1_4.aVramInfo;
3478
3479 for (i = 0; i < module_index; i++) {
3480 vram_module = (ATOM_VRAM_MODULE_V4 *)p;
3481 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3482 return -EINVAL;
3483 p += le16_to_cpu(vram_module->usModuleSize);
3484 }
3485 mclk_range_table->num_entries = (u8)
3486 ((vram_module->usModuleSize - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3487 mem_timing_size);
3488 p = (u8 *)vram_module->asMemTiming;
3489 for (i = 0; i < mclk_range_table->num_entries; i++) {
3490 format = (ATOM_MEMORY_TIMING_FORMAT *)p;
3491 mclk_range_table->mclk[i] = format->ulClkRange;
3492 p += mem_timing_size;
3493 }
3494 } else
3495 return -EINVAL;
3496 break;
3497 default:
3498 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3499 return -EINVAL;
3500 }
3501 break;
3502 case 2:
3503 DRM_ERROR("new table version %d, %d\n", frev, crev);
3504 return -EINVAL;
3505 default:
3506 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3507 return -EINVAL;
3508 }
3509 return 0;
3510 }
3511 return -EINVAL;
3512 }
3513
3514 #define MEM_ID_MASK 0xff000000
3515 #define MEM_ID_SHIFT 24
3516 #define CLOCK_RANGE_MASK 0x00ffffff
3517 #define CLOCK_RANGE_SHIFT 0
3518 #define LOW_NIBBLE_MASK 0xf
3519 #define DATA_EQU_PREV 0
3520 #define DATA_FROM_TABLE 4
3521
3522 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3523 u8 module_index,
3524 struct atom_mc_reg_table *reg_table)
3525 {
3526 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3527 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3528 u32 i = 0, j;
3529 u16 data_offset, size;
3530 union vram_info *vram_info;
3531
3532 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3533
3534 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3535 &frev, &crev, &data_offset)) {
3536 vram_info = (union vram_info *)
3537 (rdev->mode_info.atom_context->bios + data_offset);
3538 switch (frev) {
3539 case 1:
3540 DRM_ERROR("old table version %d, %d\n", frev, crev);
3541 return -EINVAL;
3542 case 2:
3543 switch (crev) {
3544 case 1:
3545 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3546 ATOM_INIT_REG_BLOCK *reg_block =
3547 (ATOM_INIT_REG_BLOCK *)
3548 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3549 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3550 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3551 ((u8 *)reg_block + (2 * sizeof(u16)) +
3552 le16_to_cpu(reg_block->usRegIndexTblSize));
3553 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3554 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3555 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3556 return -EINVAL;
3557 while (!(reg_block->asRegIndexBuf[i].ucPreRegDataLength & ACCESS_PLACEHOLDER) &&
3558 (i < num_entries)) {
3559 reg_table->mc_reg_address[i].s1 =
3560 (u16)(reg_block->asRegIndexBuf[i].usRegIndex);
3561 reg_table->mc_reg_address[i].pre_reg_data =
3562 (u8)(reg_block->asRegIndexBuf[i].ucPreRegDataLength);
3563 i++;
3564 }
3565 reg_table->last = i;
3566 while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) &&
3567 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3568 t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
3569 if (module_index == t_mem_id) {
3570 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
3571 (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT);
3572 for (i = 0, j = 1; i < reg_table->last; i++) {
3573 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
3574 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3575 (u32)*((u32 *)reg_data + j);
3576 j++;
3577 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
3578 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3579 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
3580 }
3581 }
3582 num_ranges++;
3583 }
3584 reg_data += reg_block->usRegDataBlkSize;
3585 }
3586 if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK)
3587 return -EINVAL;
3588 reg_table->num_entries = num_ranges;
3589 } else
3590 return -EINVAL;
3591 break;
3592 default:
3593 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3594 return -EINVAL;
3595 }
3596 break;
3597 default:
3598 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3599 return -EINVAL;
3600 }
3601 return 0;
3602 }
3603 return -EINVAL;
3604 }
3605
3606 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
3607 {
3608 struct radeon_device *rdev = dev->dev_private;
3609 uint32_t bios_2_scratch, bios_6_scratch;
3610
3611 if (rdev->family >= CHIP_R600) {
3612 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3613 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3614 } else {
3615 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3616 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3617 }
3618
3619 /* let the bios control the backlight */
3620 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
3621
3622 /* tell the bios not to handle mode switching */
3623 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
3624
3625 if (rdev->family >= CHIP_R600) {
3626 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3627 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3628 } else {
3629 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3630 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3631 }
3632
3633 }
3634
3635 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
3636 {
3637 uint32_t scratch_reg;
3638 int i;
3639
3640 if (rdev->family >= CHIP_R600)
3641 scratch_reg = R600_BIOS_0_SCRATCH;
3642 else
3643 scratch_reg = RADEON_BIOS_0_SCRATCH;
3644
3645 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3646 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
3647 }
3648
3649 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
3650 {
3651 uint32_t scratch_reg;
3652 int i;
3653
3654 if (rdev->family >= CHIP_R600)
3655 scratch_reg = R600_BIOS_0_SCRATCH;
3656 else
3657 scratch_reg = RADEON_BIOS_0_SCRATCH;
3658
3659 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3660 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
3661 }
3662
3663 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
3664 {
3665 struct drm_device *dev = encoder->dev;
3666 struct radeon_device *rdev = dev->dev_private;
3667 uint32_t bios_6_scratch;
3668
3669 if (rdev->family >= CHIP_R600)
3670 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3671 else
3672 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3673
3674 if (lock) {
3675 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
3676 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
3677 } else {
3678 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
3679 bios_6_scratch |= ATOM_S6_ACC_MODE;
3680 }
3681
3682 if (rdev->family >= CHIP_R600)
3683 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3684 else
3685 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3686 }
3687
3688 /* at some point we may want to break this out into individual functions */
3689 void
3690 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
3691 struct drm_encoder *encoder,
3692 bool connected)
3693 {
3694 struct drm_device *dev = connector->dev;
3695 struct radeon_device *rdev = dev->dev_private;
3696 struct radeon_connector *radeon_connector =
3697 to_radeon_connector(connector);
3698 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3699 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
3700
3701 if (rdev->family >= CHIP_R600) {
3702 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
3703 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3704 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3705 } else {
3706 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3707 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3708 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3709 }
3710
3711 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3712 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3713 if (connected) {
3714 DRM_DEBUG_KMS("TV1 connected\n");
3715 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
3716 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
3717 } else {
3718 DRM_DEBUG_KMS("TV1 disconnected\n");
3719 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
3720 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
3721 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
3722 }
3723 }
3724 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
3725 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
3726 if (connected) {
3727 DRM_DEBUG_KMS("CV connected\n");
3728 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
3729 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
3730 } else {
3731 DRM_DEBUG_KMS("CV disconnected\n");
3732 bios_0_scratch &= ~ATOM_S0_CV_MASK;
3733 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
3734 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
3735 }
3736 }
3737 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3738 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3739 if (connected) {
3740 DRM_DEBUG_KMS("LCD1 connected\n");
3741 bios_0_scratch |= ATOM_S0_LCD1;
3742 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
3743 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
3744 } else {
3745 DRM_DEBUG_KMS("LCD1 disconnected\n");
3746 bios_0_scratch &= ~ATOM_S0_LCD1;
3747 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
3748 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
3749 }
3750 }
3751 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3752 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3753 if (connected) {
3754 DRM_DEBUG_KMS("CRT1 connected\n");
3755 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
3756 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
3757 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
3758 } else {
3759 DRM_DEBUG_KMS("CRT1 disconnected\n");
3760 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
3761 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
3762 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
3763 }
3764 }
3765 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3766 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3767 if (connected) {
3768 DRM_DEBUG_KMS("CRT2 connected\n");
3769 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
3770 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
3771 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
3772 } else {
3773 DRM_DEBUG_KMS("CRT2 disconnected\n");
3774 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
3775 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
3776 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
3777 }
3778 }
3779 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3780 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3781 if (connected) {
3782 DRM_DEBUG_KMS("DFP1 connected\n");
3783 bios_0_scratch |= ATOM_S0_DFP1;
3784 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
3785 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
3786 } else {
3787 DRM_DEBUG_KMS("DFP1 disconnected\n");
3788 bios_0_scratch &= ~ATOM_S0_DFP1;
3789 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
3790 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
3791 }
3792 }
3793 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3794 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3795 if (connected) {
3796 DRM_DEBUG_KMS("DFP2 connected\n");
3797 bios_0_scratch |= ATOM_S0_DFP2;
3798 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
3799 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
3800 } else {
3801 DRM_DEBUG_KMS("DFP2 disconnected\n");
3802 bios_0_scratch &= ~ATOM_S0_DFP2;
3803 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
3804 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
3805 }
3806 }
3807 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
3808 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
3809 if (connected) {
3810 DRM_DEBUG_KMS("DFP3 connected\n");
3811 bios_0_scratch |= ATOM_S0_DFP3;
3812 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
3813 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
3814 } else {
3815 DRM_DEBUG_KMS("DFP3 disconnected\n");
3816 bios_0_scratch &= ~ATOM_S0_DFP3;
3817 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
3818 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
3819 }
3820 }
3821 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
3822 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
3823 if (connected) {
3824 DRM_DEBUG_KMS("DFP4 connected\n");
3825 bios_0_scratch |= ATOM_S0_DFP4;
3826 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
3827 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
3828 } else {
3829 DRM_DEBUG_KMS("DFP4 disconnected\n");
3830 bios_0_scratch &= ~ATOM_S0_DFP4;
3831 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
3832 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3833 }
3834 }
3835 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3836 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3837 if (connected) {
3838 DRM_DEBUG_KMS("DFP5 connected\n");
3839 bios_0_scratch |= ATOM_S0_DFP5;
3840 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3841 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3842 } else {
3843 DRM_DEBUG_KMS("DFP5 disconnected\n");
3844 bios_0_scratch &= ~ATOM_S0_DFP5;
3845 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3846 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3847 }
3848 }
3849 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3850 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3851 if (connected) {
3852 DRM_DEBUG_KMS("DFP6 connected\n");
3853 bios_0_scratch |= ATOM_S0_DFP6;
3854 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3855 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3856 } else {
3857 DRM_DEBUG_KMS("DFP6 disconnected\n");
3858 bios_0_scratch &= ~ATOM_S0_DFP6;
3859 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3860 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3861 }
3862 }
3863
3864 if (rdev->family >= CHIP_R600) {
3865 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3866 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3867 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3868 } else {
3869 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3870 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3871 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3872 }
3873 }
3874
3875 void
3876 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3877 {
3878 struct drm_device *dev = encoder->dev;
3879 struct radeon_device *rdev = dev->dev_private;
3880 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3881 uint32_t bios_3_scratch;
3882
3883 if (ASIC_IS_DCE4(rdev))
3884 return;
3885
3886 if (rdev->family >= CHIP_R600)
3887 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3888 else
3889 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3890
3891 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3892 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3893 bios_3_scratch |= (crtc << 18);
3894 }
3895 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3896 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3897 bios_3_scratch |= (crtc << 24);
3898 }
3899 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3900 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3901 bios_3_scratch |= (crtc << 16);
3902 }
3903 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3904 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3905 bios_3_scratch |= (crtc << 20);
3906 }
3907 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3908 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3909 bios_3_scratch |= (crtc << 17);
3910 }
3911 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3912 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3913 bios_3_scratch |= (crtc << 19);
3914 }
3915 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3916 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3917 bios_3_scratch |= (crtc << 23);
3918 }
3919 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3920 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3921 bios_3_scratch |= (crtc << 25);
3922 }
3923
3924 if (rdev->family >= CHIP_R600)
3925 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3926 else
3927 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3928 }
3929
3930 void
3931 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3932 {
3933 struct drm_device *dev = encoder->dev;
3934 struct radeon_device *rdev = dev->dev_private;
3935 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3936 uint32_t bios_2_scratch;
3937
3938 if (ASIC_IS_DCE4(rdev))
3939 return;
3940
3941 if (rdev->family >= CHIP_R600)
3942 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3943 else
3944 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3945
3946 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3947 if (on)
3948 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3949 else
3950 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3951 }
3952 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3953 if (on)
3954 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3955 else
3956 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3957 }
3958 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3959 if (on)
3960 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3961 else
3962 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3963 }
3964 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3965 if (on)
3966 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3967 else
3968 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3969 }
3970 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3971 if (on)
3972 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3973 else
3974 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3975 }
3976 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3977 if (on)
3978 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3979 else
3980 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3981 }
3982 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3983 if (on)
3984 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3985 else
3986 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3987 }
3988 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3989 if (on)
3990 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3991 else
3992 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3993 }
3994 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3995 if (on)
3996 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3997 else
3998 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3999 }
4000 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4001 if (on)
4002 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4003 else
4004 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4005 }
4006
4007 if (rdev->family >= CHIP_R600)
4008 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4009 else
4010 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4011 }
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