2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_reg.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35 #include <linux/acpi.h>
40 /* If you boot an IGP board with a discrete card as the primary,
41 * the IGP rom is not accessible via the rom bar as the IGP rom is
42 * part of the system bios. On boot, the system bios puts a
43 * copy of the igp rom at the start of vram if a discrete card is
46 static bool igp_read_bios_from_vram(struct radeon_device
*rdev
)
48 uint8_t __iomem
*bios
;
49 resource_size_t vram_base
;
50 resource_size_t size
= 256 * 1024; /* ??? */
52 if (!(rdev
->flags
& RADEON_IS_IGP
))
53 if (!radeon_card_posted(rdev
))
57 vram_base
= pci_resource_start(rdev
->pdev
, 0);
58 bios
= ioremap(vram_base
, size
);
63 if (size
== 0 || bios
[0] != 0x55 || bios
[1] != 0xaa) {
67 rdev
->bios
= kmalloc(size
, GFP_KERNEL
);
68 if (rdev
->bios
== NULL
) {
72 memcpy_fromio(rdev
->bios
, bios
, size
);
77 static bool radeon_read_bios(struct radeon_device
*rdev
)
79 uint8_t __iomem
*bios
;
83 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
84 bios
= pci_map_rom(rdev
->pdev
, &size
);
89 if (size
== 0 || bios
[0] != 0x55 || bios
[1] != 0xaa) {
90 pci_unmap_rom(rdev
->pdev
, bios
);
93 rdev
->bios
= kmemdup(bios
, size
, GFP_KERNEL
);
94 if (rdev
->bios
== NULL
) {
95 pci_unmap_rom(rdev
->pdev
, bios
);
98 pci_unmap_rom(rdev
->pdev
, bios
);
102 /* ATRM is used to get the BIOS on the discrete cards in
105 static bool radeon_atrm_get_bios(struct radeon_device
*rdev
)
108 int size
= 256 * 1024;
111 if (!radeon_atrm_supported(rdev
->pdev
))
114 rdev
->bios
= kmalloc(size
, GFP_KERNEL
);
116 DRM_ERROR("Unable to allocate bios\n");
120 for (i
= 0; i
< size
/ ATRM_BIOS_PAGE
; i
++) {
121 ret
= radeon_atrm_get_bios_chunk(rdev
->bios
,
122 (i
* ATRM_BIOS_PAGE
),
124 if (ret
< ATRM_BIOS_PAGE
)
128 if (i
== 0 || rdev
->bios
[0] != 0x55 || rdev
->bios
[1] != 0xaa) {
135 static bool ni_read_disabled_bios(struct radeon_device
*rdev
)
140 u32 vga_render_control
;
144 bus_cntl
= RREG32(R600_BUS_CNTL
);
145 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
146 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
147 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
148 rom_cntl
= RREG32(R600_ROM_CNTL
);
151 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
152 /* Disable VGA mode */
153 WREG32(AVIVO_D1VGA_CONTROL
,
154 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
155 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
156 WREG32(AVIVO_D2VGA_CONTROL
,
157 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
158 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
159 WREG32(AVIVO_VGA_RENDER_CONTROL
,
160 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
161 WREG32(R600_ROM_CNTL
, rom_cntl
| R600_SCK_OVERWRITE
);
163 r
= radeon_read_bios(rdev
);
166 WREG32(R600_BUS_CNTL
, bus_cntl
);
167 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
168 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
169 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
170 WREG32(R600_ROM_CNTL
, rom_cntl
);
174 static bool r700_read_disabled_bios(struct radeon_device
*rdev
)
176 uint32_t viph_control
;
178 uint32_t d1vga_control
;
179 uint32_t d2vga_control
;
180 uint32_t vga_render_control
;
182 uint32_t cg_spll_func_cntl
= 0;
183 uint32_t cg_spll_status
;
186 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
187 bus_cntl
= RREG32(R600_BUS_CNTL
);
188 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
189 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
190 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
191 rom_cntl
= RREG32(R600_ROM_CNTL
);
194 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
196 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
197 /* Disable VGA mode */
198 WREG32(AVIVO_D1VGA_CONTROL
,
199 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
200 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
201 WREG32(AVIVO_D2VGA_CONTROL
,
202 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
203 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
204 WREG32(AVIVO_VGA_RENDER_CONTROL
,
205 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
207 if (rdev
->family
== CHIP_RV730
) {
208 cg_spll_func_cntl
= RREG32(R600_CG_SPLL_FUNC_CNTL
);
210 /* enable bypass mode */
211 WREG32(R600_CG_SPLL_FUNC_CNTL
, (cg_spll_func_cntl
|
212 R600_SPLL_BYPASS_EN
));
214 /* wait for SPLL_CHG_STATUS to change to 1 */
216 while (!(cg_spll_status
& R600_SPLL_CHG_STATUS
))
217 cg_spll_status
= RREG32(R600_CG_SPLL_STATUS
);
219 WREG32(R600_ROM_CNTL
, (rom_cntl
& ~R600_SCK_OVERWRITE
));
221 WREG32(R600_ROM_CNTL
, (rom_cntl
| R600_SCK_OVERWRITE
));
223 r
= radeon_read_bios(rdev
);
226 if (rdev
->family
== CHIP_RV730
) {
227 WREG32(R600_CG_SPLL_FUNC_CNTL
, cg_spll_func_cntl
);
229 /* wait for SPLL_CHG_STATUS to change to 1 */
231 while (!(cg_spll_status
& R600_SPLL_CHG_STATUS
))
232 cg_spll_status
= RREG32(R600_CG_SPLL_STATUS
);
234 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
235 WREG32(R600_BUS_CNTL
, bus_cntl
);
236 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
237 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
238 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
239 WREG32(R600_ROM_CNTL
, rom_cntl
);
243 static bool r600_read_disabled_bios(struct radeon_device
*rdev
)
245 uint32_t viph_control
;
247 uint32_t d1vga_control
;
248 uint32_t d2vga_control
;
249 uint32_t vga_render_control
;
251 uint32_t general_pwrmgt
;
252 uint32_t low_vid_lower_gpio_cntl
;
253 uint32_t medium_vid_lower_gpio_cntl
;
254 uint32_t high_vid_lower_gpio_cntl
;
255 uint32_t ctxsw_vid_lower_gpio_cntl
;
256 uint32_t lower_gpio_enable
;
259 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
260 bus_cntl
= RREG32(R600_BUS_CNTL
);
261 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
262 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
263 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
264 rom_cntl
= RREG32(R600_ROM_CNTL
);
265 general_pwrmgt
= RREG32(R600_GENERAL_PWRMGT
);
266 low_vid_lower_gpio_cntl
= RREG32(R600_LOW_VID_LOWER_GPIO_CNTL
);
267 medium_vid_lower_gpio_cntl
= RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
);
268 high_vid_lower_gpio_cntl
= RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
);
269 ctxsw_vid_lower_gpio_cntl
= RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
);
270 lower_gpio_enable
= RREG32(R600_LOWER_GPIO_ENABLE
);
273 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
275 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
276 /* Disable VGA mode */
277 WREG32(AVIVO_D1VGA_CONTROL
,
278 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
279 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
280 WREG32(AVIVO_D2VGA_CONTROL
,
281 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
282 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
283 WREG32(AVIVO_VGA_RENDER_CONTROL
,
284 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
286 WREG32(R600_ROM_CNTL
,
287 ((rom_cntl
& ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK
) |
288 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT
) |
289 R600_SCK_OVERWRITE
));
291 WREG32(R600_GENERAL_PWRMGT
, (general_pwrmgt
& ~R600_OPEN_DRAIN_PADS
));
292 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL
,
293 (low_vid_lower_gpio_cntl
& ~0x400));
294 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
,
295 (medium_vid_lower_gpio_cntl
& ~0x400));
296 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
,
297 (high_vid_lower_gpio_cntl
& ~0x400));
298 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
,
299 (ctxsw_vid_lower_gpio_cntl
& ~0x400));
300 WREG32(R600_LOWER_GPIO_ENABLE
, (lower_gpio_enable
| 0x400));
302 r
= radeon_read_bios(rdev
);
305 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
306 WREG32(R600_BUS_CNTL
, bus_cntl
);
307 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
308 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
309 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
310 WREG32(R600_ROM_CNTL
, rom_cntl
);
311 WREG32(R600_GENERAL_PWRMGT
, general_pwrmgt
);
312 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL
, low_vid_lower_gpio_cntl
);
313 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
, medium_vid_lower_gpio_cntl
);
314 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
, high_vid_lower_gpio_cntl
);
315 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
, ctxsw_vid_lower_gpio_cntl
);
316 WREG32(R600_LOWER_GPIO_ENABLE
, lower_gpio_enable
);
320 static bool avivo_read_disabled_bios(struct radeon_device
*rdev
)
322 uint32_t seprom_cntl1
;
323 uint32_t viph_control
;
325 uint32_t d1vga_control
;
326 uint32_t d2vga_control
;
327 uint32_t vga_render_control
;
330 uint32_t gpiopad_mask
;
333 seprom_cntl1
= RREG32(RADEON_SEPROM_CNTL1
);
334 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
335 bus_cntl
= RREG32(RV370_BUS_CNTL
);
336 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
337 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
338 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
339 gpiopad_a
= RREG32(RADEON_GPIOPAD_A
);
340 gpiopad_en
= RREG32(RADEON_GPIOPAD_EN
);
341 gpiopad_mask
= RREG32(RADEON_GPIOPAD_MASK
);
343 WREG32(RADEON_SEPROM_CNTL1
,
344 ((seprom_cntl1
& ~RADEON_SCK_PRESCALE_MASK
) |
345 (0xc << RADEON_SCK_PRESCALE_SHIFT
)));
346 WREG32(RADEON_GPIOPAD_A
, 0);
347 WREG32(RADEON_GPIOPAD_EN
, 0);
348 WREG32(RADEON_GPIOPAD_MASK
, 0);
351 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
354 WREG32(RV370_BUS_CNTL
, (bus_cntl
& ~RV370_BUS_BIOS_DIS_ROM
));
356 /* Disable VGA mode */
357 WREG32(AVIVO_D1VGA_CONTROL
,
358 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
359 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
360 WREG32(AVIVO_D2VGA_CONTROL
,
361 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
362 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
363 WREG32(AVIVO_VGA_RENDER_CONTROL
,
364 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
366 r
= radeon_read_bios(rdev
);
369 WREG32(RADEON_SEPROM_CNTL1
, seprom_cntl1
);
370 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
371 WREG32(RV370_BUS_CNTL
, bus_cntl
);
372 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
373 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
374 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
375 WREG32(RADEON_GPIOPAD_A
, gpiopad_a
);
376 WREG32(RADEON_GPIOPAD_EN
, gpiopad_en
);
377 WREG32(RADEON_GPIOPAD_MASK
, gpiopad_mask
);
381 static bool legacy_read_disabled_bios(struct radeon_device
*rdev
)
383 uint32_t seprom_cntl1
;
384 uint32_t viph_control
;
386 uint32_t crtc_gen_cntl
;
387 uint32_t crtc2_gen_cntl
;
388 uint32_t crtc_ext_cntl
;
389 uint32_t fp2_gen_cntl
;
392 seprom_cntl1
= RREG32(RADEON_SEPROM_CNTL1
);
393 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
394 if (rdev
->flags
& RADEON_IS_PCIE
)
395 bus_cntl
= RREG32(RV370_BUS_CNTL
);
397 bus_cntl
= RREG32(RADEON_BUS_CNTL
);
398 crtc_gen_cntl
= RREG32(RADEON_CRTC_GEN_CNTL
);
400 crtc_ext_cntl
= RREG32(RADEON_CRTC_EXT_CNTL
);
403 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
404 fp2_gen_cntl
= RREG32(RADEON_FP2_GEN_CNTL
);
407 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
408 crtc2_gen_cntl
= RREG32(RADEON_CRTC2_GEN_CNTL
);
411 WREG32(RADEON_SEPROM_CNTL1
,
412 ((seprom_cntl1
& ~RADEON_SCK_PRESCALE_MASK
) |
413 (0xc << RADEON_SCK_PRESCALE_SHIFT
)));
416 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
419 if (rdev
->flags
& RADEON_IS_PCIE
)
420 WREG32(RV370_BUS_CNTL
, (bus_cntl
& ~RV370_BUS_BIOS_DIS_ROM
));
422 WREG32(RADEON_BUS_CNTL
, (bus_cntl
& ~RADEON_BUS_BIOS_DIS_ROM
));
424 /* Turn off mem requests and CRTC for both controllers */
425 WREG32(RADEON_CRTC_GEN_CNTL
,
426 ((crtc_gen_cntl
& ~RADEON_CRTC_EN
) |
427 (RADEON_CRTC_DISP_REQ_EN_B
|
428 RADEON_CRTC_EXT_DISP_EN
)));
429 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
430 WREG32(RADEON_CRTC2_GEN_CNTL
,
431 ((crtc2_gen_cntl
& ~RADEON_CRTC2_EN
) |
432 RADEON_CRTC2_DISP_REQ_EN_B
));
435 WREG32(RADEON_CRTC_EXT_CNTL
,
436 ((crtc_ext_cntl
& ~RADEON_CRTC_CRT_ON
) |
437 (RADEON_CRTC_SYNC_TRISTAT
|
438 RADEON_CRTC_DISPLAY_DIS
)));
440 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
441 WREG32(RADEON_FP2_GEN_CNTL
, (fp2_gen_cntl
& ~RADEON_FP2_ON
));
444 r
= radeon_read_bios(rdev
);
447 WREG32(RADEON_SEPROM_CNTL1
, seprom_cntl1
);
448 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
449 if (rdev
->flags
& RADEON_IS_PCIE
)
450 WREG32(RV370_BUS_CNTL
, bus_cntl
);
452 WREG32(RADEON_BUS_CNTL
, bus_cntl
);
453 WREG32(RADEON_CRTC_GEN_CNTL
, crtc_gen_cntl
);
454 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
455 WREG32(RADEON_CRTC2_GEN_CNTL
, crtc2_gen_cntl
);
457 WREG32(RADEON_CRTC_EXT_CNTL
, crtc_ext_cntl
);
458 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
459 WREG32(RADEON_FP2_GEN_CNTL
, fp2_gen_cntl
);
464 static bool radeon_read_disabled_bios(struct radeon_device
*rdev
)
466 if (rdev
->flags
& RADEON_IS_IGP
)
467 return igp_read_bios_from_vram(rdev
);
468 else if (rdev
->family
>= CHIP_BARTS
)
469 return ni_read_disabled_bios(rdev
);
470 else if (rdev
->family
>= CHIP_RV770
)
471 return r700_read_disabled_bios(rdev
);
472 else if (rdev
->family
>= CHIP_R600
)
473 return r600_read_disabled_bios(rdev
);
474 else if (rdev
->family
>= CHIP_RS600
)
475 return avivo_read_disabled_bios(rdev
);
477 return legacy_read_disabled_bios(rdev
);
481 static bool radeon_acpi_vfct_bios(struct radeon_device
*rdev
)
484 struct acpi_table_header
*hdr
;
486 UEFI_ACPI_VFCT
*vfct
;
487 GOP_VBIOS_CONTENT
*vbios
;
488 VFCT_IMAGE_HEADER
*vhdr
;
490 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr
, &tbl_size
)))
492 if (tbl_size
< sizeof(UEFI_ACPI_VFCT
)) {
493 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
497 vfct
= (UEFI_ACPI_VFCT
*)hdr
;
498 if (vfct
->VBIOSImageOffset
+ sizeof(VFCT_IMAGE_HEADER
) > tbl_size
) {
499 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
503 vbios
= (GOP_VBIOS_CONTENT
*)((char *)hdr
+ vfct
->VBIOSImageOffset
);
504 vhdr
= &vbios
->VbiosHeader
;
505 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
506 vhdr
->PCIBus
, vhdr
->PCIDevice
, vhdr
->PCIFunction
,
507 vhdr
->VendorID
, vhdr
->DeviceID
, vhdr
->ImageLength
);
509 if (vhdr
->PCIBus
!= rdev
->pdev
->bus
->number
||
510 vhdr
->PCIDevice
!= PCI_SLOT(rdev
->pdev
->devfn
) ||
511 vhdr
->PCIFunction
!= PCI_FUNC(rdev
->pdev
->devfn
) ||
512 vhdr
->VendorID
!= rdev
->pdev
->vendor
||
513 vhdr
->DeviceID
!= rdev
->pdev
->device
) {
514 DRM_INFO("ACPI VFCT table is not for this card\n");
518 if (vfct
->VBIOSImageOffset
+ sizeof(VFCT_IMAGE_HEADER
) + vhdr
->ImageLength
> tbl_size
) {
519 DRM_ERROR("ACPI VFCT image truncated\n");
523 rdev
->bios
= kmemdup(&vbios
->VbiosContent
, vhdr
->ImageLength
, GFP_KERNEL
);
530 static inline bool radeon_acpi_vfct_bios(struct radeon_device
*rdev
)
536 bool radeon_get_bios(struct radeon_device
*rdev
)
541 r
= radeon_atrm_get_bios(rdev
);
543 r
= radeon_acpi_vfct_bios(rdev
);
545 r
= igp_read_bios_from_vram(rdev
);
547 r
= radeon_read_bios(rdev
);
549 r
= radeon_read_disabled_bios(rdev
);
551 if (r
== false || rdev
->bios
== NULL
) {
552 DRM_ERROR("Unable to locate a BIOS ROM\n");
556 if (rdev
->bios
[0] != 0x55 || rdev
->bios
[1] != 0xaa) {
557 printk("BIOS signature incorrect %x %x\n", rdev
->bios
[0], rdev
->bios
[1]);
562 if (RBIOS8(tmp
+ 0x14) != 0x0) {
563 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
567 rdev
->bios_header_start
= RBIOS16(0x48);
568 if (!rdev
->bios_header_start
) {
571 tmp
= rdev
->bios_header_start
+ 4;
572 if (!memcmp(rdev
->bios
+ tmp
, "ATOM", 4) ||
573 !memcmp(rdev
->bios
+ tmp
, "MOTA", 4)) {
574 rdev
->is_atom_bios
= true;
576 rdev
->is_atom_bios
= false;
579 DRM_DEBUG("%sBIOS detected\n", rdev
->is_atom_bios
? "ATOM" : "COM");