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Merge branch 'sh/st-integration' into sh/urgent
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / radeon_combios.c
1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27 #include "drmP.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
39
40 /* from radeon_encoder.c */
41 extern uint32_t
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46 /* from radeon_connector.c */
47 extern void
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56 /* from radeon_legacy_encoder.c */
57 extern void
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
60
61 /* old legacy ATI BIOS routines */
62
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112 };
113
114 enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122 };
123
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133 };
134
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144 };
145
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148 {
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 if (!rdev->bios)
154 return 0;
155
156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447 }
448
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450 {
451 int edid_info;
452 struct edid *edid;
453 unsigned char *raw;
454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
460 if (edid == NULL)
461 return false;
462
463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
464
465 if (!drm_edid_is_valid(edid)) {
466 kfree(edid);
467 return false;
468 }
469
470 rdev->mode_info.bios_hardcoded_edid = edid;
471 return true;
472 }
473
474 /* this is used for atom LCDs as well */
475 struct edid *
476 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
477 {
478 if (rdev->mode_info.bios_hardcoded_edid)
479 return rdev->mode_info.bios_hardcoded_edid;
480 return NULL;
481 }
482
483 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
484 enum radeon_combios_ddc ddc,
485 u32 clk_mask,
486 u32 data_mask)
487 {
488 struct radeon_i2c_bus_rec i2c;
489 int ddc_line = 0;
490
491 /* ddc id = mask reg
492 * DDC_NONE_DETECTED = none
493 * DDC_DVI = RADEON_GPIO_DVI_DDC
494 * DDC_VGA = RADEON_GPIO_VGA_DDC
495 * DDC_LCD = RADEON_GPIOPAD_MASK
496 * DDC_GPIO = RADEON_MDGPIO_MASK
497 * r1xx/r2xx
498 * DDC_MONID = RADEON_GPIO_MONID
499 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
500 * r3xx
501 * DDC_MONID = RADEON_GPIO_MONID
502 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
503 * rs3xx/rs4xx
504 * DDC_MONID = RADEON_GPIOPAD_MASK
505 * DDC_CRT2 = RADEON_GPIO_MONID
506 */
507 switch (ddc) {
508 case DDC_NONE_DETECTED:
509 default:
510 ddc_line = 0;
511 break;
512 case DDC_DVI:
513 ddc_line = RADEON_GPIO_DVI_DDC;
514 break;
515 case DDC_VGA:
516 ddc_line = RADEON_GPIO_VGA_DDC;
517 break;
518 case DDC_LCD:
519 ddc_line = RADEON_GPIOPAD_MASK;
520 break;
521 case DDC_GPIO:
522 ddc_line = RADEON_MDGPIO_MASK;
523 break;
524 case DDC_MONID:
525 if (rdev->family == CHIP_RS300 ||
526 rdev->family == CHIP_RS400 ||
527 rdev->family == CHIP_RS480)
528 ddc_line = RADEON_GPIOPAD_MASK;
529 else
530 ddc_line = RADEON_GPIO_MONID;
531 break;
532 case DDC_CRT2:
533 if (rdev->family == CHIP_RS300 ||
534 rdev->family == CHIP_RS400 ||
535 rdev->family == CHIP_RS480)
536 ddc_line = RADEON_GPIO_MONID;
537 else if (rdev->family >= CHIP_R300) {
538 ddc_line = RADEON_GPIO_DVI_DDC;
539 ddc = DDC_DVI;
540 } else
541 ddc_line = RADEON_GPIO_CRT2_DDC;
542 break;
543 }
544
545 if (ddc_line == RADEON_GPIOPAD_MASK) {
546 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
547 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
548 i2c.a_clk_reg = RADEON_GPIOPAD_A;
549 i2c.a_data_reg = RADEON_GPIOPAD_A;
550 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
551 i2c.en_data_reg = RADEON_GPIOPAD_EN;
552 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
553 i2c.y_data_reg = RADEON_GPIOPAD_Y;
554 } else if (ddc_line == RADEON_MDGPIO_MASK) {
555 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
556 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
557 i2c.a_clk_reg = RADEON_MDGPIO_A;
558 i2c.a_data_reg = RADEON_MDGPIO_A;
559 i2c.en_clk_reg = RADEON_MDGPIO_EN;
560 i2c.en_data_reg = RADEON_MDGPIO_EN;
561 i2c.y_clk_reg = RADEON_MDGPIO_Y;
562 i2c.y_data_reg = RADEON_MDGPIO_Y;
563 } else {
564 i2c.mask_clk_reg = ddc_line;
565 i2c.mask_data_reg = ddc_line;
566 i2c.a_clk_reg = ddc_line;
567 i2c.a_data_reg = ddc_line;
568 i2c.en_clk_reg = ddc_line;
569 i2c.en_data_reg = ddc_line;
570 i2c.y_clk_reg = ddc_line;
571 i2c.y_data_reg = ddc_line;
572 }
573
574 if (clk_mask && data_mask) {
575 /* system specific masks */
576 i2c.mask_clk_mask = clk_mask;
577 i2c.mask_data_mask = data_mask;
578 i2c.a_clk_mask = clk_mask;
579 i2c.a_data_mask = data_mask;
580 i2c.en_clk_mask = clk_mask;
581 i2c.en_data_mask = data_mask;
582 i2c.y_clk_mask = clk_mask;
583 i2c.y_data_mask = data_mask;
584 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
585 (ddc_line == RADEON_MDGPIO_MASK)) {
586 /* default gpiopad masks */
587 i2c.mask_clk_mask = (0x20 << 8);
588 i2c.mask_data_mask = 0x80;
589 i2c.a_clk_mask = (0x20 << 8);
590 i2c.a_data_mask = 0x80;
591 i2c.en_clk_mask = (0x20 << 8);
592 i2c.en_data_mask = 0x80;
593 i2c.y_clk_mask = (0x20 << 8);
594 i2c.y_data_mask = 0x80;
595 } else {
596 /* default masks for ddc pads */
597 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
598 i2c.mask_data_mask = RADEON_GPIO_EN_0;
599 i2c.a_clk_mask = RADEON_GPIO_A_1;
600 i2c.a_data_mask = RADEON_GPIO_A_0;
601 i2c.en_clk_mask = RADEON_GPIO_EN_1;
602 i2c.en_data_mask = RADEON_GPIO_EN_0;
603 i2c.y_clk_mask = RADEON_GPIO_Y_1;
604 i2c.y_data_mask = RADEON_GPIO_Y_0;
605 }
606
607 switch (rdev->family) {
608 case CHIP_R100:
609 case CHIP_RV100:
610 case CHIP_RS100:
611 case CHIP_RV200:
612 case CHIP_RS200:
613 case CHIP_RS300:
614 switch (ddc_line) {
615 case RADEON_GPIO_DVI_DDC:
616 i2c.hw_capable = true;
617 break;
618 default:
619 i2c.hw_capable = false;
620 break;
621 }
622 break;
623 case CHIP_R200:
624 switch (ddc_line) {
625 case RADEON_GPIO_DVI_DDC:
626 case RADEON_GPIO_MONID:
627 i2c.hw_capable = true;
628 break;
629 default:
630 i2c.hw_capable = false;
631 break;
632 }
633 break;
634 case CHIP_RV250:
635 case CHIP_RV280:
636 switch (ddc_line) {
637 case RADEON_GPIO_VGA_DDC:
638 case RADEON_GPIO_DVI_DDC:
639 case RADEON_GPIO_CRT2_DDC:
640 i2c.hw_capable = true;
641 break;
642 default:
643 i2c.hw_capable = false;
644 break;
645 }
646 break;
647 case CHIP_R300:
648 case CHIP_R350:
649 switch (ddc_line) {
650 case RADEON_GPIO_VGA_DDC:
651 case RADEON_GPIO_DVI_DDC:
652 i2c.hw_capable = true;
653 break;
654 default:
655 i2c.hw_capable = false;
656 break;
657 }
658 break;
659 case CHIP_RV350:
660 case CHIP_RV380:
661 case CHIP_RS400:
662 case CHIP_RS480:
663 switch (ddc_line) {
664 case RADEON_GPIO_VGA_DDC:
665 case RADEON_GPIO_DVI_DDC:
666 i2c.hw_capable = true;
667 break;
668 case RADEON_GPIO_MONID:
669 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
670 * reliably on some pre-r4xx hardware; not sure why.
671 */
672 i2c.hw_capable = false;
673 break;
674 default:
675 i2c.hw_capable = false;
676 break;
677 }
678 break;
679 default:
680 i2c.hw_capable = false;
681 break;
682 }
683 i2c.mm_i2c = false;
684
685 i2c.i2c_id = ddc;
686 i2c.hpd = RADEON_HPD_NONE;
687
688 if (ddc_line)
689 i2c.valid = true;
690 else
691 i2c.valid = false;
692
693 return i2c;
694 }
695
696 void radeon_combios_i2c_init(struct radeon_device *rdev)
697 {
698 struct drm_device *dev = rdev->ddev;
699 struct radeon_i2c_bus_rec i2c;
700
701
702 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
703 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
704
705 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
706 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
707
708 i2c.valid = true;
709 i2c.hw_capable = true;
710 i2c.mm_i2c = true;
711 i2c.i2c_id = 0xa0;
712 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
713
714 if (rdev->family == CHIP_RS300 ||
715 rdev->family == CHIP_RS400 ||
716 rdev->family == CHIP_RS480) {
717 u16 offset;
718 u8 id, blocks, clk, data;
719 int i;
720
721 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
722 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
723
724 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
725 if (offset) {
726 blocks = RBIOS8(offset + 2);
727 for (i = 0; i < blocks; i++) {
728 id = RBIOS8(offset + 3 + (i * 5) + 0);
729 if (id == 136) {
730 clk = RBIOS8(offset + 3 + (i * 5) + 3);
731 data = RBIOS8(offset + 3 + (i * 5) + 4);
732 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
733 (1 << clk), (1 << data));
734 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
735 break;
736 }
737 }
738 }
739
740 } else if (rdev->family >= CHIP_R300) {
741 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
742 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
743 } else {
744 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
745 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
746
747 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
748 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
749 }
750 }
751
752 bool radeon_combios_get_clock_info(struct drm_device *dev)
753 {
754 struct radeon_device *rdev = dev->dev_private;
755 uint16_t pll_info;
756 struct radeon_pll *p1pll = &rdev->clock.p1pll;
757 struct radeon_pll *p2pll = &rdev->clock.p2pll;
758 struct radeon_pll *spll = &rdev->clock.spll;
759 struct radeon_pll *mpll = &rdev->clock.mpll;
760 int8_t rev;
761 uint16_t sclk, mclk;
762
763 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
764 if (pll_info) {
765 rev = RBIOS8(pll_info);
766
767 /* pixel clocks */
768 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
769 p1pll->reference_div = RBIOS16(pll_info + 0x10);
770 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
771 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
772 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
773 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
774
775 if (rev > 9) {
776 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
777 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
778 } else {
779 p1pll->pll_in_min = 40;
780 p1pll->pll_in_max = 500;
781 }
782 *p2pll = *p1pll;
783
784 /* system clock */
785 spll->reference_freq = RBIOS16(pll_info + 0x1a);
786 spll->reference_div = RBIOS16(pll_info + 0x1c);
787 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
788 spll->pll_out_max = RBIOS32(pll_info + 0x22);
789
790 if (rev > 10) {
791 spll->pll_in_min = RBIOS32(pll_info + 0x48);
792 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
793 } else {
794 /* ??? */
795 spll->pll_in_min = 40;
796 spll->pll_in_max = 500;
797 }
798
799 /* memory clock */
800 mpll->reference_freq = RBIOS16(pll_info + 0x26);
801 mpll->reference_div = RBIOS16(pll_info + 0x28);
802 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
803 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
804
805 if (rev > 10) {
806 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
807 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
808 } else {
809 /* ??? */
810 mpll->pll_in_min = 40;
811 mpll->pll_in_max = 500;
812 }
813
814 /* default sclk/mclk */
815 sclk = RBIOS16(pll_info + 0xa);
816 mclk = RBIOS16(pll_info + 0x8);
817 if (sclk == 0)
818 sclk = 200 * 100;
819 if (mclk == 0)
820 mclk = 200 * 100;
821
822 rdev->clock.default_sclk = sclk;
823 rdev->clock.default_mclk = mclk;
824
825 return true;
826 }
827 return false;
828 }
829
830 bool radeon_combios_sideport_present(struct radeon_device *rdev)
831 {
832 struct drm_device *dev = rdev->ddev;
833 u16 igp_info;
834
835 /* sideport is AMD only */
836 if (rdev->family == CHIP_RS400)
837 return false;
838
839 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
840
841 if (igp_info) {
842 if (RBIOS16(igp_info + 0x4))
843 return true;
844 }
845 return false;
846 }
847
848 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
849 0x00000808, /* r100 */
850 0x00000808, /* rv100 */
851 0x00000808, /* rs100 */
852 0x00000808, /* rv200 */
853 0x00000808, /* rs200 */
854 0x00000808, /* r200 */
855 0x00000808, /* rv250 */
856 0x00000000, /* rs300 */
857 0x00000808, /* rv280 */
858 0x00000808, /* r300 */
859 0x00000808, /* r350 */
860 0x00000808, /* rv350 */
861 0x00000808, /* rv380 */
862 0x00000808, /* r420 */
863 0x00000808, /* r423 */
864 0x00000808, /* rv410 */
865 0x00000000, /* rs400 */
866 0x00000000, /* rs480 */
867 };
868
869 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
870 struct radeon_encoder_primary_dac *p_dac)
871 {
872 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
873 return;
874 }
875
876 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
877 radeon_encoder
878 *encoder)
879 {
880 struct drm_device *dev = encoder->base.dev;
881 struct radeon_device *rdev = dev->dev_private;
882 uint16_t dac_info;
883 uint8_t rev, bg, dac;
884 struct radeon_encoder_primary_dac *p_dac = NULL;
885 int found = 0;
886
887 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
888 GFP_KERNEL);
889
890 if (!p_dac)
891 return NULL;
892
893 /* check CRT table */
894 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
895 if (dac_info) {
896 rev = RBIOS8(dac_info) & 0x3;
897 if (rev < 2) {
898 bg = RBIOS8(dac_info + 0x2) & 0xf;
899 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
900 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
901 } else {
902 bg = RBIOS8(dac_info + 0x2) & 0xf;
903 dac = RBIOS8(dac_info + 0x3) & 0xf;
904 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
905 }
906 /* if the values are all zeros, use the table */
907 if (p_dac->ps2_pdac_adj)
908 found = 1;
909 }
910
911 if (!found) /* fallback to defaults */
912 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
913
914 return p_dac;
915 }
916
917 enum radeon_tv_std
918 radeon_combios_get_tv_info(struct radeon_device *rdev)
919 {
920 struct drm_device *dev = rdev->ddev;
921 uint16_t tv_info;
922 enum radeon_tv_std tv_std = TV_STD_NTSC;
923
924 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
925 if (tv_info) {
926 if (RBIOS8(tv_info + 6) == 'T') {
927 switch (RBIOS8(tv_info + 7) & 0xf) {
928 case 1:
929 tv_std = TV_STD_NTSC;
930 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
931 break;
932 case 2:
933 tv_std = TV_STD_PAL;
934 DRM_DEBUG_KMS("Default TV standard: PAL\n");
935 break;
936 case 3:
937 tv_std = TV_STD_PAL_M;
938 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
939 break;
940 case 4:
941 tv_std = TV_STD_PAL_60;
942 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
943 break;
944 case 5:
945 tv_std = TV_STD_NTSC_J;
946 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
947 break;
948 case 6:
949 tv_std = TV_STD_SCART_PAL;
950 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
951 break;
952 default:
953 tv_std = TV_STD_NTSC;
954 DRM_DEBUG_KMS
955 ("Unknown TV standard; defaulting to NTSC\n");
956 break;
957 }
958
959 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
960 case 0:
961 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
962 break;
963 case 1:
964 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
965 break;
966 case 2:
967 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
968 break;
969 case 3:
970 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
971 break;
972 default:
973 break;
974 }
975 }
976 }
977 return tv_std;
978 }
979
980 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
981 0x00000000, /* r100 */
982 0x00280000, /* rv100 */
983 0x00000000, /* rs100 */
984 0x00880000, /* rv200 */
985 0x00000000, /* rs200 */
986 0x00000000, /* r200 */
987 0x00770000, /* rv250 */
988 0x00290000, /* rs300 */
989 0x00560000, /* rv280 */
990 0x00780000, /* r300 */
991 0x00770000, /* r350 */
992 0x00780000, /* rv350 */
993 0x00780000, /* rv380 */
994 0x01080000, /* r420 */
995 0x01080000, /* r423 */
996 0x01080000, /* rv410 */
997 0x00780000, /* rs400 */
998 0x00780000, /* rs480 */
999 };
1000
1001 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1002 struct radeon_encoder_tv_dac *tv_dac)
1003 {
1004 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1005 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1006 tv_dac->ps2_tvdac_adj = 0x00880000;
1007 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1008 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1009 return;
1010 }
1011
1012 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1013 radeon_encoder
1014 *encoder)
1015 {
1016 struct drm_device *dev = encoder->base.dev;
1017 struct radeon_device *rdev = dev->dev_private;
1018 uint16_t dac_info;
1019 uint8_t rev, bg, dac;
1020 struct radeon_encoder_tv_dac *tv_dac = NULL;
1021 int found = 0;
1022
1023 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1024 if (!tv_dac)
1025 return NULL;
1026
1027 /* first check TV table */
1028 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1029 if (dac_info) {
1030 rev = RBIOS8(dac_info + 0x3);
1031 if (rev > 4) {
1032 bg = RBIOS8(dac_info + 0xc) & 0xf;
1033 dac = RBIOS8(dac_info + 0xd) & 0xf;
1034 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1035
1036 bg = RBIOS8(dac_info + 0xe) & 0xf;
1037 dac = RBIOS8(dac_info + 0xf) & 0xf;
1038 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1039
1040 bg = RBIOS8(dac_info + 0x10) & 0xf;
1041 dac = RBIOS8(dac_info + 0x11) & 0xf;
1042 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1043 /* if the values are all zeros, use the table */
1044 if (tv_dac->ps2_tvdac_adj)
1045 found = 1;
1046 } else if (rev > 1) {
1047 bg = RBIOS8(dac_info + 0xc) & 0xf;
1048 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1049 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1050
1051 bg = RBIOS8(dac_info + 0xd) & 0xf;
1052 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1053 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1054
1055 bg = RBIOS8(dac_info + 0xe) & 0xf;
1056 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1057 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1058 /* if the values are all zeros, use the table */
1059 if (tv_dac->ps2_tvdac_adj)
1060 found = 1;
1061 }
1062 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1063 }
1064 if (!found) {
1065 /* then check CRT table */
1066 dac_info =
1067 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1068 if (dac_info) {
1069 rev = RBIOS8(dac_info) & 0x3;
1070 if (rev < 2) {
1071 bg = RBIOS8(dac_info + 0x3) & 0xf;
1072 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1073 tv_dac->ps2_tvdac_adj =
1074 (bg << 16) | (dac << 20);
1075 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1076 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1077 /* if the values are all zeros, use the table */
1078 if (tv_dac->ps2_tvdac_adj)
1079 found = 1;
1080 } else {
1081 bg = RBIOS8(dac_info + 0x4) & 0xf;
1082 dac = RBIOS8(dac_info + 0x5) & 0xf;
1083 tv_dac->ps2_tvdac_adj =
1084 (bg << 16) | (dac << 20);
1085 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1086 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1087 /* if the values are all zeros, use the table */
1088 if (tv_dac->ps2_tvdac_adj)
1089 found = 1;
1090 }
1091 } else {
1092 DRM_INFO("No TV DAC info found in BIOS\n");
1093 }
1094 }
1095
1096 if (!found) /* fallback to defaults */
1097 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1098
1099 return tv_dac;
1100 }
1101
1102 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1103 radeon_device
1104 *rdev)
1105 {
1106 struct radeon_encoder_lvds *lvds = NULL;
1107 uint32_t fp_vert_stretch, fp_horz_stretch;
1108 uint32_t ppll_div_sel, ppll_val;
1109 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1110
1111 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1112
1113 if (!lvds)
1114 return NULL;
1115
1116 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1117 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1118
1119 /* These should be fail-safe defaults, fingers crossed */
1120 lvds->panel_pwr_delay = 200;
1121 lvds->panel_vcc_delay = 2000;
1122
1123 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1124 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1125 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1126
1127 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1128 lvds->native_mode.vdisplay =
1129 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1130 RADEON_VERT_PANEL_SHIFT) + 1;
1131 else
1132 lvds->native_mode.vdisplay =
1133 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1134
1135 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1136 lvds->native_mode.hdisplay =
1137 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1138 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1139 else
1140 lvds->native_mode.hdisplay =
1141 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1142
1143 if ((lvds->native_mode.hdisplay < 640) ||
1144 (lvds->native_mode.vdisplay < 480)) {
1145 lvds->native_mode.hdisplay = 640;
1146 lvds->native_mode.vdisplay = 480;
1147 }
1148
1149 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1150 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1151 if ((ppll_val & 0x000707ff) == 0x1bb)
1152 lvds->use_bios_dividers = false;
1153 else {
1154 lvds->panel_ref_divider =
1155 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1156 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1157 lvds->panel_fb_divider = ppll_val & 0x7ff;
1158
1159 if ((lvds->panel_ref_divider != 0) &&
1160 (lvds->panel_fb_divider > 3))
1161 lvds->use_bios_dividers = true;
1162 }
1163 lvds->panel_vcc_delay = 200;
1164
1165 DRM_INFO("Panel info derived from registers\n");
1166 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1167 lvds->native_mode.vdisplay);
1168
1169 return lvds;
1170 }
1171
1172 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1173 *encoder)
1174 {
1175 struct drm_device *dev = encoder->base.dev;
1176 struct radeon_device *rdev = dev->dev_private;
1177 uint16_t lcd_info;
1178 uint32_t panel_setup;
1179 char stmp[30];
1180 int tmp, i;
1181 struct radeon_encoder_lvds *lvds = NULL;
1182
1183 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1184
1185 if (lcd_info) {
1186 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1187
1188 if (!lvds)
1189 return NULL;
1190
1191 for (i = 0; i < 24; i++)
1192 stmp[i] = RBIOS8(lcd_info + i + 1);
1193 stmp[24] = 0;
1194
1195 DRM_INFO("Panel ID String: %s\n", stmp);
1196
1197 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1198 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1199
1200 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1201 lvds->native_mode.vdisplay);
1202
1203 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1204 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1205
1206 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1207 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1208 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1209
1210 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1211 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1212 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1213 if ((lvds->panel_ref_divider != 0) &&
1214 (lvds->panel_fb_divider > 3))
1215 lvds->use_bios_dividers = true;
1216
1217 panel_setup = RBIOS32(lcd_info + 0x39);
1218 lvds->lvds_gen_cntl = 0xff00;
1219 if (panel_setup & 0x1)
1220 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1221
1222 if ((panel_setup >> 4) & 0x1)
1223 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1224
1225 switch ((panel_setup >> 8) & 0x7) {
1226 case 0:
1227 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1228 break;
1229 case 1:
1230 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1231 break;
1232 case 2:
1233 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1234 break;
1235 default:
1236 break;
1237 }
1238
1239 if ((panel_setup >> 16) & 0x1)
1240 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1241
1242 if ((panel_setup >> 17) & 0x1)
1243 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1244
1245 if ((panel_setup >> 18) & 0x1)
1246 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1247
1248 if ((panel_setup >> 23) & 0x1)
1249 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1250
1251 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1252
1253 for (i = 0; i < 32; i++) {
1254 tmp = RBIOS16(lcd_info + 64 + i * 2);
1255 if (tmp == 0)
1256 break;
1257
1258 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1259 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1260 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1261 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1262 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1263 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1264 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1265 (RBIOS8(tmp + 23) * 8);
1266
1267 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1268 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1269 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1270 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1271 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1272 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1273
1274 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1275 lvds->native_mode.flags = 0;
1276 /* set crtc values */
1277 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1278
1279 }
1280 }
1281 } else {
1282 DRM_INFO("No panel info found in BIOS\n");
1283 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1284 }
1285
1286 if (lvds)
1287 encoder->native_mode = lvds->native_mode;
1288 return lvds;
1289 }
1290
1291 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1292 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1293 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1294 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1295 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1296 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1297 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1298 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1299 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1300 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1301 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1302 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1303 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1304 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1307 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1308 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1309 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1310 };
1311
1312 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1313 struct radeon_encoder_int_tmds *tmds)
1314 {
1315 struct drm_device *dev = encoder->base.dev;
1316 struct radeon_device *rdev = dev->dev_private;
1317 int i;
1318
1319 for (i = 0; i < 4; i++) {
1320 tmds->tmds_pll[i].value =
1321 default_tmds_pll[rdev->family][i].value;
1322 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1323 }
1324
1325 return true;
1326 }
1327
1328 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1329 struct radeon_encoder_int_tmds *tmds)
1330 {
1331 struct drm_device *dev = encoder->base.dev;
1332 struct radeon_device *rdev = dev->dev_private;
1333 uint16_t tmds_info;
1334 int i, n;
1335 uint8_t ver;
1336
1337 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1338
1339 if (tmds_info) {
1340 ver = RBIOS8(tmds_info);
1341 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1342 if (ver == 3) {
1343 n = RBIOS8(tmds_info + 5) + 1;
1344 if (n > 4)
1345 n = 4;
1346 for (i = 0; i < n; i++) {
1347 tmds->tmds_pll[i].value =
1348 RBIOS32(tmds_info + i * 10 + 0x08);
1349 tmds->tmds_pll[i].freq =
1350 RBIOS16(tmds_info + i * 10 + 0x10);
1351 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1352 tmds->tmds_pll[i].freq,
1353 tmds->tmds_pll[i].value);
1354 }
1355 } else if (ver == 4) {
1356 int stride = 0;
1357 n = RBIOS8(tmds_info + 5) + 1;
1358 if (n > 4)
1359 n = 4;
1360 for (i = 0; i < n; i++) {
1361 tmds->tmds_pll[i].value =
1362 RBIOS32(tmds_info + stride + 0x08);
1363 tmds->tmds_pll[i].freq =
1364 RBIOS16(tmds_info + stride + 0x10);
1365 if (i == 0)
1366 stride += 10;
1367 else
1368 stride += 6;
1369 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1370 tmds->tmds_pll[i].freq,
1371 tmds->tmds_pll[i].value);
1372 }
1373 }
1374 } else {
1375 DRM_INFO("No TMDS info found in BIOS\n");
1376 return false;
1377 }
1378 return true;
1379 }
1380
1381 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1382 struct radeon_encoder_ext_tmds *tmds)
1383 {
1384 struct drm_device *dev = encoder->base.dev;
1385 struct radeon_device *rdev = dev->dev_private;
1386 struct radeon_i2c_bus_rec i2c_bus;
1387
1388 /* default for macs */
1389 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1390 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1391
1392 /* XXX some macs have duallink chips */
1393 switch (rdev->mode_info.connector_table) {
1394 case CT_POWERBOOK_EXTERNAL:
1395 case CT_MINI_EXTERNAL:
1396 default:
1397 tmds->dvo_chip = DVO_SIL164;
1398 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1399 break;
1400 }
1401
1402 return true;
1403 }
1404
1405 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1406 struct radeon_encoder_ext_tmds *tmds)
1407 {
1408 struct drm_device *dev = encoder->base.dev;
1409 struct radeon_device *rdev = dev->dev_private;
1410 uint16_t offset;
1411 uint8_t ver;
1412 enum radeon_combios_ddc gpio;
1413 struct radeon_i2c_bus_rec i2c_bus;
1414
1415 tmds->i2c_bus = NULL;
1416 if (rdev->flags & RADEON_IS_IGP) {
1417 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1418 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1419 tmds->dvo_chip = DVO_SIL164;
1420 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1421 } else {
1422 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1423 if (offset) {
1424 ver = RBIOS8(offset);
1425 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1426 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1427 tmds->slave_addr >>= 1; /* 7 bit addressing */
1428 gpio = RBIOS8(offset + 4 + 3);
1429 if (gpio == DDC_LCD) {
1430 /* MM i2c */
1431 i2c_bus.valid = true;
1432 i2c_bus.hw_capable = true;
1433 i2c_bus.mm_i2c = true;
1434 i2c_bus.i2c_id = 0xa0;
1435 } else
1436 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1437 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1438 }
1439 }
1440
1441 if (!tmds->i2c_bus) {
1442 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1443 return false;
1444 }
1445
1446 return true;
1447 }
1448
1449 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1450 {
1451 struct radeon_device *rdev = dev->dev_private;
1452 struct radeon_i2c_bus_rec ddc_i2c;
1453 struct radeon_hpd hpd;
1454
1455 rdev->mode_info.connector_table = radeon_connector_table;
1456 if (rdev->mode_info.connector_table == CT_NONE) {
1457 #ifdef CONFIG_PPC_PMAC
1458 if (of_machine_is_compatible("PowerBook3,3")) {
1459 /* powerbook with VGA */
1460 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1461 } else if (of_machine_is_compatible("PowerBook3,4") ||
1462 of_machine_is_compatible("PowerBook3,5")) {
1463 /* powerbook with internal tmds */
1464 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1465 } else if (of_machine_is_compatible("PowerBook5,1") ||
1466 of_machine_is_compatible("PowerBook5,2") ||
1467 of_machine_is_compatible("PowerBook5,3") ||
1468 of_machine_is_compatible("PowerBook5,4") ||
1469 of_machine_is_compatible("PowerBook5,5")) {
1470 /* powerbook with external single link tmds (sil164) */
1471 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1472 } else if (of_machine_is_compatible("PowerBook5,6")) {
1473 /* powerbook with external dual or single link tmds */
1474 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1475 } else if (of_machine_is_compatible("PowerBook5,7") ||
1476 of_machine_is_compatible("PowerBook5,8") ||
1477 of_machine_is_compatible("PowerBook5,9")) {
1478 /* PowerBook6,2 ? */
1479 /* powerbook with external dual link tmds (sil1178?) */
1480 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1481 } else if (of_machine_is_compatible("PowerBook4,1") ||
1482 of_machine_is_compatible("PowerBook4,2") ||
1483 of_machine_is_compatible("PowerBook4,3") ||
1484 of_machine_is_compatible("PowerBook6,3") ||
1485 of_machine_is_compatible("PowerBook6,5") ||
1486 of_machine_is_compatible("PowerBook6,7")) {
1487 /* ibook */
1488 rdev->mode_info.connector_table = CT_IBOOK;
1489 } else if (of_machine_is_compatible("PowerMac4,4")) {
1490 /* emac */
1491 rdev->mode_info.connector_table = CT_EMAC;
1492 } else if (of_machine_is_compatible("PowerMac10,1")) {
1493 /* mini with internal tmds */
1494 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1495 } else if (of_machine_is_compatible("PowerMac10,2")) {
1496 /* mini with external tmds */
1497 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1498 } else if (of_machine_is_compatible("PowerMac12,1")) {
1499 /* PowerMac8,1 ? */
1500 /* imac g5 isight */
1501 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1502 } else if ((rdev->pdev->device == 0x4a48) &&
1503 (rdev->pdev->subsystem_vendor == 0x1002) &&
1504 (rdev->pdev->subsystem_device == 0x4a48)) {
1505 /* Mac X800 */
1506 rdev->mode_info.connector_table = CT_MAC_X800;
1507 } else
1508 #endif /* CONFIG_PPC_PMAC */
1509 #ifdef CONFIG_PPC64
1510 if (ASIC_IS_RN50(rdev))
1511 rdev->mode_info.connector_table = CT_RN50_POWER;
1512 else
1513 #endif
1514 rdev->mode_info.connector_table = CT_GENERIC;
1515 }
1516
1517 switch (rdev->mode_info.connector_table) {
1518 case CT_GENERIC:
1519 DRM_INFO("Connector Table: %d (generic)\n",
1520 rdev->mode_info.connector_table);
1521 /* these are the most common settings */
1522 if (rdev->flags & RADEON_SINGLE_CRTC) {
1523 /* VGA - primary dac */
1524 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1525 hpd.hpd = RADEON_HPD_NONE;
1526 radeon_add_legacy_encoder(dev,
1527 radeon_get_encoder_enum(dev,
1528 ATOM_DEVICE_CRT1_SUPPORT,
1529 1),
1530 ATOM_DEVICE_CRT1_SUPPORT);
1531 radeon_add_legacy_connector(dev, 0,
1532 ATOM_DEVICE_CRT1_SUPPORT,
1533 DRM_MODE_CONNECTOR_VGA,
1534 &ddc_i2c,
1535 CONNECTOR_OBJECT_ID_VGA,
1536 &hpd);
1537 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1538 /* LVDS */
1539 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1540 hpd.hpd = RADEON_HPD_NONE;
1541 radeon_add_legacy_encoder(dev,
1542 radeon_get_encoder_enum(dev,
1543 ATOM_DEVICE_LCD1_SUPPORT,
1544 0),
1545 ATOM_DEVICE_LCD1_SUPPORT);
1546 radeon_add_legacy_connector(dev, 0,
1547 ATOM_DEVICE_LCD1_SUPPORT,
1548 DRM_MODE_CONNECTOR_LVDS,
1549 &ddc_i2c,
1550 CONNECTOR_OBJECT_ID_LVDS,
1551 &hpd);
1552
1553 /* VGA - primary dac */
1554 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1555 hpd.hpd = RADEON_HPD_NONE;
1556 radeon_add_legacy_encoder(dev,
1557 radeon_get_encoder_enum(dev,
1558 ATOM_DEVICE_CRT1_SUPPORT,
1559 1),
1560 ATOM_DEVICE_CRT1_SUPPORT);
1561 radeon_add_legacy_connector(dev, 1,
1562 ATOM_DEVICE_CRT1_SUPPORT,
1563 DRM_MODE_CONNECTOR_VGA,
1564 &ddc_i2c,
1565 CONNECTOR_OBJECT_ID_VGA,
1566 &hpd);
1567 } else {
1568 /* DVI-I - tv dac, int tmds */
1569 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1570 hpd.hpd = RADEON_HPD_1;
1571 radeon_add_legacy_encoder(dev,
1572 radeon_get_encoder_enum(dev,
1573 ATOM_DEVICE_DFP1_SUPPORT,
1574 0),
1575 ATOM_DEVICE_DFP1_SUPPORT);
1576 radeon_add_legacy_encoder(dev,
1577 radeon_get_encoder_enum(dev,
1578 ATOM_DEVICE_CRT2_SUPPORT,
1579 2),
1580 ATOM_DEVICE_CRT2_SUPPORT);
1581 radeon_add_legacy_connector(dev, 0,
1582 ATOM_DEVICE_DFP1_SUPPORT |
1583 ATOM_DEVICE_CRT2_SUPPORT,
1584 DRM_MODE_CONNECTOR_DVII,
1585 &ddc_i2c,
1586 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1587 &hpd);
1588
1589 /* VGA - primary dac */
1590 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1591 hpd.hpd = RADEON_HPD_NONE;
1592 radeon_add_legacy_encoder(dev,
1593 radeon_get_encoder_enum(dev,
1594 ATOM_DEVICE_CRT1_SUPPORT,
1595 1),
1596 ATOM_DEVICE_CRT1_SUPPORT);
1597 radeon_add_legacy_connector(dev, 1,
1598 ATOM_DEVICE_CRT1_SUPPORT,
1599 DRM_MODE_CONNECTOR_VGA,
1600 &ddc_i2c,
1601 CONNECTOR_OBJECT_ID_VGA,
1602 &hpd);
1603 }
1604
1605 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1606 /* TV - tv dac */
1607 ddc_i2c.valid = false;
1608 hpd.hpd = RADEON_HPD_NONE;
1609 radeon_add_legacy_encoder(dev,
1610 radeon_get_encoder_enum(dev,
1611 ATOM_DEVICE_TV1_SUPPORT,
1612 2),
1613 ATOM_DEVICE_TV1_SUPPORT);
1614 radeon_add_legacy_connector(dev, 2,
1615 ATOM_DEVICE_TV1_SUPPORT,
1616 DRM_MODE_CONNECTOR_SVIDEO,
1617 &ddc_i2c,
1618 CONNECTOR_OBJECT_ID_SVIDEO,
1619 &hpd);
1620 }
1621 break;
1622 case CT_IBOOK:
1623 DRM_INFO("Connector Table: %d (ibook)\n",
1624 rdev->mode_info.connector_table);
1625 /* LVDS */
1626 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1627 hpd.hpd = RADEON_HPD_NONE;
1628 radeon_add_legacy_encoder(dev,
1629 radeon_get_encoder_enum(dev,
1630 ATOM_DEVICE_LCD1_SUPPORT,
1631 0),
1632 ATOM_DEVICE_LCD1_SUPPORT);
1633 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1634 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1635 CONNECTOR_OBJECT_ID_LVDS,
1636 &hpd);
1637 /* VGA - TV DAC */
1638 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1639 hpd.hpd = RADEON_HPD_NONE;
1640 radeon_add_legacy_encoder(dev,
1641 radeon_get_encoder_enum(dev,
1642 ATOM_DEVICE_CRT2_SUPPORT,
1643 2),
1644 ATOM_DEVICE_CRT2_SUPPORT);
1645 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1646 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1647 CONNECTOR_OBJECT_ID_VGA,
1648 &hpd);
1649 /* TV - TV DAC */
1650 ddc_i2c.valid = false;
1651 hpd.hpd = RADEON_HPD_NONE;
1652 radeon_add_legacy_encoder(dev,
1653 radeon_get_encoder_enum(dev,
1654 ATOM_DEVICE_TV1_SUPPORT,
1655 2),
1656 ATOM_DEVICE_TV1_SUPPORT);
1657 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1658 DRM_MODE_CONNECTOR_SVIDEO,
1659 &ddc_i2c,
1660 CONNECTOR_OBJECT_ID_SVIDEO,
1661 &hpd);
1662 break;
1663 case CT_POWERBOOK_EXTERNAL:
1664 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1665 rdev->mode_info.connector_table);
1666 /* LVDS */
1667 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1668 hpd.hpd = RADEON_HPD_NONE;
1669 radeon_add_legacy_encoder(dev,
1670 radeon_get_encoder_enum(dev,
1671 ATOM_DEVICE_LCD1_SUPPORT,
1672 0),
1673 ATOM_DEVICE_LCD1_SUPPORT);
1674 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1675 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1676 CONNECTOR_OBJECT_ID_LVDS,
1677 &hpd);
1678 /* DVI-I - primary dac, ext tmds */
1679 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1680 hpd.hpd = RADEON_HPD_2; /* ??? */
1681 radeon_add_legacy_encoder(dev,
1682 radeon_get_encoder_enum(dev,
1683 ATOM_DEVICE_DFP2_SUPPORT,
1684 0),
1685 ATOM_DEVICE_DFP2_SUPPORT);
1686 radeon_add_legacy_encoder(dev,
1687 radeon_get_encoder_enum(dev,
1688 ATOM_DEVICE_CRT1_SUPPORT,
1689 1),
1690 ATOM_DEVICE_CRT1_SUPPORT);
1691 /* XXX some are SL */
1692 radeon_add_legacy_connector(dev, 1,
1693 ATOM_DEVICE_DFP2_SUPPORT |
1694 ATOM_DEVICE_CRT1_SUPPORT,
1695 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1696 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1697 &hpd);
1698 /* TV - TV DAC */
1699 ddc_i2c.valid = false;
1700 hpd.hpd = RADEON_HPD_NONE;
1701 radeon_add_legacy_encoder(dev,
1702 radeon_get_encoder_enum(dev,
1703 ATOM_DEVICE_TV1_SUPPORT,
1704 2),
1705 ATOM_DEVICE_TV1_SUPPORT);
1706 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1707 DRM_MODE_CONNECTOR_SVIDEO,
1708 &ddc_i2c,
1709 CONNECTOR_OBJECT_ID_SVIDEO,
1710 &hpd);
1711 break;
1712 case CT_POWERBOOK_INTERNAL:
1713 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1714 rdev->mode_info.connector_table);
1715 /* LVDS */
1716 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1717 hpd.hpd = RADEON_HPD_NONE;
1718 radeon_add_legacy_encoder(dev,
1719 radeon_get_encoder_enum(dev,
1720 ATOM_DEVICE_LCD1_SUPPORT,
1721 0),
1722 ATOM_DEVICE_LCD1_SUPPORT);
1723 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1724 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1725 CONNECTOR_OBJECT_ID_LVDS,
1726 &hpd);
1727 /* DVI-I - primary dac, int tmds */
1728 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1729 hpd.hpd = RADEON_HPD_1; /* ??? */
1730 radeon_add_legacy_encoder(dev,
1731 radeon_get_encoder_enum(dev,
1732 ATOM_DEVICE_DFP1_SUPPORT,
1733 0),
1734 ATOM_DEVICE_DFP1_SUPPORT);
1735 radeon_add_legacy_encoder(dev,
1736 radeon_get_encoder_enum(dev,
1737 ATOM_DEVICE_CRT1_SUPPORT,
1738 1),
1739 ATOM_DEVICE_CRT1_SUPPORT);
1740 radeon_add_legacy_connector(dev, 1,
1741 ATOM_DEVICE_DFP1_SUPPORT |
1742 ATOM_DEVICE_CRT1_SUPPORT,
1743 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1744 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1745 &hpd);
1746 /* TV - TV DAC */
1747 ddc_i2c.valid = false;
1748 hpd.hpd = RADEON_HPD_NONE;
1749 radeon_add_legacy_encoder(dev,
1750 radeon_get_encoder_enum(dev,
1751 ATOM_DEVICE_TV1_SUPPORT,
1752 2),
1753 ATOM_DEVICE_TV1_SUPPORT);
1754 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1755 DRM_MODE_CONNECTOR_SVIDEO,
1756 &ddc_i2c,
1757 CONNECTOR_OBJECT_ID_SVIDEO,
1758 &hpd);
1759 break;
1760 case CT_POWERBOOK_VGA:
1761 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1762 rdev->mode_info.connector_table);
1763 /* LVDS */
1764 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1765 hpd.hpd = RADEON_HPD_NONE;
1766 radeon_add_legacy_encoder(dev,
1767 radeon_get_encoder_enum(dev,
1768 ATOM_DEVICE_LCD1_SUPPORT,
1769 0),
1770 ATOM_DEVICE_LCD1_SUPPORT);
1771 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1772 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1773 CONNECTOR_OBJECT_ID_LVDS,
1774 &hpd);
1775 /* VGA - primary dac */
1776 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1777 hpd.hpd = RADEON_HPD_NONE;
1778 radeon_add_legacy_encoder(dev,
1779 radeon_get_encoder_enum(dev,
1780 ATOM_DEVICE_CRT1_SUPPORT,
1781 1),
1782 ATOM_DEVICE_CRT1_SUPPORT);
1783 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1784 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1785 CONNECTOR_OBJECT_ID_VGA,
1786 &hpd);
1787 /* TV - TV DAC */
1788 ddc_i2c.valid = false;
1789 hpd.hpd = RADEON_HPD_NONE;
1790 radeon_add_legacy_encoder(dev,
1791 radeon_get_encoder_enum(dev,
1792 ATOM_DEVICE_TV1_SUPPORT,
1793 2),
1794 ATOM_DEVICE_TV1_SUPPORT);
1795 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1796 DRM_MODE_CONNECTOR_SVIDEO,
1797 &ddc_i2c,
1798 CONNECTOR_OBJECT_ID_SVIDEO,
1799 &hpd);
1800 break;
1801 case CT_MINI_EXTERNAL:
1802 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1803 rdev->mode_info.connector_table);
1804 /* DVI-I - tv dac, ext tmds */
1805 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1806 hpd.hpd = RADEON_HPD_2; /* ??? */
1807 radeon_add_legacy_encoder(dev,
1808 radeon_get_encoder_enum(dev,
1809 ATOM_DEVICE_DFP2_SUPPORT,
1810 0),
1811 ATOM_DEVICE_DFP2_SUPPORT);
1812 radeon_add_legacy_encoder(dev,
1813 radeon_get_encoder_enum(dev,
1814 ATOM_DEVICE_CRT2_SUPPORT,
1815 2),
1816 ATOM_DEVICE_CRT2_SUPPORT);
1817 /* XXX are any DL? */
1818 radeon_add_legacy_connector(dev, 0,
1819 ATOM_DEVICE_DFP2_SUPPORT |
1820 ATOM_DEVICE_CRT2_SUPPORT,
1821 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1822 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1823 &hpd);
1824 /* TV - TV DAC */
1825 ddc_i2c.valid = false;
1826 hpd.hpd = RADEON_HPD_NONE;
1827 radeon_add_legacy_encoder(dev,
1828 radeon_get_encoder_enum(dev,
1829 ATOM_DEVICE_TV1_SUPPORT,
1830 2),
1831 ATOM_DEVICE_TV1_SUPPORT);
1832 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1833 DRM_MODE_CONNECTOR_SVIDEO,
1834 &ddc_i2c,
1835 CONNECTOR_OBJECT_ID_SVIDEO,
1836 &hpd);
1837 break;
1838 case CT_MINI_INTERNAL:
1839 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1840 rdev->mode_info.connector_table);
1841 /* DVI-I - tv dac, int tmds */
1842 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1843 hpd.hpd = RADEON_HPD_1; /* ??? */
1844 radeon_add_legacy_encoder(dev,
1845 radeon_get_encoder_enum(dev,
1846 ATOM_DEVICE_DFP1_SUPPORT,
1847 0),
1848 ATOM_DEVICE_DFP1_SUPPORT);
1849 radeon_add_legacy_encoder(dev,
1850 radeon_get_encoder_enum(dev,
1851 ATOM_DEVICE_CRT2_SUPPORT,
1852 2),
1853 ATOM_DEVICE_CRT2_SUPPORT);
1854 radeon_add_legacy_connector(dev, 0,
1855 ATOM_DEVICE_DFP1_SUPPORT |
1856 ATOM_DEVICE_CRT2_SUPPORT,
1857 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1858 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1859 &hpd);
1860 /* TV - TV DAC */
1861 ddc_i2c.valid = false;
1862 hpd.hpd = RADEON_HPD_NONE;
1863 radeon_add_legacy_encoder(dev,
1864 radeon_get_encoder_enum(dev,
1865 ATOM_DEVICE_TV1_SUPPORT,
1866 2),
1867 ATOM_DEVICE_TV1_SUPPORT);
1868 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1869 DRM_MODE_CONNECTOR_SVIDEO,
1870 &ddc_i2c,
1871 CONNECTOR_OBJECT_ID_SVIDEO,
1872 &hpd);
1873 break;
1874 case CT_IMAC_G5_ISIGHT:
1875 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1876 rdev->mode_info.connector_table);
1877 /* DVI-D - int tmds */
1878 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1879 hpd.hpd = RADEON_HPD_1; /* ??? */
1880 radeon_add_legacy_encoder(dev,
1881 radeon_get_encoder_enum(dev,
1882 ATOM_DEVICE_DFP1_SUPPORT,
1883 0),
1884 ATOM_DEVICE_DFP1_SUPPORT);
1885 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1886 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1887 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1888 &hpd);
1889 /* VGA - tv dac */
1890 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1891 hpd.hpd = RADEON_HPD_NONE;
1892 radeon_add_legacy_encoder(dev,
1893 radeon_get_encoder_enum(dev,
1894 ATOM_DEVICE_CRT2_SUPPORT,
1895 2),
1896 ATOM_DEVICE_CRT2_SUPPORT);
1897 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1898 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1899 CONNECTOR_OBJECT_ID_VGA,
1900 &hpd);
1901 /* TV - TV DAC */
1902 ddc_i2c.valid = false;
1903 hpd.hpd = RADEON_HPD_NONE;
1904 radeon_add_legacy_encoder(dev,
1905 radeon_get_encoder_enum(dev,
1906 ATOM_DEVICE_TV1_SUPPORT,
1907 2),
1908 ATOM_DEVICE_TV1_SUPPORT);
1909 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1910 DRM_MODE_CONNECTOR_SVIDEO,
1911 &ddc_i2c,
1912 CONNECTOR_OBJECT_ID_SVIDEO,
1913 &hpd);
1914 break;
1915 case CT_EMAC:
1916 DRM_INFO("Connector Table: %d (emac)\n",
1917 rdev->mode_info.connector_table);
1918 /* VGA - primary dac */
1919 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1920 hpd.hpd = RADEON_HPD_NONE;
1921 radeon_add_legacy_encoder(dev,
1922 radeon_get_encoder_enum(dev,
1923 ATOM_DEVICE_CRT1_SUPPORT,
1924 1),
1925 ATOM_DEVICE_CRT1_SUPPORT);
1926 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1927 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1928 CONNECTOR_OBJECT_ID_VGA,
1929 &hpd);
1930 /* VGA - tv dac */
1931 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1932 hpd.hpd = RADEON_HPD_NONE;
1933 radeon_add_legacy_encoder(dev,
1934 radeon_get_encoder_enum(dev,
1935 ATOM_DEVICE_CRT2_SUPPORT,
1936 2),
1937 ATOM_DEVICE_CRT2_SUPPORT);
1938 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1939 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1940 CONNECTOR_OBJECT_ID_VGA,
1941 &hpd);
1942 /* TV - TV DAC */
1943 ddc_i2c.valid = false;
1944 hpd.hpd = RADEON_HPD_NONE;
1945 radeon_add_legacy_encoder(dev,
1946 radeon_get_encoder_enum(dev,
1947 ATOM_DEVICE_TV1_SUPPORT,
1948 2),
1949 ATOM_DEVICE_TV1_SUPPORT);
1950 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1951 DRM_MODE_CONNECTOR_SVIDEO,
1952 &ddc_i2c,
1953 CONNECTOR_OBJECT_ID_SVIDEO,
1954 &hpd);
1955 break;
1956 case CT_RN50_POWER:
1957 DRM_INFO("Connector Table: %d (rn50-power)\n",
1958 rdev->mode_info.connector_table);
1959 /* VGA - primary dac */
1960 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1961 hpd.hpd = RADEON_HPD_NONE;
1962 radeon_add_legacy_encoder(dev,
1963 radeon_get_encoder_enum(dev,
1964 ATOM_DEVICE_CRT1_SUPPORT,
1965 1),
1966 ATOM_DEVICE_CRT1_SUPPORT);
1967 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1968 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1969 CONNECTOR_OBJECT_ID_VGA,
1970 &hpd);
1971 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1972 hpd.hpd = RADEON_HPD_NONE;
1973 radeon_add_legacy_encoder(dev,
1974 radeon_get_encoder_enum(dev,
1975 ATOM_DEVICE_CRT2_SUPPORT,
1976 2),
1977 ATOM_DEVICE_CRT2_SUPPORT);
1978 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1979 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1980 CONNECTOR_OBJECT_ID_VGA,
1981 &hpd);
1982 break;
1983 case CT_MAC_X800:
1984 DRM_INFO("Connector Table: %d (mac x800)\n",
1985 rdev->mode_info.connector_table);
1986 /* DVI - primary dac, internal tmds */
1987 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1988 hpd.hpd = RADEON_HPD_1; /* ??? */
1989 radeon_add_legacy_encoder(dev,
1990 radeon_get_encoder_enum(dev,
1991 ATOM_DEVICE_DFP1_SUPPORT,
1992 0),
1993 ATOM_DEVICE_DFP1_SUPPORT);
1994 radeon_add_legacy_encoder(dev,
1995 radeon_get_encoder_enum(dev,
1996 ATOM_DEVICE_CRT1_SUPPORT,
1997 1),
1998 ATOM_DEVICE_CRT1_SUPPORT);
1999 radeon_add_legacy_connector(dev, 0,
2000 ATOM_DEVICE_DFP1_SUPPORT |
2001 ATOM_DEVICE_CRT1_SUPPORT,
2002 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2003 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2004 &hpd);
2005 /* DVI - tv dac, dvo */
2006 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2007 hpd.hpd = RADEON_HPD_2; /* ??? */
2008 radeon_add_legacy_encoder(dev,
2009 radeon_get_encoder_enum(dev,
2010 ATOM_DEVICE_DFP2_SUPPORT,
2011 0),
2012 ATOM_DEVICE_DFP2_SUPPORT);
2013 radeon_add_legacy_encoder(dev,
2014 radeon_get_encoder_enum(dev,
2015 ATOM_DEVICE_CRT2_SUPPORT,
2016 2),
2017 ATOM_DEVICE_CRT2_SUPPORT);
2018 radeon_add_legacy_connector(dev, 1,
2019 ATOM_DEVICE_DFP2_SUPPORT |
2020 ATOM_DEVICE_CRT2_SUPPORT,
2021 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2022 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2023 &hpd);
2024 break;
2025 default:
2026 DRM_INFO("Connector table: %d (invalid)\n",
2027 rdev->mode_info.connector_table);
2028 return false;
2029 }
2030
2031 radeon_link_encoder_connector(dev);
2032
2033 return true;
2034 }
2035
2036 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2037 int bios_index,
2038 enum radeon_combios_connector
2039 *legacy_connector,
2040 struct radeon_i2c_bus_rec *ddc_i2c,
2041 struct radeon_hpd *hpd)
2042 {
2043
2044 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2045 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2046 if (dev->pdev->device == 0x515e &&
2047 dev->pdev->subsystem_vendor == 0x1014) {
2048 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2049 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2050 return false;
2051 }
2052
2053 /* X300 card with extra non-existent DVI port */
2054 if (dev->pdev->device == 0x5B60 &&
2055 dev->pdev->subsystem_vendor == 0x17af &&
2056 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2057 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2058 return false;
2059 }
2060
2061 return true;
2062 }
2063
2064 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2065 {
2066 /* Acer 5102 has non-existent TV port */
2067 if (dev->pdev->device == 0x5975 &&
2068 dev->pdev->subsystem_vendor == 0x1025 &&
2069 dev->pdev->subsystem_device == 0x009f)
2070 return false;
2071
2072 /* HP dc5750 has non-existent TV port */
2073 if (dev->pdev->device == 0x5974 &&
2074 dev->pdev->subsystem_vendor == 0x103c &&
2075 dev->pdev->subsystem_device == 0x280a)
2076 return false;
2077
2078 /* MSI S270 has non-existent TV port */
2079 if (dev->pdev->device == 0x5955 &&
2080 dev->pdev->subsystem_vendor == 0x1462 &&
2081 dev->pdev->subsystem_device == 0x0131)
2082 return false;
2083
2084 return true;
2085 }
2086
2087 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2088 {
2089 struct radeon_device *rdev = dev->dev_private;
2090 uint32_t ext_tmds_info;
2091
2092 if (rdev->flags & RADEON_IS_IGP) {
2093 if (is_dvi_d)
2094 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2095 else
2096 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2097 }
2098 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2099 if (ext_tmds_info) {
2100 uint8_t rev = RBIOS8(ext_tmds_info);
2101 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2102 if (rev >= 3) {
2103 if (is_dvi_d)
2104 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2105 else
2106 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2107 } else {
2108 if (flags & 1) {
2109 if (is_dvi_d)
2110 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2111 else
2112 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2113 }
2114 }
2115 }
2116 if (is_dvi_d)
2117 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2118 else
2119 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2120 }
2121
2122 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2123 {
2124 struct radeon_device *rdev = dev->dev_private;
2125 uint32_t conn_info, entry, devices;
2126 uint16_t tmp, connector_object_id;
2127 enum radeon_combios_ddc ddc_type;
2128 enum radeon_combios_connector connector;
2129 int i = 0;
2130 struct radeon_i2c_bus_rec ddc_i2c;
2131 struct radeon_hpd hpd;
2132
2133 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2134 if (conn_info) {
2135 for (i = 0; i < 4; i++) {
2136 entry = conn_info + 2 + i * 2;
2137
2138 if (!RBIOS16(entry))
2139 break;
2140
2141 tmp = RBIOS16(entry);
2142
2143 connector = (tmp >> 12) & 0xf;
2144
2145 ddc_type = (tmp >> 8) & 0xf;
2146 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2147
2148 switch (connector) {
2149 case CONNECTOR_PROPRIETARY_LEGACY:
2150 case CONNECTOR_DVI_I_LEGACY:
2151 case CONNECTOR_DVI_D_LEGACY:
2152 if ((tmp >> 4) & 0x1)
2153 hpd.hpd = RADEON_HPD_2;
2154 else
2155 hpd.hpd = RADEON_HPD_1;
2156 break;
2157 default:
2158 hpd.hpd = RADEON_HPD_NONE;
2159 break;
2160 }
2161
2162 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2163 &ddc_i2c, &hpd))
2164 continue;
2165
2166 switch (connector) {
2167 case CONNECTOR_PROPRIETARY_LEGACY:
2168 if ((tmp >> 4) & 0x1)
2169 devices = ATOM_DEVICE_DFP2_SUPPORT;
2170 else
2171 devices = ATOM_DEVICE_DFP1_SUPPORT;
2172 radeon_add_legacy_encoder(dev,
2173 radeon_get_encoder_enum
2174 (dev, devices, 0),
2175 devices);
2176 radeon_add_legacy_connector(dev, i, devices,
2177 legacy_connector_convert
2178 [connector],
2179 &ddc_i2c,
2180 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2181 &hpd);
2182 break;
2183 case CONNECTOR_CRT_LEGACY:
2184 if (tmp & 0x1) {
2185 devices = ATOM_DEVICE_CRT2_SUPPORT;
2186 radeon_add_legacy_encoder(dev,
2187 radeon_get_encoder_enum
2188 (dev,
2189 ATOM_DEVICE_CRT2_SUPPORT,
2190 2),
2191 ATOM_DEVICE_CRT2_SUPPORT);
2192 } else {
2193 devices = ATOM_DEVICE_CRT1_SUPPORT;
2194 radeon_add_legacy_encoder(dev,
2195 radeon_get_encoder_enum
2196 (dev,
2197 ATOM_DEVICE_CRT1_SUPPORT,
2198 1),
2199 ATOM_DEVICE_CRT1_SUPPORT);
2200 }
2201 radeon_add_legacy_connector(dev,
2202 i,
2203 devices,
2204 legacy_connector_convert
2205 [connector],
2206 &ddc_i2c,
2207 CONNECTOR_OBJECT_ID_VGA,
2208 &hpd);
2209 break;
2210 case CONNECTOR_DVI_I_LEGACY:
2211 devices = 0;
2212 if (tmp & 0x1) {
2213 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2214 radeon_add_legacy_encoder(dev,
2215 radeon_get_encoder_enum
2216 (dev,
2217 ATOM_DEVICE_CRT2_SUPPORT,
2218 2),
2219 ATOM_DEVICE_CRT2_SUPPORT);
2220 } else {
2221 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2222 radeon_add_legacy_encoder(dev,
2223 radeon_get_encoder_enum
2224 (dev,
2225 ATOM_DEVICE_CRT1_SUPPORT,
2226 1),
2227 ATOM_DEVICE_CRT1_SUPPORT);
2228 }
2229 if ((tmp >> 4) & 0x1) {
2230 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2231 radeon_add_legacy_encoder(dev,
2232 radeon_get_encoder_enum
2233 (dev,
2234 ATOM_DEVICE_DFP2_SUPPORT,
2235 0),
2236 ATOM_DEVICE_DFP2_SUPPORT);
2237 connector_object_id = combios_check_dl_dvi(dev, 0);
2238 } else {
2239 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2240 radeon_add_legacy_encoder(dev,
2241 radeon_get_encoder_enum
2242 (dev,
2243 ATOM_DEVICE_DFP1_SUPPORT,
2244 0),
2245 ATOM_DEVICE_DFP1_SUPPORT);
2246 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2247 }
2248 radeon_add_legacy_connector(dev,
2249 i,
2250 devices,
2251 legacy_connector_convert
2252 [connector],
2253 &ddc_i2c,
2254 connector_object_id,
2255 &hpd);
2256 break;
2257 case CONNECTOR_DVI_D_LEGACY:
2258 if ((tmp >> 4) & 0x1) {
2259 devices = ATOM_DEVICE_DFP2_SUPPORT;
2260 connector_object_id = combios_check_dl_dvi(dev, 1);
2261 } else {
2262 devices = ATOM_DEVICE_DFP1_SUPPORT;
2263 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2264 }
2265 radeon_add_legacy_encoder(dev,
2266 radeon_get_encoder_enum
2267 (dev, devices, 0),
2268 devices);
2269 radeon_add_legacy_connector(dev, i, devices,
2270 legacy_connector_convert
2271 [connector],
2272 &ddc_i2c,
2273 connector_object_id,
2274 &hpd);
2275 break;
2276 case CONNECTOR_CTV_LEGACY:
2277 case CONNECTOR_STV_LEGACY:
2278 radeon_add_legacy_encoder(dev,
2279 radeon_get_encoder_enum
2280 (dev,
2281 ATOM_DEVICE_TV1_SUPPORT,
2282 2),
2283 ATOM_DEVICE_TV1_SUPPORT);
2284 radeon_add_legacy_connector(dev, i,
2285 ATOM_DEVICE_TV1_SUPPORT,
2286 legacy_connector_convert
2287 [connector],
2288 &ddc_i2c,
2289 CONNECTOR_OBJECT_ID_SVIDEO,
2290 &hpd);
2291 break;
2292 default:
2293 DRM_ERROR("Unknown connector type: %d\n",
2294 connector);
2295 continue;
2296 }
2297
2298 }
2299 } else {
2300 uint16_t tmds_info =
2301 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2302 if (tmds_info) {
2303 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2304
2305 radeon_add_legacy_encoder(dev,
2306 radeon_get_encoder_enum(dev,
2307 ATOM_DEVICE_CRT1_SUPPORT,
2308 1),
2309 ATOM_DEVICE_CRT1_SUPPORT);
2310 radeon_add_legacy_encoder(dev,
2311 radeon_get_encoder_enum(dev,
2312 ATOM_DEVICE_DFP1_SUPPORT,
2313 0),
2314 ATOM_DEVICE_DFP1_SUPPORT);
2315
2316 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2317 hpd.hpd = RADEON_HPD_1;
2318 radeon_add_legacy_connector(dev,
2319 0,
2320 ATOM_DEVICE_CRT1_SUPPORT |
2321 ATOM_DEVICE_DFP1_SUPPORT,
2322 DRM_MODE_CONNECTOR_DVII,
2323 &ddc_i2c,
2324 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2325 &hpd);
2326 } else {
2327 uint16_t crt_info =
2328 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2329 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2330 if (crt_info) {
2331 radeon_add_legacy_encoder(dev,
2332 radeon_get_encoder_enum(dev,
2333 ATOM_DEVICE_CRT1_SUPPORT,
2334 1),
2335 ATOM_DEVICE_CRT1_SUPPORT);
2336 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2337 hpd.hpd = RADEON_HPD_NONE;
2338 radeon_add_legacy_connector(dev,
2339 0,
2340 ATOM_DEVICE_CRT1_SUPPORT,
2341 DRM_MODE_CONNECTOR_VGA,
2342 &ddc_i2c,
2343 CONNECTOR_OBJECT_ID_VGA,
2344 &hpd);
2345 } else {
2346 DRM_DEBUG_KMS("No connector info found\n");
2347 return false;
2348 }
2349 }
2350 }
2351
2352 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2353 uint16_t lcd_info =
2354 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2355 if (lcd_info) {
2356 uint16_t lcd_ddc_info =
2357 combios_get_table_offset(dev,
2358 COMBIOS_LCD_DDC_INFO_TABLE);
2359
2360 radeon_add_legacy_encoder(dev,
2361 radeon_get_encoder_enum(dev,
2362 ATOM_DEVICE_LCD1_SUPPORT,
2363 0),
2364 ATOM_DEVICE_LCD1_SUPPORT);
2365
2366 if (lcd_ddc_info) {
2367 ddc_type = RBIOS8(lcd_ddc_info + 2);
2368 switch (ddc_type) {
2369 case DDC_LCD:
2370 ddc_i2c =
2371 combios_setup_i2c_bus(rdev,
2372 DDC_LCD,
2373 RBIOS32(lcd_ddc_info + 3),
2374 RBIOS32(lcd_ddc_info + 7));
2375 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2376 break;
2377 case DDC_GPIO:
2378 ddc_i2c =
2379 combios_setup_i2c_bus(rdev,
2380 DDC_GPIO,
2381 RBIOS32(lcd_ddc_info + 3),
2382 RBIOS32(lcd_ddc_info + 7));
2383 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2384 break;
2385 default:
2386 ddc_i2c =
2387 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2388 break;
2389 }
2390 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2391 } else
2392 ddc_i2c.valid = false;
2393
2394 hpd.hpd = RADEON_HPD_NONE;
2395 radeon_add_legacy_connector(dev,
2396 5,
2397 ATOM_DEVICE_LCD1_SUPPORT,
2398 DRM_MODE_CONNECTOR_LVDS,
2399 &ddc_i2c,
2400 CONNECTOR_OBJECT_ID_LVDS,
2401 &hpd);
2402 }
2403 }
2404
2405 /* check TV table */
2406 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2407 uint32_t tv_info =
2408 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2409 if (tv_info) {
2410 if (RBIOS8(tv_info + 6) == 'T') {
2411 if (radeon_apply_legacy_tv_quirks(dev)) {
2412 hpd.hpd = RADEON_HPD_NONE;
2413 ddc_i2c.valid = false;
2414 radeon_add_legacy_encoder(dev,
2415 radeon_get_encoder_enum
2416 (dev,
2417 ATOM_DEVICE_TV1_SUPPORT,
2418 2),
2419 ATOM_DEVICE_TV1_SUPPORT);
2420 radeon_add_legacy_connector(dev, 6,
2421 ATOM_DEVICE_TV1_SUPPORT,
2422 DRM_MODE_CONNECTOR_SVIDEO,
2423 &ddc_i2c,
2424 CONNECTOR_OBJECT_ID_SVIDEO,
2425 &hpd);
2426 }
2427 }
2428 }
2429 }
2430
2431 radeon_link_encoder_connector(dev);
2432
2433 return true;
2434 }
2435
2436 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2437 {
2438 struct drm_device *dev = rdev->ddev;
2439 u16 offset, misc, misc2 = 0;
2440 u8 rev, blocks, tmp;
2441 int state_index = 0;
2442
2443 rdev->pm.default_power_state_index = -1;
2444
2445 /* allocate 2 power states */
2446 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2447 if (!rdev->pm.power_state) {
2448 rdev->pm.default_power_state_index = state_index;
2449 rdev->pm.num_power_states = 0;
2450
2451 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2452 rdev->pm.current_clock_mode_index = 0;
2453 return;
2454 }
2455
2456 if (rdev->flags & RADEON_IS_MOBILITY) {
2457 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2458 if (offset) {
2459 rev = RBIOS8(offset);
2460 blocks = RBIOS8(offset + 0x2);
2461 /* power mode 0 tends to be the only valid one */
2462 rdev->pm.power_state[state_index].num_clock_modes = 1;
2463 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2464 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2465 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2466 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2467 goto default_mode;
2468 rdev->pm.power_state[state_index].type =
2469 POWER_STATE_TYPE_BATTERY;
2470 misc = RBIOS16(offset + 0x5 + 0x0);
2471 if (rev > 4)
2472 misc2 = RBIOS16(offset + 0x5 + 0xe);
2473 rdev->pm.power_state[state_index].misc = misc;
2474 rdev->pm.power_state[state_index].misc2 = misc2;
2475 if (misc & 0x4) {
2476 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2477 if (misc & 0x8)
2478 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2479 true;
2480 else
2481 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2482 false;
2483 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2484 if (rev < 6) {
2485 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2486 RBIOS16(offset + 0x5 + 0xb) * 4;
2487 tmp = RBIOS8(offset + 0x5 + 0xd);
2488 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2489 } else {
2490 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2491 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2492 if (entries && voltage_table_offset) {
2493 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2494 RBIOS16(voltage_table_offset) * 4;
2495 tmp = RBIOS8(voltage_table_offset + 0x2);
2496 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2497 } else
2498 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2499 }
2500 switch ((misc2 & 0x700) >> 8) {
2501 case 0:
2502 default:
2503 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2504 break;
2505 case 1:
2506 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2507 break;
2508 case 2:
2509 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2510 break;
2511 case 3:
2512 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2513 break;
2514 case 4:
2515 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2516 break;
2517 }
2518 } else
2519 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2520 if (rev > 6)
2521 rdev->pm.power_state[state_index].pcie_lanes =
2522 RBIOS8(offset + 0x5 + 0x10);
2523 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2524 state_index++;
2525 } else {
2526 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2527 }
2528 } else {
2529 /* XXX figure out some good default low power mode for desktop cards */
2530 }
2531
2532 default_mode:
2533 /* add the default mode */
2534 rdev->pm.power_state[state_index].type =
2535 POWER_STATE_TYPE_DEFAULT;
2536 rdev->pm.power_state[state_index].num_clock_modes = 1;
2537 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2538 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2539 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2540 if ((state_index > 0) &&
2541 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2542 rdev->pm.power_state[state_index].clock_info[0].voltage =
2543 rdev->pm.power_state[0].clock_info[0].voltage;
2544 else
2545 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2546 rdev->pm.power_state[state_index].pcie_lanes = 16;
2547 rdev->pm.power_state[state_index].flags = 0;
2548 rdev->pm.default_power_state_index = state_index;
2549 rdev->pm.num_power_states = state_index + 1;
2550
2551 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2552 rdev->pm.current_clock_mode_index = 0;
2553 }
2554
2555 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2556 {
2557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2558 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2559
2560 if (!tmds)
2561 return;
2562
2563 switch (tmds->dvo_chip) {
2564 case DVO_SIL164:
2565 /* sil 164 */
2566 radeon_i2c_put_byte(tmds->i2c_bus,
2567 tmds->slave_addr,
2568 0x08, 0x30);
2569 radeon_i2c_put_byte(tmds->i2c_bus,
2570 tmds->slave_addr,
2571 0x09, 0x00);
2572 radeon_i2c_put_byte(tmds->i2c_bus,
2573 tmds->slave_addr,
2574 0x0a, 0x90);
2575 radeon_i2c_put_byte(tmds->i2c_bus,
2576 tmds->slave_addr,
2577 0x0c, 0x89);
2578 radeon_i2c_put_byte(tmds->i2c_bus,
2579 tmds->slave_addr,
2580 0x08, 0x3b);
2581 break;
2582 case DVO_SIL1178:
2583 /* sil 1178 - untested */
2584 /*
2585 * 0x0f, 0x44
2586 * 0x0f, 0x4c
2587 * 0x0e, 0x01
2588 * 0x0a, 0x80
2589 * 0x09, 0x30
2590 * 0x0c, 0xc9
2591 * 0x0d, 0x70
2592 * 0x08, 0x32
2593 * 0x08, 0x33
2594 */
2595 break;
2596 default:
2597 break;
2598 }
2599
2600 }
2601
2602 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2603 {
2604 struct drm_device *dev = encoder->dev;
2605 struct radeon_device *rdev = dev->dev_private;
2606 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2607 uint16_t offset;
2608 uint8_t blocks, slave_addr, rev;
2609 uint32_t index, id;
2610 uint32_t reg, val, and_mask, or_mask;
2611 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2612
2613 if (!tmds)
2614 return false;
2615
2616 if (rdev->flags & RADEON_IS_IGP) {
2617 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2618 rev = RBIOS8(offset);
2619 if (offset) {
2620 rev = RBIOS8(offset);
2621 if (rev > 1) {
2622 blocks = RBIOS8(offset + 3);
2623 index = offset + 4;
2624 while (blocks > 0) {
2625 id = RBIOS16(index);
2626 index += 2;
2627 switch (id >> 13) {
2628 case 0:
2629 reg = (id & 0x1fff) * 4;
2630 val = RBIOS32(index);
2631 index += 4;
2632 WREG32(reg, val);
2633 break;
2634 case 2:
2635 reg = (id & 0x1fff) * 4;
2636 and_mask = RBIOS32(index);
2637 index += 4;
2638 or_mask = RBIOS32(index);
2639 index += 4;
2640 val = RREG32(reg);
2641 val = (val & and_mask) | or_mask;
2642 WREG32(reg, val);
2643 break;
2644 case 3:
2645 val = RBIOS16(index);
2646 index += 2;
2647 udelay(val);
2648 break;
2649 case 4:
2650 val = RBIOS16(index);
2651 index += 2;
2652 udelay(val * 1000);
2653 break;
2654 case 6:
2655 slave_addr = id & 0xff;
2656 slave_addr >>= 1; /* 7 bit addressing */
2657 index++;
2658 reg = RBIOS8(index);
2659 index++;
2660 val = RBIOS8(index);
2661 index++;
2662 radeon_i2c_put_byte(tmds->i2c_bus,
2663 slave_addr,
2664 reg, val);
2665 break;
2666 default:
2667 DRM_ERROR("Unknown id %d\n", id >> 13);
2668 break;
2669 }
2670 blocks--;
2671 }
2672 return true;
2673 }
2674 }
2675 } else {
2676 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2677 if (offset) {
2678 index = offset + 10;
2679 id = RBIOS16(index);
2680 while (id != 0xffff) {
2681 index += 2;
2682 switch (id >> 13) {
2683 case 0:
2684 reg = (id & 0x1fff) * 4;
2685 val = RBIOS32(index);
2686 WREG32(reg, val);
2687 break;
2688 case 2:
2689 reg = (id & 0x1fff) * 4;
2690 and_mask = RBIOS32(index);
2691 index += 4;
2692 or_mask = RBIOS32(index);
2693 index += 4;
2694 val = RREG32(reg);
2695 val = (val & and_mask) | or_mask;
2696 WREG32(reg, val);
2697 break;
2698 case 4:
2699 val = RBIOS16(index);
2700 index += 2;
2701 udelay(val);
2702 break;
2703 case 5:
2704 reg = id & 0x1fff;
2705 and_mask = RBIOS32(index);
2706 index += 4;
2707 or_mask = RBIOS32(index);
2708 index += 4;
2709 val = RREG32_PLL(reg);
2710 val = (val & and_mask) | or_mask;
2711 WREG32_PLL(reg, val);
2712 break;
2713 case 6:
2714 reg = id & 0x1fff;
2715 val = RBIOS8(index);
2716 index += 1;
2717 radeon_i2c_put_byte(tmds->i2c_bus,
2718 tmds->slave_addr,
2719 reg, val);
2720 break;
2721 default:
2722 DRM_ERROR("Unknown id %d\n", id >> 13);
2723 break;
2724 }
2725 id = RBIOS16(index);
2726 }
2727 return true;
2728 }
2729 }
2730 return false;
2731 }
2732
2733 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2734 {
2735 struct radeon_device *rdev = dev->dev_private;
2736
2737 if (offset) {
2738 while (RBIOS16(offset)) {
2739 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2740 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2741 uint32_t val, and_mask, or_mask;
2742 uint32_t tmp;
2743
2744 offset += 2;
2745 switch (cmd) {
2746 case 0:
2747 val = RBIOS32(offset);
2748 offset += 4;
2749 WREG32(addr, val);
2750 break;
2751 case 1:
2752 val = RBIOS32(offset);
2753 offset += 4;
2754 WREG32(addr, val);
2755 break;
2756 case 2:
2757 and_mask = RBIOS32(offset);
2758 offset += 4;
2759 or_mask = RBIOS32(offset);
2760 offset += 4;
2761 tmp = RREG32(addr);
2762 tmp &= and_mask;
2763 tmp |= or_mask;
2764 WREG32(addr, tmp);
2765 break;
2766 case 3:
2767 and_mask = RBIOS32(offset);
2768 offset += 4;
2769 or_mask = RBIOS32(offset);
2770 offset += 4;
2771 tmp = RREG32(addr);
2772 tmp &= and_mask;
2773 tmp |= or_mask;
2774 WREG32(addr, tmp);
2775 break;
2776 case 4:
2777 val = RBIOS16(offset);
2778 offset += 2;
2779 udelay(val);
2780 break;
2781 case 5:
2782 val = RBIOS16(offset);
2783 offset += 2;
2784 switch (addr) {
2785 case 8:
2786 while (val--) {
2787 if (!
2788 (RREG32_PLL
2789 (RADEON_CLK_PWRMGT_CNTL) &
2790 RADEON_MC_BUSY))
2791 break;
2792 }
2793 break;
2794 case 9:
2795 while (val--) {
2796 if ((RREG32(RADEON_MC_STATUS) &
2797 RADEON_MC_IDLE))
2798 break;
2799 }
2800 break;
2801 default:
2802 break;
2803 }
2804 break;
2805 default:
2806 break;
2807 }
2808 }
2809 }
2810 }
2811
2812 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2813 {
2814 struct radeon_device *rdev = dev->dev_private;
2815
2816 if (offset) {
2817 while (RBIOS8(offset)) {
2818 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2819 uint8_t addr = (RBIOS8(offset) & 0x3f);
2820 uint32_t val, shift, tmp;
2821 uint32_t and_mask, or_mask;
2822
2823 offset++;
2824 switch (cmd) {
2825 case 0:
2826 val = RBIOS32(offset);
2827 offset += 4;
2828 WREG32_PLL(addr, val);
2829 break;
2830 case 1:
2831 shift = RBIOS8(offset) * 8;
2832 offset++;
2833 and_mask = RBIOS8(offset) << shift;
2834 and_mask |= ~(0xff << shift);
2835 offset++;
2836 or_mask = RBIOS8(offset) << shift;
2837 offset++;
2838 tmp = RREG32_PLL(addr);
2839 tmp &= and_mask;
2840 tmp |= or_mask;
2841 WREG32_PLL(addr, tmp);
2842 break;
2843 case 2:
2844 case 3:
2845 tmp = 1000;
2846 switch (addr) {
2847 case 1:
2848 udelay(150);
2849 break;
2850 case 2:
2851 udelay(1000);
2852 break;
2853 case 3:
2854 while (tmp--) {
2855 if (!
2856 (RREG32_PLL
2857 (RADEON_CLK_PWRMGT_CNTL) &
2858 RADEON_MC_BUSY))
2859 break;
2860 }
2861 break;
2862 case 4:
2863 while (tmp--) {
2864 if (RREG32_PLL
2865 (RADEON_CLK_PWRMGT_CNTL) &
2866 RADEON_DLL_READY)
2867 break;
2868 }
2869 break;
2870 case 5:
2871 tmp =
2872 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2873 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2874 #if 0
2875 uint32_t mclk_cntl =
2876 RREG32_PLL
2877 (RADEON_MCLK_CNTL);
2878 mclk_cntl &= 0xffff0000;
2879 /*mclk_cntl |= 0x00001111;*//* ??? */
2880 WREG32_PLL(RADEON_MCLK_CNTL,
2881 mclk_cntl);
2882 udelay(10000);
2883 #endif
2884 WREG32_PLL
2885 (RADEON_CLK_PWRMGT_CNTL,
2886 tmp &
2887 ~RADEON_CG_NO1_DEBUG_0);
2888 udelay(10000);
2889 }
2890 break;
2891 default:
2892 break;
2893 }
2894 break;
2895 default:
2896 break;
2897 }
2898 }
2899 }
2900 }
2901
2902 static void combios_parse_ram_reset_table(struct drm_device *dev,
2903 uint16_t offset)
2904 {
2905 struct radeon_device *rdev = dev->dev_private;
2906 uint32_t tmp;
2907
2908 if (offset) {
2909 uint8_t val = RBIOS8(offset);
2910 while (val != 0xff) {
2911 offset++;
2912
2913 if (val == 0x0f) {
2914 uint32_t channel_complete_mask;
2915
2916 if (ASIC_IS_R300(rdev))
2917 channel_complete_mask =
2918 R300_MEM_PWRUP_COMPLETE;
2919 else
2920 channel_complete_mask =
2921 RADEON_MEM_PWRUP_COMPLETE;
2922 tmp = 20000;
2923 while (tmp--) {
2924 if ((RREG32(RADEON_MEM_STR_CNTL) &
2925 channel_complete_mask) ==
2926 channel_complete_mask)
2927 break;
2928 }
2929 } else {
2930 uint32_t or_mask = RBIOS16(offset);
2931 offset += 2;
2932
2933 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2934 tmp &= RADEON_SDRAM_MODE_MASK;
2935 tmp |= or_mask;
2936 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2937
2938 or_mask = val << 24;
2939 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2940 tmp &= RADEON_B3MEM_RESET_MASK;
2941 tmp |= or_mask;
2942 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2943 }
2944 val = RBIOS8(offset);
2945 }
2946 }
2947 }
2948
2949 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2950 int mem_addr_mapping)
2951 {
2952 struct radeon_device *rdev = dev->dev_private;
2953 uint32_t mem_cntl;
2954 uint32_t mem_size;
2955 uint32_t addr = 0;
2956
2957 mem_cntl = RREG32(RADEON_MEM_CNTL);
2958 if (mem_cntl & RV100_HALF_MODE)
2959 ram /= 2;
2960 mem_size = ram;
2961 mem_cntl &= ~(0xff << 8);
2962 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2963 WREG32(RADEON_MEM_CNTL, mem_cntl);
2964 RREG32(RADEON_MEM_CNTL);
2965
2966 /* sdram reset ? */
2967
2968 /* something like this???? */
2969 while (ram--) {
2970 addr = ram * 1024 * 1024;
2971 /* write to each page */
2972 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2973 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2974 /* read back and verify */
2975 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2976 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2977 return 0;
2978 }
2979
2980 return mem_size;
2981 }
2982
2983 static void combios_write_ram_size(struct drm_device *dev)
2984 {
2985 struct radeon_device *rdev = dev->dev_private;
2986 uint8_t rev;
2987 uint16_t offset;
2988 uint32_t mem_size = 0;
2989 uint32_t mem_cntl = 0;
2990
2991 /* should do something smarter here I guess... */
2992 if (rdev->flags & RADEON_IS_IGP)
2993 return;
2994
2995 /* first check detected mem table */
2996 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2997 if (offset) {
2998 rev = RBIOS8(offset);
2999 if (rev < 3) {
3000 mem_cntl = RBIOS32(offset + 1);
3001 mem_size = RBIOS16(offset + 5);
3002 if ((rdev->family < CHIP_R200) &&
3003 !ASIC_IS_RN50(rdev))
3004 WREG32(RADEON_MEM_CNTL, mem_cntl);
3005 }
3006 }
3007
3008 if (!mem_size) {
3009 offset =
3010 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3011 if (offset) {
3012 rev = RBIOS8(offset - 1);
3013 if (rev < 1) {
3014 if ((rdev->family < CHIP_R200)
3015 && !ASIC_IS_RN50(rdev)) {
3016 int ram = 0;
3017 int mem_addr_mapping = 0;
3018
3019 while (RBIOS8(offset)) {
3020 ram = RBIOS8(offset);
3021 mem_addr_mapping =
3022 RBIOS8(offset + 1);
3023 if (mem_addr_mapping != 0x25)
3024 ram *= 2;
3025 mem_size =
3026 combios_detect_ram(dev, ram,
3027 mem_addr_mapping);
3028 if (mem_size)
3029 break;
3030 offset += 2;
3031 }
3032 } else
3033 mem_size = RBIOS8(offset);
3034 } else {
3035 mem_size = RBIOS8(offset);
3036 mem_size *= 2; /* convert to MB */
3037 }
3038 }
3039 }
3040
3041 mem_size *= (1024 * 1024); /* convert to bytes */
3042 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3043 }
3044
3045 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3046 {
3047 uint16_t dyn_clk_info =
3048 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3049
3050 if (dyn_clk_info)
3051 combios_parse_pll_table(dev, dyn_clk_info);
3052 }
3053
3054 void radeon_combios_asic_init(struct drm_device *dev)
3055 {
3056 struct radeon_device *rdev = dev->dev_private;
3057 uint16_t table;
3058
3059 /* port hardcoded mac stuff from radeonfb */
3060 if (rdev->bios == NULL)
3061 return;
3062
3063 /* ASIC INIT 1 */
3064 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3065 if (table)
3066 combios_parse_mmio_table(dev, table);
3067
3068 /* PLL INIT */
3069 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3070 if (table)
3071 combios_parse_pll_table(dev, table);
3072
3073 /* ASIC INIT 2 */
3074 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3075 if (table)
3076 combios_parse_mmio_table(dev, table);
3077
3078 if (!(rdev->flags & RADEON_IS_IGP)) {
3079 /* ASIC INIT 4 */
3080 table =
3081 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3082 if (table)
3083 combios_parse_mmio_table(dev, table);
3084
3085 /* RAM RESET */
3086 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3087 if (table)
3088 combios_parse_ram_reset_table(dev, table);
3089
3090 /* ASIC INIT 3 */
3091 table =
3092 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3093 if (table)
3094 combios_parse_mmio_table(dev, table);
3095
3096 /* write CONFIG_MEMSIZE */
3097 combios_write_ram_size(dev);
3098 }
3099
3100 /* quirk for rs4xx HP nx6125 laptop to make it resume
3101 * - it hangs on resume inside the dynclk 1 table.
3102 */
3103 if (rdev->family == CHIP_RS480 &&
3104 rdev->pdev->subsystem_vendor == 0x103c &&
3105 rdev->pdev->subsystem_device == 0x308b)
3106 return;
3107
3108 /* quirk for rs4xx HP dv5000 laptop to make it resume
3109 * - it hangs on resume inside the dynclk 1 table.
3110 */
3111 if (rdev->family == CHIP_RS480 &&
3112 rdev->pdev->subsystem_vendor == 0x103c &&
3113 rdev->pdev->subsystem_device == 0x30a4)
3114 return;
3115
3116 /* DYN CLK 1 */
3117 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3118 if (table)
3119 combios_parse_pll_table(dev, table);
3120
3121 }
3122
3123 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3124 {
3125 struct radeon_device *rdev = dev->dev_private;
3126 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3127
3128 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3129 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3130 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3131
3132 /* let the bios control the backlight */
3133 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3134
3135 /* tell the bios not to handle mode switching */
3136 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3137 RADEON_ACC_MODE_CHANGE);
3138
3139 /* tell the bios a driver is loaded */
3140 bios_7_scratch |= RADEON_DRV_LOADED;
3141
3142 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3143 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3144 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3145 }
3146
3147 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3148 {
3149 struct drm_device *dev = encoder->dev;
3150 struct radeon_device *rdev = dev->dev_private;
3151 uint32_t bios_6_scratch;
3152
3153 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3154
3155 if (lock)
3156 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3157 else
3158 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3159
3160 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3161 }
3162
3163 void
3164 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3165 struct drm_encoder *encoder,
3166 bool connected)
3167 {
3168 struct drm_device *dev = connector->dev;
3169 struct radeon_device *rdev = dev->dev_private;
3170 struct radeon_connector *radeon_connector =
3171 to_radeon_connector(connector);
3172 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3173 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3174 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3175
3176 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3177 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3178 if (connected) {
3179 DRM_DEBUG_KMS("TV1 connected\n");
3180 /* fix me */
3181 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3182 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3183 bios_5_scratch |= RADEON_TV1_ON;
3184 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3185 } else {
3186 DRM_DEBUG_KMS("TV1 disconnected\n");
3187 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3188 bios_5_scratch &= ~RADEON_TV1_ON;
3189 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3190 }
3191 }
3192 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3193 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3194 if (connected) {
3195 DRM_DEBUG_KMS("LCD1 connected\n");
3196 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3197 bios_5_scratch |= RADEON_LCD1_ON;
3198 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3199 } else {
3200 DRM_DEBUG_KMS("LCD1 disconnected\n");
3201 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3202 bios_5_scratch &= ~RADEON_LCD1_ON;
3203 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3204 }
3205 }
3206 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3207 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3208 if (connected) {
3209 DRM_DEBUG_KMS("CRT1 connected\n");
3210 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3211 bios_5_scratch |= RADEON_CRT1_ON;
3212 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3213 } else {
3214 DRM_DEBUG_KMS("CRT1 disconnected\n");
3215 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3216 bios_5_scratch &= ~RADEON_CRT1_ON;
3217 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3218 }
3219 }
3220 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3221 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3222 if (connected) {
3223 DRM_DEBUG_KMS("CRT2 connected\n");
3224 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3225 bios_5_scratch |= RADEON_CRT2_ON;
3226 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3227 } else {
3228 DRM_DEBUG_KMS("CRT2 disconnected\n");
3229 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3230 bios_5_scratch &= ~RADEON_CRT2_ON;
3231 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3232 }
3233 }
3234 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3235 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3236 if (connected) {
3237 DRM_DEBUG_KMS("DFP1 connected\n");
3238 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3239 bios_5_scratch |= RADEON_DFP1_ON;
3240 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3241 } else {
3242 DRM_DEBUG_KMS("DFP1 disconnected\n");
3243 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3244 bios_5_scratch &= ~RADEON_DFP1_ON;
3245 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3246 }
3247 }
3248 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3249 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3250 if (connected) {
3251 DRM_DEBUG_KMS("DFP2 connected\n");
3252 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3253 bios_5_scratch |= RADEON_DFP2_ON;
3254 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3255 } else {
3256 DRM_DEBUG_KMS("DFP2 disconnected\n");
3257 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3258 bios_5_scratch &= ~RADEON_DFP2_ON;
3259 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3260 }
3261 }
3262 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3263 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3264 }
3265
3266 void
3267 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3268 {
3269 struct drm_device *dev = encoder->dev;
3270 struct radeon_device *rdev = dev->dev_private;
3271 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3272 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3273
3274 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3275 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3276 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3277 }
3278 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3279 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3280 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3281 }
3282 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3283 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3284 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3285 }
3286 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3287 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3288 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3289 }
3290 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3291 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3292 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3293 }
3294 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3295 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3296 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3297 }
3298 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3299 }
3300
3301 void
3302 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3303 {
3304 struct drm_device *dev = encoder->dev;
3305 struct radeon_device *rdev = dev->dev_private;
3306 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3307 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3308
3309 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3310 if (on)
3311 bios_6_scratch |= RADEON_TV_DPMS_ON;
3312 else
3313 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3314 }
3315 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3316 if (on)
3317 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3318 else
3319 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3320 }
3321 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3322 if (on)
3323 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3324 else
3325 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3326 }
3327 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3328 if (on)
3329 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3330 else
3331 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3332 }
3333 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3334 }
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