2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/list_sort.h>
29 #include <drm/radeon_drm.h>
30 #include "radeon_reg.h"
32 #include "radeon_trace.h"
34 #define RADEON_CS_MAX_PRIORITY 32u
35 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
37 /* This is based on the bucket sort with O(n) time complexity.
38 * An item with priority "i" is added to bucket[i]. The lists are then
39 * concatenated in descending order.
41 struct radeon_cs_buckets
{
42 struct list_head bucket
[RADEON_CS_NUM_BUCKETS
];
45 static void radeon_cs_buckets_init(struct radeon_cs_buckets
*b
)
49 for (i
= 0; i
< RADEON_CS_NUM_BUCKETS
; i
++)
50 INIT_LIST_HEAD(&b
->bucket
[i
]);
53 static void radeon_cs_buckets_add(struct radeon_cs_buckets
*b
,
54 struct list_head
*item
, unsigned priority
)
56 /* Since buffers which appear sooner in the relocation list are
57 * likely to be used more often than buffers which appear later
58 * in the list, the sort mustn't change the ordering of buffers
59 * with the same priority, i.e. it must be stable.
61 list_add_tail(item
, &b
->bucket
[min(priority
, RADEON_CS_MAX_PRIORITY
)]);
64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets
*b
,
65 struct list_head
*out_list
)
69 /* Connect the sorted buckets in the output list. */
70 for (i
= 0; i
< RADEON_CS_NUM_BUCKETS
; i
++) {
71 list_splice(&b
->bucket
[i
], out_list
);
75 static int radeon_cs_parser_relocs(struct radeon_cs_parser
*p
)
77 struct drm_device
*ddev
= p
->rdev
->ddev
;
78 struct radeon_cs_chunk
*chunk
;
79 struct radeon_cs_buckets buckets
;
83 if (p
->chunk_relocs_idx
== -1) {
86 chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
88 /* FIXME: we assume that each relocs use 4 dwords */
89 p
->nrelocs
= chunk
->length_dw
/ 4;
90 p
->relocs_ptr
= kcalloc(p
->nrelocs
, sizeof(void *), GFP_KERNEL
);
91 if (p
->relocs_ptr
== NULL
) {
94 p
->relocs
= kcalloc(p
->nrelocs
, sizeof(struct radeon_cs_reloc
), GFP_KERNEL
);
95 if (p
->relocs
== NULL
) {
99 radeon_cs_buckets_init(&buckets
);
101 for (i
= 0; i
< p
->nrelocs
; i
++) {
102 struct drm_radeon_cs_reloc
*r
;
106 r
= (struct drm_radeon_cs_reloc
*)&chunk
->kdata
[i
*4];
107 for (j
= 0; j
< i
; j
++) {
108 if (r
->handle
== p
->relocs
[j
].handle
) {
109 p
->relocs_ptr
[i
] = &p
->relocs
[j
];
115 p
->relocs
[i
].handle
= 0;
119 p
->relocs
[i
].gobj
= drm_gem_object_lookup(ddev
, p
->filp
,
121 if (p
->relocs
[i
].gobj
== NULL
) {
122 DRM_ERROR("gem object lookup failed 0x%x\n",
126 p
->relocs_ptr
[i
] = &p
->relocs
[i
];
127 p
->relocs
[i
].robj
= gem_to_radeon_bo(p
->relocs
[i
].gobj
);
129 /* The userspace buffer priorities are from 0 to 15. A higher
130 * number means the buffer is more important.
131 * Also, the buffers used for write have a higher priority than
132 * the buffers used for read only, which doubles the range
133 * to 0 to 31. 32 is reserved for the kernel driver.
135 priority
= (r
->flags
& 0xf) * 2 + !!r
->write_domain
;
137 /* the first reloc of an UVD job is the msg and that must be in
138 VRAM, also but everything into VRAM on AGP cards to avoid
140 if (p
->ring
== R600_RING_TYPE_UVD_INDEX
&&
141 (i
== 0 || drm_pci_device_is_agp(p
->rdev
->ddev
))) {
142 /* TODO: is this still needed for NI+ ? */
143 p
->relocs
[i
].prefered_domains
=
144 RADEON_GEM_DOMAIN_VRAM
;
146 p
->relocs
[i
].allowed_domains
=
147 RADEON_GEM_DOMAIN_VRAM
;
149 /* prioritize this over any other relocation */
150 priority
= RADEON_CS_MAX_PRIORITY
;
152 uint32_t domain
= r
->write_domain
?
153 r
->write_domain
: r
->read_domains
;
155 if (domain
& RADEON_GEM_DOMAIN_CPU
) {
156 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
157 "for command submission\n");
161 p
->relocs
[i
].prefered_domains
= domain
;
162 if (domain
== RADEON_GEM_DOMAIN_VRAM
)
163 domain
|= RADEON_GEM_DOMAIN_GTT
;
164 p
->relocs
[i
].allowed_domains
= domain
;
167 p
->relocs
[i
].tv
.bo
= &p
->relocs
[i
].robj
->tbo
;
168 p
->relocs
[i
].handle
= r
->handle
;
170 radeon_cs_buckets_add(&buckets
, &p
->relocs
[i
].tv
.head
,
174 radeon_cs_buckets_get_list(&buckets
, &p
->validated
);
176 if (p
->cs_flags
& RADEON_CS_USE_VM
)
177 p
->vm_bos
= radeon_vm_get_bos(p
->rdev
, p
->ib
.vm
,
180 return radeon_bo_list_validate(p
->rdev
, &p
->ticket
, &p
->validated
, p
->ring
);
183 static int radeon_cs_get_ring(struct radeon_cs_parser
*p
, u32 ring
, s32 priority
)
185 p
->priority
= priority
;
189 DRM_ERROR("unknown ring id: %d\n", ring
);
191 case RADEON_CS_RING_GFX
:
192 p
->ring
= RADEON_RING_TYPE_GFX_INDEX
;
194 case RADEON_CS_RING_COMPUTE
:
195 if (p
->rdev
->family
>= CHIP_TAHITI
) {
197 p
->ring
= CAYMAN_RING_TYPE_CP1_INDEX
;
199 p
->ring
= CAYMAN_RING_TYPE_CP2_INDEX
;
201 p
->ring
= RADEON_RING_TYPE_GFX_INDEX
;
203 case RADEON_CS_RING_DMA
:
204 if (p
->rdev
->family
>= CHIP_CAYMAN
) {
206 p
->ring
= R600_RING_TYPE_DMA_INDEX
;
208 p
->ring
= CAYMAN_RING_TYPE_DMA1_INDEX
;
209 } else if (p
->rdev
->family
>= CHIP_RV770
) {
210 p
->ring
= R600_RING_TYPE_DMA_INDEX
;
215 case RADEON_CS_RING_UVD
:
216 p
->ring
= R600_RING_TYPE_UVD_INDEX
;
218 case RADEON_CS_RING_VCE
:
219 /* TODO: only use the low priority ring for now */
220 p
->ring
= TN_RING_TYPE_VCE1_INDEX
;
226 static void radeon_cs_sync_rings(struct radeon_cs_parser
*p
)
230 for (i
= 0; i
< p
->nrelocs
; i
++) {
231 if (!p
->relocs
[i
].robj
)
234 radeon_semaphore_sync_to(p
->ib
.semaphore
,
235 p
->relocs
[i
].robj
->tbo
.sync_obj
);
239 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
240 int radeon_cs_parser_init(struct radeon_cs_parser
*p
, void *data
)
242 struct drm_radeon_cs
*cs
= data
;
243 uint64_t *chunk_array_ptr
;
245 u32 ring
= RADEON_CS_RING_GFX
;
248 if (!cs
->num_chunks
) {
252 INIT_LIST_HEAD(&p
->validated
);
255 p
->ib
.semaphore
= NULL
;
256 p
->const_ib
.sa_bo
= NULL
;
257 p
->const_ib
.semaphore
= NULL
;
258 p
->chunk_ib_idx
= -1;
259 p
->chunk_relocs_idx
= -1;
260 p
->chunk_flags_idx
= -1;
261 p
->chunk_const_ib_idx
= -1;
262 p
->chunks_array
= kcalloc(cs
->num_chunks
, sizeof(uint64_t), GFP_KERNEL
);
263 if (p
->chunks_array
== NULL
) {
266 chunk_array_ptr
= (uint64_t *)(unsigned long)(cs
->chunks
);
267 if (copy_from_user(p
->chunks_array
, chunk_array_ptr
,
268 sizeof(uint64_t)*cs
->num_chunks
)) {
272 p
->nchunks
= cs
->num_chunks
;
273 p
->chunks
= kcalloc(p
->nchunks
, sizeof(struct radeon_cs_chunk
), GFP_KERNEL
);
274 if (p
->chunks
== NULL
) {
277 for (i
= 0; i
< p
->nchunks
; i
++) {
278 struct drm_radeon_cs_chunk __user
**chunk_ptr
= NULL
;
279 struct drm_radeon_cs_chunk user_chunk
;
280 uint32_t __user
*cdata
;
282 chunk_ptr
= (void __user
*)(unsigned long)p
->chunks_array
[i
];
283 if (copy_from_user(&user_chunk
, chunk_ptr
,
284 sizeof(struct drm_radeon_cs_chunk
))) {
287 p
->chunks
[i
].length_dw
= user_chunk
.length_dw
;
288 p
->chunks
[i
].chunk_id
= user_chunk
.chunk_id
;
289 if (p
->chunks
[i
].chunk_id
== RADEON_CHUNK_ID_RELOCS
) {
290 p
->chunk_relocs_idx
= i
;
292 if (p
->chunks
[i
].chunk_id
== RADEON_CHUNK_ID_IB
) {
294 /* zero length IB isn't useful */
295 if (p
->chunks
[i
].length_dw
== 0)
298 if (p
->chunks
[i
].chunk_id
== RADEON_CHUNK_ID_CONST_IB
) {
299 p
->chunk_const_ib_idx
= i
;
300 /* zero length CONST IB isn't useful */
301 if (p
->chunks
[i
].length_dw
== 0)
304 if (p
->chunks
[i
].chunk_id
== RADEON_CHUNK_ID_FLAGS
) {
305 p
->chunk_flags_idx
= i
;
306 /* zero length flags aren't useful */
307 if (p
->chunks
[i
].length_dw
== 0)
311 size
= p
->chunks
[i
].length_dw
;
312 cdata
= (void __user
*)(unsigned long)user_chunk
.chunk_data
;
313 p
->chunks
[i
].user_ptr
= cdata
;
314 if (p
->chunks
[i
].chunk_id
== RADEON_CHUNK_ID_CONST_IB
)
317 if (p
->chunks
[i
].chunk_id
== RADEON_CHUNK_ID_IB
) {
318 if (!p
->rdev
|| !(p
->rdev
->flags
& RADEON_IS_AGP
))
322 p
->chunks
[i
].kdata
= drm_malloc_ab(size
, sizeof(uint32_t));
323 size
*= sizeof(uint32_t);
324 if (p
->chunks
[i
].kdata
== NULL
) {
327 if (copy_from_user(p
->chunks
[i
].kdata
, cdata
, size
)) {
330 if (p
->chunks
[i
].chunk_id
== RADEON_CHUNK_ID_FLAGS
) {
331 p
->cs_flags
= p
->chunks
[i
].kdata
[0];
332 if (p
->chunks
[i
].length_dw
> 1)
333 ring
= p
->chunks
[i
].kdata
[1];
334 if (p
->chunks
[i
].length_dw
> 2)
335 priority
= (s32
)p
->chunks
[i
].kdata
[2];
339 /* these are KMS only */
341 if ((p
->cs_flags
& RADEON_CS_USE_VM
) &&
342 !p
->rdev
->vm_manager
.enabled
) {
343 DRM_ERROR("VM not active on asic!\n");
347 if (radeon_cs_get_ring(p
, ring
, priority
))
350 /* we only support VM on some SI+ rings */
351 if ((p
->cs_flags
& RADEON_CS_USE_VM
) == 0) {
352 if (p
->rdev
->asic
->ring
[p
->ring
]->cs_parse
== NULL
) {
353 DRM_ERROR("Ring %d requires VM!\n", p
->ring
);
357 if (p
->rdev
->asic
->ring
[p
->ring
]->ib_parse
== NULL
) {
358 DRM_ERROR("VM not supported on ring %d!\n",
368 static int cmp_size_smaller_first(void *priv
, struct list_head
*a
,
371 struct radeon_cs_reloc
*la
= list_entry(a
, struct radeon_cs_reloc
, tv
.head
);
372 struct radeon_cs_reloc
*lb
= list_entry(b
, struct radeon_cs_reloc
, tv
.head
);
374 /* Sort A before B if A is smaller. */
375 return (int)la
->robj
->tbo
.num_pages
- (int)lb
->robj
->tbo
.num_pages
;
379 * cs_parser_fini() - clean parser states
380 * @parser: parser structure holding parsing context.
381 * @error: error number
383 * If error is set than unvalidate buffer, otherwise just free memory
384 * used by parsing context.
386 static void radeon_cs_parser_fini(struct radeon_cs_parser
*parser
, int error
, bool backoff
)
391 /* Sort the buffer list from the smallest to largest buffer,
392 * which affects the order of buffers in the LRU list.
393 * This assures that the smallest buffers are added first
394 * to the LRU list, so they are likely to be later evicted
395 * first, instead of large buffers whose eviction is more
398 * This slightly lowers the number of bytes moved by TTM
399 * per frame under memory pressure.
401 list_sort(NULL
, &parser
->validated
, cmp_size_smaller_first
);
403 ttm_eu_fence_buffer_objects(&parser
->ticket
,
406 } else if (backoff
) {
407 ttm_eu_backoff_reservation(&parser
->ticket
,
411 if (parser
->relocs
!= NULL
) {
412 for (i
= 0; i
< parser
->nrelocs
; i
++) {
413 if (parser
->relocs
[i
].gobj
)
414 drm_gem_object_unreference_unlocked(parser
->relocs
[i
].gobj
);
417 kfree(parser
->track
);
418 kfree(parser
->relocs
);
419 kfree(parser
->relocs_ptr
);
420 kfree(parser
->vm_bos
);
421 for (i
= 0; i
< parser
->nchunks
; i
++)
422 drm_free_large(parser
->chunks
[i
].kdata
);
423 kfree(parser
->chunks
);
424 kfree(parser
->chunks_array
);
425 radeon_ib_free(parser
->rdev
, &parser
->ib
);
426 radeon_ib_free(parser
->rdev
, &parser
->const_ib
);
429 static int radeon_cs_ib_chunk(struct radeon_device
*rdev
,
430 struct radeon_cs_parser
*parser
)
434 if (parser
->chunk_ib_idx
== -1)
437 if (parser
->cs_flags
& RADEON_CS_USE_VM
)
440 r
= radeon_cs_parse(rdev
, parser
->ring
, parser
);
441 if (r
|| parser
->parser_error
) {
442 DRM_ERROR("Invalid command stream !\n");
446 if (parser
->ring
== R600_RING_TYPE_UVD_INDEX
)
447 radeon_uvd_note_usage(rdev
);
448 else if ((parser
->ring
== TN_RING_TYPE_VCE1_INDEX
) ||
449 (parser
->ring
== TN_RING_TYPE_VCE2_INDEX
))
450 radeon_vce_note_usage(rdev
);
452 radeon_cs_sync_rings(parser
);
453 r
= radeon_ib_schedule(rdev
, &parser
->ib
, NULL
);
455 DRM_ERROR("Failed to schedule IB !\n");
460 static int radeon_bo_vm_update_pte(struct radeon_cs_parser
*p
,
461 struct radeon_vm
*vm
)
463 struct radeon_device
*rdev
= p
->rdev
;
466 r
= radeon_vm_update_page_directory(rdev
, vm
);
470 r
= radeon_vm_bo_update(rdev
, vm
, rdev
->ring_tmp_bo
.bo
,
471 &rdev
->ring_tmp_bo
.bo
->tbo
.mem
);
475 for (i
= 0; i
< p
->nrelocs
; i
++) {
476 struct radeon_bo
*bo
;
478 /* ignore duplicates */
479 if (p
->relocs_ptr
[i
] != &p
->relocs
[i
])
482 bo
= p
->relocs
[i
].robj
;
483 r
= radeon_vm_bo_update(rdev
, vm
, bo
, &bo
->tbo
.mem
);
490 static int radeon_cs_ib_vm_chunk(struct radeon_device
*rdev
,
491 struct radeon_cs_parser
*parser
)
493 struct radeon_fpriv
*fpriv
= parser
->filp
->driver_priv
;
494 struct radeon_vm
*vm
= &fpriv
->vm
;
497 if (parser
->chunk_ib_idx
== -1)
499 if ((parser
->cs_flags
& RADEON_CS_USE_VM
) == 0)
502 if (parser
->const_ib
.length_dw
) {
503 r
= radeon_ring_ib_parse(rdev
, parser
->ring
, &parser
->const_ib
);
509 r
= radeon_ring_ib_parse(rdev
, parser
->ring
, &parser
->ib
);
514 if (parser
->ring
== R600_RING_TYPE_UVD_INDEX
)
515 radeon_uvd_note_usage(rdev
);
517 mutex_lock(&vm
->mutex
);
518 r
= radeon_bo_vm_update_pte(parser
, vm
);
522 radeon_cs_sync_rings(parser
);
523 radeon_semaphore_sync_to(parser
->ib
.semaphore
, vm
->fence
);
525 if ((rdev
->family
>= CHIP_TAHITI
) &&
526 (parser
->chunk_const_ib_idx
!= -1)) {
527 r
= radeon_ib_schedule(rdev
, &parser
->ib
, &parser
->const_ib
);
529 r
= radeon_ib_schedule(rdev
, &parser
->ib
, NULL
);
533 mutex_unlock(&vm
->mutex
);
537 static int radeon_cs_handle_lockup(struct radeon_device
*rdev
, int r
)
540 r
= radeon_gpu_reset(rdev
);
547 static int radeon_cs_ib_fill(struct radeon_device
*rdev
, struct radeon_cs_parser
*parser
)
549 struct radeon_cs_chunk
*ib_chunk
;
550 struct radeon_vm
*vm
= NULL
;
553 if (parser
->chunk_ib_idx
== -1)
556 if (parser
->cs_flags
& RADEON_CS_USE_VM
) {
557 struct radeon_fpriv
*fpriv
= parser
->filp
->driver_priv
;
560 if ((rdev
->family
>= CHIP_TAHITI
) &&
561 (parser
->chunk_const_ib_idx
!= -1)) {
562 ib_chunk
= &parser
->chunks
[parser
->chunk_const_ib_idx
];
563 if (ib_chunk
->length_dw
> RADEON_IB_VM_MAX_SIZE
) {
564 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk
->length_dw
);
567 r
= radeon_ib_get(rdev
, parser
->ring
, &parser
->const_ib
,
568 vm
, ib_chunk
->length_dw
* 4);
570 DRM_ERROR("Failed to get const ib !\n");
573 parser
->const_ib
.is_const_ib
= true;
574 parser
->const_ib
.length_dw
= ib_chunk
->length_dw
;
575 if (copy_from_user(parser
->const_ib
.ptr
,
577 ib_chunk
->length_dw
* 4))
581 ib_chunk
= &parser
->chunks
[parser
->chunk_ib_idx
];
582 if (ib_chunk
->length_dw
> RADEON_IB_VM_MAX_SIZE
) {
583 DRM_ERROR("cs IB too big: %d\n", ib_chunk
->length_dw
);
587 ib_chunk
= &parser
->chunks
[parser
->chunk_ib_idx
];
589 r
= radeon_ib_get(rdev
, parser
->ring
, &parser
->ib
,
590 vm
, ib_chunk
->length_dw
* 4);
592 DRM_ERROR("Failed to get ib !\n");
595 parser
->ib
.length_dw
= ib_chunk
->length_dw
;
597 memcpy(parser
->ib
.ptr
, ib_chunk
->kdata
, ib_chunk
->length_dw
* 4);
598 else if (copy_from_user(parser
->ib
.ptr
, ib_chunk
->user_ptr
, ib_chunk
->length_dw
* 4))
603 int radeon_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
605 struct radeon_device
*rdev
= dev
->dev_private
;
606 struct radeon_cs_parser parser
;
609 down_read(&rdev
->exclusive_lock
);
610 if (!rdev
->accel_working
) {
611 up_read(&rdev
->exclusive_lock
);
614 /* initialize parser */
615 memset(&parser
, 0, sizeof(struct radeon_cs_parser
));
618 parser
.dev
= rdev
->dev
;
619 parser
.family
= rdev
->family
;
620 r
= radeon_cs_parser_init(&parser
, data
);
622 DRM_ERROR("Failed to initialize parser !\n");
623 radeon_cs_parser_fini(&parser
, r
, false);
624 up_read(&rdev
->exclusive_lock
);
625 r
= radeon_cs_handle_lockup(rdev
, r
);
629 r
= radeon_cs_ib_fill(rdev
, &parser
);
631 r
= radeon_cs_parser_relocs(&parser
);
632 if (r
&& r
!= -ERESTARTSYS
)
633 DRM_ERROR("Failed to parse relocation %d!\n", r
);
637 radeon_cs_parser_fini(&parser
, r
, false);
638 up_read(&rdev
->exclusive_lock
);
639 r
= radeon_cs_handle_lockup(rdev
, r
);
643 trace_radeon_cs(&parser
);
645 r
= radeon_cs_ib_chunk(rdev
, &parser
);
649 r
= radeon_cs_ib_vm_chunk(rdev
, &parser
);
654 radeon_cs_parser_fini(&parser
, r
, true);
655 up_read(&rdev
->exclusive_lock
);
656 r
= radeon_cs_handle_lockup(rdev
, r
);
661 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
662 * @parser: parser structure holding parsing context.
663 * @pkt: where to store packet information
665 * Assume that chunk_ib_index is properly set. Will return -EINVAL
666 * if packet is bigger than remaining ib size. or if packets is unknown.
668 int radeon_cs_packet_parse(struct radeon_cs_parser
*p
,
669 struct radeon_cs_packet
*pkt
,
672 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
673 struct radeon_device
*rdev
= p
->rdev
;
676 if (idx
>= ib_chunk
->length_dw
) {
677 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
678 idx
, ib_chunk
->length_dw
);
681 header
= radeon_get_ib_value(p
, idx
);
683 pkt
->type
= RADEON_CP_PACKET_GET_TYPE(header
);
684 pkt
->count
= RADEON_CP_PACKET_GET_COUNT(header
);
687 case RADEON_PACKET_TYPE0
:
688 if (rdev
->family
< CHIP_R600
) {
689 pkt
->reg
= R100_CP_PACKET0_GET_REG(header
);
691 RADEON_CP_PACKET0_GET_ONE_REG_WR(header
);
693 pkt
->reg
= R600_CP_PACKET0_GET_REG(header
);
695 case RADEON_PACKET_TYPE3
:
696 pkt
->opcode
= RADEON_CP_PACKET3_GET_OPCODE(header
);
698 case RADEON_PACKET_TYPE2
:
702 DRM_ERROR("Unknown packet type %d at %d !\n", pkt
->type
, idx
);
705 if ((pkt
->count
+ 1 + pkt
->idx
) >= ib_chunk
->length_dw
) {
706 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
707 pkt
->idx
, pkt
->type
, pkt
->count
, ib_chunk
->length_dw
);
714 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
715 * @p: structure holding the parser context.
717 * Check if the next packet is NOP relocation packet3.
719 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser
*p
)
721 struct radeon_cs_packet p3reloc
;
724 r
= radeon_cs_packet_parse(p
, &p3reloc
, p
->idx
);
727 if (p3reloc
.type
!= RADEON_PACKET_TYPE3
)
729 if (p3reloc
.opcode
!= RADEON_PACKET3_NOP
)
735 * radeon_cs_dump_packet() - dump raw packet context
736 * @p: structure holding the parser context.
737 * @pkt: structure holding the packet.
739 * Used mostly for debugging and error reporting.
741 void radeon_cs_dump_packet(struct radeon_cs_parser
*p
,
742 struct radeon_cs_packet
*pkt
)
744 volatile uint32_t *ib
;
750 for (i
= 0; i
<= (pkt
->count
+ 1); i
++, idx
++)
751 DRM_INFO("ib[%d]=0x%08X\n", idx
, ib
[idx
]);
755 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
756 * @parser: parser structure holding parsing context.
757 * @data: pointer to relocation data
758 * @offset_start: starting offset
759 * @offset_mask: offset mask (to align start offset on)
760 * @reloc: reloc informations
762 * Check if next packet is relocation packet3, do bo validation and compute
763 * GPU offset using the provided start.
765 int radeon_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
766 struct radeon_cs_reloc
**cs_reloc
,
769 struct radeon_cs_chunk
*relocs_chunk
;
770 struct radeon_cs_packet p3reloc
;
774 if (p
->chunk_relocs_idx
== -1) {
775 DRM_ERROR("No relocation chunk !\n");
779 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
780 r
= radeon_cs_packet_parse(p
, &p3reloc
, p
->idx
);
783 p
->idx
+= p3reloc
.count
+ 2;
784 if (p3reloc
.type
!= RADEON_PACKET_TYPE3
||
785 p3reloc
.opcode
!= RADEON_PACKET3_NOP
) {
786 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
788 radeon_cs_dump_packet(p
, &p3reloc
);
791 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
792 if (idx
>= relocs_chunk
->length_dw
) {
793 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
794 idx
, relocs_chunk
->length_dw
);
795 radeon_cs_dump_packet(p
, &p3reloc
);
798 /* FIXME: we assume reloc size is 4 dwords */
800 *cs_reloc
= p
->relocs
;
801 (*cs_reloc
)->gpu_offset
=
802 (u64
)relocs_chunk
->kdata
[idx
+ 3] << 32;
803 (*cs_reloc
)->gpu_offset
|= relocs_chunk
->kdata
[idx
+ 0];
805 *cs_reloc
= p
->relocs_ptr
[(idx
/ 4)];