drivers/gpu/drm/radeon/radeon_cursor.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
  31 {
  32         struct radeon_device *rdev = crtc->dev->dev_private;
  33         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  34         uint32_t cur_lock;
  35
  36         if (ASIC_IS_DCE4(rdev)) {
  37                 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
  38                 if (lock)
  39                         cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
  40                 else
  41                         cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
  42                 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
  43         } else if (ASIC_IS_AVIVO(rdev)) {
  44                 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
  45                 if (lock)
  46                         cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
  47                 else
  48                         cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
  49                 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
  50         } else {
  51                 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
  52                 if (lock)
  53                         cur_lock |= RADEON_CUR_LOCK;
  54                 else
  55                         cur_lock &= ~RADEON_CUR_LOCK;
  56                 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
  57         }
  58 }
  59
  60 static void radeon_hide_cursor(struct drm_crtc *crtc)
  61 {
  62         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  63         struct radeon_device *rdev = crtc->dev->dev_private;
  64
  65         if (ASIC_IS_DCE4(rdev)) {
  66                 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
  67                            EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
  68                            EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
  69         } else if (ASIC_IS_AVIVO(rdev)) {
  70                 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
  71                            (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
  72         } else {
  73                 u32 reg;
  74                 switch (radeon_crtc->crtc_id) {
  75                 case 0:
  76                         reg = RADEON_CRTC_GEN_CNTL;
  77                         break;
  78                 case 1:
  79                         reg = RADEON_CRTC2_GEN_CNTL;
  80                         break;
  81                 default:
  82                         return;
  83                 }
  84                 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
  85         }
  86 }
  87
  88 static void radeon_show_cursor(struct drm_crtc *crtc)
  89 {
  90         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  91         struct radeon_device *rdev = crtc->dev->dev_private;
  92
  93         if (ASIC_IS_DCE4(rdev)) {
  94                 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
  95                 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
  96                        EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
  97                        EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
  98         } else if (ASIC_IS_AVIVO(rdev)) {
  99                 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
 100                 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
 101                        (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
 102         } else {
 103                 switch (radeon_crtc->crtc_id) {
 104                 case 0:
 105                         WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
 106                         break;
 107                 case 1:
 108                         WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
 109                         break;
 110                 default:
 111                         return;
 112                 }
 113
 114                 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
 115                                           (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
 116                          ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
 117         }
 118 }
 119
 120 static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y);
 121
 122 static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
 123                               uint64_t gpu_addr, int hot_x, int hot_y)
 124 {
 125         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 126         struct radeon_device *rdev = crtc->dev->dev_private;
 127
 128         if (ASIC_IS_DCE4(rdev)) {
 129                 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 130                        upper_32_bits(gpu_addr));
 131                 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 132                        gpu_addr & 0xffffffff);
 133         } else if (ASIC_IS_AVIVO(rdev)) {
 134                 if (rdev->family >= CHIP_RV770) {
 135                         if (radeon_crtc->crtc_id)
 136                                 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
 137                         else
 138                                 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
 139                 }
 140                 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 141                        gpu_addr & 0xffffffff);
 142         } else {
 143                 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
 144                 /* offset is from DISP(2)_BASE_ADDRESS */
 145                 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
 146         }
 147
 148         if (hot_x != radeon_crtc->cursor_hot_x ||
 149             hot_y != radeon_crtc->cursor_hot_y) {
 150                 int x, y;
 151
 152                 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;
 153                 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;
 154
 155                 radeon_cursor_move_locked(crtc, x, y);
 156
 157                 radeon_crtc->cursor_hot_x = hot_x;
 158                 radeon_crtc->cursor_hot_y = hot_y;
 159         }
 160 }
 161
 162 int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
 163                             struct drm_file *file_priv,
 164                             uint32_t handle,
 165                             uint32_t width,
 166                             uint32_t height,
 167                             int32_t hot_x,
 168                             int32_t hot_y)
 169 {
 170         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 171         struct radeon_device *rdev = crtc->dev->dev_private;
 172         struct drm_gem_object *obj;
 173         struct radeon_bo *robj;
 174         uint64_t gpu_addr;
 175         int ret;
 176
 177         if (!handle) {
 178                 /* turn off cursor */
 179                 radeon_hide_cursor(crtc);
 180                 obj = NULL;
 181                 goto unpin;
 182         }
 183
 184         if ((width > radeon_crtc->max_cursor_width) ||
 185             (height > radeon_crtc->max_cursor_height)) {
 186                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
 187                 return -EINVAL;
 188         }
 189
 190         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
 191         if (!obj) {
 192                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
 193                 return -ENOENT;
 194         }
 195
 196         robj = gem_to_radeon_bo(obj);
 197         ret = radeon_bo_reserve(robj, false);
 198         if (unlikely(ret != 0))
 199                 goto fail;
 200         /* Only 27 bit offset for legacy cursor */
 201         ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
 202                                        ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
 203                                        &gpu_addr);
 204         radeon_bo_unreserve(robj);
 205         if (ret)
 206                 goto fail;
 207
 208         radeon_crtc->cursor_width = width;
 209         radeon_crtc->cursor_height = height;
 210
 211         radeon_lock_cursor(crtc, true);
 212         radeon_set_cursor(crtc, obj, gpu_addr, hot_x, hot_y);
 213         radeon_show_cursor(crtc);
 214         radeon_lock_cursor(crtc, false);
 215
 216 unpin:
 217         if (radeon_crtc->cursor_bo) {
 218                 robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
 219                 ret = radeon_bo_reserve(robj, false);
 220                 if (likely(ret == 0)) {
 221                         radeon_bo_unpin(robj);
 222                         radeon_bo_unreserve(robj);
 223                 }
 224                 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
 225         }
 226
 227         radeon_crtc->cursor_bo = obj;
 228         return 0;
 229 fail:
 230         drm_gem_object_unreference_unlocked(obj);
 231
 232         return ret;
 233 }
 234
 235 static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
 236 {
 237         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 238         struct radeon_device *rdev = crtc->dev->dev_private;
 239         int xorigin = 0, yorigin = 0;
 240         int w = radeon_crtc->cursor_width;
 241
 242         if (ASIC_IS_AVIVO(rdev)) {
 243                 /* avivo cursor are offset into the total surface */
 244                 x += crtc->x;
 245                 y += crtc->y;
 246         }
 247         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
 248
 249         if (x < 0) {
 250                 xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
 251                 x = 0;
 252         }
 253         if (y < 0) {
 254                 yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
 255                 y = 0;
 256         }
 257
 258         /* fixed on DCE6 and newer */
 259         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
 260                 int i = 0;
 261                 struct drm_crtc *crtc_p;
 262
 263                 /*
 264                  * avivo cursor image can't end on 128 pixel boundary or
 265                  * go past the end of the frame if both crtcs are enabled
 266                  *
 267                  * NOTE: It is safe to access crtc->enabled of other crtcs
 268                  * without holding either the mode_config lock or the other
 269                  * crtc's lock as long as write access to this flag _always_
 270                  * grabs all locks.
 271                  */
 272                 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
 273                         if (crtc_p->enabled)
 274                                 i++;
 275                 }
 276                 if (i > 1) {
 277                         int cursor_end, frame_end;
 278
 279                         cursor_end = x - xorigin + w;
 280                         frame_end = crtc->x + crtc->mode.crtc_hdisplay;
 281                         if (cursor_end >= frame_end) {
 282                                 w = w - (cursor_end - frame_end);
 283                                 if (!(frame_end & 0x7f))
 284                                         w--;
 285                         } else {
 286                                 if (!(cursor_end & 0x7f))
 287                                         w--;
 288                         }
 289                         if (w <= 0) {
 290                                 w = 1;
 291                                 cursor_end = x - xorigin + w;
 292                                 if (!(cursor_end & 0x7f)) {
 293                                         x--;
 294                                         WARN_ON_ONCE(x < 0);
 295                                 }
 296                         }
 297                 }
 298         }
 299
 300         if (ASIC_IS_DCE4(rdev)) {
 301                 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
 302                 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
 303                 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
 304                        ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
 305         } else if (ASIC_IS_AVIVO(rdev)) {
 306                 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
 307                 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
 308                 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
 309                        ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
 310         } else {
 311                 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
 312                         y *= 2;
 313
 314                 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
 315                        (RADEON_CUR_LOCK
 316                         | (xorigin << 16)
 317                         | yorigin));
 318                 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
 319                        (RADEON_CUR_LOCK
 320                         | (x << 16)
 321                         | y));
 322                 /* offset is from DISP(2)_BASE_ADDRESS */
 323                 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
 324                                                                       (yorigin * 256)));
 325         }
 326
 327         radeon_crtc->cursor_x = x;
 328         radeon_crtc->cursor_y = y;
 329
 330         return 0;
 331 }
 332
 333 int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 334                             int x, int y)
 335 {
 336         int ret;
 337
 338         radeon_lock_cursor(crtc, true);
 339         ret = radeon_cursor_move_locked(crtc, x, y);
 340         radeon_lock_cursor(crtc, false);
 341
 342         return ret;
 343 }