drivers/gpu/drm/radeon/radeon_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "atom.h"
  38
  39 static const char radeon_family_name[][16] = {
  40         "R100",
  41         "RV100",
  42         "RS100",
  43         "RV200",
  44         "RS200",
  45         "R200",
  46         "RV250",
  47         "RS300",
  48         "RV280",
  49         "R300",
  50         "R350",
  51         "RV350",
  52         "RV380",
  53         "R420",
  54         "R423",
  55         "RV410",
  56         "RS400",
  57         "RS480",
  58         "RS600",
  59         "RS690",
  60         "RS740",
  61         "RV515",
  62         "R520",
  63         "RV530",
  64         "RV560",
  65         "RV570",
  66         "R580",
  67         "R600",
  68         "RV610",
  69         "RV630",
  70         "RV670",
  71         "RV620",
  72         "RV635",
  73         "RS780",
  74         "RS880",
  75         "RV770",
  76         "RV730",
  77         "RV710",
  78         "RV740",
  79         "CEDAR",
  80         "REDWOOD",
  81         "JUNIPER",
  82         "CYPRESS",
  83         "HEMLOCK",
  84         "LAST",
  85 };
  86
  87 /*
  88  * Clear GPU surface registers.
  89  */
  90 void radeon_surface_init(struct radeon_device *rdev)
  91 {
  92         /* FIXME: check this out */
  93         if (rdev->family < CHIP_R600) {
  94                 int i;
  95
  96                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  97                         if (rdev->surface_regs[i].bo)
  98                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
  99                         else
 100                                 radeon_clear_surface_reg(rdev, i);
 101                 }
 102                 /* enable surfaces */
 103                 WREG32(RADEON_SURFACE_CNTL, 0);
 104         }
 105 }
 106
 107 /*
 108  * GPU scratch registers helpers function.
 109  */
 110 void radeon_scratch_init(struct radeon_device *rdev)
 111 {
 112         int i;
 113
 114         /* FIXME: check this out */
 115         if (rdev->family < CHIP_R300) {
 116                 rdev->scratch.num_reg = 5;
 117         } else {
 118                 rdev->scratch.num_reg = 7;
 119         }
 120         rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 121         for (i = 0; i < rdev->scratch.num_reg; i++) {
 122                 rdev->scratch.free[i] = true;
 123                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 124         }
 125 }
 126
 127 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 128 {
 129         int i;
 130
 131         for (i = 0; i < rdev->scratch.num_reg; i++) {
 132                 if (rdev->scratch.free[i]) {
 133                         rdev->scratch.free[i] = false;
 134                         *reg = rdev->scratch.reg[i];
 135                         return 0;
 136                 }
 137         }
 138         return -EINVAL;
 139 }
 140
 141 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 142 {
 143         int i;
 144
 145         for (i = 0; i < rdev->scratch.num_reg; i++) {
 146                 if (rdev->scratch.reg[i] == reg) {
 147                         rdev->scratch.free[i] = true;
 148                         return;
 149                 }
 150         }
 151 }
 152
 153 void radeon_wb_disable(struct radeon_device *rdev)
 154 {
 155         int r;
 156
 157         if (rdev->wb.wb_obj) {
 158                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 159                 if (unlikely(r != 0))
 160                         return;
 161                 radeon_bo_kunmap(rdev->wb.wb_obj);
 162                 radeon_bo_unpin(rdev->wb.wb_obj);
 163                 radeon_bo_unreserve(rdev->wb.wb_obj);
 164         }
 165         rdev->wb.enabled = false;
 166 }
 167
 168 void radeon_wb_fini(struct radeon_device *rdev)
 169 {
 170         radeon_wb_disable(rdev);
 171         if (rdev->wb.wb_obj) {
 172                 radeon_bo_unref(&rdev->wb.wb_obj);
 173                 rdev->wb.wb = NULL;
 174                 rdev->wb.wb_obj = NULL;
 175         }
 176 }
 177
 178 int radeon_wb_init(struct radeon_device *rdev)
 179 {
 180         int r;
 181
 182         if (rdev->wb.wb_obj == NULL) {
 183                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 184                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
 185                 if (r) {
 186                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 187                         return r;
 188                 }
 189         }
 190         r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 191         if (unlikely(r != 0)) {
 192                 radeon_wb_fini(rdev);
 193                 return r;
 194         }
 195         r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 196                           &rdev->wb.gpu_addr);
 197         if (r) {
 198                 radeon_bo_unreserve(rdev->wb.wb_obj);
 199                 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 200                 radeon_wb_fini(rdev);
 201                 return r;
 202         }
 203         r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 204         radeon_bo_unreserve(rdev->wb.wb_obj);
 205         if (r) {
 206                 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 207                 radeon_wb_fini(rdev);
 208                 return r;
 209         }
 210
 211         /* disable event_write fences */
 212         rdev->wb.use_event = false;
 213         /* disabled via module param */
 214         if (radeon_no_wb == 1)
 215                 rdev->wb.enabled = false;
 216         else {
 217                 /* often unreliable on AGP */
 218                 if (rdev->flags & RADEON_IS_AGP) {
 219                         rdev->wb.enabled = false;
 220                 } else {
 221                         rdev->wb.enabled = true;
 222                         /* event_write fences are only available on r600+ */
 223                         if (rdev->family >= CHIP_R600)
 224                                 rdev->wb.use_event = true;
 225                 }
 226         }
 227
 228         dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 229
 230         return 0;
 231 }
 232
 233 /**
 234  * radeon_vram_location - try to find VRAM location
 235  * @rdev: radeon device structure holding all necessary informations
 236  * @mc: memory controller structure holding memory informations
 237  * @base: base address at which to put VRAM
 238  *
 239  * Function will place try to place VRAM at base address provided
 240  * as parameter (which is so far either PCI aperture address or
 241  * for IGP TOM base address).
 242  *
 243  * If there is not enough space to fit the unvisible VRAM in the 32bits
 244  * address space then we limit the VRAM size to the aperture.
 245  *
 246  * If we are using AGP and if the AGP aperture doesn't allow us to have
 247  * room for all the VRAM than we restrict the VRAM to the PCI aperture
 248  * size and print a warning.
 249  *
 250  * This function will never fails, worst case are limiting VRAM.
 251  *
 252  * Note: GTT start, end, size should be initialized before calling this
 253  * function on AGP platform.
 254  *
 255  * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
 256  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 257  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 258  * not IGP.
 259  *
 260  * Note: we use mc_vram_size as on some board we need to program the mc to
 261  * cover the whole aperture even if VRAM size is inferior to aperture size
 262  * Novell bug 204882 + along with lots of ubuntu ones
 263  *
 264  * Note: when limiting vram it's safe to overwritte real_vram_size because
 265  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 266  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 267  * ones)
 268  *
 269  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 270  * explicitly check for that thought.
 271  *
 272  * FIXME: when reducing VRAM size align new size on power of 2.
 273  */
 274 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 275 {
 276         mc->vram_start = base;
 277         if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
 278                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 279                 mc->real_vram_size = mc->aper_size;
 280                 mc->mc_vram_size = mc->aper_size;
 281         }
 282         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 283         if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 284                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 285                 mc->real_vram_size = mc->aper_size;
 286                 mc->mc_vram_size = mc->aper_size;
 287         }
 288         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 289         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 290                         mc->mc_vram_size >> 20, mc->vram_start,
 291                         mc->vram_end, mc->real_vram_size >> 20);
 292 }
 293
 294 /**
 295  * radeon_gtt_location - try to find GTT location
 296  * @rdev: radeon device structure holding all necessary informations
 297  * @mc: memory controller structure holding memory informations
 298  *
 299  * Function will place try to place GTT before or after VRAM.
 300  *
 301  * If GTT size is bigger than space left then we ajust GTT size.
 302  * Thus function will never fails.
 303  *
 304  * FIXME: when reducing GTT size align new size on power of 2.
 305  */
 306 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 307 {
 308         u64 size_af, size_bf;
 309
 310         size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 311         size_bf = mc->vram_start & ~mc->gtt_base_align;
 312         if (size_bf > size_af) {
 313                 if (mc->gtt_size > size_bf) {
 314                         dev_warn(rdev->dev, "limiting GTT\n");
 315                         mc->gtt_size = size_bf;
 316                 }
 317                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 318         } else {
 319                 if (mc->gtt_size > size_af) {
 320                         dev_warn(rdev->dev, "limiting GTT\n");
 321                         mc->gtt_size = size_af;
 322                 }
 323                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 324         }
 325         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 326         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 327                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 328 }
 329
 330 /*
 331  * GPU helpers function.
 332  */
 333 bool radeon_card_posted(struct radeon_device *rdev)
 334 {
 335         uint32_t reg;
 336
 337         /* first check CRTCs */
 338         if (ASIC_IS_DCE4(rdev)) {
 339                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 340                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
 341                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 342                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
 343                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 344                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 345                 if (reg & EVERGREEN_CRTC_MASTER_EN)
 346                         return true;
 347         } else if (ASIC_IS_AVIVO(rdev)) {
 348                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 349                       RREG32(AVIVO_D2CRTC_CONTROL);
 350                 if (reg & AVIVO_CRTC_EN) {
 351                         return true;
 352                 }
 353         } else {
 354                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 355                       RREG32(RADEON_CRTC2_GEN_CNTL);
 356                 if (reg & RADEON_CRTC_EN) {
 357                         return true;
 358                 }
 359         }
 360
 361         /* then check MEM_SIZE, in case the crtcs are off */
 362         if (rdev->family >= CHIP_R600)
 363                 reg = RREG32(R600_CONFIG_MEMSIZE);
 364         else
 365                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
 366
 367         if (reg)
 368                 return true;
 369
 370         return false;
 371
 372 }
 373
 374 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 375 {
 376         fixed20_12 a;
 377         u32 sclk = rdev->pm.current_sclk;
 378         u32 mclk = rdev->pm.current_mclk;
 379
 380         /* sclk/mclk in Mhz */
 381         a.full = dfixed_const(100);
 382         rdev->pm.sclk.full = dfixed_const(sclk);
 383         rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 384         rdev->pm.mclk.full = dfixed_const(mclk);
 385         rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 386
 387         if (rdev->flags & RADEON_IS_IGP) {
 388                 a.full = dfixed_const(16);
 389                 /* core_bandwidth = sclk(Mhz) * 16 */
 390                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 391         }
 392 }
 393
 394 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 395 {
 396         if (radeon_card_posted(rdev))
 397                 return true;
 398
 399         if (rdev->bios) {
 400                 DRM_INFO("GPU not posted. posting now...\n");
 401                 if (rdev->is_atom_bios)
 402                         atom_asic_init(rdev->mode_info.atom_context);
 403                 else
 404                         radeon_combios_asic_init(rdev->ddev);
 405                 return true;
 406         } else {
 407                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 408                 return false;
 409         }
 410 }
 411
 412 int radeon_dummy_page_init(struct radeon_device *rdev)
 413 {
 414         if (rdev->dummy_page.page)
 415                 return 0;
 416         rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 417         if (rdev->dummy_page.page == NULL)
 418                 return -ENOMEM;
 419         rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 420                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 421         if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 422                 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 423                 __free_page(rdev->dummy_page.page);
 424                 rdev->dummy_page.page = NULL;
 425                 return -ENOMEM;
 426         }
 427         return 0;
 428 }
 429
 430 void radeon_dummy_page_fini(struct radeon_device *rdev)
 431 {
 432         if (rdev->dummy_page.page == NULL)
 433                 return;
 434         pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 435                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 436         __free_page(rdev->dummy_page.page);
 437         rdev->dummy_page.page = NULL;
 438 }
 439
 440
 441 /* ATOM accessor methods */
 442 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 443 {
 444         struct radeon_device *rdev = info->dev->dev_private;
 445         uint32_t r;
 446
 447         r = rdev->pll_rreg(rdev, reg);
 448         return r;
 449 }
 450
 451 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 452 {
 453         struct radeon_device *rdev = info->dev->dev_private;
 454
 455         rdev->pll_wreg(rdev, reg, val);
 456 }
 457
 458 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 459 {
 460         struct radeon_device *rdev = info->dev->dev_private;
 461         uint32_t r;
 462
 463         r = rdev->mc_rreg(rdev, reg);
 464         return r;
 465 }
 466
 467 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 468 {
 469         struct radeon_device *rdev = info->dev->dev_private;
 470
 471         rdev->mc_wreg(rdev, reg, val);
 472 }
 473
 474 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 475 {
 476         struct radeon_device *rdev = info->dev->dev_private;
 477
 478         WREG32(reg*4, val);
 479 }
 480
 481 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 482 {
 483         struct radeon_device *rdev = info->dev->dev_private;
 484         uint32_t r;
 485
 486         r = RREG32(reg*4);
 487         return r;
 488 }
 489
 490 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 491 {
 492         struct radeon_device *rdev = info->dev->dev_private;
 493
 494         WREG32_IO(reg*4, val);
 495 }
 496
 497 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 498 {
 499         struct radeon_device *rdev = info->dev->dev_private;
 500         uint32_t r;
 501
 502         r = RREG32_IO(reg*4);
 503         return r;
 504 }
 505
 506 int radeon_atombios_init(struct radeon_device *rdev)
 507 {
 508         struct card_info *atom_card_info =
 509             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 510
 511         if (!atom_card_info)
 512                 return -ENOMEM;
 513
 514         rdev->mode_info.atom_card_info = atom_card_info;
 515         atom_card_info->dev = rdev->ddev;
 516         atom_card_info->reg_read = cail_reg_read;
 517         atom_card_info->reg_write = cail_reg_write;
 518         /* needed for iio ops */
 519         if (rdev->rio_mem) {
 520                 atom_card_info->ioreg_read = cail_ioreg_read;
 521                 atom_card_info->ioreg_write = cail_ioreg_write;
 522         } else {
 523                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 524                 atom_card_info->ioreg_read = cail_reg_read;
 525                 atom_card_info->ioreg_write = cail_reg_write;
 526         }
 527         atom_card_info->mc_read = cail_mc_read;
 528         atom_card_info->mc_write = cail_mc_write;
 529         atom_card_info->pll_read = cail_pll_read;
 530         atom_card_info->pll_write = cail_pll_write;
 531
 532         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 533         mutex_init(&rdev->mode_info.atom_context->mutex);
 534         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 535         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 536         return 0;
 537 }
 538
 539 void radeon_atombios_fini(struct radeon_device *rdev)
 540 {
 541         if (rdev->mode_info.atom_context) {
 542                 kfree(rdev->mode_info.atom_context->scratch);
 543                 kfree(rdev->mode_info.atom_context);
 544         }
 545         kfree(rdev->mode_info.atom_card_info);
 546 }
 547
 548 int radeon_combios_init(struct radeon_device *rdev)
 549 {
 550         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
 551         return 0;
 552 }
 553
 554 void radeon_combios_fini(struct radeon_device *rdev)
 555 {
 556 }
 557
 558 /* if we get transitioned to only one device, tak VGA back */
 559 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 560 {
 561         struct radeon_device *rdev = cookie;
 562         radeon_vga_set_state(rdev, state);
 563         if (state)
 564                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 565                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 566         else
 567                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 568 }
 569
 570 void radeon_check_arguments(struct radeon_device *rdev)
 571 {
 572         /* vramlimit must be a power of two */
 573         switch (radeon_vram_limit) {
 574         case 0:
 575         case 4:
 576         case 8:
 577         case 16:
 578         case 32:
 579         case 64:
 580         case 128:
 581         case 256:
 582         case 512:
 583         case 1024:
 584         case 2048:
 585         case 4096:
 586                 break;
 587         default:
 588                 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
 589                                 radeon_vram_limit);
 590                 radeon_vram_limit = 0;
 591                 break;
 592         }
 593         radeon_vram_limit = radeon_vram_limit << 20;
 594         /* gtt size must be power of two and greater or equal to 32M */
 595         switch (radeon_gart_size) {
 596         case 4:
 597         case 8:
 598         case 16:
 599                 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
 600                                 radeon_gart_size);
 601                 radeon_gart_size = 512;
 602                 break;
 603         case 32:
 604         case 64:
 605         case 128:
 606         case 256:
 607         case 512:
 608         case 1024:
 609         case 2048:
 610         case 4096:
 611                 break;
 612         default:
 613                 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
 614                                 radeon_gart_size);
 615                 radeon_gart_size = 512;
 616                 break;
 617         }
 618         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 619         /* AGP mode can only be -1, 1, 2, 4, 8 */
 620         switch (radeon_agpmode) {
 621         case -1:
 622         case 0:
 623         case 1:
 624         case 2:
 625         case 4:
 626         case 8:
 627                 break;
 628         default:
 629                 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
 630                                 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
 631                 radeon_agpmode = 0;
 632                 break;
 633         }
 634 }
 635
 636 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 637 {
 638         struct drm_device *dev = pci_get_drvdata(pdev);
 639         struct radeon_device *rdev = dev->dev_private;
 640         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 641         if (state == VGA_SWITCHEROO_ON) {
 642                 printk(KERN_INFO "radeon: switched on\n");
 643                 /* don't suspend or resume card normally */
 644                 rdev->powered_down = false;
 645                 radeon_resume_kms(dev);
 646                 drm_kms_helper_poll_enable(dev);
 647         } else {
 648                 printk(KERN_INFO "radeon: switched off\n");
 649                 drm_kms_helper_poll_disable(dev);
 650                 radeon_suspend_kms(dev, pmm);
 651                 /* don't suspend or resume card normally */
 652                 rdev->powered_down = true;
 653         }
 654 }
 655
 656 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
 657 {
 658         struct drm_device *dev = pci_get_drvdata(pdev);
 659         bool can_switch;
 660
 661         spin_lock(&dev->count_lock);
 662         can_switch = (dev->open_count == 0);
 663         spin_unlock(&dev->count_lock);
 664         return can_switch;
 665 }
 666
 667
 668 int radeon_device_init(struct radeon_device *rdev,
 669                        struct drm_device *ddev,
 670                        struct pci_dev *pdev,
 671                        uint32_t flags)
 672 {
 673         int r, i;
 674         int dma_bits;
 675
 676         rdev->shutdown = false;
 677         rdev->dev = &pdev->dev;
 678         rdev->ddev = ddev;
 679         rdev->pdev = pdev;
 680         rdev->flags = flags;
 681         rdev->family = flags & RADEON_FAMILY_MASK;
 682         rdev->is_atom_bios = false;
 683         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 684         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 685         rdev->gpu_lockup = false;
 686         rdev->accel_working = false;
 687
 688         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
 689                 radeon_family_name[rdev->family], pdev->vendor, pdev->device);
 690
 691         /* mutex initialization are all done here so we
 692          * can recall function without having locking issues */
 693         mutex_init(&rdev->cs_mutex);
 694         mutex_init(&rdev->ib_pool.mutex);
 695         mutex_init(&rdev->cp.mutex);
 696         mutex_init(&rdev->dc_hw_i2c_mutex);
 697         if (rdev->family >= CHIP_R600)
 698                 spin_lock_init(&rdev->ih.lock);
 699         mutex_init(&rdev->gem.mutex);
 700         mutex_init(&rdev->pm.mutex);
 701         mutex_init(&rdev->vram_mutex);
 702         rwlock_init(&rdev->fence_drv.lock);
 703         INIT_LIST_HEAD(&rdev->gem.objects);
 704         init_waitqueue_head(&rdev->irq.vblank_queue);
 705         init_waitqueue_head(&rdev->irq.idle_queue);
 706
 707         /* setup workqueue */
 708         rdev->wq = create_workqueue("radeon");
 709         if (rdev->wq == NULL)
 710                 return -ENOMEM;
 711
 712         /* Set asic functions */
 713         r = radeon_asic_init(rdev);
 714         if (r)
 715                 return r;
 716         radeon_check_arguments(rdev);
 717
 718         /* all of the newer IGP chips have an internal gart
 719          * However some rs4xx report as AGP, so remove that here.
 720          */
 721         if ((rdev->family >= CHIP_RS400) &&
 722             (rdev->flags & RADEON_IS_IGP)) {
 723                 rdev->flags &= ~RADEON_IS_AGP;
 724         }
 725
 726         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
 727                 radeon_agp_disable(rdev);
 728         }
 729
 730         /* set DMA mask + need_dma32 flags.
 731          * PCIE - can handle 40-bits.
 732          * IGP - can handle 40-bits (in theory)
 733          * AGP - generally dma32 is safest
 734          * PCI - only dma32
 735          */
 736         rdev->need_dma32 = false;
 737         if (rdev->flags & RADEON_IS_AGP)
 738                 rdev->need_dma32 = true;
 739         if (rdev->flags & RADEON_IS_PCI)
 740                 rdev->need_dma32 = true;
 741
 742         dma_bits = rdev->need_dma32 ? 32 : 40;
 743         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 744         if (r) {
 745                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
 746         }
 747
 748         /* Registers mapping */
 749         /* TODO: block userspace mapping of io register */
 750         rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 751         rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 752         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
 753         if (rdev->rmmio == NULL) {
 754                 return -ENOMEM;
 755         }
 756         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 757         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 758
 759         /* io port mapping */
 760         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 761                 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
 762                         rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
 763                         rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
 764                         break;
 765                 }
 766         }
 767         if (rdev->rio_mem == NULL)
 768                 DRM_ERROR("Unable to find PCI I/O BAR\n");
 769
 770         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
 771         /* this will fail for cards that aren't VGA class devices, just
 772          * ignore it */
 773         vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 774         vga_switcheroo_register_client(rdev->pdev,
 775                                        radeon_switcheroo_set_state,
 776                                        radeon_switcheroo_can_switch);
 777
 778         r = radeon_init(rdev);
 779         if (r)
 780                 return r;
 781
 782         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
 783                 /* Acceleration not working on AGP card try again
 784                  * with fallback to PCI or PCIE GART
 785                  */
 786                 radeon_asic_reset(rdev);
 787                 radeon_fini(rdev);
 788                 radeon_agp_disable(rdev);
 789                 r = radeon_init(rdev);
 790                 if (r)
 791                         return r;
 792         }
 793         if (radeon_testing) {
 794                 radeon_test_moves(rdev);
 795         }
 796         if (radeon_benchmarking) {
 797                 radeon_benchmark(rdev);
 798         }
 799         return 0;
 800 }
 801
 802 void radeon_device_fini(struct radeon_device *rdev)
 803 {
 804         DRM_INFO("radeon: finishing device.\n");
 805         rdev->shutdown = true;
 806         /* evict vram memory */
 807         radeon_bo_evict_vram(rdev);
 808         radeon_fini(rdev);
 809         destroy_workqueue(rdev->wq);
 810         vga_switcheroo_unregister_client(rdev->pdev);
 811         vga_client_register(rdev->pdev, NULL, NULL, NULL);
 812         if (rdev->rio_mem)
 813                 pci_iounmap(rdev->pdev, rdev->rio_mem);
 814         rdev->rio_mem = NULL;
 815         iounmap(rdev->rmmio);
 816         rdev->rmmio = NULL;
 817 }
 818
 819
 820 /*
 821  * Suspend & resume.
 822  */
 823 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 824 {
 825         struct radeon_device *rdev;
 826         struct drm_crtc *crtc;
 827         struct drm_connector *connector;
 828         int r;
 829
 830         if (dev == NULL || dev->dev_private == NULL) {
 831                 return -ENODEV;
 832         }
 833         if (state.event == PM_EVENT_PRETHAW) {
 834                 return 0;
 835         }
 836         rdev = dev->dev_private;
 837
 838         if (rdev->powered_down)
 839                 return 0;
 840
 841         /* turn off display hw */
 842         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 843                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
 844         }
 845
 846         /* unpin the front buffers */
 847         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 848                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
 849                 struct radeon_bo *robj;
 850
 851                 if (rfb == NULL || rfb->obj == NULL) {
 852                         continue;
 853                 }
 854                 robj = rfb->obj->driver_private;
 855                 /* don't unpin kernel fb objects */
 856                 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
 857                         r = radeon_bo_reserve(robj, false);
 858                         if (r == 0) {
 859                                 radeon_bo_unpin(robj);
 860                                 radeon_bo_unreserve(robj);
 861                         }
 862                 }
 863         }
 864         /* evict vram memory */
 865         radeon_bo_evict_vram(rdev);
 866         /* wait for gpu to finish processing current batch */
 867         radeon_fence_wait_last(rdev);
 868
 869         radeon_save_bios_scratch_regs(rdev);
 870
 871         radeon_pm_suspend(rdev);
 872         radeon_suspend(rdev);
 873         radeon_hpd_fini(rdev);
 874         /* evict remaining vram memory */
 875         radeon_bo_evict_vram(rdev);
 876
 877         radeon_agp_suspend(rdev);
 878
 879         pci_save_state(dev->pdev);
 880         if (state.event == PM_EVENT_SUSPEND) {
 881                 /* Shut down the device */
 882                 pci_disable_device(dev->pdev);
 883                 pci_set_power_state(dev->pdev, PCI_D3hot);
 884         }
 885         acquire_console_sem();
 886         radeon_fbdev_set_suspend(rdev, 1);
 887         release_console_sem();
 888         return 0;
 889 }
 890
 891 int radeon_resume_kms(struct drm_device *dev)
 892 {
 893         struct drm_connector *connector;
 894         struct radeon_device *rdev = dev->dev_private;
 895
 896         if (rdev->powered_down)
 897                 return 0;
 898
 899         acquire_console_sem();
 900         pci_set_power_state(dev->pdev, PCI_D0);
 901         pci_restore_state(dev->pdev);
 902         if (pci_enable_device(dev->pdev)) {
 903                 release_console_sem();
 904                 return -1;
 905         }
 906         pci_set_master(dev->pdev);
 907         /* resume AGP if in use */
 908         radeon_agp_resume(rdev);
 909         radeon_resume(rdev);
 910         radeon_pm_resume(rdev);
 911         radeon_restore_bios_scratch_regs(rdev);
 912
 913         /* turn on display hw */
 914         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 915                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
 916         }
 917
 918         radeon_fbdev_set_suspend(rdev, 0);
 919         release_console_sem();
 920
 921         /* reset hpd state */
 922         radeon_hpd_init(rdev);
 923         /* blat the mode back in */
 924         drm_helper_resume_force_mode(dev);
 925         return 0;
 926 }
 927
 928 int radeon_gpu_reset(struct radeon_device *rdev)
 929 {
 930         int r;
 931
 932         radeon_save_bios_scratch_regs(rdev);
 933         radeon_suspend(rdev);
 934
 935         r = radeon_asic_reset(rdev);
 936         if (!r) {
 937                 dev_info(rdev->dev, "GPU reset succeed\n");
 938                 radeon_resume(rdev);
 939                 radeon_restore_bios_scratch_regs(rdev);
 940                 drm_helper_resume_force_mode(rdev->ddev);
 941                 return 0;
 942         }
 943         /* bad news, how to tell it to userspace ? */
 944         dev_info(rdev->dev, "GPU reset failed\n");
 945         return r;
 946 }
 947
 948
 949 /*
 950  * Debugfs
 951  */
 952 struct radeon_debugfs {
 953         struct drm_info_list    *files;
 954         unsigned                num_files;
 955 };
 956 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
 957 static unsigned _radeon_debugfs_count = 0;
 958
 959 int radeon_debugfs_add_files(struct radeon_device *rdev,
 960                              struct drm_info_list *files,
 961                              unsigned nfiles)
 962 {
 963         unsigned i;
 964
 965         for (i = 0; i < _radeon_debugfs_count; i++) {
 966                 if (_radeon_debugfs[i].files == files) {
 967                         /* Already registered */
 968                         return 0;
 969                 }
 970         }
 971         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
 972                 DRM_ERROR("Reached maximum number of debugfs files.\n");
 973                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
 974                 return -EINVAL;
 975         }
 976         _radeon_debugfs[_radeon_debugfs_count].files = files;
 977         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
 978         _radeon_debugfs_count++;
 979 #if defined(CONFIG_DEBUG_FS)
 980         drm_debugfs_create_files(files, nfiles,
 981                                  rdev->ddev->control->debugfs_root,
 982                                  rdev->ddev->control);
 983         drm_debugfs_create_files(files, nfiles,
 984                                  rdev->ddev->primary->debugfs_root,
 985                                  rdev->ddev->primary);
 986 #endif
 987         return 0;
 988 }
 989
 990 #if defined(CONFIG_DEBUG_FS)
 991 int radeon_debugfs_init(struct drm_minor *minor)
 992 {
 993         return 0;
 994 }
 995
 996 void radeon_debugfs_cleanup(struct drm_minor *minor)
 997 {
 998         unsigned i;
 999
1000         for (i = 0; i < _radeon_debugfs_count; i++) {
1001                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1002                                          _radeon_debugfs[i].num_files, minor);
1003         }
1004 }
1005 #endif