]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/gpu/drm/radeon/radeon_display.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/radeon/kms: fallback to default connector table
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
72 {
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77 uint32_t dac2_cntl;
78
79 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
80 if (radeon_crtc->crtc_id == 0)
81 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
82 else
83 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
84 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
85
86 WREG8(RADEON_PALETTE_INDEX, 0);
87 for (i = 0; i < 256; i++) {
88 WREG32(RADEON_PALETTE_30_DATA,
89 (radeon_crtc->lut_r[i] << 20) |
90 (radeon_crtc->lut_g[i] << 10) |
91 (radeon_crtc->lut_b[i] << 0));
92 }
93 }
94
95 void radeon_crtc_load_lut(struct drm_crtc *crtc)
96 {
97 struct drm_device *dev = crtc->dev;
98 struct radeon_device *rdev = dev->dev_private;
99
100 if (!crtc->enabled)
101 return;
102
103 if (ASIC_IS_AVIVO(rdev))
104 avivo_crtc_load_lut(crtc);
105 else
106 legacy_crtc_load_lut(crtc);
107 }
108
109 /** Sets the color ramps on behalf of fbcon */
110 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
111 u16 blue, int regno)
112 {
113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
114
115 radeon_crtc->lut_r[regno] = red >> 6;
116 radeon_crtc->lut_g[regno] = green >> 6;
117 radeon_crtc->lut_b[regno] = blue >> 6;
118 }
119
120 /** Gets the color ramps on behalf of fbcon */
121 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
122 u16 *blue, int regno)
123 {
124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125
126 *red = radeon_crtc->lut_r[regno] << 6;
127 *green = radeon_crtc->lut_g[regno] << 6;
128 *blue = radeon_crtc->lut_b[regno] << 6;
129 }
130
131 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
132 u16 *blue, uint32_t size)
133 {
134 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
135 int i;
136
137 if (size != 256) {
138 return;
139 }
140
141 /* userspace palettes are always correct as is */
142 for (i = 0; i < 256; i++) {
143 radeon_crtc->lut_r[i] = red[i] >> 6;
144 radeon_crtc->lut_g[i] = green[i] >> 6;
145 radeon_crtc->lut_b[i] = blue[i] >> 6;
146 }
147 radeon_crtc_load_lut(crtc);
148 }
149
150 static void radeon_crtc_destroy(struct drm_crtc *crtc)
151 {
152 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
153
154 drm_crtc_cleanup(crtc);
155 kfree(radeon_crtc);
156 }
157
158 static const struct drm_crtc_funcs radeon_crtc_funcs = {
159 .cursor_set = radeon_crtc_cursor_set,
160 .cursor_move = radeon_crtc_cursor_move,
161 .gamma_set = radeon_crtc_gamma_set,
162 .set_config = drm_crtc_helper_set_config,
163 .destroy = radeon_crtc_destroy,
164 };
165
166 static void radeon_crtc_init(struct drm_device *dev, int index)
167 {
168 struct radeon_device *rdev = dev->dev_private;
169 struct radeon_crtc *radeon_crtc;
170 int i;
171
172 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
173 if (radeon_crtc == NULL)
174 return;
175
176 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
177
178 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
179 radeon_crtc->crtc_id = index;
180 rdev->mode_info.crtcs[index] = radeon_crtc;
181
182 #if 0
183 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
184 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
185 radeon_crtc->mode_set.num_connectors = 0;
186 #endif
187
188 for (i = 0; i < 256; i++) {
189 radeon_crtc->lut_r[i] = i << 2;
190 radeon_crtc->lut_g[i] = i << 2;
191 radeon_crtc->lut_b[i] = i << 2;
192 }
193
194 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
195 radeon_atombios_init_crtc(dev, radeon_crtc);
196 else
197 radeon_legacy_init_crtc(dev, radeon_crtc);
198 }
199
200 static const char *encoder_names[34] = {
201 "NONE",
202 "INTERNAL_LVDS",
203 "INTERNAL_TMDS1",
204 "INTERNAL_TMDS2",
205 "INTERNAL_DAC1",
206 "INTERNAL_DAC2",
207 "INTERNAL_SDVOA",
208 "INTERNAL_SDVOB",
209 "SI170B",
210 "CH7303",
211 "CH7301",
212 "INTERNAL_DVO1",
213 "EXTERNAL_SDVOA",
214 "EXTERNAL_SDVOB",
215 "TITFP513",
216 "INTERNAL_LVTM1",
217 "VT1623",
218 "HDMI_SI1930",
219 "HDMI_INTERNAL",
220 "INTERNAL_KLDSCP_TMDS1",
221 "INTERNAL_KLDSCP_DVO1",
222 "INTERNAL_KLDSCP_DAC1",
223 "INTERNAL_KLDSCP_DAC2",
224 "SI178",
225 "MVPU_FPGA",
226 "INTERNAL_DDI",
227 "VT1625",
228 "HDMI_SI1932",
229 "DP_AN9801",
230 "DP_DP501",
231 "INTERNAL_UNIPHY",
232 "INTERNAL_KLDSCP_LVTMA",
233 "INTERNAL_UNIPHY1",
234 "INTERNAL_UNIPHY2",
235 };
236
237 static const char *connector_names[13] = {
238 "Unknown",
239 "VGA",
240 "DVI-I",
241 "DVI-D",
242 "DVI-A",
243 "Composite",
244 "S-video",
245 "LVDS",
246 "Component",
247 "DIN",
248 "DisplayPort",
249 "HDMI-A",
250 "HDMI-B",
251 };
252
253 static const char *hpd_names[7] = {
254 "NONE",
255 "HPD1",
256 "HPD2",
257 "HPD3",
258 "HPD4",
259 "HPD5",
260 "HPD6",
261 };
262
263 static void radeon_print_display_setup(struct drm_device *dev)
264 {
265 struct drm_connector *connector;
266 struct radeon_connector *radeon_connector;
267 struct drm_encoder *encoder;
268 struct radeon_encoder *radeon_encoder;
269 uint32_t devices;
270 int i = 0;
271
272 DRM_INFO("Radeon Display Connectors\n");
273 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
274 radeon_connector = to_radeon_connector(connector);
275 DRM_INFO("Connector %d:\n", i);
276 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
277 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
278 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
279 if (radeon_connector->ddc_bus)
280 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
281 radeon_connector->ddc_bus->rec.mask_clk_reg,
282 radeon_connector->ddc_bus->rec.mask_data_reg,
283 radeon_connector->ddc_bus->rec.a_clk_reg,
284 radeon_connector->ddc_bus->rec.a_data_reg,
285 radeon_connector->ddc_bus->rec.en_clk_reg,
286 radeon_connector->ddc_bus->rec.en_data_reg,
287 radeon_connector->ddc_bus->rec.y_clk_reg,
288 radeon_connector->ddc_bus->rec.y_data_reg);
289 DRM_INFO(" Encoders:\n");
290 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
291 radeon_encoder = to_radeon_encoder(encoder);
292 devices = radeon_encoder->devices & radeon_connector->devices;
293 if (devices) {
294 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
295 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
296 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
297 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
298 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
299 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
300 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
301 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
302 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
303 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
304 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
305 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
306 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
307 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
308 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
309 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
310 if (devices & ATOM_DEVICE_TV1_SUPPORT)
311 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
312 if (devices & ATOM_DEVICE_CV_SUPPORT)
313 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
314 }
315 }
316 i++;
317 }
318 }
319
320 static bool radeon_setup_enc_conn(struct drm_device *dev)
321 {
322 struct radeon_device *rdev = dev->dev_private;
323 struct drm_connector *drm_connector;
324 bool ret = false;
325
326 if (rdev->bios) {
327 if (rdev->is_atom_bios) {
328 if (rdev->family >= CHIP_R600)
329 ret = radeon_get_atom_connector_info_from_object_table(dev);
330 else
331 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
332 } else {
333 ret = radeon_get_legacy_connector_info_from_bios(dev);
334 if (ret == false)
335 ret = radeon_get_legacy_connector_info_from_table(dev);
336 }
337 } else {
338 if (!ASIC_IS_AVIVO(rdev))
339 ret = radeon_get_legacy_connector_info_from_table(dev);
340 }
341 if (ret) {
342 radeon_setup_encoder_clones(dev);
343 radeon_print_display_setup(dev);
344 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
345 radeon_ddc_dump(drm_connector);
346 }
347
348 return ret;
349 }
350
351 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
352 {
353 int ret = 0;
354
355 if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
356 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
357 if (dig->dp_i2c_bus)
358 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
359 }
360 if (!radeon_connector->ddc_bus)
361 return -1;
362 if (!radeon_connector->edid) {
363 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
364 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
365 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
366 }
367
368 if (radeon_connector->edid) {
369 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
370 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
371 return ret;
372 }
373 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
374 return 0;
375 }
376
377 static int radeon_ddc_dump(struct drm_connector *connector)
378 {
379 struct edid *edid;
380 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
381 int ret = 0;
382
383 if (!radeon_connector->ddc_bus)
384 return -1;
385 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
386 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
387 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
388 if (edid) {
389 kfree(edid);
390 }
391 return ret;
392 }
393
394 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
395 {
396 uint64_t mod;
397
398 n += d / 2;
399
400 mod = do_div(n, d);
401 return n;
402 }
403
404 void radeon_compute_pll(struct radeon_pll *pll,
405 uint64_t freq,
406 uint32_t *dot_clock_p,
407 uint32_t *fb_div_p,
408 uint32_t *frac_fb_div_p,
409 uint32_t *ref_div_p,
410 uint32_t *post_div_p,
411 int flags)
412 {
413 uint32_t min_ref_div = pll->min_ref_div;
414 uint32_t max_ref_div = pll->max_ref_div;
415 uint32_t min_fractional_feed_div = 0;
416 uint32_t max_fractional_feed_div = 0;
417 uint32_t best_vco = pll->best_vco;
418 uint32_t best_post_div = 1;
419 uint32_t best_ref_div = 1;
420 uint32_t best_feedback_div = 1;
421 uint32_t best_frac_feedback_div = 0;
422 uint32_t best_freq = -1;
423 uint32_t best_error = 0xffffffff;
424 uint32_t best_vco_diff = 1;
425 uint32_t post_div;
426
427 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
428 freq = freq * 1000;
429
430 if (flags & RADEON_PLL_USE_REF_DIV)
431 min_ref_div = max_ref_div = pll->reference_div;
432 else {
433 while (min_ref_div < max_ref_div-1) {
434 uint32_t mid = (min_ref_div + max_ref_div) / 2;
435 uint32_t pll_in = pll->reference_freq / mid;
436 if (pll_in < pll->pll_in_min)
437 max_ref_div = mid;
438 else if (pll_in > pll->pll_in_max)
439 min_ref_div = mid;
440 else
441 break;
442 }
443 }
444
445 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
446 min_fractional_feed_div = pll->min_frac_feedback_div;
447 max_fractional_feed_div = pll->max_frac_feedback_div;
448 }
449
450 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
451 uint32_t ref_div;
452
453 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
454 continue;
455
456 /* legacy radeons only have a few post_divs */
457 if (flags & RADEON_PLL_LEGACY) {
458 if ((post_div == 5) ||
459 (post_div == 7) ||
460 (post_div == 9) ||
461 (post_div == 10) ||
462 (post_div == 11) ||
463 (post_div == 13) ||
464 (post_div == 14) ||
465 (post_div == 15))
466 continue;
467 }
468
469 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
470 uint32_t feedback_div, current_freq = 0, error, vco_diff;
471 uint32_t pll_in = pll->reference_freq / ref_div;
472 uint32_t min_feed_div = pll->min_feedback_div;
473 uint32_t max_feed_div = pll->max_feedback_div + 1;
474
475 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
476 continue;
477
478 while (min_feed_div < max_feed_div) {
479 uint32_t vco;
480 uint32_t min_frac_feed_div = min_fractional_feed_div;
481 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
482 uint32_t frac_feedback_div;
483 uint64_t tmp;
484
485 feedback_div = (min_feed_div + max_feed_div) / 2;
486
487 tmp = (uint64_t)pll->reference_freq * feedback_div;
488 vco = radeon_div(tmp, ref_div);
489
490 if (vco < pll->pll_out_min) {
491 min_feed_div = feedback_div + 1;
492 continue;
493 } else if (vco > pll->pll_out_max) {
494 max_feed_div = feedback_div;
495 continue;
496 }
497
498 while (min_frac_feed_div < max_frac_feed_div) {
499 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
500 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
501 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
502 current_freq = radeon_div(tmp, ref_div * post_div);
503
504 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
505 error = freq - current_freq;
506 error = error < 0 ? 0xffffffff : error;
507 } else
508 error = abs(current_freq - freq);
509 vco_diff = abs(vco - best_vco);
510
511 if ((best_vco == 0 && error < best_error) ||
512 (best_vco != 0 &&
513 (error < best_error - 100 ||
514 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
515 best_post_div = post_div;
516 best_ref_div = ref_div;
517 best_feedback_div = feedback_div;
518 best_frac_feedback_div = frac_feedback_div;
519 best_freq = current_freq;
520 best_error = error;
521 best_vco_diff = vco_diff;
522 } else if (current_freq == freq) {
523 if (best_freq == -1) {
524 best_post_div = post_div;
525 best_ref_div = ref_div;
526 best_feedback_div = feedback_div;
527 best_frac_feedback_div = frac_feedback_div;
528 best_freq = current_freq;
529 best_error = error;
530 best_vco_diff = vco_diff;
531 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
532 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
533 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
534 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
535 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
536 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
537 best_post_div = post_div;
538 best_ref_div = ref_div;
539 best_feedback_div = feedback_div;
540 best_frac_feedback_div = frac_feedback_div;
541 best_freq = current_freq;
542 best_error = error;
543 best_vco_diff = vco_diff;
544 }
545 }
546 if (current_freq < freq)
547 min_frac_feed_div = frac_feedback_div + 1;
548 else
549 max_frac_feed_div = frac_feedback_div;
550 }
551 if (current_freq < freq)
552 min_feed_div = feedback_div + 1;
553 else
554 max_feed_div = feedback_div;
555 }
556 }
557 }
558
559 *dot_clock_p = best_freq / 10000;
560 *fb_div_p = best_feedback_div;
561 *frac_fb_div_p = best_frac_feedback_div;
562 *ref_div_p = best_ref_div;
563 *post_div_p = best_post_div;
564 }
565
566 void radeon_compute_pll_avivo(struct radeon_pll *pll,
567 uint64_t freq,
568 uint32_t *dot_clock_p,
569 uint32_t *fb_div_p,
570 uint32_t *frac_fb_div_p,
571 uint32_t *ref_div_p,
572 uint32_t *post_div_p,
573 int flags)
574 {
575 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
576 fixed20_12 pll_out_max, pll_out_min;
577 fixed20_12 pll_in_max, pll_in_min;
578 fixed20_12 reference_freq;
579 fixed20_12 error, ffreq, a, b;
580
581 pll_out_max.full = rfixed_const(pll->pll_out_max);
582 pll_out_min.full = rfixed_const(pll->pll_out_min);
583 pll_in_max.full = rfixed_const(pll->pll_in_max);
584 pll_in_min.full = rfixed_const(pll->pll_in_min);
585 reference_freq.full = rfixed_const(pll->reference_freq);
586 do_div(freq, 10);
587 ffreq.full = rfixed_const(freq);
588 error.full = rfixed_const(100 * 100);
589
590 /* max p */
591 p.full = rfixed_div(pll_out_max, ffreq);
592 p.full = rfixed_floor(p);
593
594 /* min m */
595 m.full = rfixed_div(reference_freq, pll_in_max);
596 m.full = rfixed_ceil(m);
597
598 while (1) {
599 n.full = rfixed_div(ffreq, reference_freq);
600 n.full = rfixed_mul(n, m);
601 n.full = rfixed_mul(n, p);
602
603 f_vco.full = rfixed_div(n, m);
604 f_vco.full = rfixed_mul(f_vco, reference_freq);
605
606 f_pclk.full = rfixed_div(f_vco, p);
607
608 if (f_pclk.full > ffreq.full)
609 error.full = f_pclk.full - ffreq.full;
610 else
611 error.full = ffreq.full - f_pclk.full;
612 error.full = rfixed_div(error, f_pclk);
613 a.full = rfixed_const(100 * 100);
614 error.full = rfixed_mul(error, a);
615
616 a.full = rfixed_mul(m, p);
617 a.full = rfixed_div(n, a);
618 best_freq.full = rfixed_mul(reference_freq, a);
619
620 if (rfixed_trunc(error) < 25)
621 break;
622
623 a.full = rfixed_const(1);
624 m.full = m.full + a.full;
625 a.full = rfixed_div(reference_freq, m);
626 if (a.full >= pll_in_min.full)
627 continue;
628
629 m.full = rfixed_div(reference_freq, pll_in_max);
630 m.full = rfixed_ceil(m);
631 a.full= rfixed_const(1);
632 p.full = p.full - a.full;
633 a.full = rfixed_mul(p, ffreq);
634 if (a.full >= pll_out_min.full)
635 continue;
636 else {
637 DRM_ERROR("Unable to find pll dividers\n");
638 break;
639 }
640 }
641
642 a.full = rfixed_const(10);
643 b.full = rfixed_mul(n, a);
644
645 frac_n.full = rfixed_floor(n);
646 frac_n.full = rfixed_mul(frac_n, a);
647 frac_n.full = b.full - frac_n.full;
648
649 *dot_clock_p = rfixed_trunc(best_freq);
650 *fb_div_p = rfixed_trunc(n);
651 *frac_fb_div_p = rfixed_trunc(frac_n);
652 *ref_div_p = rfixed_trunc(m);
653 *post_div_p = rfixed_trunc(p);
654
655 DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
656 }
657
658 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
659 {
660 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
661 struct drm_device *dev = fb->dev;
662
663 if (fb->fbdev)
664 radeonfb_remove(dev, fb);
665
666 if (radeon_fb->obj) {
667 radeon_gem_object_unpin(radeon_fb->obj);
668 mutex_lock(&dev->struct_mutex);
669 drm_gem_object_unreference(radeon_fb->obj);
670 mutex_unlock(&dev->struct_mutex);
671 }
672 drm_framebuffer_cleanup(fb);
673 kfree(radeon_fb);
674 }
675
676 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
677 struct drm_file *file_priv,
678 unsigned int *handle)
679 {
680 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
681
682 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
683 }
684
685 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
686 .destroy = radeon_user_framebuffer_destroy,
687 .create_handle = radeon_user_framebuffer_create_handle,
688 };
689
690 struct drm_framebuffer *
691 radeon_framebuffer_create(struct drm_device *dev,
692 struct drm_mode_fb_cmd *mode_cmd,
693 struct drm_gem_object *obj)
694 {
695 struct radeon_framebuffer *radeon_fb;
696
697 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
698 if (radeon_fb == NULL) {
699 return NULL;
700 }
701 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
702 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
703 radeon_fb->obj = obj;
704 return &radeon_fb->base;
705 }
706
707 static struct drm_framebuffer *
708 radeon_user_framebuffer_create(struct drm_device *dev,
709 struct drm_file *file_priv,
710 struct drm_mode_fb_cmd *mode_cmd)
711 {
712 struct drm_gem_object *obj;
713
714 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
715
716 return radeon_framebuffer_create(dev, mode_cmd, obj);
717 }
718
719 static const struct drm_mode_config_funcs radeon_mode_funcs = {
720 .fb_create = radeon_user_framebuffer_create,
721 .fb_changed = radeonfb_probe,
722 };
723
724 struct drm_prop_enum_list {
725 int type;
726 char *name;
727 };
728
729 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
730 { { 0, "driver" },
731 { 1, "bios" },
732 };
733
734 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
735 { { TV_STD_NTSC, "ntsc" },
736 { TV_STD_PAL, "pal" },
737 { TV_STD_PAL_M, "pal-m" },
738 { TV_STD_PAL_60, "pal-60" },
739 { TV_STD_NTSC_J, "ntsc-j" },
740 { TV_STD_SCART_PAL, "scart-pal" },
741 { TV_STD_PAL_CN, "pal-cn" },
742 { TV_STD_SECAM, "secam" },
743 };
744
745 static int radeon_modeset_create_props(struct radeon_device *rdev)
746 {
747 int i, sz;
748
749 if (rdev->is_atom_bios) {
750 rdev->mode_info.coherent_mode_property =
751 drm_property_create(rdev->ddev,
752 DRM_MODE_PROP_RANGE,
753 "coherent", 2);
754 if (!rdev->mode_info.coherent_mode_property)
755 return -ENOMEM;
756
757 rdev->mode_info.coherent_mode_property->values[0] = 0;
758 rdev->mode_info.coherent_mode_property->values[1] = 1;
759 }
760
761 if (!ASIC_IS_AVIVO(rdev)) {
762 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
763 rdev->mode_info.tmds_pll_property =
764 drm_property_create(rdev->ddev,
765 DRM_MODE_PROP_ENUM,
766 "tmds_pll", sz);
767 for (i = 0; i < sz; i++) {
768 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
769 i,
770 radeon_tmds_pll_enum_list[i].type,
771 radeon_tmds_pll_enum_list[i].name);
772 }
773 }
774
775 rdev->mode_info.load_detect_property =
776 drm_property_create(rdev->ddev,
777 DRM_MODE_PROP_RANGE,
778 "load detection", 2);
779 if (!rdev->mode_info.load_detect_property)
780 return -ENOMEM;
781 rdev->mode_info.load_detect_property->values[0] = 0;
782 rdev->mode_info.load_detect_property->values[1] = 1;
783
784 drm_mode_create_scaling_mode_property(rdev->ddev);
785
786 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
787 rdev->mode_info.tv_std_property =
788 drm_property_create(rdev->ddev,
789 DRM_MODE_PROP_ENUM,
790 "tv standard", sz);
791 for (i = 0; i < sz; i++) {
792 drm_property_add_enum(rdev->mode_info.tv_std_property,
793 i,
794 radeon_tv_std_enum_list[i].type,
795 radeon_tv_std_enum_list[i].name);
796 }
797
798 return 0;
799 }
800
801 int radeon_modeset_init(struct radeon_device *rdev)
802 {
803 int num_crtc = 2, i;
804 int ret;
805
806 drm_mode_config_init(rdev->ddev);
807 rdev->mode_info.mode_config_initialized = true;
808
809 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
810
811 if (ASIC_IS_AVIVO(rdev)) {
812 rdev->ddev->mode_config.max_width = 8192;
813 rdev->ddev->mode_config.max_height = 8192;
814 } else {
815 rdev->ddev->mode_config.max_width = 4096;
816 rdev->ddev->mode_config.max_height = 4096;
817 }
818
819 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
820
821 ret = radeon_modeset_create_props(rdev);
822 if (ret) {
823 return ret;
824 }
825
826 if (rdev->flags & RADEON_SINGLE_CRTC)
827 num_crtc = 1;
828
829 /* allocate crtcs */
830 for (i = 0; i < num_crtc; i++) {
831 radeon_crtc_init(rdev->ddev, i);
832 }
833
834 /* okay we should have all the bios connectors */
835 ret = radeon_setup_enc_conn(rdev->ddev);
836 if (!ret) {
837 return ret;
838 }
839 /* initialize hpd */
840 radeon_hpd_init(rdev);
841 drm_helper_initial_config(rdev->ddev);
842 return 0;
843 }
844
845 void radeon_modeset_fini(struct radeon_device *rdev)
846 {
847 if (rdev->mode_info.mode_config_initialized) {
848 radeon_hpd_fini(rdev);
849 drm_mode_config_cleanup(rdev->ddev);
850 rdev->mode_info.mode_config_initialized = false;
851 }
852 }
853
854 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
855 struct drm_display_mode *mode,
856 struct drm_display_mode *adjusted_mode)
857 {
858 struct drm_device *dev = crtc->dev;
859 struct drm_encoder *encoder;
860 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
861 struct radeon_encoder *radeon_encoder;
862 bool first = true;
863
864 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
865 radeon_encoder = to_radeon_encoder(encoder);
866 if (encoder->crtc != crtc)
867 continue;
868 if (first) {
869 /* set scaling */
870 if (radeon_encoder->rmx_type == RMX_OFF)
871 radeon_crtc->rmx_type = RMX_OFF;
872 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
873 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
874 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
875 else
876 radeon_crtc->rmx_type = RMX_OFF;
877 /* copy native mode */
878 memcpy(&radeon_crtc->native_mode,
879 &radeon_encoder->native_mode,
880 sizeof(struct drm_display_mode));
881 first = false;
882 } else {
883 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
884 /* WARNING: Right now this can't happen but
885 * in the future we need to check that scaling
886 * are consistent accross different encoder
887 * (ie all encoder can work with the same
888 * scaling).
889 */
890 DRM_ERROR("Scaling not consistent accross encoder.\n");
891 return false;
892 }
893 }
894 }
895 if (radeon_crtc->rmx_type != RMX_OFF) {
896 fixed20_12 a, b;
897 a.full = rfixed_const(crtc->mode.vdisplay);
898 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
899 radeon_crtc->vsc.full = rfixed_div(a, b);
900 a.full = rfixed_const(crtc->mode.hdisplay);
901 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
902 radeon_crtc->hsc.full = rfixed_div(a, b);
903 } else {
904 radeon_crtc->vsc.full = rfixed_const(1);
905 radeon_crtc->hsc.full = rfixed_const(1);
906 }
907 return true;
908 }
Ubuntu Artful kernel mirror