2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector
*connector
);
38 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 struct drm_device
*dev
= crtc
->dev
;
42 struct radeon_device
*rdev
= dev
->dev_private
;
45 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
46 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
57 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
61 for (i
= 0; i
< 256; i
++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR
,
63 (radeon_crtc
->lut_r
[i
] << 20) |
64 (radeon_crtc
->lut_g
[i
] << 10) |
65 (radeon_crtc
->lut_b
[i
] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
);
71 static void dce4_crtc_load_lut(struct drm_crtc
*crtc
)
73 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
74 struct drm_device
*dev
= crtc
->dev
;
75 struct radeon_device
*rdev
= dev
->dev_private
;
78 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
79 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
93 for (i
= 0; i
< 256; i
++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
95 (radeon_crtc
->lut_r
[i
] << 20) |
96 (radeon_crtc
->lut_g
[i
] << 10) |
97 (radeon_crtc
->lut_b
[i
] << 0));
101 static void dce5_crtc_load_lut(struct drm_crtc
*crtc
)
103 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
104 struct drm_device
*dev
= crtc
->dev
;
105 struct radeon_device
*rdev
= dev
->dev_private
;
108 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
110 WREG32(NI_INPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
111 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS
) |
112 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS
)));
113 WREG32(NI_PRESCALE_GRPH_CONTROL
+ radeon_crtc
->crtc_offset
,
114 NI_GRPH_PRESCALE_BYPASS
);
115 WREG32(NI_PRESCALE_OVL_CONTROL
+ radeon_crtc
->crtc_offset
,
116 NI_OVL_PRESCALE_BYPASS
);
117 WREG32(NI_INPUT_GAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
118 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
) |
119 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
)));
121 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
132 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
134 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
135 for (i
= 0; i
< 256; i
++) {
136 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
137 (radeon_crtc
->lut_r
[i
] << 20) |
138 (radeon_crtc
->lut_g
[i
] << 10) |
139 (radeon_crtc
->lut_b
[i
] << 0));
142 WREG32(NI_DEGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
143 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
144 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
145 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
146 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
)));
147 WREG32(NI_GAMUT_REMAP_CONTROL
+ radeon_crtc
->crtc_offset
,
148 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
) |
149 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
)));
150 WREG32(NI_REGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
151 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS
) |
152 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS
)));
153 WREG32(NI_OUTPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
154 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS
) |
155 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS
)));
156 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
157 WREG32(0x6940 + radeon_crtc
->crtc_offset
, 0);
161 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
163 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
164 struct drm_device
*dev
= crtc
->dev
;
165 struct radeon_device
*rdev
= dev
->dev_private
;
169 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
170 if (radeon_crtc
->crtc_id
== 0)
171 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
173 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
174 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
176 WREG8(RADEON_PALETTE_INDEX
, 0);
177 for (i
= 0; i
< 256; i
++) {
178 WREG32(RADEON_PALETTE_30_DATA
,
179 (radeon_crtc
->lut_r
[i
] << 20) |
180 (radeon_crtc
->lut_g
[i
] << 10) |
181 (radeon_crtc
->lut_b
[i
] << 0));
185 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
187 struct drm_device
*dev
= crtc
->dev
;
188 struct radeon_device
*rdev
= dev
->dev_private
;
193 if (ASIC_IS_DCE5(rdev
))
194 dce5_crtc_load_lut(crtc
);
195 else if (ASIC_IS_DCE4(rdev
))
196 dce4_crtc_load_lut(crtc
);
197 else if (ASIC_IS_AVIVO(rdev
))
198 avivo_crtc_load_lut(crtc
);
200 legacy_crtc_load_lut(crtc
);
203 /** Sets the color ramps on behalf of fbcon */
204 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
207 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
209 radeon_crtc
->lut_r
[regno
] = red
>> 6;
210 radeon_crtc
->lut_g
[regno
] = green
>> 6;
211 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
214 /** Gets the color ramps on behalf of fbcon */
215 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
216 u16
*blue
, int regno
)
218 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
220 *red
= radeon_crtc
->lut_r
[regno
] << 6;
221 *green
= radeon_crtc
->lut_g
[regno
] << 6;
222 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
225 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
226 u16
*blue
, uint32_t start
, uint32_t size
)
228 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
229 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
231 /* userspace palettes are always correct as is */
232 for (i
= start
; i
< end
; i
++) {
233 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
234 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
235 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
237 radeon_crtc_load_lut(crtc
);
240 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
242 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
244 drm_crtc_cleanup(crtc
);
249 * Handle unpin events outside the interrupt handler proper.
251 static void radeon_unpin_work_func(struct work_struct
*__work
)
253 struct radeon_unpin_work
*work
=
254 container_of(__work
, struct radeon_unpin_work
, work
);
257 /* unpin of the old buffer */
258 r
= radeon_bo_reserve(work
->old_rbo
, false);
259 if (likely(r
== 0)) {
260 r
= radeon_bo_unpin(work
->old_rbo
);
261 if (unlikely(r
!= 0)) {
262 DRM_ERROR("failed to unpin buffer after flip\n");
264 radeon_bo_unreserve(work
->old_rbo
);
266 DRM_ERROR("failed to reserve buffer after flip\n");
270 void radeon_crtc_handle_flip(struct radeon_device
*rdev
, int crtc_id
)
272 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
273 struct radeon_unpin_work
*work
;
274 struct drm_pending_vblank_event
*e
;
280 spin_lock_irqsave(&rdev
->ddev
->event_lock
, flags
);
281 work
= radeon_crtc
->unpin_work
;
283 !radeon_fence_signaled(work
->fence
)) {
284 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc
->deferred_flip_completion
) {
289 /* do the flip (mmio) */
290 update_pending
= radeon_page_flip(rdev
, crtc_id
, work
->new_crtc_base
);
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
297 radeon_crtc
->deferred_flip_completion
= 0;
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
303 if (update_pending
&&
304 (DRM_SCANOUTPOS_VALID
& radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc_id
,
307 (vpos
< (99 * rdev
->mode_info
.crtcs
[crtc_id
]->base
.hwmode
.crtc_vdisplay
)/100)) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. It will complete it
310 * in next vblank interval, so complete the flip at
313 radeon_crtc
->deferred_flip_completion
= 1;
314 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
318 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
319 radeon_crtc
->unpin_work
= NULL
;
321 /* wakeup userspace */
324 e
->event
.sequence
= drm_vblank_count_and_time(rdev
->ddev
, crtc_id
, &now
);
325 e
->event
.tv_sec
= now
.tv_sec
;
326 e
->event
.tv_usec
= now
.tv_usec
;
327 list_add_tail(&e
->base
.link
, &e
->base
.file_priv
->event_list
);
328 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
330 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
332 drm_vblank_put(rdev
->ddev
, radeon_crtc
->crtc_id
);
333 radeon_fence_unref(&work
->fence
);
334 radeon_post_page_flip(work
->rdev
, work
->crtc_id
);
335 schedule_work(&work
->work
);
338 static int radeon_crtc_page_flip(struct drm_crtc
*crtc
,
339 struct drm_framebuffer
*fb
,
340 struct drm_pending_vblank_event
*event
)
342 struct drm_device
*dev
= crtc
->dev
;
343 struct radeon_device
*rdev
= dev
->dev_private
;
344 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
345 struct radeon_framebuffer
*old_radeon_fb
;
346 struct radeon_framebuffer
*new_radeon_fb
;
347 struct drm_gem_object
*obj
;
348 struct radeon_bo
*rbo
;
349 struct radeon_fence
*fence
;
350 struct radeon_unpin_work
*work
;
352 u32 tiling_flags
, pitch_pixels
;
356 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
360 r
= radeon_fence_create(rdev
, &fence
);
361 if (unlikely(r
!= 0)) {
363 DRM_ERROR("flip queue: failed to create fence.\n");
368 work
->crtc_id
= radeon_crtc
->crtc_id
;
369 work
->fence
= radeon_fence_ref(fence
);
370 old_radeon_fb
= to_radeon_framebuffer(crtc
->fb
);
371 new_radeon_fb
= to_radeon_framebuffer(fb
);
372 /* schedule unpin of the old buffer */
373 obj
= old_radeon_fb
->obj
;
374 rbo
= obj
->driver_private
;
376 INIT_WORK(&work
->work
, radeon_unpin_work_func
);
378 /* We borrow the event spin lock for protecting unpin_work */
379 spin_lock_irqsave(&dev
->event_lock
, flags
);
380 if (radeon_crtc
->unpin_work
) {
381 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
383 radeon_fence_unref(&fence
);
385 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
388 radeon_crtc
->unpin_work
= work
;
389 radeon_crtc
->deferred_flip_completion
= 0;
390 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
392 /* pin the new buffer */
393 obj
= new_radeon_fb
->obj
;
394 rbo
= obj
->driver_private
;
396 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
399 r
= radeon_bo_reserve(rbo
, false);
400 if (unlikely(r
!= 0)) {
401 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
404 r
= radeon_bo_pin(rbo
, RADEON_GEM_DOMAIN_VRAM
, &base
);
405 if (unlikely(r
!= 0)) {
406 radeon_bo_unreserve(rbo
);
408 DRM_ERROR("failed to pin new rbo buffer before flip\n");
411 radeon_bo_get_tiling_flags(rbo
, &tiling_flags
, NULL
);
412 radeon_bo_unreserve(rbo
);
414 if (!ASIC_IS_AVIVO(rdev
)) {
415 /* crtc offset is from display base addr not FB location */
416 base
-= radeon_crtc
->legacy_display_base_addr
;
417 pitch_pixels
= fb
->pitch
/ (fb
->bits_per_pixel
/ 8);
419 if (tiling_flags
& RADEON_TILING_MACRO
) {
420 if (ASIC_IS_R300(rdev
)) {
423 int byteshift
= fb
->bits_per_pixel
>> 4;
424 int tile_addr
= (((crtc
->y
>> 3) * pitch_pixels
+ crtc
->x
) >> (8 - byteshift
)) << 11;
425 base
+= tile_addr
+ ((crtc
->x
<< byteshift
) % 256) + ((crtc
->y
% 8) << 8);
428 int offset
= crtc
->y
* pitch_pixels
+ crtc
->x
;
429 switch (fb
->bits_per_pixel
) {
450 spin_lock_irqsave(&dev
->event_lock
, flags
);
451 work
->new_crtc_base
= base
;
452 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
457 r
= drm_vblank_get(dev
, radeon_crtc
->crtc_id
);
459 DRM_ERROR("failed to get vblank before flip\n");
463 /* 32 ought to cover us */
464 r
= radeon_ring_lock(rdev
, 32);
466 DRM_ERROR("failed to lock the ring before flip\n");
471 radeon_fence_emit(rdev
, fence
);
472 /* set the proper interrupt */
473 radeon_pre_page_flip(rdev
, radeon_crtc
->crtc_id
);
475 radeon_ring_unlock_commit(rdev
);
480 drm_vblank_put(dev
, radeon_crtc
->crtc_id
);
483 r
= radeon_bo_reserve(rbo
, false);
484 if (unlikely(r
!= 0)) {
485 DRM_ERROR("failed to reserve new rbo in error path\n");
488 r
= radeon_bo_unpin(rbo
);
489 if (unlikely(r
!= 0)) {
490 radeon_bo_unreserve(rbo
);
492 DRM_ERROR("failed to unpin new rbo in error path\n");
495 radeon_bo_unreserve(rbo
);
498 spin_lock_irqsave(&dev
->event_lock
, flags
);
499 radeon_crtc
->unpin_work
= NULL
;
500 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
501 radeon_fence_unref(&fence
);
507 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
508 .cursor_set
= radeon_crtc_cursor_set
,
509 .cursor_move
= radeon_crtc_cursor_move
,
510 .gamma_set
= radeon_crtc_gamma_set
,
511 .set_config
= drm_crtc_helper_set_config
,
512 .destroy
= radeon_crtc_destroy
,
513 .page_flip
= radeon_crtc_page_flip
,
516 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
518 struct radeon_device
*rdev
= dev
->dev_private
;
519 struct radeon_crtc
*radeon_crtc
;
522 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
523 if (radeon_crtc
== NULL
)
526 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
528 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
529 radeon_crtc
->crtc_id
= index
;
530 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
533 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
534 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
535 radeon_crtc
->mode_set
.num_connectors
= 0;
538 for (i
= 0; i
< 256; i
++) {
539 radeon_crtc
->lut_r
[i
] = i
<< 2;
540 radeon_crtc
->lut_g
[i
] = i
<< 2;
541 radeon_crtc
->lut_b
[i
] = i
<< 2;
544 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
545 radeon_atombios_init_crtc(dev
, radeon_crtc
);
547 radeon_legacy_init_crtc(dev
, radeon_crtc
);
550 static const char *encoder_names
[36] = {
570 "INTERNAL_KLDSCP_TMDS1",
571 "INTERNAL_KLDSCP_DVO1",
572 "INTERNAL_KLDSCP_DAC1",
573 "INTERNAL_KLDSCP_DAC2",
582 "INTERNAL_KLDSCP_LVTMA",
589 static const char *connector_names
[15] = {
607 static const char *hpd_names
[6] = {
616 static void radeon_print_display_setup(struct drm_device
*dev
)
618 struct drm_connector
*connector
;
619 struct radeon_connector
*radeon_connector
;
620 struct drm_encoder
*encoder
;
621 struct radeon_encoder
*radeon_encoder
;
625 DRM_INFO("Radeon Display Connectors\n");
626 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
627 radeon_connector
= to_radeon_connector(connector
);
628 DRM_INFO("Connector %d:\n", i
);
629 DRM_INFO(" %s\n", connector_names
[connector
->connector_type
]);
630 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
631 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
632 if (radeon_connector
->ddc_bus
) {
633 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
634 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
635 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
636 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
637 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
638 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
639 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
640 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
641 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
642 if (radeon_connector
->router
.ddc_valid
)
643 DRM_INFO(" DDC Router 0x%x/0x%x\n",
644 radeon_connector
->router
.ddc_mux_control_pin
,
645 radeon_connector
->router
.ddc_mux_state
);
646 if (radeon_connector
->router
.cd_valid
)
647 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
648 radeon_connector
->router
.cd_mux_control_pin
,
649 radeon_connector
->router
.cd_mux_state
);
651 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
652 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
653 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
654 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
655 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
656 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
657 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
659 DRM_INFO(" Encoders:\n");
660 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
661 radeon_encoder
= to_radeon_encoder(encoder
);
662 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
664 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
665 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
666 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
667 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
668 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
669 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
670 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
671 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
672 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
673 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
674 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
675 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
676 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
677 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
678 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
679 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
680 if (devices
& ATOM_DEVICE_DFP6_SUPPORT
)
681 DRM_INFO(" DFP6: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
682 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
683 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
684 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
685 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
692 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
694 struct radeon_device
*rdev
= dev
->dev_private
;
695 struct drm_connector
*drm_connector
;
699 if (rdev
->is_atom_bios
) {
700 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
702 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
704 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
706 ret
= radeon_get_legacy_connector_info_from_table(dev
);
709 if (!ASIC_IS_AVIVO(rdev
))
710 ret
= radeon_get_legacy_connector_info_from_table(dev
);
713 radeon_setup_encoder_clones(dev
);
714 radeon_print_display_setup(dev
);
715 list_for_each_entry(drm_connector
, &dev
->mode_config
.connector_list
, head
)
716 radeon_ddc_dump(drm_connector
);
722 int radeon_ddc_get_modes(struct radeon_connector
*radeon_connector
)
724 struct drm_device
*dev
= radeon_connector
->base
.dev
;
725 struct radeon_device
*rdev
= dev
->dev_private
;
728 /* on hw with routers, select right port */
729 if (radeon_connector
->router
.ddc_valid
)
730 radeon_router_select_ddc_port(radeon_connector
);
732 if ((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_DisplayPort
) ||
733 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
734 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
735 if ((dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
||
736 dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
) && dig
->dp_i2c_bus
)
737 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &dig
->dp_i2c_bus
->adapter
);
739 if (!radeon_connector
->ddc_bus
)
741 if (!radeon_connector
->edid
) {
742 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
, &radeon_connector
->ddc_bus
->adapter
);
745 if (!radeon_connector
->edid
) {
746 if (rdev
->is_atom_bios
) {
747 /* some laptops provide a hardcoded edid in rom for LCDs */
748 if (((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_LVDS
) ||
749 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)))
750 radeon_connector
->edid
= radeon_bios_get_hardcoded_edid(rdev
);
752 /* some servers provide a hardcoded edid in rom for KVMs */
753 radeon_connector
->edid
= radeon_bios_get_hardcoded_edid(rdev
);
755 if (radeon_connector
->edid
) {
756 drm_mode_connector_update_edid_property(&radeon_connector
->base
, radeon_connector
->edid
);
757 ret
= drm_add_edid_modes(&radeon_connector
->base
, radeon_connector
->edid
);
760 drm_mode_connector_update_edid_property(&radeon_connector
->base
, NULL
);
764 static int radeon_ddc_dump(struct drm_connector
*connector
)
767 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
770 /* on hw with routers, select right port */
771 if (radeon_connector
->router
.ddc_valid
)
772 radeon_router_select_ddc_port(radeon_connector
);
774 if (!radeon_connector
->ddc_bus
)
776 edid
= drm_get_edid(connector
, &radeon_connector
->ddc_bus
->adapter
);
784 static void avivo_get_fb_div(struct radeon_pll
*pll
,
791 u32 tmp
= post_div
* ref_div
;
794 *fb_div
= tmp
/ pll
->reference_freq
;
795 *frac_fb_div
= tmp
% pll
->reference_freq
;
798 static u32
avivo_get_post_div(struct radeon_pll
*pll
,
801 u32 vco
, post_div
, tmp
;
803 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
804 return pll
->post_div
;
806 if (pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
) {
807 if (pll
->flags
& RADEON_PLL_IS_LCD
)
808 vco
= pll
->lcd_pll_out_min
;
810 vco
= pll
->pll_out_min
;
812 if (pll
->flags
& RADEON_PLL_IS_LCD
)
813 vco
= pll
->lcd_pll_out_max
;
815 vco
= pll
->pll_out_max
;
818 post_div
= vco
/ target_clock
;
819 tmp
= vco
% target_clock
;
821 if (pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
) {
832 #define MAX_TOLERANCE 10
834 void radeon_compute_pll_avivo(struct radeon_pll
*pll
,
842 u32 target_clock
= freq
/ 10;
843 u32 post_div
= avivo_get_post_div(pll
, target_clock
);
844 u32 ref_div
= pll
->min_ref_div
;
845 u32 fb_div
= 0, frac_fb_div
= 0, tmp
;
847 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
848 ref_div
= pll
->reference_div
;
850 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
851 avivo_get_fb_div(pll
, target_clock
, post_div
, ref_div
, &fb_div
, &frac_fb_div
);
852 frac_fb_div
= (100 * frac_fb_div
) / pll
->reference_freq
;
853 if (frac_fb_div
>= 5) {
855 frac_fb_div
= frac_fb_div
/ 10;
858 if (frac_fb_div
>= 10) {
863 while (ref_div
<= pll
->max_ref_div
) {
864 avivo_get_fb_div(pll
, target_clock
, post_div
, ref_div
,
865 &fb_div
, &frac_fb_div
);
866 if (frac_fb_div
>= (pll
->reference_freq
/ 2))
869 tmp
= (pll
->reference_freq
* fb_div
) / (post_div
* ref_div
);
870 tmp
= (tmp
* 10000) / target_clock
;
872 if (tmp
> (10000 + MAX_TOLERANCE
))
874 else if (tmp
>= (10000 - MAX_TOLERANCE
))
881 *dot_clock_p
= ((pll
->reference_freq
* fb_div
* 10) + (pll
->reference_freq
* frac_fb_div
)) /
882 (ref_div
* post_div
* 10);
884 *frac_fb_div_p
= frac_fb_div
;
885 *ref_div_p
= ref_div
;
886 *post_div_p
= post_div
;
887 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
888 *dot_clock_p
, fb_div
, frac_fb_div
, ref_div
, post_div
);
892 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
902 void radeon_compute_pll_legacy(struct radeon_pll
*pll
,
904 uint32_t *dot_clock_p
,
906 uint32_t *frac_fb_div_p
,
908 uint32_t *post_div_p
)
910 uint32_t min_ref_div
= pll
->min_ref_div
;
911 uint32_t max_ref_div
= pll
->max_ref_div
;
912 uint32_t min_post_div
= pll
->min_post_div
;
913 uint32_t max_post_div
= pll
->max_post_div
;
914 uint32_t min_fractional_feed_div
= 0;
915 uint32_t max_fractional_feed_div
= 0;
916 uint32_t best_vco
= pll
->best_vco
;
917 uint32_t best_post_div
= 1;
918 uint32_t best_ref_div
= 1;
919 uint32_t best_feedback_div
= 1;
920 uint32_t best_frac_feedback_div
= 0;
921 uint32_t best_freq
= -1;
922 uint32_t best_error
= 0xffffffff;
923 uint32_t best_vco_diff
= 1;
925 u32 pll_out_min
, pll_out_max
;
927 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
930 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
931 pll_out_min
= pll
->lcd_pll_out_min
;
932 pll_out_max
= pll
->lcd_pll_out_max
;
934 pll_out_min
= pll
->pll_out_min
;
935 pll_out_max
= pll
->pll_out_max
;
938 if (pll_out_min
> 64800)
941 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
942 min_ref_div
= max_ref_div
= pll
->reference_div
;
944 while (min_ref_div
< max_ref_div
-1) {
945 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
946 uint32_t pll_in
= pll
->reference_freq
/ mid
;
947 if (pll_in
< pll
->pll_in_min
)
949 else if (pll_in
> pll
->pll_in_max
)
956 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
957 min_post_div
= max_post_div
= pll
->post_div
;
959 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
960 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
961 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
964 for (post_div
= min_post_div
; post_div
<= max_post_div
; ++post_div
) {
967 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
970 /* legacy radeons only have a few post_divs */
971 if (pll
->flags
& RADEON_PLL_LEGACY
) {
972 if ((post_div
== 5) ||
983 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
984 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
985 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
986 uint32_t min_feed_div
= pll
->min_feedback_div
;
987 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
989 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
992 while (min_feed_div
< max_feed_div
) {
994 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
995 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
996 uint32_t frac_feedback_div
;
999 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
1001 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
1002 vco
= radeon_div(tmp
, ref_div
);
1004 if (vco
< pll_out_min
) {
1005 min_feed_div
= feedback_div
+ 1;
1007 } else if (vco
> pll_out_max
) {
1008 max_feed_div
= feedback_div
;
1012 while (min_frac_feed_div
< max_frac_feed_div
) {
1013 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
1014 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
1015 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
1016 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
1018 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
1019 if (freq
< current_freq
)
1022 error
= freq
- current_freq
;
1024 error
= abs(current_freq
- freq
);
1025 vco_diff
= abs(vco
- best_vco
);
1027 if ((best_vco
== 0 && error
< best_error
) ||
1029 ((best_error
> 100 && error
< best_error
- 100) ||
1030 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
1031 best_post_div
= post_div
;
1032 best_ref_div
= ref_div
;
1033 best_feedback_div
= feedback_div
;
1034 best_frac_feedback_div
= frac_feedback_div
;
1035 best_freq
= current_freq
;
1037 best_vco_diff
= vco_diff
;
1038 } else if (current_freq
== freq
) {
1039 if (best_freq
== -1) {
1040 best_post_div
= post_div
;
1041 best_ref_div
= ref_div
;
1042 best_feedback_div
= feedback_div
;
1043 best_frac_feedback_div
= frac_feedback_div
;
1044 best_freq
= current_freq
;
1046 best_vco_diff
= vco_diff
;
1047 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
1048 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
1049 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
1050 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
1051 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
1052 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
1053 best_post_div
= post_div
;
1054 best_ref_div
= ref_div
;
1055 best_feedback_div
= feedback_div
;
1056 best_frac_feedback_div
= frac_feedback_div
;
1057 best_freq
= current_freq
;
1059 best_vco_diff
= vco_diff
;
1062 if (current_freq
< freq
)
1063 min_frac_feed_div
= frac_feedback_div
+ 1;
1065 max_frac_feed_div
= frac_feedback_div
;
1067 if (current_freq
< freq
)
1068 min_feed_div
= feedback_div
+ 1;
1070 max_feed_div
= feedback_div
;
1075 *dot_clock_p
= best_freq
/ 10000;
1076 *fb_div_p
= best_feedback_div
;
1077 *frac_fb_div_p
= best_frac_feedback_div
;
1078 *ref_div_p
= best_ref_div
;
1079 *post_div_p
= best_post_div
;
1080 DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1081 freq
, best_freq
/ 1000, best_feedback_div
, best_frac_feedback_div
,
1082 best_ref_div
, best_post_div
);
1086 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
1088 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1090 if (radeon_fb
->obj
) {
1091 drm_gem_object_unreference_unlocked(radeon_fb
->obj
);
1093 drm_framebuffer_cleanup(fb
);
1097 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
1098 struct drm_file
*file_priv
,
1099 unsigned int *handle
)
1101 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1103 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
1106 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
1107 .destroy
= radeon_user_framebuffer_destroy
,
1108 .create_handle
= radeon_user_framebuffer_create_handle
,
1112 radeon_framebuffer_init(struct drm_device
*dev
,
1113 struct radeon_framebuffer
*rfb
,
1114 struct drm_mode_fb_cmd
*mode_cmd
,
1115 struct drm_gem_object
*obj
)
1118 drm_framebuffer_init(dev
, &rfb
->base
, &radeon_fb_funcs
);
1119 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
1122 static struct drm_framebuffer
*
1123 radeon_user_framebuffer_create(struct drm_device
*dev
,
1124 struct drm_file
*file_priv
,
1125 struct drm_mode_fb_cmd
*mode_cmd
)
1127 struct drm_gem_object
*obj
;
1128 struct radeon_framebuffer
*radeon_fb
;
1130 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handle
);
1132 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
1133 "can't create framebuffer\n", mode_cmd
->handle
);
1134 return ERR_PTR(-ENOENT
);
1137 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
1138 if (radeon_fb
== NULL
)
1139 return ERR_PTR(-ENOMEM
);
1141 radeon_framebuffer_init(dev
, radeon_fb
, mode_cmd
, obj
);
1143 return &radeon_fb
->base
;
1146 static void radeon_output_poll_changed(struct drm_device
*dev
)
1148 struct radeon_device
*rdev
= dev
->dev_private
;
1149 radeon_fb_output_poll_changed(rdev
);
1152 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
1153 .fb_create
= radeon_user_framebuffer_create
,
1154 .output_poll_changed
= radeon_output_poll_changed
1157 struct drm_prop_enum_list
{
1162 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
1167 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
1168 { { TV_STD_NTSC
, "ntsc" },
1169 { TV_STD_PAL
, "pal" },
1170 { TV_STD_PAL_M
, "pal-m" },
1171 { TV_STD_PAL_60
, "pal-60" },
1172 { TV_STD_NTSC_J
, "ntsc-j" },
1173 { TV_STD_SCART_PAL
, "scart-pal" },
1174 { TV_STD_PAL_CN
, "pal-cn" },
1175 { TV_STD_SECAM
, "secam" },
1178 static struct drm_prop_enum_list radeon_underscan_enum_list
[] =
1179 { { UNDERSCAN_OFF
, "off" },
1180 { UNDERSCAN_ON
, "on" },
1181 { UNDERSCAN_AUTO
, "auto" },
1184 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
1188 if (rdev
->is_atom_bios
) {
1189 rdev
->mode_info
.coherent_mode_property
=
1190 drm_property_create(rdev
->ddev
,
1191 DRM_MODE_PROP_RANGE
,
1193 if (!rdev
->mode_info
.coherent_mode_property
)
1196 rdev
->mode_info
.coherent_mode_property
->values
[0] = 0;
1197 rdev
->mode_info
.coherent_mode_property
->values
[1] = 1;
1200 if (!ASIC_IS_AVIVO(rdev
)) {
1201 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
1202 rdev
->mode_info
.tmds_pll_property
=
1203 drm_property_create(rdev
->ddev
,
1206 for (i
= 0; i
< sz
; i
++) {
1207 drm_property_add_enum(rdev
->mode_info
.tmds_pll_property
,
1209 radeon_tmds_pll_enum_list
[i
].type
,
1210 radeon_tmds_pll_enum_list
[i
].name
);
1214 rdev
->mode_info
.load_detect_property
=
1215 drm_property_create(rdev
->ddev
,
1216 DRM_MODE_PROP_RANGE
,
1217 "load detection", 2);
1218 if (!rdev
->mode_info
.load_detect_property
)
1220 rdev
->mode_info
.load_detect_property
->values
[0] = 0;
1221 rdev
->mode_info
.load_detect_property
->values
[1] = 1;
1223 drm_mode_create_scaling_mode_property(rdev
->ddev
);
1225 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
1226 rdev
->mode_info
.tv_std_property
=
1227 drm_property_create(rdev
->ddev
,
1230 for (i
= 0; i
< sz
; i
++) {
1231 drm_property_add_enum(rdev
->mode_info
.tv_std_property
,
1233 radeon_tv_std_enum_list
[i
].type
,
1234 radeon_tv_std_enum_list
[i
].name
);
1237 sz
= ARRAY_SIZE(radeon_underscan_enum_list
);
1238 rdev
->mode_info
.underscan_property
=
1239 drm_property_create(rdev
->ddev
,
1242 for (i
= 0; i
< sz
; i
++) {
1243 drm_property_add_enum(rdev
->mode_info
.underscan_property
,
1245 radeon_underscan_enum_list
[i
].type
,
1246 radeon_underscan_enum_list
[i
].name
);
1249 rdev
->mode_info
.underscan_hborder_property
=
1250 drm_property_create(rdev
->ddev
,
1251 DRM_MODE_PROP_RANGE
,
1252 "underscan hborder", 2);
1253 if (!rdev
->mode_info
.underscan_hborder_property
)
1255 rdev
->mode_info
.underscan_hborder_property
->values
[0] = 0;
1256 rdev
->mode_info
.underscan_hborder_property
->values
[1] = 128;
1258 rdev
->mode_info
.underscan_vborder_property
=
1259 drm_property_create(rdev
->ddev
,
1260 DRM_MODE_PROP_RANGE
,
1261 "underscan vborder", 2);
1262 if (!rdev
->mode_info
.underscan_vborder_property
)
1264 rdev
->mode_info
.underscan_vborder_property
->values
[0] = 0;
1265 rdev
->mode_info
.underscan_vborder_property
->values
[1] = 128;
1270 void radeon_update_display_priority(struct radeon_device
*rdev
)
1272 /* adjustment options for the display watermarks */
1273 if ((radeon_disp_priority
== 0) || (radeon_disp_priority
> 2)) {
1274 /* set display priority to high for r3xx, rv515 chips
1275 * this avoids flickering due to underflow to the
1276 * display controllers during heavy acceleration.
1277 * Don't force high on rs4xx igp chips as it seems to
1278 * affect the sound card. See kernel bug 15982.
1280 if ((ASIC_IS_R300(rdev
) || (rdev
->family
== CHIP_RV515
)) &&
1281 !(rdev
->flags
& RADEON_IS_IGP
))
1282 rdev
->disp_priority
= 2;
1284 rdev
->disp_priority
= 0;
1286 rdev
->disp_priority
= radeon_disp_priority
;
1290 int radeon_modeset_init(struct radeon_device
*rdev
)
1295 drm_mode_config_init(rdev
->ddev
);
1296 rdev
->mode_info
.mode_config_initialized
= true;
1298 rdev
->ddev
->mode_config
.funcs
= (void *)&radeon_mode_funcs
;
1300 if (ASIC_IS_DCE5(rdev
)) {
1301 rdev
->ddev
->mode_config
.max_width
= 16384;
1302 rdev
->ddev
->mode_config
.max_height
= 16384;
1303 } else if (ASIC_IS_AVIVO(rdev
)) {
1304 rdev
->ddev
->mode_config
.max_width
= 8192;
1305 rdev
->ddev
->mode_config
.max_height
= 8192;
1307 rdev
->ddev
->mode_config
.max_width
= 4096;
1308 rdev
->ddev
->mode_config
.max_height
= 4096;
1311 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
1313 ret
= radeon_modeset_create_props(rdev
);
1318 /* init i2c buses */
1319 radeon_i2c_init(rdev
);
1321 /* check combios for a valid hardcoded EDID - Sun servers */
1322 if (!rdev
->is_atom_bios
) {
1323 /* check for hardcoded EDID in BIOS */
1324 radeon_combios_check_hardcoded_edid(rdev
);
1327 /* allocate crtcs */
1328 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1329 radeon_crtc_init(rdev
->ddev
, i
);
1332 /* okay we should have all the bios connectors */
1333 ret
= radeon_setup_enc_conn(rdev
->ddev
);
1337 /* initialize hpd */
1338 radeon_hpd_init(rdev
);
1340 /* Initialize power management */
1341 radeon_pm_init(rdev
);
1343 radeon_fbdev_init(rdev
);
1344 drm_kms_helper_poll_init(rdev
->ddev
);
1349 void radeon_modeset_fini(struct radeon_device
*rdev
)
1351 radeon_fbdev_fini(rdev
);
1352 kfree(rdev
->mode_info
.bios_hardcoded_edid
);
1353 radeon_pm_fini(rdev
);
1355 if (rdev
->mode_info
.mode_config_initialized
) {
1356 drm_kms_helper_poll_fini(rdev
->ddev
);
1357 radeon_hpd_fini(rdev
);
1358 drm_mode_config_cleanup(rdev
->ddev
);
1359 rdev
->mode_info
.mode_config_initialized
= false;
1361 /* free i2c buses */
1362 radeon_i2c_fini(rdev
);
1365 static bool is_hdtv_mode(struct drm_display_mode
*mode
)
1367 /* try and guess if this is a tv or a monitor */
1368 if ((mode
->vdisplay
== 480 && mode
->hdisplay
== 720) || /* 480p */
1369 (mode
->vdisplay
== 576) || /* 576p */
1370 (mode
->vdisplay
== 720) || /* 720p */
1371 (mode
->vdisplay
== 1080)) /* 1080p */
1377 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
1378 struct drm_display_mode
*mode
,
1379 struct drm_display_mode
*adjusted_mode
)
1381 struct drm_device
*dev
= crtc
->dev
;
1382 struct radeon_device
*rdev
= dev
->dev_private
;
1383 struct drm_encoder
*encoder
;
1384 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1385 struct radeon_encoder
*radeon_encoder
;
1386 struct drm_connector
*connector
;
1387 struct radeon_connector
*radeon_connector
;
1389 u32 src_v
= 1, dst_v
= 1;
1390 u32 src_h
= 1, dst_h
= 1;
1392 radeon_crtc
->h_border
= 0;
1393 radeon_crtc
->v_border
= 0;
1395 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1396 if (encoder
->crtc
!= crtc
)
1398 radeon_encoder
= to_radeon_encoder(encoder
);
1399 connector
= radeon_get_connector_for_encoder(encoder
);
1400 radeon_connector
= to_radeon_connector(connector
);
1404 if (radeon_encoder
->rmx_type
== RMX_OFF
)
1405 radeon_crtc
->rmx_type
= RMX_OFF
;
1406 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
1407 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
1408 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
1410 radeon_crtc
->rmx_type
= RMX_OFF
;
1411 /* copy native mode */
1412 memcpy(&radeon_crtc
->native_mode
,
1413 &radeon_encoder
->native_mode
,
1414 sizeof(struct drm_display_mode
));
1415 src_v
= crtc
->mode
.vdisplay
;
1416 dst_v
= radeon_crtc
->native_mode
.vdisplay
;
1417 src_h
= crtc
->mode
.hdisplay
;
1418 dst_h
= radeon_crtc
->native_mode
.hdisplay
;
1420 /* fix up for overscan on hdmi */
1421 if (ASIC_IS_AVIVO(rdev
) &&
1422 (!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
)) &&
1423 ((radeon_encoder
->underscan_type
== UNDERSCAN_ON
) ||
1424 ((radeon_encoder
->underscan_type
== UNDERSCAN_AUTO
) &&
1425 drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
1426 is_hdtv_mode(mode
)))) {
1427 if (radeon_encoder
->underscan_hborder
!= 0)
1428 radeon_crtc
->h_border
= radeon_encoder
->underscan_hborder
;
1430 radeon_crtc
->h_border
= (mode
->hdisplay
>> 5) + 16;
1431 if (radeon_encoder
->underscan_vborder
!= 0)
1432 radeon_crtc
->v_border
= radeon_encoder
->underscan_vborder
;
1434 radeon_crtc
->v_border
= (mode
->vdisplay
>> 5) + 16;
1435 radeon_crtc
->rmx_type
= RMX_FULL
;
1436 src_v
= crtc
->mode
.vdisplay
;
1437 dst_v
= crtc
->mode
.vdisplay
- (radeon_crtc
->v_border
* 2);
1438 src_h
= crtc
->mode
.hdisplay
;
1439 dst_h
= crtc
->mode
.hdisplay
- (radeon_crtc
->h_border
* 2);
1443 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
1444 /* WARNING: Right now this can't happen but
1445 * in the future we need to check that scaling
1446 * are consistent across different encoder
1447 * (ie all encoder can work with the same
1450 DRM_ERROR("Scaling not consistent across encoder.\n");
1455 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
1457 a
.full
= dfixed_const(src_v
);
1458 b
.full
= dfixed_const(dst_v
);
1459 radeon_crtc
->vsc
.full
= dfixed_div(a
, b
);
1460 a
.full
= dfixed_const(src_h
);
1461 b
.full
= dfixed_const(dst_h
);
1462 radeon_crtc
->hsc
.full
= dfixed_div(a
, b
);
1464 radeon_crtc
->vsc
.full
= dfixed_const(1);
1465 radeon_crtc
->hsc
.full
= dfixed_const(1);
1471 * Retrieve current video scanout position of crtc on a given gpu.
1473 * \param dev Device to query.
1474 * \param crtc Crtc to query.
1475 * \param *vpos Location where vertical scanout position should be stored.
1476 * \param *hpos Location where horizontal scanout position should go.
1478 * Returns vpos as a positive number while in active scanout area.
1479 * Returns vpos as a negative number inside vblank, counting the number
1480 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1481 * until start of active scanout / end of vblank."
1483 * \return Flags, or'ed together as follows:
1485 * DRM_SCANOUTPOS_VALID = Query successfull.
1486 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1487 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1488 * this flag means that returned position may be offset by a constant but
1489 * unknown small number of scanlines wrt. real scanout position.
1492 int radeon_get_crtc_scanoutpos(struct drm_device
*dev
, int crtc
, int *vpos
, int *hpos
)
1494 u32 stat_crtc
= 0, vbl
= 0, position
= 0;
1495 int vbl_start
, vbl_end
, vtotal
, ret
= 0;
1498 struct radeon_device
*rdev
= dev
->dev_private
;
1500 if (ASIC_IS_DCE4(rdev
)) {
1502 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1503 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1504 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1505 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1506 ret
|= DRM_SCANOUTPOS_VALID
;
1509 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1510 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1511 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1512 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1513 ret
|= DRM_SCANOUTPOS_VALID
;
1516 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1517 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1518 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1519 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1520 ret
|= DRM_SCANOUTPOS_VALID
;
1523 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1524 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1525 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1526 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1527 ret
|= DRM_SCANOUTPOS_VALID
;
1530 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1531 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1532 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1533 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1534 ret
|= DRM_SCANOUTPOS_VALID
;
1537 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1538 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1539 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1540 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1541 ret
|= DRM_SCANOUTPOS_VALID
;
1543 } else if (ASIC_IS_AVIVO(rdev
)) {
1545 vbl
= RREG32(AVIVO_D1CRTC_V_BLANK_START_END
);
1546 position
= RREG32(AVIVO_D1CRTC_STATUS_POSITION
);
1547 ret
|= DRM_SCANOUTPOS_VALID
;
1550 vbl
= RREG32(AVIVO_D2CRTC_V_BLANK_START_END
);
1551 position
= RREG32(AVIVO_D2CRTC_STATUS_POSITION
);
1552 ret
|= DRM_SCANOUTPOS_VALID
;
1555 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1557 /* Assume vbl_end == 0, get vbl_start from
1560 vbl
= (RREG32(RADEON_CRTC_V_TOTAL_DISP
) &
1561 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1562 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1563 position
= (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1564 stat_crtc
= RREG32(RADEON_CRTC_STATUS
);
1565 if (!(stat_crtc
& 1))
1568 ret
|= DRM_SCANOUTPOS_VALID
;
1571 vbl
= (RREG32(RADEON_CRTC2_V_TOTAL_DISP
) &
1572 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1573 position
= (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1574 stat_crtc
= RREG32(RADEON_CRTC2_STATUS
);
1575 if (!(stat_crtc
& 1))
1578 ret
|= DRM_SCANOUTPOS_VALID
;
1582 /* Decode into vertical and horizontal scanout position. */
1583 *vpos
= position
& 0x1fff;
1584 *hpos
= (position
>> 16) & 0x1fff;
1586 /* Valid vblank area boundaries from gpu retrieved? */
1589 ret
|= DRM_SCANOUTPOS_ACCURATE
;
1590 vbl_start
= vbl
& 0x1fff;
1591 vbl_end
= (vbl
>> 16) & 0x1fff;
1594 /* No: Fake something reasonable which gives at least ok results. */
1595 vbl_start
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vdisplay
;
1599 /* Test scanout position against vblank region. */
1600 if ((*vpos
< vbl_start
) && (*vpos
>= vbl_end
))
1603 /* Check if inside vblank area and apply corrective offsets:
1604 * vpos will then be >=0 in video scanout area, but negative
1605 * within vblank area, counting down the number of lines until
1609 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1610 if (in_vbl
&& (*vpos
>= vbl_start
)) {
1611 vtotal
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vtotal
;
1612 *vpos
= *vpos
- vtotal
;
1615 /* Correct for shifted end of vbl at vbl_end. */
1616 *vpos
= *vpos
- vbl_end
;
1620 ret
|= DRM_SCANOUTPOS_INVBL
;