2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug
;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
36 struct drm_display_mode
*mode
);
38 static uint32_t radeon_encoder_clones(struct drm_encoder
*encoder
)
40 struct drm_device
*dev
= encoder
->dev
;
41 struct radeon_device
*rdev
= dev
->dev_private
;
42 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
43 struct drm_encoder
*clone_encoder
;
44 uint32_t index_mask
= 0;
47 /* DIG routing gets problematic */
48 if (rdev
->family
>= CHIP_R600
)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)
58 list_for_each_entry(clone_encoder
, &dev
->mode_config
.encoder_list
, head
) {
59 struct radeon_encoder
*radeon_clone
= to_radeon_encoder(clone_encoder
);
62 if (clone_encoder
== encoder
)
64 if (radeon_clone
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
66 if (radeon_clone
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)
69 index_mask
|= (1 << count
);
74 void radeon_setup_encoder_clones(struct drm_device
*dev
)
76 struct drm_encoder
*encoder
;
78 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
79 encoder
->possible_clones
= radeon_encoder_clones(encoder
);
84 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
, uint8_t dac
)
86 struct radeon_device
*rdev
= dev
->dev_private
;
89 switch (supported_device
) {
90 case ATOM_DEVICE_CRT1_SUPPORT
:
91 case ATOM_DEVICE_TV1_SUPPORT
:
92 case ATOM_DEVICE_TV2_SUPPORT
:
93 case ATOM_DEVICE_CRT2_SUPPORT
:
94 case ATOM_DEVICE_CV_SUPPORT
:
97 if ((rdev
->family
== CHIP_RS300
) ||
98 (rdev
->family
== CHIP_RS400
) ||
99 (rdev
->family
== CHIP_RS480
))
100 ret
= ENCODER_OBJECT_ID_INTERNAL_DAC2
;
101 else if (ASIC_IS_AVIVO(rdev
))
102 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
;
104 ret
= ENCODER_OBJECT_ID_INTERNAL_DAC1
;
107 if (ASIC_IS_AVIVO(rdev
))
108 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
113 ret
= ENCODER_OBJECT_ID_INTERNAL_DAC2
;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev
))
118 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
;
120 ret
= ENCODER_OBJECT_ID_INTERNAL_DVO1
;
124 case ATOM_DEVICE_LCD1_SUPPORT
:
125 if (ASIC_IS_AVIVO(rdev
))
126 ret
= ENCODER_OBJECT_ID_INTERNAL_LVTM1
;
128 ret
= ENCODER_OBJECT_ID_INTERNAL_LVDS
;
130 case ATOM_DEVICE_DFP1_SUPPORT
:
131 if ((rdev
->family
== CHIP_RS300
) ||
132 (rdev
->family
== CHIP_RS400
) ||
133 (rdev
->family
== CHIP_RS480
))
134 ret
= ENCODER_OBJECT_ID_INTERNAL_DVO1
;
135 else if (ASIC_IS_AVIVO(rdev
))
136 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
;
138 ret
= ENCODER_OBJECT_ID_INTERNAL_TMDS1
;
140 case ATOM_DEVICE_LCD2_SUPPORT
:
141 case ATOM_DEVICE_DFP2_SUPPORT
:
142 if ((rdev
->family
== CHIP_RS600
) ||
143 (rdev
->family
== CHIP_RS690
) ||
144 (rdev
->family
== CHIP_RS740
))
145 ret
= ENCODER_OBJECT_ID_INTERNAL_DDI
;
146 else if (ASIC_IS_AVIVO(rdev
))
147 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
;
149 ret
= ENCODER_OBJECT_ID_INTERNAL_DVO1
;
151 case ATOM_DEVICE_DFP3_SUPPORT
:
152 ret
= ENCODER_OBJECT_ID_INTERNAL_LVTM1
;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder
*encoder
)
161 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
162 switch (radeon_encoder
->encoder_id
) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
180 radeon_link_encoder_connector(struct drm_device
*dev
)
182 struct drm_connector
*connector
;
183 struct radeon_connector
*radeon_connector
;
184 struct drm_encoder
*encoder
;
185 struct radeon_encoder
*radeon_encoder
;
187 /* walk the list and link encoders to connectors */
188 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
189 radeon_connector
= to_radeon_connector(connector
);
190 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
191 radeon_encoder
= to_radeon_encoder(encoder
);
192 if (radeon_encoder
->devices
& radeon_connector
->devices
)
193 drm_mode_connector_attach_encoder(connector
, encoder
);
198 void radeon_encoder_set_active_device(struct drm_encoder
*encoder
)
200 struct drm_device
*dev
= encoder
->dev
;
201 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
202 struct drm_connector
*connector
;
204 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
205 if (connector
->encoder
== encoder
) {
206 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
207 radeon_encoder
->active_device
= radeon_encoder
->devices
& radeon_connector
->devices
;
208 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
209 radeon_encoder
->active_device
, radeon_encoder
->devices
,
210 radeon_connector
->devices
, encoder
->encoder_type
);
215 static struct drm_connector
*
216 radeon_get_connector_for_encoder(struct drm_encoder
*encoder
)
218 struct drm_device
*dev
= encoder
->dev
;
219 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
220 struct drm_connector
*connector
;
221 struct radeon_connector
*radeon_connector
;
223 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
224 radeon_connector
= to_radeon_connector(connector
);
225 if (radeon_encoder
->active_device
& radeon_connector
->devices
)
231 static struct radeon_connector_atom_dig
*
232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder
*encoder
)
234 struct drm_device
*dev
= encoder
->dev
;
235 struct radeon_device
*rdev
= dev
->dev_private
;
236 struct drm_connector
*connector
;
237 struct radeon_connector
*radeon_connector
;
238 struct radeon_connector_atom_dig
*dig_connector
;
240 if (!rdev
->is_atom_bios
)
243 connector
= radeon_get_connector_for_encoder(encoder
);
247 radeon_connector
= to_radeon_connector(connector
);
249 if (!radeon_connector
->con_priv
)
252 dig_connector
= radeon_connector
->con_priv
;
254 return dig_connector
;
257 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
258 struct drm_display_mode
*mode
,
259 struct drm_display_mode
*adjusted_mode
)
261 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
262 struct drm_device
*dev
= encoder
->dev
;
263 struct radeon_device
*rdev
= dev
->dev_private
;
265 /* adjust pm to upcoming mode change */
266 radeon_pm_compute_clocks(rdev
);
268 /* set the active encoder to connector routing */
269 radeon_encoder_set_active_device(encoder
);
270 drm_mode_set_crtcinfo(adjusted_mode
, 0);
273 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
274 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
275 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
277 /* get the native mode for LVDS */
278 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
)) {
279 struct drm_display_mode
*native_mode
= &radeon_encoder
->native_mode
;
280 int mode_id
= adjusted_mode
->base
.id
;
281 *adjusted_mode
= *native_mode
;
282 if (!ASIC_IS_AVIVO(rdev
)) {
283 adjusted_mode
->hdisplay
= mode
->hdisplay
;
284 adjusted_mode
->vdisplay
= mode
->vdisplay
;
285 adjusted_mode
->crtc_hdisplay
= mode
->hdisplay
;
286 adjusted_mode
->crtc_vdisplay
= mode
->vdisplay
;
288 adjusted_mode
->base
.id
= mode_id
;
291 /* get the native mode for TV */
292 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)) {
293 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
295 if (tv_dac
->tv_std
== TV_STD_NTSC
||
296 tv_dac
->tv_std
== TV_STD_NTSC_J
||
297 tv_dac
->tv_std
== TV_STD_PAL_M
)
298 radeon_atom_get_tv_timings(rdev
, 0, adjusted_mode
);
300 radeon_atom_get_tv_timings(rdev
, 1, adjusted_mode
);
304 if (ASIC_IS_DCE3(rdev
) &&
305 (radeon_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
))) {
306 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
307 radeon_dp_set_link_config(connector
, mode
);
314 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
316 struct drm_device
*dev
= encoder
->dev
;
317 struct radeon_device
*rdev
= dev
->dev_private
;
318 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
319 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
320 int index
= 0, num
= 0;
321 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
322 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
324 if (dac_info
->tv_std
)
325 tv_std
= dac_info
->tv_std
;
327 memset(&args
, 0, sizeof(args
));
329 switch (radeon_encoder
->encoder_id
) {
330 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
331 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
332 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
335 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
336 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
337 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
342 args
.ucAction
= action
;
344 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
345 args
.ucDacStandard
= ATOM_DAC1_PS2
;
346 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
347 args
.ucDacStandard
= ATOM_DAC1_CV
;
352 case TV_STD_SCART_PAL
:
355 args
.ucDacStandard
= ATOM_DAC1_PAL
;
361 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
365 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
367 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
372 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
374 struct drm_device
*dev
= encoder
->dev
;
375 struct radeon_device
*rdev
= dev
->dev_private
;
376 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
377 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
379 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
380 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
382 if (dac_info
->tv_std
)
383 tv_std
= dac_info
->tv_std
;
385 memset(&args
, 0, sizeof(args
));
387 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
389 args
.sTVEncoder
.ucAction
= action
;
391 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
392 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
396 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
399 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
402 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
405 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
408 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
410 case TV_STD_SCART_PAL
:
411 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
414 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
417 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
420 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
425 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
427 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
432 atombios_external_tmds_setup(struct drm_encoder
*encoder
, int action
)
434 struct drm_device
*dev
= encoder
->dev
;
435 struct radeon_device
*rdev
= dev
->dev_private
;
436 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
437 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args
;
440 memset(&args
, 0, sizeof(args
));
442 index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
444 args
.sXTmdsEncoder
.ucEnable
= action
;
446 if (radeon_encoder
->pixel_clock
> 165000)
447 args
.sXTmdsEncoder
.ucMisc
= PANEL_ENCODER_MISC_DUAL
;
449 /*if (pScrn->rgbBits == 8)*/
450 args
.sXTmdsEncoder
.ucMisc
|= (1 << 1);
452 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
457 atombios_ddia_setup(struct drm_encoder
*encoder
, int action
)
459 struct drm_device
*dev
= encoder
->dev
;
460 struct radeon_device
*rdev
= dev
->dev_private
;
461 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
462 DVO_ENCODER_CONTROL_PS_ALLOCATION args
;
465 memset(&args
, 0, sizeof(args
));
467 index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
469 args
.sDVOEncoder
.ucAction
= action
;
470 args
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
472 if (radeon_encoder
->pixel_clock
> 165000)
473 args
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
= PANEL_ENCODER_MISC_DUAL
;
475 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
479 union lvds_encoder_control
{
480 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
481 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
485 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
487 struct drm_device
*dev
= encoder
->dev
;
488 struct radeon_device
*rdev
= dev
->dev_private
;
489 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
490 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
491 struct radeon_connector_atom_dig
*dig_connector
=
492 radeon_get_atom_connector_priv_from_encoder(encoder
);
493 union lvds_encoder_control args
;
495 int hdmi_detected
= 0;
498 if (!dig
|| !dig_connector
)
501 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
504 memset(&args
, 0, sizeof(args
));
506 switch (radeon_encoder
->encoder_id
) {
507 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
508 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
510 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
511 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
512 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
514 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
515 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
516 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
518 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
522 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
530 args
.v1
.ucAction
= action
;
532 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
533 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
534 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
535 if (dig
->lvds_misc
& ATOM_PANEL_MISC_DUAL
)
536 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
537 if (dig
->lvds_misc
& ATOM_PANEL_MISC_888RGB
)
538 args
.v1
.ucMisc
|= (1 << 1);
540 if (dig_connector
->linkb
)
541 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
542 if (radeon_encoder
->pixel_clock
> 165000)
543 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
544 /*if (pScrn->rgbBits == 8) */
545 args
.v1
.ucMisc
|= (1 << 1);
551 args
.v2
.ucAction
= action
;
553 if (dig
->coherent_mode
)
554 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
557 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
558 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
559 args
.v2
.ucTruncate
= 0;
560 args
.v2
.ucSpatial
= 0;
561 args
.v2
.ucTemporal
= 0;
563 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
564 if (dig
->lvds_misc
& ATOM_PANEL_MISC_DUAL
)
565 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
566 if (dig
->lvds_misc
& ATOM_PANEL_MISC_SPATIAL
) {
567 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
568 if (dig
->lvds_misc
& ATOM_PANEL_MISC_888RGB
)
569 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
571 if (dig
->lvds_misc
& ATOM_PANEL_MISC_TEMPORAL
) {
572 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
573 if (dig
->lvds_misc
& ATOM_PANEL_MISC_888RGB
)
574 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
575 if (((dig
->lvds_misc
>> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
) & 0x3) == 2)
576 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
579 if (dig_connector
->linkb
)
580 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
581 if (radeon_encoder
->pixel_clock
> 165000)
582 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
586 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
591 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
595 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
596 r600_hdmi_enable(encoder
, hdmi_detected
);
600 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
602 struct drm_connector
*connector
;
603 struct radeon_connector
*radeon_connector
;
604 struct radeon_connector_atom_dig
*dig_connector
;
606 connector
= radeon_get_connector_for_encoder(encoder
);
610 radeon_connector
= to_radeon_connector(connector
);
612 switch (connector
->connector_type
) {
613 case DRM_MODE_CONNECTOR_DVII
:
614 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
615 if (drm_detect_hdmi_monitor(radeon_connector
->edid
))
616 return ATOM_ENCODER_MODE_HDMI
;
617 else if (radeon_connector
->use_digital
)
618 return ATOM_ENCODER_MODE_DVI
;
620 return ATOM_ENCODER_MODE_CRT
;
622 case DRM_MODE_CONNECTOR_DVID
:
623 case DRM_MODE_CONNECTOR_HDMIA
:
625 if (drm_detect_hdmi_monitor(radeon_connector
->edid
))
626 return ATOM_ENCODER_MODE_HDMI
;
628 return ATOM_ENCODER_MODE_DVI
;
630 case DRM_MODE_CONNECTOR_LVDS
:
631 return ATOM_ENCODER_MODE_LVDS
;
633 case DRM_MODE_CONNECTOR_DisplayPort
:
634 case DRM_MODE_CONNECTOR_eDP
:
635 dig_connector
= radeon_connector
->con_priv
;
636 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
637 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
))
638 return ATOM_ENCODER_MODE_DP
;
639 else if (drm_detect_hdmi_monitor(radeon_connector
->edid
))
640 return ATOM_ENCODER_MODE_HDMI
;
642 return ATOM_ENCODER_MODE_DVI
;
644 case DRM_MODE_CONNECTOR_DVIA
:
645 case DRM_MODE_CONNECTOR_VGA
:
646 return ATOM_ENCODER_MODE_CRT
;
648 case DRM_MODE_CONNECTOR_Composite
:
649 case DRM_MODE_CONNECTOR_SVIDEO
:
650 case DRM_MODE_CONNECTOR_9PinDIN
:
652 return ATOM_ENCODER_MODE_TV
;
653 /*return ATOM_ENCODER_MODE_CV;*/
659 * DIG Encoder/Transmitter Setup
662 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
663 * Supports up to 3 digital outputs
664 * - 2 DIG encoder blocks.
665 * DIG1 can drive UNIPHY link A or link B
666 * DIG2 can drive UNIPHY link B or LVTMA
669 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
670 * Supports up to 5 digital outputs
671 * - 2 DIG encoder blocks.
672 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
675 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
677 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
678 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
679 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
680 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
683 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
)
685 struct drm_device
*dev
= encoder
->dev
;
686 struct radeon_device
*rdev
= dev
->dev_private
;
687 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
688 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
689 struct radeon_connector_atom_dig
*dig_connector
=
690 radeon_get_atom_connector_priv_from_encoder(encoder
);
691 DIG_ENCODER_CONTROL_PS_ALLOCATION args
;
692 int index
= 0, num
= 0;
695 if (!dig
|| !dig_connector
)
698 memset(&args
, 0, sizeof(args
));
700 if (dig
->dig_encoder
)
701 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
703 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
704 num
= dig
->dig_encoder
+ 1;
706 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
708 args
.ucAction
= action
;
709 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
711 if (ASIC_IS_DCE32(rdev
)) {
712 switch (radeon_encoder
->encoder_id
) {
713 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
714 args
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
716 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
717 args
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
719 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
720 args
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
724 switch (radeon_encoder
->encoder_id
) {
725 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
726 args
.ucConfig
= ATOM_ENCODER_CONFIG_TRANSMITTER1
;
728 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
729 args
.ucConfig
= ATOM_ENCODER_CONFIG_TRANSMITTER2
;
734 args
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
736 if (args
.ucEncoderMode
== ATOM_ENCODER_MODE_DP
) {
737 if (dig_connector
->dp_clock
== 270000)
738 args
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
739 args
.ucLaneNum
= dig_connector
->dp_lane_count
;
740 } else if (radeon_encoder
->pixel_clock
> 165000)
745 if (dig_connector
->linkb
)
746 args
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
748 args
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
750 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
754 union dig_transmitter_control
{
755 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
756 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
760 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
, uint8_t lane_num
, uint8_t lane_set
)
762 struct drm_device
*dev
= encoder
->dev
;
763 struct radeon_device
*rdev
= dev
->dev_private
;
764 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
765 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
766 struct radeon_connector_atom_dig
*dig_connector
=
767 radeon_get_atom_connector_priv_from_encoder(encoder
);
768 struct drm_connector
*connector
;
769 struct radeon_connector
*radeon_connector
;
770 union dig_transmitter_control args
;
771 int index
= 0, num
= 0;
775 if (!dig
|| !dig_connector
)
778 connector
= radeon_get_connector_for_encoder(encoder
);
779 radeon_connector
= to_radeon_connector(connector
);
781 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_DP
)
784 memset(&args
, 0, sizeof(args
));
786 if (ASIC_IS_DCE32(rdev
))
787 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
789 switch (radeon_encoder
->encoder_id
) {
790 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
791 index
= GetIndexIntoMasterTable(COMMAND
, DIG1TransmitterControl
);
793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
794 index
= GetIndexIntoMasterTable(COMMAND
, DIG2TransmitterControl
);
799 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
801 args
.v1
.ucAction
= action
;
802 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
803 args
.v1
.usInitInfo
= radeon_connector
->connector_object_id
;
804 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
805 args
.v1
.asMode
.ucLaneSel
= lane_num
;
806 args
.v1
.asMode
.ucLaneSet
= lane_set
;
809 args
.v1
.usPixelClock
=
810 cpu_to_le16(dig_connector
->dp_clock
/ 10);
811 else if (radeon_encoder
->pixel_clock
> 165000)
812 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
814 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
816 if (ASIC_IS_DCE32(rdev
)) {
817 if (dig
->dig_encoder
== 1)
818 args
.v2
.acConfig
.ucEncoderSel
= 1;
819 if (dig_connector
->linkb
)
820 args
.v2
.acConfig
.ucLinkSel
= 1;
822 switch (radeon_encoder
->encoder_id
) {
823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
824 args
.v2
.acConfig
.ucTransmitterSel
= 0;
827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
828 args
.v2
.acConfig
.ucTransmitterSel
= 1;
831 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
832 args
.v2
.acConfig
.ucTransmitterSel
= 2;
838 args
.v2
.acConfig
.fCoherentMode
= 1;
839 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
840 if (dig
->coherent_mode
)
841 args
.v2
.acConfig
.fCoherentMode
= 1;
845 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
847 if (dig
->dig_encoder
)
848 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
850 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
852 switch (radeon_encoder
->encoder_id
) {
853 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
854 if (rdev
->flags
& RADEON_IS_IGP
) {
855 if (radeon_encoder
->pixel_clock
> 165000) {
856 if (dig_connector
->igp_lane_info
& 0x3)
857 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
858 else if (dig_connector
->igp_lane_info
& 0xc)
859 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
861 if (dig_connector
->igp_lane_info
& 0x1)
862 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
863 else if (dig_connector
->igp_lane_info
& 0x2)
864 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
865 else if (dig_connector
->igp_lane_info
& 0x4)
866 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
867 else if (dig_connector
->igp_lane_info
& 0x8)
868 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
874 if (radeon_encoder
->pixel_clock
> 165000)
875 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
877 if (dig_connector
->linkb
)
878 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
880 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
883 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
884 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
885 if (dig
->coherent_mode
)
886 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
890 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
894 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
896 struct drm_device
*dev
= encoder
->dev
;
897 struct radeon_device
*rdev
= dev
->dev_private
;
898 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
899 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
900 ENABLE_YUV_PS_ALLOCATION args
;
901 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
904 memset(&args
, 0, sizeof(args
));
906 if (rdev
->family
>= CHIP_R600
)
907 reg
= R600_BIOS_3_SCRATCH
;
909 reg
= RADEON_BIOS_3_SCRATCH
;
911 /* XXX: fix up scratch reg handling */
913 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
914 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
915 (radeon_crtc
->crtc_id
<< 18)));
916 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
917 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
922 args
.ucEnable
= ATOM_ENABLE
;
923 args
.ucCRTC
= radeon_crtc
->crtc_id
;
925 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
931 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
933 struct drm_device
*dev
= encoder
->dev
;
934 struct radeon_device
*rdev
= dev
->dev_private
;
935 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
936 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
940 memset(&args
, 0, sizeof(args
));
942 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
943 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
944 radeon_encoder
->active_device
);
945 switch (radeon_encoder
->encoder_id
) {
946 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
947 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
948 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
950 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
951 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
952 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
953 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
956 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
957 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
958 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
959 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
961 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
962 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
964 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
965 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
966 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
968 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
970 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
971 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
972 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
973 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
974 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
975 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
977 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
979 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
980 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
981 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
982 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
983 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
984 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
986 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
992 case DRM_MODE_DPMS_ON
:
993 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
, 0, 0);
995 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
996 dp_link_train(encoder
, connector
);
999 case DRM_MODE_DPMS_STANDBY
:
1000 case DRM_MODE_DPMS_SUSPEND
:
1001 case DRM_MODE_DPMS_OFF
:
1002 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
, 0, 0);
1007 case DRM_MODE_DPMS_ON
:
1008 args
.ucAction
= ATOM_ENABLE
;
1010 case DRM_MODE_DPMS_STANDBY
:
1011 case DRM_MODE_DPMS_SUSPEND
:
1012 case DRM_MODE_DPMS_OFF
:
1013 args
.ucAction
= ATOM_DISABLE
;
1016 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1018 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
1020 /* adjust pm to dpms change */
1021 radeon_pm_compute_clocks(rdev
);
1024 union crtc_source_param
{
1025 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1026 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1030 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
1032 struct drm_device
*dev
= encoder
->dev
;
1033 struct radeon_device
*rdev
= dev
->dev_private
;
1034 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1035 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1036 union crtc_source_param args
;
1037 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1039 struct radeon_encoder_atom_dig
*dig
;
1041 memset(&args
, 0, sizeof(args
));
1043 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
1050 if (ASIC_IS_AVIVO(rdev
))
1051 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1053 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
1054 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1056 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
1059 switch (radeon_encoder
->encoder_id
) {
1060 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1061 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1062 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1064 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1065 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1066 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1067 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1069 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1071 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1072 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1073 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1074 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1076 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1077 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1078 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1079 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1080 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1081 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1083 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1085 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1086 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1087 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1088 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1089 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1090 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1092 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1097 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1098 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1099 switch (radeon_encoder
->encoder_id
) {
1100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1101 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1103 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1104 dig
= radeon_encoder
->enc_priv
;
1105 if (dig
->dig_encoder
)
1106 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1108 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1110 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1111 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1113 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1114 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1115 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1116 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1117 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1119 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1121 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1122 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1123 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1124 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1125 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1127 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1134 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1138 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1142 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1143 struct drm_display_mode
*mode
)
1145 struct drm_device
*dev
= encoder
->dev
;
1146 struct radeon_device
*rdev
= dev
->dev_private
;
1147 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1148 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1150 /* Funky macbooks */
1151 if ((dev
->pdev
->device
== 0x71C5) &&
1152 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1153 (dev
->pdev
->subsystem_device
== 0x0080)) {
1154 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1155 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1157 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1158 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1160 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1164 /* set scaler clears this on some chips */
1165 if (!(radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))) {
1166 if (ASIC_IS_AVIVO(rdev
) && (mode
->flags
& DRM_MODE_FLAG_INTERLACE
))
1167 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1168 AVIVO_D1MODE_INTERLEAVE_EN
);
1172 static int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder
)
1174 struct drm_device
*dev
= encoder
->dev
;
1175 struct radeon_device
*rdev
= dev
->dev_private
;
1176 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1177 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1178 struct drm_encoder
*test_encoder
;
1179 struct radeon_encoder_atom_dig
*dig
;
1180 uint32_t dig_enc_in_use
= 0;
1181 /* on DCE32 and encoder can driver any block so just crtc id */
1182 if (ASIC_IS_DCE32(rdev
)) {
1183 return radeon_crtc
->crtc_id
;
1186 /* on DCE3 - LVTMA can only be driven by DIGB */
1187 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
1188 struct radeon_encoder
*radeon_test_encoder
;
1190 if (encoder
== test_encoder
)
1193 if (!radeon_encoder_is_digital(test_encoder
))
1196 radeon_test_encoder
= to_radeon_encoder(test_encoder
);
1197 dig
= radeon_test_encoder
->enc_priv
;
1199 if (dig
->dig_encoder
>= 0)
1200 dig_enc_in_use
|= (1 << dig
->dig_encoder
);
1203 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
) {
1204 if (dig_enc_in_use
& 0x2)
1205 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1208 if (!(dig_enc_in_use
& 1))
1214 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
1215 struct drm_display_mode
*mode
,
1216 struct drm_display_mode
*adjusted_mode
)
1218 struct drm_device
*dev
= encoder
->dev
;
1219 struct radeon_device
*rdev
= dev
->dev_private
;
1220 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1221 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1223 if (radeon_encoder
->active_device
&
1224 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) {
1225 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1227 dig
->dig_encoder
= radeon_atom_pick_dig_encoder(encoder
);
1229 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
1231 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1232 atombios_set_encoder_crtc_source(encoder
);
1234 if (ASIC_IS_AVIVO(rdev
)) {
1235 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
1236 atombios_yuv_setup(encoder
, true);
1238 atombios_yuv_setup(encoder
, false);
1241 switch (radeon_encoder
->encoder_id
) {
1242 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1243 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1244 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1245 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1246 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
1248 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1249 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1251 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1252 /* disable the encoder and transmitter */
1253 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1254 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
);
1256 /* setup and enable the encoder and transmitter */
1257 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
);
1258 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
1259 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
, 0, 0);
1260 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1262 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1263 atombios_ddia_setup(encoder
, ATOM_ENABLE
);
1265 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1266 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1267 atombios_external_tmds_setup(encoder
, ATOM_ENABLE
);
1269 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1270 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1271 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1272 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1273 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1274 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
1275 atombios_tv_setup(encoder
, ATOM_ENABLE
);
1278 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
1280 r600_hdmi_setmode(encoder
, adjusted_mode
);
1284 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1286 struct drm_device
*dev
= encoder
->dev
;
1287 struct radeon_device
*rdev
= dev
->dev_private
;
1288 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1289 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1291 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
1292 ATOM_DEVICE_CV_SUPPORT
|
1293 ATOM_DEVICE_CRT_SUPPORT
)) {
1294 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
1295 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
1298 memset(&args
, 0, sizeof(args
));
1300 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
1302 args
.sDacload
.ucMisc
= 0;
1304 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
1305 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
1306 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
1308 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
1310 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
1311 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
1312 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
1313 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
1314 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1315 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
1317 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1318 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1319 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
1321 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1324 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1331 static enum drm_connector_status
1332 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1334 struct drm_device
*dev
= encoder
->dev
;
1335 struct radeon_device
*rdev
= dev
->dev_private
;
1336 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1337 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1338 uint32_t bios_0_scratch
;
1340 if (!atombios_dac_load_detect(encoder
, connector
)) {
1341 DRM_DEBUG("detect returned false \n");
1342 return connector_status_unknown
;
1345 if (rdev
->family
>= CHIP_R600
)
1346 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1348 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1350 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
1351 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1352 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1353 return connector_status_connected
;
1355 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1356 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1357 return connector_status_connected
;
1359 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1360 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1361 return connector_status_connected
;
1363 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1364 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1365 return connector_status_connected
; /* CTV */
1366 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1367 return connector_status_connected
; /* STV */
1369 return connector_status_disconnected
;
1372 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
1374 radeon_atom_output_lock(encoder
, true);
1375 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1378 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
1380 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
1381 radeon_atom_output_lock(encoder
, false);
1384 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
1386 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1387 struct radeon_encoder_atom_dig
*dig
;
1388 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1390 if (radeon_encoder_is_digital(encoder
)) {
1391 dig
= radeon_encoder
->enc_priv
;
1392 dig
->dig_encoder
= -1;
1394 radeon_encoder
->active_device
= 0;
1397 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
1398 .dpms
= radeon_atom_encoder_dpms
,
1399 .mode_fixup
= radeon_atom_mode_fixup
,
1400 .prepare
= radeon_atom_encoder_prepare
,
1401 .mode_set
= radeon_atom_encoder_mode_set
,
1402 .commit
= radeon_atom_encoder_commit
,
1403 .disable
= radeon_atom_encoder_disable
,
1404 /* no detect for TMDS/LVDS yet */
1407 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
1408 .dpms
= radeon_atom_encoder_dpms
,
1409 .mode_fixup
= radeon_atom_mode_fixup
,
1410 .prepare
= radeon_atom_encoder_prepare
,
1411 .mode_set
= radeon_atom_encoder_mode_set
,
1412 .commit
= radeon_atom_encoder_commit
,
1413 .detect
= radeon_atom_dac_detect
,
1416 void radeon_enc_destroy(struct drm_encoder
*encoder
)
1418 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1419 kfree(radeon_encoder
->enc_priv
);
1420 drm_encoder_cleanup(encoder
);
1421 kfree(radeon_encoder
);
1424 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
1425 .destroy
= radeon_enc_destroy
,
1428 struct radeon_encoder_atom_dac
*
1429 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
1431 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
1436 dac
->tv_std
= TV_STD_NTSC
;
1440 struct radeon_encoder_atom_dig
*
1441 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
1443 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1448 /* coherent mode by default */
1449 dig
->coherent_mode
= true;
1450 dig
->dig_encoder
= -1;
1456 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_id
, uint32_t supported_device
)
1458 struct radeon_device
*rdev
= dev
->dev_private
;
1459 struct drm_encoder
*encoder
;
1460 struct radeon_encoder
*radeon_encoder
;
1462 /* see if we already added it */
1463 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1464 radeon_encoder
= to_radeon_encoder(encoder
);
1465 if (radeon_encoder
->encoder_id
== encoder_id
) {
1466 radeon_encoder
->devices
|= supported_device
;
1473 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
1474 if (!radeon_encoder
)
1477 encoder
= &radeon_encoder
->base
;
1478 if (rdev
->flags
& RADEON_SINGLE_CRTC
)
1479 encoder
->possible_crtcs
= 0x1;
1481 encoder
->possible_crtcs
= 0x3;
1483 radeon_encoder
->enc_priv
= NULL
;
1485 radeon_encoder
->encoder_id
= encoder_id
;
1486 radeon_encoder
->devices
= supported_device
;
1487 radeon_encoder
->rmx_type
= RMX_OFF
;
1489 switch (radeon_encoder
->encoder_id
) {
1490 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1491 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1492 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1493 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1494 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1495 radeon_encoder
->rmx_type
= RMX_FULL
;
1496 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
1497 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
1499 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
1500 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
1502 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
1504 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1505 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
1506 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
1508 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1509 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1510 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1511 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
1512 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
1513 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
1515 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1516 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1517 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1518 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1519 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1520 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1521 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1522 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1523 radeon_encoder
->rmx_type
= RMX_FULL
;
1524 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
1525 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
1527 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
1528 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
1530 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
1534 r600_hdmi_init(encoder
);