1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
34 #include <drm/radeon_drm.h>
35 #include "radeon_drv.h"
37 void radeon_irq_set_state(struct drm_device
*dev
, u32 mask
, int state
)
39 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
42 dev_priv
->irq_enable_reg
|= mask
;
44 dev_priv
->irq_enable_reg
&= ~mask
;
47 RADEON_WRITE(RADEON_GEN_INT_CNTL
, dev_priv
->irq_enable_reg
);
50 static void r500_vbl_irq_set_state(struct drm_device
*dev
, u32 mask
, int state
)
52 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
55 dev_priv
->r500_disp_irq_reg
|= mask
;
57 dev_priv
->r500_disp_irq_reg
&= ~mask
;
60 RADEON_WRITE(R500_DxMODE_INT_MASK
, dev_priv
->r500_disp_irq_reg
);
63 int radeon_enable_vblank(struct drm_device
*dev
, int crtc
)
65 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
67 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RS600
) {
70 r500_vbl_irq_set_state(dev
, R500_D1MODE_INT_MASK
, 1);
73 r500_vbl_irq_set_state(dev
, R500_D2MODE_INT_MASK
, 1);
76 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
83 radeon_irq_set_state(dev
, RADEON_CRTC_VBLANK_MASK
, 1);
86 radeon_irq_set_state(dev
, RADEON_CRTC2_VBLANK_MASK
, 1);
89 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
98 void radeon_disable_vblank(struct drm_device
*dev
, int crtc
)
100 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
102 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RS600
) {
105 r500_vbl_irq_set_state(dev
, R500_D1MODE_INT_MASK
, 0);
108 r500_vbl_irq_set_state(dev
, R500_D2MODE_INT_MASK
, 0);
111 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
118 radeon_irq_set_state(dev
, RADEON_CRTC_VBLANK_MASK
, 0);
121 radeon_irq_set_state(dev
, RADEON_CRTC2_VBLANK_MASK
, 0);
124 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
131 static u32
radeon_acknowledge_irqs(drm_radeon_private_t
*dev_priv
, u32
*r500_disp_int
)
133 u32 irqs
= RADEON_READ(RADEON_GEN_INT_STATUS
);
134 u32 irq_mask
= RADEON_SW_INT_TEST
;
137 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RS600
) {
138 /* vbl interrupts in a different place */
140 if (irqs
& R500_DISPLAY_INT_STATUS
) {
141 /* if a display interrupt */
144 disp_irq
= RADEON_READ(R500_DISP_INTERRUPT_STATUS
);
146 *r500_disp_int
= disp_irq
;
147 if (disp_irq
& R500_D1_VBLANK_INTERRUPT
)
148 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS
, R500_VBLANK_ACK
);
149 if (disp_irq
& R500_D2_VBLANK_INTERRUPT
)
150 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS
, R500_VBLANK_ACK
);
152 irq_mask
|= R500_DISPLAY_INT_STATUS
;
154 irq_mask
|= RADEON_CRTC_VBLANK_STAT
| RADEON_CRTC2_VBLANK_STAT
;
159 RADEON_WRITE(RADEON_GEN_INT_STATUS
, irqs
);
164 /* Interrupts - Used for device synchronization and flushing in the
165 * following circumstances:
167 * - Exclusive FB access with hw idle:
168 * - Wait for GUI Idle (?) interrupt, then do normal flush.
170 * - Frame throttling, NV_fence:
171 * - Drop marker irq's into command stream ahead of time.
172 * - Wait on irq's with lock *not held*
173 * - Check each for termination condition
175 * - Internally in cp_getbuffer, etc:
176 * - as above, but wait with lock held???
178 * NOTE: These functions are misleadingly named -- the irq's aren't
179 * tied to dma at all, this is just a hangover from dri prehistory.
182 irqreturn_t
radeon_driver_irq_handler(DRM_IRQ_ARGS
)
184 struct drm_device
*dev
= (struct drm_device
*) arg
;
185 drm_radeon_private_t
*dev_priv
=
186 (drm_radeon_private_t
*) dev
->dev_private
;
190 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
193 /* Only consider the bits we're interested in - others could be used
196 stat
= radeon_acknowledge_irqs(dev_priv
, &r500_disp_int
);
200 stat
&= dev_priv
->irq_enable_reg
;
203 if (stat
& RADEON_SW_INT_TEST
)
204 DRM_WAKEUP(&dev_priv
->swi_queue
);
206 /* VBLANK interrupt */
207 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RS600
) {
208 if (r500_disp_int
& R500_D1_VBLANK_INTERRUPT
)
209 drm_handle_vblank(dev
, 0);
210 if (r500_disp_int
& R500_D2_VBLANK_INTERRUPT
)
211 drm_handle_vblank(dev
, 1);
213 if (stat
& RADEON_CRTC_VBLANK_STAT
)
214 drm_handle_vblank(dev
, 0);
215 if (stat
& RADEON_CRTC2_VBLANK_STAT
)
216 drm_handle_vblank(dev
, 1);
221 static int radeon_emit_irq(struct drm_device
* dev
)
223 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
227 atomic_inc(&dev_priv
->swi_emitted
);
228 ret
= atomic_read(&dev_priv
->swi_emitted
);
231 OUT_RING_REG(RADEON_LAST_SWI_REG
, ret
);
232 OUT_RING_REG(RADEON_GEN_INT_STATUS
, RADEON_SW_INT_FIRE
);
239 static int radeon_wait_irq(struct drm_device
* dev
, int swi_nr
)
241 drm_radeon_private_t
*dev_priv
=
242 (drm_radeon_private_t
*) dev
->dev_private
;
245 if (RADEON_READ(RADEON_LAST_SWI_REG
) >= swi_nr
)
248 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
250 DRM_WAIT_ON(ret
, dev_priv
->swi_queue
, 3 * DRM_HZ
,
251 RADEON_READ(RADEON_LAST_SWI_REG
) >= swi_nr
);
256 u32
radeon_get_vblank_counter(struct drm_device
*dev
, int crtc
)
258 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
261 DRM_ERROR("called with no initialization\n");
265 if (crtc
< 0 || crtc
> 1) {
266 DRM_ERROR("Invalid crtc %d\n", crtc
);
270 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RS600
) {
272 return RADEON_READ(R500_D1CRTC_FRAME_COUNT
);
274 return RADEON_READ(R500_D2CRTC_FRAME_COUNT
);
277 return RADEON_READ(RADEON_CRTC_CRNT_FRAME
);
279 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME
);
283 /* Needs the lock as it touches the ring.
285 int radeon_irq_emit(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
287 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
288 drm_radeon_irq_emit_t
*emit
= data
;
292 DRM_ERROR("called with no initialization\n");
296 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
299 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
301 result
= radeon_emit_irq(dev
);
303 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
304 DRM_ERROR("copy_to_user\n");
311 /* Doesn't need the hardware lock.
313 int radeon_irq_wait(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
315 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
316 drm_radeon_irq_wait_t
*irqwait
= data
;
319 DRM_ERROR("called with no initialization\n");
323 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
326 return radeon_wait_irq(dev
, irqwait
->irq_seq
);
331 void radeon_driver_irq_preinstall(struct drm_device
* dev
)
333 drm_radeon_private_t
*dev_priv
=
334 (drm_radeon_private_t
*) dev
->dev_private
;
337 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
340 /* Disable *all* interrupts */
341 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RS600
)
342 RADEON_WRITE(R500_DxMODE_INT_MASK
, 0);
343 RADEON_WRITE(RADEON_GEN_INT_CNTL
, 0);
345 /* Clear bits if they're already high */
346 radeon_acknowledge_irqs(dev_priv
, &dummy
);
349 int radeon_driver_irq_postinstall(struct drm_device
*dev
)
351 drm_radeon_private_t
*dev_priv
=
352 (drm_radeon_private_t
*) dev
->dev_private
;
354 atomic_set(&dev_priv
->swi_emitted
, 0);
355 DRM_INIT_WAITQUEUE(&dev_priv
->swi_queue
);
357 dev
->max_vblank_count
= 0x001fffff;
359 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
362 radeon_irq_set_state(dev
, RADEON_SW_INT_ENABLE
, 1);
367 void radeon_driver_irq_uninstall(struct drm_device
* dev
)
369 drm_radeon_private_t
*dev_priv
=
370 (drm_radeon_private_t
*) dev
->dev_private
;
374 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_R600
)
377 if ((dev_priv
->flags
& RADEON_FAMILY_MASK
) >= CHIP_RS600
)
378 RADEON_WRITE(R500_DxMODE_INT_MASK
, 0);
379 /* Disable *all* interrupts */
380 RADEON_WRITE(RADEON_GEN_INT_CNTL
, 0);
384 int radeon_vblank_crtc_get(struct drm_device
*dev
)
386 drm_radeon_private_t
*dev_priv
= (drm_radeon_private_t
*) dev
->dev_private
;
388 return dev_priv
->vblank_crtc
;
391 int radeon_vblank_crtc_set(struct drm_device
*dev
, int64_t value
)
393 drm_radeon_private_t
*dev_priv
= (drm_radeon_private_t
*) dev
->dev_private
;
394 if (value
& ~(DRM_RADEON_VBLANK_CRTC1
| DRM_RADEON_VBLANK_CRTC2
)) {
395 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value
);
398 dev_priv
->vblank_crtc
= (unsigned int)value
;