2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device
*rdev
);
41 void radeon_ttm_fini(struct radeon_device
*rdev
);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo
*bo
);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 static void radeon_update_memory_usage(struct radeon_bo
*bo
,
50 unsigned mem_type
, int sign
)
52 struct radeon_device
*rdev
= bo
->rdev
;
53 u64 size
= (u64
)bo
->tbo
.num_pages
<< PAGE_SHIFT
;
58 atomic64_add(size
, &rdev
->gtt_usage
);
60 atomic64_sub(size
, &rdev
->gtt_usage
);
64 atomic64_add(size
, &rdev
->vram_usage
);
66 atomic64_sub(size
, &rdev
->vram_usage
);
71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object
*tbo
)
75 bo
= container_of(tbo
, struct radeon_bo
, tbo
);
77 radeon_update_memory_usage(bo
, bo
->tbo
.mem
.mem_type
, -1);
79 mutex_lock(&bo
->rdev
->gem
.mutex
);
80 list_del_init(&bo
->list
);
81 mutex_unlock(&bo
->rdev
->gem
.mutex
);
82 radeon_bo_clear_surface_reg(bo
);
83 WARN_ON(!list_empty(&bo
->va
));
84 drm_gem_object_release(&bo
->gem_base
);
88 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo
)
90 if (bo
->destroy
== &radeon_ttm_bo_destroy
)
95 void radeon_ttm_placement_from_domain(struct radeon_bo
*rbo
, u32 domain
)
99 rbo
->placement
.placement
= rbo
->placements
;
100 rbo
->placement
.busy_placement
= rbo
->placements
;
101 if (domain
& RADEON_GEM_DOMAIN_VRAM
) {
102 /* Try placing BOs which don't need CPU access outside of the
103 * CPU accessible part of VRAM
105 if ((rbo
->flags
& RADEON_GEM_NO_CPU_ACCESS
) &&
106 rbo
->rdev
->mc
.visible_vram_size
< rbo
->rdev
->mc
.real_vram_size
) {
107 rbo
->placements
[c
].fpfn
=
108 rbo
->rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
109 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
110 TTM_PL_FLAG_UNCACHED
|
114 rbo
->placements
[c
].fpfn
= 0;
115 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
116 TTM_PL_FLAG_UNCACHED
|
120 if (domain
& RADEON_GEM_DOMAIN_GTT
) {
121 if (rbo
->flags
& RADEON_GEM_GTT_UC
) {
122 rbo
->placements
[c
].fpfn
= 0;
123 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
126 } else if ((rbo
->flags
& RADEON_GEM_GTT_WC
) ||
127 (rbo
->rdev
->flags
& RADEON_IS_AGP
)) {
128 rbo
->placements
[c
].fpfn
= 0;
129 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
130 TTM_PL_FLAG_UNCACHED
|
133 rbo
->placements
[c
].fpfn
= 0;
134 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_CACHED
|
139 if (domain
& RADEON_GEM_DOMAIN_CPU
) {
140 if (rbo
->flags
& RADEON_GEM_GTT_UC
) {
141 rbo
->placements
[c
].fpfn
= 0;
142 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
145 } else if ((rbo
->flags
& RADEON_GEM_GTT_WC
) ||
146 rbo
->rdev
->flags
& RADEON_IS_AGP
) {
147 rbo
->placements
[c
].fpfn
= 0;
148 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
149 TTM_PL_FLAG_UNCACHED
|
152 rbo
->placements
[c
].fpfn
= 0;
153 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_CACHED
|
158 rbo
->placements
[c
].fpfn
= 0;
159 rbo
->placements
[c
++].flags
= TTM_PL_MASK_CACHING
|
163 rbo
->placement
.num_placement
= c
;
164 rbo
->placement
.num_busy_placement
= c
;
166 for (i
= 0; i
< c
; ++i
) {
167 if ((rbo
->flags
& RADEON_GEM_CPU_ACCESS
) &&
168 (rbo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
169 !rbo
->placements
[i
].fpfn
)
170 rbo
->placements
[i
].lpfn
=
171 rbo
->rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
173 rbo
->placements
[i
].lpfn
= 0;
177 int radeon_bo_create(struct radeon_device
*rdev
,
178 unsigned long size
, int byte_align
, bool kernel
,
179 u32 domain
, u32 flags
, struct sg_table
*sg
,
180 struct reservation_object
*resv
,
181 struct radeon_bo
**bo_ptr
)
183 struct radeon_bo
*bo
;
184 enum ttm_bo_type type
;
185 unsigned long page_align
= roundup(byte_align
, PAGE_SIZE
) >> PAGE_SHIFT
;
189 size
= ALIGN(size
, PAGE_SIZE
);
192 type
= ttm_bo_type_kernel
;
194 type
= ttm_bo_type_sg
;
196 type
= ttm_bo_type_device
;
200 acc_size
= ttm_bo_dma_acc_size(&rdev
->mman
.bdev
, size
,
201 sizeof(struct radeon_bo
));
203 bo
= kzalloc(sizeof(struct radeon_bo
), GFP_KERNEL
);
206 r
= drm_gem_object_init(rdev
->ddev
, &bo
->gem_base
, size
);
212 bo
->surface_reg
= -1;
213 INIT_LIST_HEAD(&bo
->list
);
214 INIT_LIST_HEAD(&bo
->va
);
215 bo
->initial_domain
= domain
& (RADEON_GEM_DOMAIN_VRAM
|
216 RADEON_GEM_DOMAIN_GTT
|
217 RADEON_GEM_DOMAIN_CPU
);
220 /* PCI GART is always snooped */
221 if (!(rdev
->flags
& RADEON_IS_PCIE
))
222 bo
->flags
&= ~(RADEON_GEM_GTT_WC
| RADEON_GEM_GTT_UC
);
225 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
226 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
228 bo
->flags
&= ~RADEON_GEM_GTT_WC
;
229 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
230 /* Don't try to enable write-combining when it can't work, or things
232 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
235 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
236 thanks to write-combining
238 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
239 "better performance thanks to write-combining\n");
240 bo
->flags
&= ~RADEON_GEM_GTT_WC
;
243 radeon_ttm_placement_from_domain(bo
, domain
);
244 /* Kernel allocation are uninterruptible */
245 down_read(&rdev
->pm
.mclk_lock
);
246 r
= ttm_bo_init(&rdev
->mman
.bdev
, &bo
->tbo
, size
, type
,
247 &bo
->placement
, page_align
, !kernel
, NULL
,
248 acc_size
, sg
, resv
, &radeon_ttm_bo_destroy
);
249 up_read(&rdev
->pm
.mclk_lock
);
250 if (unlikely(r
!= 0)) {
255 trace_radeon_bo_create(bo
);
260 int radeon_bo_kmap(struct radeon_bo
*bo
, void **ptr
)
271 r
= ttm_bo_kmap(&bo
->tbo
, 0, bo
->tbo
.num_pages
, &bo
->kmap
);
275 bo
->kptr
= ttm_kmap_obj_virtual(&bo
->kmap
, &is_iomem
);
279 radeon_bo_check_tiling(bo
, 0, 0);
283 void radeon_bo_kunmap(struct radeon_bo
*bo
)
285 if (bo
->kptr
== NULL
)
288 radeon_bo_check_tiling(bo
, 0, 0);
289 ttm_bo_kunmap(&bo
->kmap
);
292 struct radeon_bo
*radeon_bo_ref(struct radeon_bo
*bo
)
297 ttm_bo_reference(&bo
->tbo
);
301 void radeon_bo_unref(struct radeon_bo
**bo
)
303 struct ttm_buffer_object
*tbo
;
304 struct radeon_device
*rdev
;
315 int radeon_bo_pin_restricted(struct radeon_bo
*bo
, u32 domain
, u64 max_offset
,
320 if (radeon_ttm_tt_has_userptr(bo
->tbo
.ttm
))
326 *gpu_addr
= radeon_bo_gpu_offset(bo
);
328 if (max_offset
!= 0) {
331 if (domain
== RADEON_GEM_DOMAIN_VRAM
)
332 domain_start
= bo
->rdev
->mc
.vram_start
;
334 domain_start
= bo
->rdev
->mc
.gtt_start
;
335 WARN_ON_ONCE(max_offset
<
336 (radeon_bo_gpu_offset(bo
) - domain_start
));
341 radeon_ttm_placement_from_domain(bo
, domain
);
342 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
343 /* force to pin into visible video ram */
344 if ((bo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
345 !(bo
->flags
& RADEON_GEM_NO_CPU_ACCESS
) &&
346 (!max_offset
|| max_offset
> bo
->rdev
->mc
.visible_vram_size
))
347 bo
->placements
[i
].lpfn
=
348 bo
->rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
350 bo
->placements
[i
].lpfn
= max_offset
>> PAGE_SHIFT
;
352 bo
->placements
[i
].flags
|= TTM_PL_FLAG_NO_EVICT
;
355 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
356 if (likely(r
== 0)) {
358 if (gpu_addr
!= NULL
)
359 *gpu_addr
= radeon_bo_gpu_offset(bo
);
360 if (domain
== RADEON_GEM_DOMAIN_VRAM
)
361 bo
->rdev
->vram_pin_size
+= radeon_bo_size(bo
);
363 bo
->rdev
->gart_pin_size
+= radeon_bo_size(bo
);
365 dev_err(bo
->rdev
->dev
, "%p pin failed\n", bo
);
370 int radeon_bo_pin(struct radeon_bo
*bo
, u32 domain
, u64
*gpu_addr
)
372 return radeon_bo_pin_restricted(bo
, domain
, 0, gpu_addr
);
375 int radeon_bo_unpin(struct radeon_bo
*bo
)
379 if (!bo
->pin_count
) {
380 dev_warn(bo
->rdev
->dev
, "%p unpin not necessary\n", bo
);
386 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
387 bo
->placements
[i
].lpfn
= 0;
388 bo
->placements
[i
].flags
&= ~TTM_PL_FLAG_NO_EVICT
;
390 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
391 if (likely(r
== 0)) {
392 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
393 bo
->rdev
->vram_pin_size
-= radeon_bo_size(bo
);
395 bo
->rdev
->gart_pin_size
-= radeon_bo_size(bo
);
397 dev_err(bo
->rdev
->dev
, "%p validate failed for unpin\n", bo
);
402 int radeon_bo_evict_vram(struct radeon_device
*rdev
)
404 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
405 if (0 && (rdev
->flags
& RADEON_IS_IGP
)) {
406 if (rdev
->mc
.igp_sideport_enabled
== false)
407 /* Useless to evict on IGP chips */
410 return ttm_bo_evict_mm(&rdev
->mman
.bdev
, TTM_PL_VRAM
);
413 void radeon_bo_force_delete(struct radeon_device
*rdev
)
415 struct radeon_bo
*bo
, *n
;
417 if (list_empty(&rdev
->gem
.objects
)) {
420 dev_err(rdev
->dev
, "Userspace still has active objects !\n");
421 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
422 mutex_lock(&rdev
->ddev
->struct_mutex
);
423 dev_err(rdev
->dev
, "%p %p %lu %lu force free\n",
424 &bo
->gem_base
, bo
, (unsigned long)bo
->gem_base
.size
,
425 *((unsigned long *)&bo
->gem_base
.refcount
));
426 mutex_lock(&bo
->rdev
->gem
.mutex
);
427 list_del_init(&bo
->list
);
428 mutex_unlock(&bo
->rdev
->gem
.mutex
);
429 /* this should unref the ttm bo */
430 drm_gem_object_unreference(&bo
->gem_base
);
431 mutex_unlock(&rdev
->ddev
->struct_mutex
);
435 int radeon_bo_init(struct radeon_device
*rdev
)
437 /* Add an MTRR for the VRAM */
438 if (!rdev
->fastfb_working
) {
439 rdev
->mc
.vram_mtrr
= arch_phys_wc_add(rdev
->mc
.aper_base
,
442 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
443 rdev
->mc
.mc_vram_size
>> 20,
444 (unsigned long long)rdev
->mc
.aper_size
>> 20);
445 DRM_INFO("RAM width %dbits %cDR\n",
446 rdev
->mc
.vram_width
, rdev
->mc
.vram_is_ddr
? 'D' : 'S');
447 return radeon_ttm_init(rdev
);
450 void radeon_bo_fini(struct radeon_device
*rdev
)
452 radeon_ttm_fini(rdev
);
453 arch_phys_wc_del(rdev
->mc
.vram_mtrr
);
456 /* Returns how many bytes TTM can move per IB.
458 static u64
radeon_bo_get_threshold_for_moves(struct radeon_device
*rdev
)
460 u64 real_vram_size
= rdev
->mc
.real_vram_size
;
461 u64 vram_usage
= atomic64_read(&rdev
->vram_usage
);
463 /* This function is based on the current VRAM usage.
465 * - If all of VRAM is free, allow relocating the number of bytes that
466 * is equal to 1/4 of the size of VRAM for this IB.
468 * - If more than one half of VRAM is occupied, only allow relocating
469 * 1 MB of data for this IB.
471 * - From 0 to one half of used VRAM, the threshold decreases
486 * Note: It's a threshold, not a limit. The threshold must be crossed
487 * for buffer relocations to stop, so any buffer of an arbitrary size
488 * can be moved as long as the threshold isn't crossed before
489 * the relocation takes place. We don't want to disable buffer
490 * relocations completely.
492 * The idea is that buffers should be placed in VRAM at creation time
493 * and TTM should only do a minimum number of relocations during
494 * command submission. In practice, you need to submit at least
495 * a dozen IBs to move all buffers to VRAM if they are in GTT.
497 * Also, things can get pretty crazy under memory pressure and actual
498 * VRAM usage can change a lot, so playing safe even at 50% does
499 * consistently increase performance.
502 u64 half_vram
= real_vram_size
>> 1;
503 u64 half_free_vram
= vram_usage
>= half_vram
? 0 : half_vram
- vram_usage
;
504 u64 bytes_moved_threshold
= half_free_vram
>> 1;
505 return max(bytes_moved_threshold
, 1024*1024ull);
508 int radeon_bo_list_validate(struct radeon_device
*rdev
,
509 struct ww_acquire_ctx
*ticket
,
510 struct list_head
*head
, int ring
)
512 struct radeon_bo_list
*lobj
;
513 struct list_head duplicates
;
515 u64 bytes_moved
= 0, initial_bytes_moved
;
516 u64 bytes_moved_threshold
= radeon_bo_get_threshold_for_moves(rdev
);
518 INIT_LIST_HEAD(&duplicates
);
519 r
= ttm_eu_reserve_buffers(ticket
, head
, true, &duplicates
);
520 if (unlikely(r
!= 0)) {
524 list_for_each_entry(lobj
, head
, tv
.head
) {
525 struct radeon_bo
*bo
= lobj
->robj
;
526 if (!bo
->pin_count
) {
527 u32 domain
= lobj
->prefered_domains
;
528 u32 allowed
= lobj
->allowed_domains
;
530 radeon_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
532 /* Check if this buffer will be moved and don't move it
533 * if we have moved too many buffers for this IB already.
535 * Note that this allows moving at least one buffer of
536 * any size, because it doesn't take the current "bo"
537 * into account. We don't want to disallow buffer moves
540 if ((allowed
& current_domain
) != 0 &&
541 (domain
& current_domain
) == 0 && /* will be moved */
542 bytes_moved
> bytes_moved_threshold
) {
544 domain
= current_domain
;
548 radeon_ttm_placement_from_domain(bo
, domain
);
549 if (ring
== R600_RING_TYPE_UVD_INDEX
)
550 radeon_uvd_force_into_uvd_segment(bo
, allowed
);
552 initial_bytes_moved
= atomic64_read(&rdev
->num_bytes_moved
);
553 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
554 bytes_moved
+= atomic64_read(&rdev
->num_bytes_moved
) -
558 if (r
!= -ERESTARTSYS
&&
559 domain
!= lobj
->allowed_domains
) {
560 domain
= lobj
->allowed_domains
;
563 ttm_eu_backoff_reservation(ticket
, head
);
567 lobj
->gpu_offset
= radeon_bo_gpu_offset(bo
);
568 lobj
->tiling_flags
= bo
->tiling_flags
;
571 list_for_each_entry(lobj
, &duplicates
, tv
.head
) {
572 lobj
->gpu_offset
= radeon_bo_gpu_offset(lobj
->robj
);
573 lobj
->tiling_flags
= lobj
->robj
->tiling_flags
;
579 int radeon_bo_get_surface_reg(struct radeon_bo
*bo
)
581 struct radeon_device
*rdev
= bo
->rdev
;
582 struct radeon_surface_reg
*reg
;
583 struct radeon_bo
*old_object
;
587 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
589 if (!bo
->tiling_flags
)
592 if (bo
->surface_reg
>= 0) {
593 reg
= &rdev
->surface_regs
[bo
->surface_reg
];
599 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
601 reg
= &rdev
->surface_regs
[i
];
605 old_object
= reg
->bo
;
606 if (old_object
->pin_count
== 0)
610 /* if we are all out */
611 if (i
== RADEON_GEM_MAX_SURFACES
) {
614 /* find someone with a surface reg and nuke their BO */
615 reg
= &rdev
->surface_regs
[steal
];
616 old_object
= reg
->bo
;
617 /* blow away the mapping */
618 DRM_DEBUG("stealing surface reg %d from %p\n", steal
, old_object
);
619 ttm_bo_unmap_virtual(&old_object
->tbo
);
620 old_object
->surface_reg
= -1;
628 radeon_set_surface_reg(rdev
, i
, bo
->tiling_flags
, bo
->pitch
,
629 bo
->tbo
.mem
.start
<< PAGE_SHIFT
,
630 bo
->tbo
.num_pages
<< PAGE_SHIFT
);
634 static void radeon_bo_clear_surface_reg(struct radeon_bo
*bo
)
636 struct radeon_device
*rdev
= bo
->rdev
;
637 struct radeon_surface_reg
*reg
;
639 if (bo
->surface_reg
== -1)
642 reg
= &rdev
->surface_regs
[bo
->surface_reg
];
643 radeon_clear_surface_reg(rdev
, bo
->surface_reg
);
646 bo
->surface_reg
= -1;
649 int radeon_bo_set_tiling_flags(struct radeon_bo
*bo
,
650 uint32_t tiling_flags
, uint32_t pitch
)
652 struct radeon_device
*rdev
= bo
->rdev
;
655 if (rdev
->family
>= CHIP_CEDAR
) {
656 unsigned bankw
, bankh
, mtaspect
, tilesplit
, stilesplit
;
658 bankw
= (tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
659 bankh
= (tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
660 mtaspect
= (tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
661 tilesplit
= (tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
662 stilesplit
= (tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
696 if (stilesplit
> 6) {
700 r
= radeon_bo_reserve(bo
, false);
701 if (unlikely(r
!= 0))
703 bo
->tiling_flags
= tiling_flags
;
705 radeon_bo_unreserve(bo
);
709 void radeon_bo_get_tiling_flags(struct radeon_bo
*bo
,
710 uint32_t *tiling_flags
,
713 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
716 *tiling_flags
= bo
->tiling_flags
;
721 int radeon_bo_check_tiling(struct radeon_bo
*bo
, bool has_moved
,
725 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
727 if (!(bo
->tiling_flags
& RADEON_TILING_SURFACE
))
731 radeon_bo_clear_surface_reg(bo
);
735 if (bo
->tbo
.mem
.mem_type
!= TTM_PL_VRAM
) {
739 if (bo
->surface_reg
>= 0)
740 radeon_bo_clear_surface_reg(bo
);
744 if ((bo
->surface_reg
>= 0) && !has_moved
)
747 return radeon_bo_get_surface_reg(bo
);
750 void radeon_bo_move_notify(struct ttm_buffer_object
*bo
,
751 struct ttm_mem_reg
*new_mem
)
753 struct radeon_bo
*rbo
;
755 if (!radeon_ttm_bo_is_radeon_bo(bo
))
758 rbo
= container_of(bo
, struct radeon_bo
, tbo
);
759 radeon_bo_check_tiling(rbo
, 0, 1);
760 radeon_vm_bo_invalidate(rbo
->rdev
, rbo
);
762 /* update statistics */
766 radeon_update_memory_usage(rbo
, bo
->mem
.mem_type
, -1);
767 radeon_update_memory_usage(rbo
, new_mem
->mem_type
, 1);
770 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object
*bo
)
772 struct radeon_device
*rdev
;
773 struct radeon_bo
*rbo
;
774 unsigned long offset
, size
, lpfn
;
777 if (!radeon_ttm_bo_is_radeon_bo(bo
))
779 rbo
= container_of(bo
, struct radeon_bo
, tbo
);
780 radeon_bo_check_tiling(rbo
, 0, 0);
782 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
)
785 size
= bo
->mem
.num_pages
<< PAGE_SHIFT
;
786 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
787 if ((offset
+ size
) <= rdev
->mc
.visible_vram_size
)
790 /* hurrah the memory is not visible ! */
791 radeon_ttm_placement_from_domain(rbo
, RADEON_GEM_DOMAIN_VRAM
);
792 lpfn
= rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
793 for (i
= 0; i
< rbo
->placement
.num_placement
; i
++) {
794 /* Force into visible VRAM */
795 if ((rbo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
796 (!rbo
->placements
[i
].lpfn
|| rbo
->placements
[i
].lpfn
> lpfn
))
797 rbo
->placements
[i
].lpfn
= lpfn
;
799 r
= ttm_bo_validate(bo
, &rbo
->placement
, false, false);
800 if (unlikely(r
== -ENOMEM
)) {
801 radeon_ttm_placement_from_domain(rbo
, RADEON_GEM_DOMAIN_GTT
);
802 return ttm_bo_validate(bo
, &rbo
->placement
, false, false);
803 } else if (unlikely(r
!= 0)) {
807 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
808 /* this should never happen */
809 if ((offset
+ size
) > rdev
->mc
.visible_vram_size
)
815 int radeon_bo_wait(struct radeon_bo
*bo
, u32
*mem_type
, bool no_wait
)
819 r
= ttm_bo_reserve(&bo
->tbo
, true, no_wait
, false, NULL
);
820 if (unlikely(r
!= 0))
823 *mem_type
= bo
->tbo
.mem
.mem_type
;
825 r
= ttm_bo_wait(&bo
->tbo
, true, true, no_wait
);
826 ttm_bo_unreserve(&bo
->tbo
);
831 * radeon_bo_fence - add fence to buffer object
833 * @bo: buffer object in question
834 * @fence: fence to add
835 * @shared: true if fence should be added shared
838 void radeon_bo_fence(struct radeon_bo
*bo
, struct radeon_fence
*fence
,
841 struct reservation_object
*resv
= bo
->tbo
.resv
;
844 reservation_object_add_shared_fence(resv
, &fence
->base
);
846 reservation_object_add_excl_fence(resv
, &fence
->base
);