drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #ifdef CONFIG_ACPI
  28 #include <linux/acpi.h>
  29 #endif
  30 #include <linux/power_supply.h>
  31 #include <linux/hwmon.h>
  32 #include <linux/hwmon-sysfs.h>
  33
  34 #define RADEON_IDLE_LOOP_MS 100
  35 #define RADEON_RECLOCK_DELAY_MS 200
  36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  37 #define RADEON_WAIT_IDLE_TIMEOUT 200
  38
  39 static const char *radeon_pm_state_type_name[5] = {
  40         "Default",
  41         "Powersave",
  42         "Battery",
  43         "Balanced",
  44         "Performance",
  45 };
  46
  47 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  48 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  49 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  51 static void radeon_pm_update_profile(struct radeon_device *rdev);
  52 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  53
  54 #define ACPI_AC_CLASS           "ac_adapter"
  55
  56 #ifdef CONFIG_ACPI
  57 static int radeon_acpi_event(struct notifier_block *nb,
  58                              unsigned long val,
  59                              void *data)
  60 {
  61         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  62         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  63
  64         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  65                 if (power_supply_is_system_supplied() > 0)
  66                         DRM_DEBUG_DRIVER("pm: AC\n");
  67                 else
  68                         DRM_DEBUG_DRIVER("pm: DC\n");
  69
  70                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  71                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  72                                 mutex_lock(&rdev->pm.mutex);
  73                                 radeon_pm_update_profile(rdev);
  74                                 radeon_pm_set_clocks(rdev);
  75                                 mutex_unlock(&rdev->pm.mutex);
  76                         }
  77                 }
  78         }
  79
  80         return NOTIFY_OK;
  81 }
  82 #endif
  83
  84 static void radeon_pm_update_profile(struct radeon_device *rdev)
  85 {
  86         switch (rdev->pm.profile) {
  87         case PM_PROFILE_DEFAULT:
  88                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  89                 break;
  90         case PM_PROFILE_AUTO:
  91                 if (power_supply_is_system_supplied() > 0) {
  92                         if (rdev->pm.active_crtc_count > 1)
  93                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  94                         else
  95                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  96                 } else {
  97                         if (rdev->pm.active_crtc_count > 1)
  98                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  99                         else
 100                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 101                 }
 102                 break;
 103         case PM_PROFILE_LOW:
 104                 if (rdev->pm.active_crtc_count > 1)
 105                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 106                 else
 107                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 108                 break;
 109         case PM_PROFILE_MID:
 110                 if (rdev->pm.active_crtc_count > 1)
 111                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 112                 else
 113                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 114                 break;
 115         case PM_PROFILE_HIGH:
 116                 if (rdev->pm.active_crtc_count > 1)
 117                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 118                 else
 119                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 120                 break;
 121         }
 122
 123         if (rdev->pm.active_crtc_count == 0) {
 124                 rdev->pm.requested_power_state_index =
 125                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 126                 rdev->pm.requested_clock_mode_index =
 127                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 128         } else {
 129                 rdev->pm.requested_power_state_index =
 130                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 131                 rdev->pm.requested_clock_mode_index =
 132                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 133         }
 134 }
 135
 136 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 137 {
 138         struct radeon_bo *bo, *n;
 139
 140         if (list_empty(&rdev->gem.objects))
 141                 return;
 142
 143         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 144                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 145                         ttm_bo_unmap_virtual(&bo->tbo);
 146         }
 147 }
 148
 149 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 150 {
 151         if (rdev->pm.active_crtcs) {
 152                 rdev->pm.vblank_sync = false;
 153                 wait_event_timeout(
 154                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 155                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 156         }
 157 }
 158
 159 static void radeon_set_power_state(struct radeon_device *rdev)
 160 {
 161         u32 sclk, mclk;
 162         bool misc_after = false;
 163
 164         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 165             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 166                 return;
 167
 168         if (radeon_gui_idle(rdev)) {
 169                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 170                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 171                 if (sclk > rdev->pm.default_sclk)
 172                         sclk = rdev->pm.default_sclk;
 173
 174                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 175                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 176                 if (mclk > rdev->pm.default_mclk)
 177                         mclk = rdev->pm.default_mclk;
 178
 179                 /* upvolt before raising clocks, downvolt after lowering clocks */
 180                 if (sclk < rdev->pm.current_sclk)
 181                         misc_after = true;
 182
 183                 radeon_sync_with_vblank(rdev);
 184
 185                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 186                         if (!radeon_pm_in_vbl(rdev))
 187                                 return;
 188                 }
 189
 190                 radeon_pm_prepare(rdev);
 191
 192                 if (!misc_after)
 193                         /* voltage, pcie lanes, etc.*/
 194                         radeon_pm_misc(rdev);
 195
 196                 /* set engine clock */
 197                 if (sclk != rdev->pm.current_sclk) {
 198                         radeon_pm_debug_check_in_vbl(rdev, false);
 199                         radeon_set_engine_clock(rdev, sclk);
 200                         radeon_pm_debug_check_in_vbl(rdev, true);
 201                         rdev->pm.current_sclk = sclk;
 202                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 203                 }
 204
 205                 /* set memory clock */
 206                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 207                         radeon_pm_debug_check_in_vbl(rdev, false);
 208                         radeon_set_memory_clock(rdev, mclk);
 209                         radeon_pm_debug_check_in_vbl(rdev, true);
 210                         rdev->pm.current_mclk = mclk;
 211                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 212                 }
 213
 214                 if (misc_after)
 215                         /* voltage, pcie lanes, etc.*/
 216                         radeon_pm_misc(rdev);
 217
 218                 radeon_pm_finish(rdev);
 219
 220                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 221                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 222         } else
 223                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 224 }
 225
 226 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 227 {
 228         int i;
 229
 230         /* no need to take locks, etc. if nothing's going to change */
 231         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 232             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 233                 return;
 234
 235         mutex_lock(&rdev->ddev->struct_mutex);
 236         mutex_lock(&rdev->vram_mutex);
 237         mutex_lock(&rdev->cp.mutex);
 238
 239         /* gui idle int has issues on older chips it seems */
 240         if (rdev->family >= CHIP_R600) {
 241                 if (rdev->irq.installed) {
 242                         /* wait for GPU idle */
 243                         rdev->pm.gui_idle = false;
 244                         rdev->irq.gui_idle = true;
 245                         radeon_irq_set(rdev);
 246                         wait_event_interruptible_timeout(
 247                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 248                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 249                         rdev->irq.gui_idle = false;
 250                         radeon_irq_set(rdev);
 251                 }
 252         } else {
 253                 if (rdev->cp.ready) {
 254                         struct radeon_fence *fence;
 255                         radeon_ring_alloc(rdev, 64);
 256                         radeon_fence_create(rdev, &fence);
 257                         radeon_fence_emit(rdev, fence);
 258                         radeon_ring_commit(rdev);
 259                         radeon_fence_wait(fence, false);
 260                         radeon_fence_unref(&fence);
 261                 }
 262         }
 263         radeon_unmap_vram_bos(rdev);
 264
 265         if (rdev->irq.installed) {
 266                 for (i = 0; i < rdev->num_crtc; i++) {
 267                         if (rdev->pm.active_crtcs & (1 << i)) {
 268                                 rdev->pm.req_vblank |= (1 << i);
 269                                 drm_vblank_get(rdev->ddev, i);
 270                         }
 271                 }
 272         }
 273
 274         radeon_set_power_state(rdev);
 275
 276         if (rdev->irq.installed) {
 277                 for (i = 0; i < rdev->num_crtc; i++) {
 278                         if (rdev->pm.req_vblank & (1 << i)) {
 279                                 rdev->pm.req_vblank &= ~(1 << i);
 280                                 drm_vblank_put(rdev->ddev, i);
 281                         }
 282                 }
 283         }
 284
 285         /* update display watermarks based on new power state */
 286         radeon_update_bandwidth_info(rdev);
 287         if (rdev->pm.active_crtc_count)
 288                 radeon_bandwidth_update(rdev);
 289
 290         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 291
 292         mutex_unlock(&rdev->cp.mutex);
 293         mutex_unlock(&rdev->vram_mutex);
 294         mutex_unlock(&rdev->ddev->struct_mutex);
 295 }
 296
 297 static void radeon_pm_print_states(struct radeon_device *rdev)
 298 {
 299         int i, j;
 300         struct radeon_power_state *power_state;
 301         struct radeon_pm_clock_info *clock_info;
 302
 303         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 304         for (i = 0; i < rdev->pm.num_power_states; i++) {
 305                 power_state = &rdev->pm.power_state[i];
 306                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 307                         radeon_pm_state_type_name[power_state->type]);
 308                 if (i == rdev->pm.default_power_state_index)
 309                         DRM_DEBUG_DRIVER("\tDefault");
 310                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 311                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 312                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 313                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 314                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 315                 for (j = 0; j < power_state->num_clock_modes; j++) {
 316                         clock_info = &(power_state->clock_info[j]);
 317                         if (rdev->flags & RADEON_IS_IGP)
 318                                 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
 319                                         j,
 320                                         clock_info->sclk * 10,
 321                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 322                         else
 323                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
 324                                         j,
 325                                         clock_info->sclk * 10,
 326                                         clock_info->mclk * 10,
 327                                         clock_info->voltage.voltage,
 328                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 329                 }
 330         }
 331 }
 332
 333 static ssize_t radeon_get_pm_profile(struct device *dev,
 334                                      struct device_attribute *attr,
 335                                      char *buf)
 336 {
 337         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 338         struct radeon_device *rdev = ddev->dev_private;
 339         int cp = rdev->pm.profile;
 340
 341         return snprintf(buf, PAGE_SIZE, "%s\n",
 342                         (cp == PM_PROFILE_AUTO) ? "auto" :
 343                         (cp == PM_PROFILE_LOW) ? "low" :
 344                         (cp == PM_PROFILE_MID) ? "mid" :
 345                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 346 }
 347
 348 static ssize_t radeon_set_pm_profile(struct device *dev,
 349                                      struct device_attribute *attr,
 350                                      const char *buf,
 351                                      size_t count)
 352 {
 353         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 354         struct radeon_device *rdev = ddev->dev_private;
 355
 356         mutex_lock(&rdev->pm.mutex);
 357         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 358                 if (strncmp("default", buf, strlen("default")) == 0)
 359                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 360                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 361                         rdev->pm.profile = PM_PROFILE_AUTO;
 362                 else if (strncmp("low", buf, strlen("low")) == 0)
 363                         rdev->pm.profile = PM_PROFILE_LOW;
 364                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 365                         rdev->pm.profile = PM_PROFILE_MID;
 366                 else if (strncmp("high", buf, strlen("high")) == 0)
 367                         rdev->pm.profile = PM_PROFILE_HIGH;
 368                 else {
 369                         count = -EINVAL;
 370                         goto fail;
 371                 }
 372                 radeon_pm_update_profile(rdev);
 373                 radeon_pm_set_clocks(rdev);
 374         } else
 375                 count = -EINVAL;
 376
 377 fail:
 378         mutex_unlock(&rdev->pm.mutex);
 379
 380         return count;
 381 }
 382
 383 static ssize_t radeon_get_pm_method(struct device *dev,
 384                                     struct device_attribute *attr,
 385                                     char *buf)
 386 {
 387         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 388         struct radeon_device *rdev = ddev->dev_private;
 389         int pm = rdev->pm.pm_method;
 390
 391         return snprintf(buf, PAGE_SIZE, "%s\n",
 392                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 393 }
 394
 395 static ssize_t radeon_set_pm_method(struct device *dev,
 396                                     struct device_attribute *attr,
 397                                     const char *buf,
 398                                     size_t count)
 399 {
 400         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 401         struct radeon_device *rdev = ddev->dev_private;
 402
 403
 404         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 405                 mutex_lock(&rdev->pm.mutex);
 406                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 407                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 408                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 409                 mutex_unlock(&rdev->pm.mutex);
 410         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 411                 mutex_lock(&rdev->pm.mutex);
 412                 /* disable dynpm */
 413                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 414                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 415                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 416                 mutex_unlock(&rdev->pm.mutex);
 417                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 418         } else {
 419                 count = -EINVAL;
 420                 goto fail;
 421         }
 422         radeon_pm_compute_clocks(rdev);
 423 fail:
 424         return count;
 425 }
 426
 427 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 428 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 429
 430 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 431                                       struct device_attribute *attr,
 432                                       char *buf)
 433 {
 434         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 435         struct radeon_device *rdev = ddev->dev_private;
 436         int temp;
 437
 438         switch (rdev->pm.int_thermal_type) {
 439         case THERMAL_TYPE_RV6XX:
 440                 temp = rv6xx_get_temp(rdev);
 441                 break;
 442         case THERMAL_TYPE_RV770:
 443                 temp = rv770_get_temp(rdev);
 444                 break;
 445         case THERMAL_TYPE_EVERGREEN:
 446         case THERMAL_TYPE_NI:
 447                 temp = evergreen_get_temp(rdev);
 448                 break;
 449         case THERMAL_TYPE_SUMO:
 450                 temp = sumo_get_temp(rdev);
 451                 break;
 452         default:
 453                 temp = 0;
 454                 break;
 455         }
 456
 457         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 458 }
 459
 460 static ssize_t radeon_hwmon_show_name(struct device *dev,
 461                                       struct device_attribute *attr,
 462                                       char *buf)
 463 {
 464         return sprintf(buf, "radeon\n");
 465 }
 466
 467 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 468 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 469
 470 static struct attribute *hwmon_attributes[] = {
 471         &sensor_dev_attr_temp1_input.dev_attr.attr,
 472         &sensor_dev_attr_name.dev_attr.attr,
 473         NULL
 474 };
 475
 476 static const struct attribute_group hwmon_attrgroup = {
 477         .attrs = hwmon_attributes,
 478 };
 479
 480 static int radeon_hwmon_init(struct radeon_device *rdev)
 481 {
 482         int err = 0;
 483
 484         rdev->pm.int_hwmon_dev = NULL;
 485
 486         switch (rdev->pm.int_thermal_type) {
 487         case THERMAL_TYPE_RV6XX:
 488         case THERMAL_TYPE_RV770:
 489         case THERMAL_TYPE_EVERGREEN:
 490         case THERMAL_TYPE_SUMO:
 491                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 492                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 493                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 494                         dev_err(rdev->dev,
 495                                 "Unable to register hwmon device: %d\n", err);
 496                         break;
 497                 }
 498                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 499                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 500                                          &hwmon_attrgroup);
 501                 if (err) {
 502                         dev_err(rdev->dev,
 503                                 "Unable to create hwmon sysfs file: %d\n", err);
 504                         hwmon_device_unregister(rdev->dev);
 505                 }
 506                 break;
 507         default:
 508                 break;
 509         }
 510
 511         return err;
 512 }
 513
 514 static void radeon_hwmon_fini(struct radeon_device *rdev)
 515 {
 516         if (rdev->pm.int_hwmon_dev) {
 517                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 518                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 519         }
 520 }
 521
 522 void radeon_pm_suspend(struct radeon_device *rdev)
 523 {
 524         mutex_lock(&rdev->pm.mutex);
 525         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 526                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 527                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 528         }
 529         mutex_unlock(&rdev->pm.mutex);
 530
 531         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 532 }
 533
 534 void radeon_pm_resume(struct radeon_device *rdev)
 535 {
 536         /* set up the default clocks if the MC ucode is loaded */
 537         if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
 538                 if (rdev->pm.default_vddc)
 539                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 540                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 541                 if (rdev->pm.default_sclk)
 542                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 543                 if (rdev->pm.default_mclk)
 544                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 545         }
 546         /* asic init will reset the default power state */
 547         mutex_lock(&rdev->pm.mutex);
 548         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 549         rdev->pm.current_clock_mode_index = 0;
 550         rdev->pm.current_sclk = rdev->pm.default_sclk;
 551         rdev->pm.current_mclk = rdev->pm.default_mclk;
 552         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 553         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 554             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 555                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 556                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 557                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 558         }
 559         mutex_unlock(&rdev->pm.mutex);
 560         radeon_pm_compute_clocks(rdev);
 561 }
 562
 563 int radeon_pm_init(struct radeon_device *rdev)
 564 {
 565         int ret;
 566
 567         /* default to profile method */
 568         rdev->pm.pm_method = PM_METHOD_PROFILE;
 569         rdev->pm.profile = PM_PROFILE_DEFAULT;
 570         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 571         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 572         rdev->pm.dynpm_can_upclock = true;
 573         rdev->pm.dynpm_can_downclock = true;
 574         rdev->pm.default_sclk = rdev->clock.default_sclk;
 575         rdev->pm.default_mclk = rdev->clock.default_mclk;
 576         rdev->pm.current_sclk = rdev->clock.default_sclk;
 577         rdev->pm.current_mclk = rdev->clock.default_mclk;
 578         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 579
 580         if (rdev->bios) {
 581                 if (rdev->is_atom_bios)
 582                         radeon_atombios_get_power_modes(rdev);
 583                 else
 584                         radeon_combios_get_power_modes(rdev);
 585                 radeon_pm_print_states(rdev);
 586                 radeon_pm_init_profile(rdev);
 587                 /* set up the default clocks if the MC ucode is loaded */
 588                 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
 589                         if (rdev->pm.default_vddc)
 590                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 591                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 592                         if (rdev->pm.default_sclk)
 593                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 594                         if (rdev->pm.default_mclk)
 595                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 596                 }
 597         }
 598
 599         /* set up the internal thermal sensor if applicable */
 600         ret = radeon_hwmon_init(rdev);
 601         if (ret)
 602                 return ret;
 603
 604         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 605
 606         if (rdev->pm.num_power_states > 1) {
 607                 /* where's the best place to put these? */
 608                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 609                 if (ret)
 610                         DRM_ERROR("failed to create device file for power profile\n");
 611                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 612                 if (ret)
 613                         DRM_ERROR("failed to create device file for power method\n");
 614
 615 #ifdef CONFIG_ACPI
 616                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 617                 register_acpi_notifier(&rdev->acpi_nb);
 618 #endif
 619                 if (radeon_debugfs_pm_init(rdev)) {
 620                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 621                 }
 622
 623                 DRM_INFO("radeon: power management initialized\n");
 624         }
 625
 626         return 0;
 627 }
 628
 629 void radeon_pm_fini(struct radeon_device *rdev)
 630 {
 631         if (rdev->pm.num_power_states > 1) {
 632                 mutex_lock(&rdev->pm.mutex);
 633                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 634                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 635                         radeon_pm_update_profile(rdev);
 636                         radeon_pm_set_clocks(rdev);
 637                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 638                         /* reset default clocks */
 639                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 640                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 641                         radeon_pm_set_clocks(rdev);
 642                 }
 643                 mutex_unlock(&rdev->pm.mutex);
 644
 645                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 646
 647                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 648                 device_remove_file(rdev->dev, &dev_attr_power_method);
 649 #ifdef CONFIG_ACPI
 650                 unregister_acpi_notifier(&rdev->acpi_nb);
 651 #endif
 652         }
 653
 654         if (rdev->pm.power_state)
 655                 kfree(rdev->pm.power_state);
 656
 657         radeon_hwmon_fini(rdev);
 658 }
 659
 660 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 661 {
 662         struct drm_device *ddev = rdev->ddev;
 663         struct drm_crtc *crtc;
 664         struct radeon_crtc *radeon_crtc;
 665
 666         if (rdev->pm.num_power_states < 2)
 667                 return;
 668
 669         mutex_lock(&rdev->pm.mutex);
 670
 671         rdev->pm.active_crtcs = 0;
 672         rdev->pm.active_crtc_count = 0;
 673         list_for_each_entry(crtc,
 674                 &ddev->mode_config.crtc_list, head) {
 675                 radeon_crtc = to_radeon_crtc(crtc);
 676                 if (radeon_crtc->enabled) {
 677                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 678                         rdev->pm.active_crtc_count++;
 679                 }
 680         }
 681
 682         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 683                 radeon_pm_update_profile(rdev);
 684                 radeon_pm_set_clocks(rdev);
 685         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 686                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 687                         if (rdev->pm.active_crtc_count > 1) {
 688                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 689                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 690
 691                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 692                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 693                                         radeon_pm_get_dynpm_state(rdev);
 694                                         radeon_pm_set_clocks(rdev);
 695
 696                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
 697                                 }
 698                         } else if (rdev->pm.active_crtc_count == 1) {
 699                                 /* TODO: Increase clocks if needed for current mode */
 700
 701                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 702                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 703                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 704                                         radeon_pm_get_dynpm_state(rdev);
 705                                         radeon_pm_set_clocks(rdev);
 706
 707                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 708                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 709                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 710                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 711                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 712                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 713                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
 714                                 }
 715                         } else { /* count == 0 */
 716                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 717                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 718
 719                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 720                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 721                                         radeon_pm_get_dynpm_state(rdev);
 722                                         radeon_pm_set_clocks(rdev);
 723                                 }
 724                         }
 725                 }
 726         }
 727
 728         mutex_unlock(&rdev->pm.mutex);
 729 }
 730
 731 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 732 {
 733         int  crtc, vpos, hpos, vbl_status;
 734         bool in_vbl = true;
 735
 736         /* Iterate over all active crtc's. All crtc's must be in vblank,
 737          * otherwise return in_vbl == false.
 738          */
 739         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
 740                 if (rdev->pm.active_crtcs & (1 << crtc)) {
 741                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
 742                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
 743                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
 744                                 in_vbl = false;
 745                 }
 746         }
 747
 748         return in_vbl;
 749 }
 750
 751 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 752 {
 753         u32 stat_crtc = 0;
 754         bool in_vbl = radeon_pm_in_vbl(rdev);
 755
 756         if (in_vbl == false)
 757                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
 758                          finish ? "exit" : "entry");
 759         return in_vbl;
 760 }
 761
 762 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 763 {
 764         struct radeon_device *rdev;
 765         int resched;
 766         rdev = container_of(work, struct radeon_device,
 767                                 pm.dynpm_idle_work.work);
 768
 769         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 770         mutex_lock(&rdev->pm.mutex);
 771         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 772                 unsigned long irq_flags;
 773                 int not_processed = 0;
 774
 775                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 776                 if (!list_empty(&rdev->fence_drv.emited)) {
 777                         struct list_head *ptr;
 778                         list_for_each(ptr, &rdev->fence_drv.emited) {
 779                                 /* count up to 3, that's enought info */
 780                                 if (++not_processed >= 3)
 781                                         break;
 782                         }
 783                 }
 784                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 785
 786                 if (not_processed >= 3) { /* should upclock */
 787                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 788                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 789                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 790                                    rdev->pm.dynpm_can_upclock) {
 791                                 rdev->pm.dynpm_planned_action =
 792                                         DYNPM_ACTION_UPCLOCK;
 793                                 rdev->pm.dynpm_action_timeout = jiffies +
 794                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 795                         }
 796                 } else if (not_processed == 0) { /* should downclock */
 797                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 798                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 799                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 800                                    rdev->pm.dynpm_can_downclock) {
 801                                 rdev->pm.dynpm_planned_action =
 802                                         DYNPM_ACTION_DOWNCLOCK;
 803                                 rdev->pm.dynpm_action_timeout = jiffies +
 804                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 805                         }
 806                 }
 807
 808                 /* Note, radeon_pm_set_clocks is called with static_switch set
 809                  * to false since we want to wait for vbl to avoid flicker.
 810                  */
 811                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 812                     jiffies > rdev->pm.dynpm_action_timeout) {
 813                         radeon_pm_get_dynpm_state(rdev);
 814                         radeon_pm_set_clocks(rdev);
 815                 }
 816
 817                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 818                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 819         }
 820         mutex_unlock(&rdev->pm.mutex);
 821         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 822 }
 823
 824 /*
 825  * Debugfs info
 826  */
 827 #if defined(CONFIG_DEBUG_FS)
 828
 829 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 830 {
 831         struct drm_info_node *node = (struct drm_info_node *) m->private;
 832         struct drm_device *dev = node->minor->dev;
 833         struct radeon_device *rdev = dev->dev_private;
 834
 835         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 836         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 837         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 838         if (rdev->asic->get_memory_clock)
 839                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 840         if (rdev->pm.current_vddc)
 841                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 842         if (rdev->asic->get_pcie_lanes)
 843                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 844
 845         return 0;
 846 }
 847
 848 static struct drm_info_list radeon_pm_info_list[] = {
 849         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 850 };
 851 #endif
 852
 853 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 854 {
 855 #if defined(CONFIG_DEBUG_FS)
 856         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 857 #else
 858         return 0;
 859 #endif
 860 }