2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
28 #include <linux/acpi.h>
30 #include <linux/power_supply.h>
31 #include <linux/hwmon.h>
32 #include <linux/hwmon-sysfs.h>
34 #define RADEON_IDLE_LOOP_MS 100
35 #define RADEON_RECLOCK_DELAY_MS 200
36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
37 #define RADEON_WAIT_IDLE_TIMEOUT 200
39 static const char *radeon_pm_state_type_name
[5] = {
47 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
);
48 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
49 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
);
50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
51 static void radeon_pm_update_profile(struct radeon_device
*rdev
);
52 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
54 #define ACPI_AC_CLASS "ac_adapter"
56 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
57 enum radeon_pm_state_type ps_type
,
61 int found_instance
= -1;
63 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
64 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
66 if (found_instance
== instance
)
70 /* return default if no match */
71 return rdev
->pm
.default_power_state_index
;
75 static int radeon_acpi_event(struct notifier_block
*nb
,
79 struct radeon_device
*rdev
= container_of(nb
, struct radeon_device
, acpi_nb
);
80 struct acpi_bus_event
*entry
= (struct acpi_bus_event
*)data
;
82 if (strcmp(entry
->device_class
, ACPI_AC_CLASS
) == 0) {
83 if (power_supply_is_system_supplied() > 0)
84 DRM_DEBUG_DRIVER("pm: AC\n");
86 DRM_DEBUG_DRIVER("pm: DC\n");
88 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
89 if (rdev
->pm
.profile
== PM_PROFILE_AUTO
) {
90 mutex_lock(&rdev
->pm
.mutex
);
91 radeon_pm_update_profile(rdev
);
92 radeon_pm_set_clocks(rdev
);
93 mutex_unlock(&rdev
->pm
.mutex
);
102 static void radeon_pm_update_profile(struct radeon_device
*rdev
)
104 switch (rdev
->pm
.profile
) {
105 case PM_PROFILE_DEFAULT
:
106 rdev
->pm
.profile_index
= PM_PROFILE_DEFAULT_IDX
;
108 case PM_PROFILE_AUTO
:
109 if (power_supply_is_system_supplied() > 0) {
110 if (rdev
->pm
.active_crtc_count
> 1)
111 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
113 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
115 if (rdev
->pm
.active_crtc_count
> 1)
116 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
118 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
122 if (rdev
->pm
.active_crtc_count
> 1)
123 rdev
->pm
.profile_index
= PM_PROFILE_LOW_MH_IDX
;
125 rdev
->pm
.profile_index
= PM_PROFILE_LOW_SH_IDX
;
128 if (rdev
->pm
.active_crtc_count
> 1)
129 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
131 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
133 case PM_PROFILE_HIGH
:
134 if (rdev
->pm
.active_crtc_count
> 1)
135 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
137 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
141 if (rdev
->pm
.active_crtc_count
== 0) {
142 rdev
->pm
.requested_power_state_index
=
143 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_ps_idx
;
144 rdev
->pm
.requested_clock_mode_index
=
145 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_cm_idx
;
147 rdev
->pm
.requested_power_state_index
=
148 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_ps_idx
;
149 rdev
->pm
.requested_clock_mode_index
=
150 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_cm_idx
;
154 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
156 struct radeon_bo
*bo
, *n
;
158 if (list_empty(&rdev
->gem
.objects
))
161 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
162 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
163 ttm_bo_unmap_virtual(&bo
->tbo
);
167 static void radeon_sync_with_vblank(struct radeon_device
*rdev
)
169 if (rdev
->pm
.active_crtcs
) {
170 rdev
->pm
.vblank_sync
= false;
172 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
173 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
177 static void radeon_set_power_state(struct radeon_device
*rdev
)
180 bool misc_after
= false;
182 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
183 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
186 if (radeon_gui_idle(rdev
)) {
187 sclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
188 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
;
189 if (sclk
> rdev
->pm
.default_sclk
)
190 sclk
= rdev
->pm
.default_sclk
;
192 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
193 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
;
194 if (mclk
> rdev
->pm
.default_mclk
)
195 mclk
= rdev
->pm
.default_mclk
;
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk
< rdev
->pm
.current_sclk
)
201 radeon_sync_with_vblank(rdev
);
203 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
204 if (!radeon_pm_in_vbl(rdev
))
208 radeon_pm_prepare(rdev
);
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev
);
214 /* set engine clock */
215 if (sclk
!= rdev
->pm
.current_sclk
) {
216 radeon_pm_debug_check_in_vbl(rdev
, false);
217 radeon_set_engine_clock(rdev
, sclk
);
218 radeon_pm_debug_check_in_vbl(rdev
, true);
219 rdev
->pm
.current_sclk
= sclk
;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk
);
223 /* set memory clock */
224 if (rdev
->asic
->set_memory_clock
&& (mclk
!= rdev
->pm
.current_mclk
)) {
225 radeon_pm_debug_check_in_vbl(rdev
, false);
226 radeon_set_memory_clock(rdev
, mclk
);
227 radeon_pm_debug_check_in_vbl(rdev
, true);
228 rdev
->pm
.current_mclk
= mclk
;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk
);
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev
);
236 radeon_pm_finish(rdev
);
238 rdev
->pm
.current_power_state_index
= rdev
->pm
.requested_power_state_index
;
239 rdev
->pm
.current_clock_mode_index
= rdev
->pm
.requested_clock_mode_index
;
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
244 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
250 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
253 mutex_lock(&rdev
->ddev
->struct_mutex
);
254 mutex_lock(&rdev
->vram_mutex
);
255 mutex_lock(&rdev
->cp
.mutex
);
257 /* gui idle int has issues on older chips it seems */
258 if (rdev
->family
>= CHIP_R600
) {
259 if (rdev
->irq
.installed
) {
260 /* wait for GPU idle */
261 rdev
->pm
.gui_idle
= false;
262 rdev
->irq
.gui_idle
= true;
263 radeon_irq_set(rdev
);
264 wait_event_interruptible_timeout(
265 rdev
->irq
.idle_queue
, rdev
->pm
.gui_idle
,
266 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT
));
267 rdev
->irq
.gui_idle
= false;
268 radeon_irq_set(rdev
);
271 if (rdev
->cp
.ready
) {
272 struct radeon_fence
*fence
;
273 radeon_ring_alloc(rdev
, 64);
274 radeon_fence_create(rdev
, &fence
);
275 radeon_fence_emit(rdev
, fence
);
276 radeon_ring_commit(rdev
);
277 radeon_fence_wait(fence
, false);
278 radeon_fence_unref(&fence
);
281 radeon_unmap_vram_bos(rdev
);
283 if (rdev
->irq
.installed
) {
284 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
285 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
286 rdev
->pm
.req_vblank
|= (1 << i
);
287 drm_vblank_get(rdev
->ddev
, i
);
292 radeon_set_power_state(rdev
);
294 if (rdev
->irq
.installed
) {
295 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
296 if (rdev
->pm
.req_vblank
& (1 << i
)) {
297 rdev
->pm
.req_vblank
&= ~(1 << i
);
298 drm_vblank_put(rdev
->ddev
, i
);
303 /* update display watermarks based on new power state */
304 radeon_update_bandwidth_info(rdev
);
305 if (rdev
->pm
.active_crtc_count
)
306 radeon_bandwidth_update(rdev
);
308 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
310 mutex_unlock(&rdev
->cp
.mutex
);
311 mutex_unlock(&rdev
->vram_mutex
);
312 mutex_unlock(&rdev
->ddev
->struct_mutex
);
315 static void radeon_pm_print_states(struct radeon_device
*rdev
)
318 struct radeon_power_state
*power_state
;
319 struct radeon_pm_clock_info
*clock_info
;
321 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev
->pm
.num_power_states
);
322 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
323 power_state
= &rdev
->pm
.power_state
[i
];
324 DRM_DEBUG_DRIVER("State %d: %s\n", i
,
325 radeon_pm_state_type_name
[power_state
->type
]);
326 if (i
== rdev
->pm
.default_power_state_index
)
327 DRM_DEBUG_DRIVER("\tDefault");
328 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
329 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state
->pcie_lanes
);
330 if (power_state
->flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
331 DRM_DEBUG_DRIVER("\tSingle display only\n");
332 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state
->num_clock_modes
);
333 for (j
= 0; j
< power_state
->num_clock_modes
; j
++) {
334 clock_info
= &(power_state
->clock_info
[j
]);
335 if (rdev
->flags
& RADEON_IS_IGP
)
336 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
338 clock_info
->sclk
* 10,
339 clock_info
->flags
& RADEON_PM_MODE_NO_DISPLAY
? "\tNo display only" : "");
341 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
343 clock_info
->sclk
* 10,
344 clock_info
->mclk
* 10,
345 clock_info
->voltage
.voltage
,
346 clock_info
->flags
& RADEON_PM_MODE_NO_DISPLAY
? "\tNo display only" : "");
351 static ssize_t
radeon_get_pm_profile(struct device
*dev
,
352 struct device_attribute
*attr
,
355 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
356 struct radeon_device
*rdev
= ddev
->dev_private
;
357 int cp
= rdev
->pm
.profile
;
359 return snprintf(buf
, PAGE_SIZE
, "%s\n",
360 (cp
== PM_PROFILE_AUTO
) ? "auto" :
361 (cp
== PM_PROFILE_LOW
) ? "low" :
362 (cp
== PM_PROFILE_MID
) ? "mid" :
363 (cp
== PM_PROFILE_HIGH
) ? "high" : "default");
366 static ssize_t
radeon_set_pm_profile(struct device
*dev
,
367 struct device_attribute
*attr
,
371 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
372 struct radeon_device
*rdev
= ddev
->dev_private
;
374 mutex_lock(&rdev
->pm
.mutex
);
375 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
376 if (strncmp("default", buf
, strlen("default")) == 0)
377 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
378 else if (strncmp("auto", buf
, strlen("auto")) == 0)
379 rdev
->pm
.profile
= PM_PROFILE_AUTO
;
380 else if (strncmp("low", buf
, strlen("low")) == 0)
381 rdev
->pm
.profile
= PM_PROFILE_LOW
;
382 else if (strncmp("mid", buf
, strlen("mid")) == 0)
383 rdev
->pm
.profile
= PM_PROFILE_MID
;
384 else if (strncmp("high", buf
, strlen("high")) == 0)
385 rdev
->pm
.profile
= PM_PROFILE_HIGH
;
390 radeon_pm_update_profile(rdev
);
391 radeon_pm_set_clocks(rdev
);
396 mutex_unlock(&rdev
->pm
.mutex
);
401 static ssize_t
radeon_get_pm_method(struct device
*dev
,
402 struct device_attribute
*attr
,
405 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
406 struct radeon_device
*rdev
= ddev
->dev_private
;
407 int pm
= rdev
->pm
.pm_method
;
409 return snprintf(buf
, PAGE_SIZE
, "%s\n",
410 (pm
== PM_METHOD_DYNPM
) ? "dynpm" : "profile");
413 static ssize_t
radeon_set_pm_method(struct device
*dev
,
414 struct device_attribute
*attr
,
418 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
419 struct radeon_device
*rdev
= ddev
->dev_private
;
422 if (strncmp("dynpm", buf
, strlen("dynpm")) == 0) {
423 mutex_lock(&rdev
->pm
.mutex
);
424 rdev
->pm
.pm_method
= PM_METHOD_DYNPM
;
425 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
426 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
427 mutex_unlock(&rdev
->pm
.mutex
);
428 } else if (strncmp("profile", buf
, strlen("profile")) == 0) {
429 mutex_lock(&rdev
->pm
.mutex
);
431 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
432 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
433 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
434 mutex_unlock(&rdev
->pm
.mutex
);
435 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
440 radeon_pm_compute_clocks(rdev
);
445 static DEVICE_ATTR(power_profile
, S_IRUGO
| S_IWUSR
, radeon_get_pm_profile
, radeon_set_pm_profile
);
446 static DEVICE_ATTR(power_method
, S_IRUGO
| S_IWUSR
, radeon_get_pm_method
, radeon_set_pm_method
);
448 static ssize_t
radeon_hwmon_show_temp(struct device
*dev
,
449 struct device_attribute
*attr
,
452 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
453 struct radeon_device
*rdev
= ddev
->dev_private
;
456 switch (rdev
->pm
.int_thermal_type
) {
457 case THERMAL_TYPE_RV6XX
:
458 temp
= rv6xx_get_temp(rdev
);
460 case THERMAL_TYPE_RV770
:
461 temp
= rv770_get_temp(rdev
);
463 case THERMAL_TYPE_EVERGREEN
:
464 case THERMAL_TYPE_NI
:
465 temp
= evergreen_get_temp(rdev
);
467 case THERMAL_TYPE_SUMO
:
468 temp
= sumo_get_temp(rdev
);
475 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
478 static ssize_t
radeon_hwmon_show_name(struct device
*dev
,
479 struct device_attribute
*attr
,
482 return sprintf(buf
, "radeon\n");
485 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, radeon_hwmon_show_temp
, NULL
, 0);
486 static SENSOR_DEVICE_ATTR(name
, S_IRUGO
, radeon_hwmon_show_name
, NULL
, 0);
488 static struct attribute
*hwmon_attributes
[] = {
489 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
490 &sensor_dev_attr_name
.dev_attr
.attr
,
494 static const struct attribute_group hwmon_attrgroup
= {
495 .attrs
= hwmon_attributes
,
498 static int radeon_hwmon_init(struct radeon_device
*rdev
)
502 rdev
->pm
.int_hwmon_dev
= NULL
;
504 switch (rdev
->pm
.int_thermal_type
) {
505 case THERMAL_TYPE_RV6XX
:
506 case THERMAL_TYPE_RV770
:
507 case THERMAL_TYPE_EVERGREEN
:
508 case THERMAL_TYPE_NI
:
509 case THERMAL_TYPE_SUMO
:
510 rdev
->pm
.int_hwmon_dev
= hwmon_device_register(rdev
->dev
);
511 if (IS_ERR(rdev
->pm
.int_hwmon_dev
)) {
512 err
= PTR_ERR(rdev
->pm
.int_hwmon_dev
);
514 "Unable to register hwmon device: %d\n", err
);
517 dev_set_drvdata(rdev
->pm
.int_hwmon_dev
, rdev
->ddev
);
518 err
= sysfs_create_group(&rdev
->pm
.int_hwmon_dev
->kobj
,
522 "Unable to create hwmon sysfs file: %d\n", err
);
523 hwmon_device_unregister(rdev
->dev
);
533 static void radeon_hwmon_fini(struct radeon_device
*rdev
)
535 if (rdev
->pm
.int_hwmon_dev
) {
536 sysfs_remove_group(&rdev
->pm
.int_hwmon_dev
->kobj
, &hwmon_attrgroup
);
537 hwmon_device_unregister(rdev
->pm
.int_hwmon_dev
);
541 void radeon_pm_suspend(struct radeon_device
*rdev
)
543 mutex_lock(&rdev
->pm
.mutex
);
544 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
545 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
)
546 rdev
->pm
.dynpm_state
= DYNPM_STATE_SUSPENDED
;
548 mutex_unlock(&rdev
->pm
.mutex
);
550 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
553 void radeon_pm_resume(struct radeon_device
*rdev
)
555 /* set up the default clocks if the MC ucode is loaded */
556 if (ASIC_IS_DCE5(rdev
) && rdev
->mc_fw
) {
557 if (rdev
->pm
.default_vddc
)
558 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
559 SET_VOLTAGE_TYPE_ASIC_VDDC
);
560 if (rdev
->pm
.default_vddci
)
561 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
562 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
563 if (rdev
->pm
.default_sclk
)
564 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
565 if (rdev
->pm
.default_mclk
)
566 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
568 /* asic init will reset the default power state */
569 mutex_lock(&rdev
->pm
.mutex
);
570 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
571 rdev
->pm
.current_clock_mode_index
= 0;
572 rdev
->pm
.current_sclk
= rdev
->pm
.default_sclk
;
573 rdev
->pm
.current_mclk
= rdev
->pm
.default_mclk
;
574 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
575 rdev
->pm
.current_vddci
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.vddci
;
576 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
577 && rdev
->pm
.dynpm_state
== DYNPM_STATE_SUSPENDED
) {
578 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
579 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
580 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
582 mutex_unlock(&rdev
->pm
.mutex
);
583 radeon_pm_compute_clocks(rdev
);
586 int radeon_pm_init(struct radeon_device
*rdev
)
590 /* default to profile method */
591 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
592 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
593 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
594 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
595 rdev
->pm
.dynpm_can_upclock
= true;
596 rdev
->pm
.dynpm_can_downclock
= true;
597 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
598 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
599 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
600 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
601 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
604 if (rdev
->is_atom_bios
)
605 radeon_atombios_get_power_modes(rdev
);
607 radeon_combios_get_power_modes(rdev
);
608 radeon_pm_print_states(rdev
);
609 radeon_pm_init_profile(rdev
);
610 /* set up the default clocks if the MC ucode is loaded */
611 if (ASIC_IS_DCE5(rdev
) && rdev
->mc_fw
) {
612 if (rdev
->pm
.default_vddc
)
613 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
614 SET_VOLTAGE_TYPE_ASIC_VDDC
);
615 if (rdev
->pm
.default_vddci
)
616 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
617 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
618 if (rdev
->pm
.default_sclk
)
619 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
620 if (rdev
->pm
.default_mclk
)
621 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
625 /* set up the internal thermal sensor if applicable */
626 ret
= radeon_hwmon_init(rdev
);
630 INIT_DELAYED_WORK(&rdev
->pm
.dynpm_idle_work
, radeon_dynpm_idle_work_handler
);
632 if (rdev
->pm
.num_power_states
> 1) {
633 /* where's the best place to put these? */
634 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
636 DRM_ERROR("failed to create device file for power profile\n");
637 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
639 DRM_ERROR("failed to create device file for power method\n");
642 rdev
->acpi_nb
.notifier_call
= radeon_acpi_event
;
643 register_acpi_notifier(&rdev
->acpi_nb
);
645 if (radeon_debugfs_pm_init(rdev
)) {
646 DRM_ERROR("Failed to register debugfs file for PM!\n");
649 DRM_INFO("radeon: power management initialized\n");
655 void radeon_pm_fini(struct radeon_device
*rdev
)
657 if (rdev
->pm
.num_power_states
> 1) {
658 mutex_lock(&rdev
->pm
.mutex
);
659 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
660 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
661 radeon_pm_update_profile(rdev
);
662 radeon_pm_set_clocks(rdev
);
663 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
664 /* reset default clocks */
665 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
666 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
667 radeon_pm_set_clocks(rdev
);
669 mutex_unlock(&rdev
->pm
.mutex
);
671 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
673 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
674 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
676 unregister_acpi_notifier(&rdev
->acpi_nb
);
680 if (rdev
->pm
.power_state
)
681 kfree(rdev
->pm
.power_state
);
683 radeon_hwmon_fini(rdev
);
686 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
688 struct drm_device
*ddev
= rdev
->ddev
;
689 struct drm_crtc
*crtc
;
690 struct radeon_crtc
*radeon_crtc
;
692 if (rdev
->pm
.num_power_states
< 2)
695 mutex_lock(&rdev
->pm
.mutex
);
697 rdev
->pm
.active_crtcs
= 0;
698 rdev
->pm
.active_crtc_count
= 0;
699 list_for_each_entry(crtc
,
700 &ddev
->mode_config
.crtc_list
, head
) {
701 radeon_crtc
= to_radeon_crtc(crtc
);
702 if (radeon_crtc
->enabled
) {
703 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
704 rdev
->pm
.active_crtc_count
++;
708 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
709 radeon_pm_update_profile(rdev
);
710 radeon_pm_set_clocks(rdev
);
711 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
712 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_DISABLED
) {
713 if (rdev
->pm
.active_crtc_count
> 1) {
714 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
715 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
717 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
718 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
719 radeon_pm_get_dynpm_state(rdev
);
720 radeon_pm_set_clocks(rdev
);
722 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
724 } else if (rdev
->pm
.active_crtc_count
== 1) {
725 /* TODO: Increase clocks if needed for current mode */
727 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_MINIMUM
) {
728 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
729 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_UPCLOCK
;
730 radeon_pm_get_dynpm_state(rdev
);
731 radeon_pm_set_clocks(rdev
);
733 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
734 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
735 } else if (rdev
->pm
.dynpm_state
== DYNPM_STATE_PAUSED
) {
736 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
737 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
738 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
739 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
741 } else { /* count == 0 */
742 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_MINIMUM
) {
743 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
745 rdev
->pm
.dynpm_state
= DYNPM_STATE_MINIMUM
;
746 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_MINIMUM
;
747 radeon_pm_get_dynpm_state(rdev
);
748 radeon_pm_set_clocks(rdev
);
754 mutex_unlock(&rdev
->pm
.mutex
);
757 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
)
759 int crtc
, vpos
, hpos
, vbl_status
;
762 /* Iterate over all active crtc's. All crtc's must be in vblank,
763 * otherwise return in_vbl == false.
765 for (crtc
= 0; (crtc
< rdev
->num_crtc
) && in_vbl
; crtc
++) {
766 if (rdev
->pm
.active_crtcs
& (1 << crtc
)) {
767 vbl_status
= radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc
, &vpos
, &hpos
);
768 if ((vbl_status
& DRM_SCANOUTPOS_VALID
) &&
769 !(vbl_status
& DRM_SCANOUTPOS_INVBL
))
777 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
780 bool in_vbl
= radeon_pm_in_vbl(rdev
);
783 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc
,
784 finish
? "exit" : "entry");
788 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
)
790 struct radeon_device
*rdev
;
792 rdev
= container_of(work
, struct radeon_device
,
793 pm
.dynpm_idle_work
.work
);
795 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
796 mutex_lock(&rdev
->pm
.mutex
);
797 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
798 unsigned long irq_flags
;
799 int not_processed
= 0;
801 read_lock_irqsave(&rdev
->fence_drv
.lock
, irq_flags
);
802 if (!list_empty(&rdev
->fence_drv
.emited
)) {
803 struct list_head
*ptr
;
804 list_for_each(ptr
, &rdev
->fence_drv
.emited
) {
805 /* count up to 3, that's enought info */
806 if (++not_processed
>= 3)
810 read_unlock_irqrestore(&rdev
->fence_drv
.lock
, irq_flags
);
812 if (not_processed
>= 3) { /* should upclock */
813 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_DOWNCLOCK
) {
814 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
815 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
816 rdev
->pm
.dynpm_can_upclock
) {
817 rdev
->pm
.dynpm_planned_action
=
818 DYNPM_ACTION_UPCLOCK
;
819 rdev
->pm
.dynpm_action_timeout
= jiffies
+
820 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
822 } else if (not_processed
== 0) { /* should downclock */
823 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_UPCLOCK
) {
824 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
825 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
826 rdev
->pm
.dynpm_can_downclock
) {
827 rdev
->pm
.dynpm_planned_action
=
828 DYNPM_ACTION_DOWNCLOCK
;
829 rdev
->pm
.dynpm_action_timeout
= jiffies
+
830 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
834 /* Note, radeon_pm_set_clocks is called with static_switch set
835 * to false since we want to wait for vbl to avoid flicker.
837 if (rdev
->pm
.dynpm_planned_action
!= DYNPM_ACTION_NONE
&&
838 jiffies
> rdev
->pm
.dynpm_action_timeout
) {
839 radeon_pm_get_dynpm_state(rdev
);
840 radeon_pm_set_clocks(rdev
);
843 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
844 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
846 mutex_unlock(&rdev
->pm
.mutex
);
847 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
853 #if defined(CONFIG_DEBUG_FS)
855 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
857 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
858 struct drm_device
*dev
= node
->minor
->dev
;
859 struct radeon_device
*rdev
= dev
->dev_private
;
861 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->pm
.default_sclk
);
862 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
863 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->pm
.default_mclk
);
864 if (rdev
->asic
->get_memory_clock
)
865 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
866 if (rdev
->pm
.current_vddc
)
867 seq_printf(m
, "voltage: %u mV\n", rdev
->pm
.current_vddc
);
868 if (rdev
->asic
->get_pcie_lanes
)
869 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
874 static struct drm_info_list radeon_pm_info_list
[] = {
875 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
879 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
881 #if defined(CONFIG_DEBUG_FS)
882 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));