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radeon: Use fences to gate entry to reclocking on <r600
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1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "atom.h"
35
36 int radeon_debugfs_ib_init(struct radeon_device *rdev);
37
38 void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
39 {
40 struct radeon_ib *ib, *n;
41
42 list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
43 list_del(&ib->list);
44 vfree(ib->ptr);
45 kfree(ib);
46 }
47 }
48
49 void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
50 {
51 struct radeon_ib *bib;
52
53 bib = kmalloc(sizeof(*bib), GFP_KERNEL);
54 if (bib == NULL)
55 return;
56 bib->ptr = vmalloc(ib->length_dw * 4);
57 if (bib->ptr == NULL) {
58 kfree(bib);
59 return;
60 }
61 memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
62 bib->length_dw = ib->length_dw;
63 mutex_lock(&rdev->ib_pool.mutex);
64 list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
65 mutex_unlock(&rdev->ib_pool.mutex);
66 }
67
68 /*
69 * IB.
70 */
71 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
72 {
73 struct radeon_fence *fence;
74 struct radeon_ib *nib;
75 int r = 0, i, c;
76
77 *ib = NULL;
78 r = radeon_fence_create(rdev, &fence);
79 if (r) {
80 dev_err(rdev->dev, "failed to create fence for new IB\n");
81 return r;
82 }
83 mutex_lock(&rdev->ib_pool.mutex);
84 for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
85 i &= (RADEON_IB_POOL_SIZE - 1);
86 if (rdev->ib_pool.ibs[i].free) {
87 nib = &rdev->ib_pool.ibs[i];
88 break;
89 }
90 }
91 if (nib == NULL) {
92 /* This should never happen, it means we allocated all
93 * IB and haven't scheduled one yet, return EBUSY to
94 * userspace hoping that on ioctl recall we get better
95 * luck
96 */
97 dev_err(rdev->dev, "no free indirect buffer !\n");
98 mutex_unlock(&rdev->ib_pool.mutex);
99 radeon_fence_unref(&fence);
100 return -EBUSY;
101 }
102 rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
103 nib->free = false;
104 if (nib->fence) {
105 mutex_unlock(&rdev->ib_pool.mutex);
106 r = radeon_fence_wait(nib->fence, false);
107 if (r) {
108 dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
109 nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
110 mutex_lock(&rdev->ib_pool.mutex);
111 nib->free = true;
112 mutex_unlock(&rdev->ib_pool.mutex);
113 radeon_fence_unref(&fence);
114 return r;
115 }
116 mutex_lock(&rdev->ib_pool.mutex);
117 }
118 radeon_fence_unref(&nib->fence);
119 nib->fence = fence;
120 nib->length_dw = 0;
121 mutex_unlock(&rdev->ib_pool.mutex);
122 *ib = nib;
123 return 0;
124 }
125
126 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
127 {
128 struct radeon_ib *tmp = *ib;
129
130 *ib = NULL;
131 if (tmp == NULL) {
132 return;
133 }
134 if (!tmp->fence->emited)
135 radeon_fence_unref(&tmp->fence);
136 mutex_lock(&rdev->ib_pool.mutex);
137 tmp->free = true;
138 mutex_unlock(&rdev->ib_pool.mutex);
139 }
140
141 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
142 {
143 int r = 0;
144
145 if (!ib->length_dw || !rdev->cp.ready) {
146 /* TODO: Nothings in the ib we should report. */
147 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
148 return -EINVAL;
149 }
150
151 /* 64 dwords should be enough for fence too */
152 r = radeon_ring_lock(rdev, 64);
153 if (r) {
154 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
155 return r;
156 }
157 radeon_ring_ib_execute(rdev, ib);
158 radeon_fence_emit(rdev, ib->fence);
159 mutex_lock(&rdev->ib_pool.mutex);
160 /* once scheduled IB is considered free and protected by the fence */
161 ib->free = true;
162 mutex_unlock(&rdev->ib_pool.mutex);
163 radeon_ring_unlock_commit(rdev);
164 return 0;
165 }
166
167 int radeon_ib_pool_init(struct radeon_device *rdev)
168 {
169 void *ptr;
170 uint64_t gpu_addr;
171 int i;
172 int r = 0;
173
174 if (rdev->ib_pool.robj)
175 return 0;
176 INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
177 /* Allocate 1M object buffer */
178 r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
179 true, RADEON_GEM_DOMAIN_GTT,
180 &rdev->ib_pool.robj);
181 if (r) {
182 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
183 return r;
184 }
185 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
186 if (unlikely(r != 0))
187 return r;
188 r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
189 if (r) {
190 radeon_bo_unreserve(rdev->ib_pool.robj);
191 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
192 return r;
193 }
194 r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
195 radeon_bo_unreserve(rdev->ib_pool.robj);
196 if (r) {
197 DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
198 return r;
199 }
200 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
201 unsigned offset;
202
203 offset = i * 64 * 1024;
204 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
205 rdev->ib_pool.ibs[i].ptr = ptr + offset;
206 rdev->ib_pool.ibs[i].idx = i;
207 rdev->ib_pool.ibs[i].length_dw = 0;
208 rdev->ib_pool.ibs[i].free = true;
209 }
210 rdev->ib_pool.head_id = 0;
211 rdev->ib_pool.ready = true;
212 DRM_INFO("radeon: ib pool ready.\n");
213 if (radeon_debugfs_ib_init(rdev)) {
214 DRM_ERROR("Failed to register debugfs file for IB !\n");
215 }
216 return r;
217 }
218
219 void radeon_ib_pool_fini(struct radeon_device *rdev)
220 {
221 int r;
222
223 if (!rdev->ib_pool.ready) {
224 return;
225 }
226 mutex_lock(&rdev->ib_pool.mutex);
227 radeon_ib_bogus_cleanup(rdev);
228
229 if (rdev->ib_pool.robj) {
230 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
231 if (likely(r == 0)) {
232 radeon_bo_kunmap(rdev->ib_pool.robj);
233 radeon_bo_unpin(rdev->ib_pool.robj);
234 radeon_bo_unreserve(rdev->ib_pool.robj);
235 }
236 radeon_bo_unref(&rdev->ib_pool.robj);
237 rdev->ib_pool.robj = NULL;
238 }
239 mutex_unlock(&rdev->ib_pool.mutex);
240 }
241
242
243 /*
244 * Ring.
245 */
246 void radeon_ring_free_size(struct radeon_device *rdev)
247 {
248 if (rdev->family >= CHIP_R600)
249 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
250 else
251 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
252 /* This works because ring_size is a power of 2 */
253 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
254 rdev->cp.ring_free_dw -= rdev->cp.wptr;
255 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
256 if (!rdev->cp.ring_free_dw) {
257 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
258 }
259 }
260
261 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw)
262 {
263 int r;
264
265 /* Align requested size with padding so unlock_commit can
266 * pad safely */
267 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
268 while (ndw > (rdev->cp.ring_free_dw - 1)) {
269 radeon_ring_free_size(rdev);
270 if (ndw < rdev->cp.ring_free_dw) {
271 break;
272 }
273 r = radeon_fence_wait_next(rdev);
274 if (r)
275 return r;
276 }
277 rdev->cp.count_dw = ndw;
278 rdev->cp.wptr_old = rdev->cp.wptr;
279 return 0;
280 }
281
282 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
283 {
284 int r;
285
286 mutex_lock(&rdev->cp.mutex);
287 r = radeon_ring_alloc(rdev, ndw);
288 if (r) {
289 mutex_unlock(&rdev->cp.mutex);
290 return r;
291 }
292 return 0;
293 }
294
295 void radeon_ring_commit(struct radeon_device *rdev)
296 {
297 unsigned count_dw_pad;
298 unsigned i;
299
300 /* We pad to match fetch size */
301 count_dw_pad = (rdev->cp.align_mask + 1) -
302 (rdev->cp.wptr & rdev->cp.align_mask);
303 for (i = 0; i < count_dw_pad; i++) {
304 radeon_ring_write(rdev, 2 << 30);
305 }
306 DRM_MEMORYBARRIER();
307 radeon_cp_commit(rdev);
308 }
309
310 void radeon_ring_unlock_commit(struct radeon_device *rdev)
311 {
312 radeon_ring_commit(rdev);
313 mutex_unlock(&rdev->cp.mutex);
314 }
315
316 void radeon_ring_unlock_undo(struct radeon_device *rdev)
317 {
318 rdev->cp.wptr = rdev->cp.wptr_old;
319 mutex_unlock(&rdev->cp.mutex);
320 }
321
322 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
323 {
324 int r;
325
326 rdev->cp.ring_size = ring_size;
327 /* Allocate ring buffer */
328 if (rdev->cp.ring_obj == NULL) {
329 r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
330 RADEON_GEM_DOMAIN_GTT,
331 &rdev->cp.ring_obj);
332 if (r) {
333 dev_err(rdev->dev, "(%d) ring create failed\n", r);
334 return r;
335 }
336 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
337 if (unlikely(r != 0))
338 return r;
339 r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
340 &rdev->cp.gpu_addr);
341 if (r) {
342 radeon_bo_unreserve(rdev->cp.ring_obj);
343 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
344 return r;
345 }
346 r = radeon_bo_kmap(rdev->cp.ring_obj,
347 (void **)&rdev->cp.ring);
348 radeon_bo_unreserve(rdev->cp.ring_obj);
349 if (r) {
350 dev_err(rdev->dev, "(%d) ring map failed\n", r);
351 return r;
352 }
353 }
354 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
355 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
356 return 0;
357 }
358
359 void radeon_ring_fini(struct radeon_device *rdev)
360 {
361 int r;
362
363 mutex_lock(&rdev->cp.mutex);
364 if (rdev->cp.ring_obj) {
365 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
366 if (likely(r == 0)) {
367 radeon_bo_kunmap(rdev->cp.ring_obj);
368 radeon_bo_unpin(rdev->cp.ring_obj);
369 radeon_bo_unreserve(rdev->cp.ring_obj);
370 }
371 radeon_bo_unref(&rdev->cp.ring_obj);
372 rdev->cp.ring = NULL;
373 rdev->cp.ring_obj = NULL;
374 }
375 mutex_unlock(&rdev->cp.mutex);
376 }
377
378
379 /*
380 * Debugfs info
381 */
382 #if defined(CONFIG_DEBUG_FS)
383 static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
384 {
385 struct drm_info_node *node = (struct drm_info_node *) m->private;
386 struct radeon_ib *ib = node->info_ent->data;
387 unsigned i;
388
389 if (ib == NULL) {
390 return 0;
391 }
392 seq_printf(m, "IB %04u\n", ib->idx);
393 seq_printf(m, "IB fence %p\n", ib->fence);
394 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
395 for (i = 0; i < ib->length_dw; i++) {
396 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
397 }
398 return 0;
399 }
400
401 static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
402 {
403 struct drm_info_node *node = (struct drm_info_node *) m->private;
404 struct radeon_device *rdev = node->info_ent->data;
405 struct radeon_ib *ib;
406 unsigned i;
407
408 mutex_lock(&rdev->ib_pool.mutex);
409 if (list_empty(&rdev->ib_pool.bogus_ib)) {
410 mutex_unlock(&rdev->ib_pool.mutex);
411 seq_printf(m, "no bogus IB recorded\n");
412 return 0;
413 }
414 ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
415 list_del_init(&ib->list);
416 mutex_unlock(&rdev->ib_pool.mutex);
417 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
418 for (i = 0; i < ib->length_dw; i++) {
419 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
420 }
421 vfree(ib->ptr);
422 kfree(ib);
423 return 0;
424 }
425
426 static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
427 static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
428
429 static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
430 {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
431 };
432 #endif
433
434 int radeon_debugfs_ib_init(struct radeon_device *rdev)
435 {
436 #if defined(CONFIG_DEBUG_FS)
437 unsigned i;
438 int r;
439
440 radeon_debugfs_ib_bogus_info_list[0].data = rdev;
441 r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
442 if (r)
443 return r;
444 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
445 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
446 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
447 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
448 radeon_debugfs_ib_list[i].driver_features = 0;
449 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
450 }
451 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
452 RADEON_IB_POOL_SIZE);
453 #else
454 return 0;
455 #endif
456 }