2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
34 /* This files gather functions specifics to : rs400,rs480 */
35 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
);
37 void rs400_gart_adjust_size(struct radeon_device
*rdev
)
40 switch (rdev
->mc
.gtt_size
/(1024*1024)) {
50 DRM_ERROR("Unable to use IGP GART size %uM\n",
51 (unsigned)(rdev
->mc
.gtt_size
>> 20));
52 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
53 DRM_ERROR("Forcing to 32M GART size\n");
54 rdev
->mc
.gtt_size
= 32 * 1024 * 1024;
57 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
58 /* FIXME: RS400 & RS480 seems to have issue with GART size
59 * if 4G of system memory (needs more testing) */
60 rdev
->mc
.gtt_size
= 32 * 1024 * 1024;
61 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
65 void rs400_gart_tlb_flush(struct radeon_device
*rdev
)
68 unsigned int timeout
= rdev
->usec_timeout
;
70 WREG32_MC(RS480_GART_CACHE_CNTRL
, RS480_GART_CACHE_INVALIDATE
);
72 tmp
= RREG32_MC(RS480_GART_CACHE_CNTRL
);
73 if ((tmp
& RS480_GART_CACHE_INVALIDATE
) == 0)
77 } while (timeout
> 0);
78 WREG32_MC(RS480_GART_CACHE_CNTRL
, 0);
81 int rs400_gart_init(struct radeon_device
*rdev
)
85 if (rdev
->gart
.table
.ram
.ptr
) {
86 WARN(1, "RS400 GART already initialized.\n");
90 switch(rdev
->mc
.gtt_size
/ (1024 * 1024)) {
102 /* Initialize common gart structure */
103 r
= radeon_gart_init(rdev
);
106 if (rs400_debugfs_pcie_gart_info_init(rdev
))
107 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
108 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
109 return radeon_gart_table_ram_alloc(rdev
);
112 int rs400_gart_enable(struct radeon_device
*rdev
)
117 radeon_gart_restore(rdev
);
118 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
119 tmp
|= RS690_DIS_OUT_OF_PCI_GART_ACCESS
;
120 WREG32_MC(RS690_AIC_CTRL_SCRATCH
, tmp
);
121 /* Check gart size */
122 switch(rdev
->mc
.gtt_size
/ (1024 * 1024)) {
124 size_reg
= RS480_VA_SIZE_32MB
;
127 size_reg
= RS480_VA_SIZE_64MB
;
130 size_reg
= RS480_VA_SIZE_128MB
;
133 size_reg
= RS480_VA_SIZE_256MB
;
136 size_reg
= RS480_VA_SIZE_512MB
;
139 size_reg
= RS480_VA_SIZE_1GB
;
142 size_reg
= RS480_VA_SIZE_2GB
;
147 /* It should be fine to program it to max value */
148 if (rdev
->family
== CHIP_RS690
|| (rdev
->family
== CHIP_RS740
)) {
149 WREG32_MC(RS690_MCCFG_AGP_BASE
, 0xFFFFFFFF);
150 WREG32_MC(RS690_MCCFG_AGP_BASE_2
, 0);
152 WREG32(RADEON_AGP_BASE
, 0xFFFFFFFF);
153 WREG32(RS480_AGP_BASE_2
, 0);
155 tmp
= REG_SET(RS690_MC_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
156 tmp
|= REG_SET(RS690_MC_AGP_START
, rdev
->mc
.gtt_start
>> 16);
157 if ((rdev
->family
== CHIP_RS690
) || (rdev
->family
== CHIP_RS740
)) {
158 WREG32_MC(RS690_MCCFG_AGP_LOCATION
, tmp
);
159 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RS600_BUS_MASTER_DIS
;
160 WREG32(RADEON_BUS_CNTL
, tmp
);
162 WREG32(RADEON_MC_AGP_LOCATION
, tmp
);
163 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
164 WREG32(RADEON_BUS_CNTL
, tmp
);
166 /* Table should be in 32bits address space so ignore bits above. */
167 tmp
= (u32
)rdev
->gart
.table_addr
& 0xfffff000;
168 tmp
|= (upper_32_bits(rdev
->gart
.table_addr
) & 0xff) << 4;
170 WREG32_MC(RS480_GART_BASE
, tmp
);
171 /* TODO: more tweaking here */
172 WREG32_MC(RS480_GART_FEATURE_ID
,
174 RS480_GTW_LAC_EN
| RS480_1LEVEL_GART
));
175 /* Disable snooping */
176 WREG32_MC(RS480_AGP_MODE_CNTL
,
177 (1 << RS480_REQ_TYPE_SNOOP_SHIFT
) | RS480_REQ_TYPE_SNOOP_DIS
);
178 /* Disable AGP mode */
179 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
180 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
181 if ((rdev
->family
== CHIP_RS690
) || (rdev
->family
== CHIP_RS740
)) {
182 WREG32_MC(RS480_MC_MISC_CNTL
,
183 (RS480_GART_INDEX_REG_EN
| RS690_BLOCK_GFX_D3_EN
));
185 WREG32_MC(RS480_MC_MISC_CNTL
, RS480_GART_INDEX_REG_EN
);
188 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
, (RS480_GART_EN
| size_reg
));
189 rs400_gart_tlb_flush(rdev
);
190 rdev
->gart
.ready
= true;
194 void rs400_gart_disable(struct radeon_device
*rdev
)
198 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
199 tmp
|= RS690_DIS_OUT_OF_PCI_GART_ACCESS
;
200 WREG32_MC(RS690_AIC_CTRL_SCRATCH
, tmp
);
201 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
, 0);
204 void rs400_gart_fini(struct radeon_device
*rdev
)
206 rs400_gart_disable(rdev
);
207 radeon_gart_table_ram_free(rdev
);
208 radeon_gart_fini(rdev
);
211 int rs400_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
215 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
219 entry
= (lower_32_bits(addr
) & PAGE_MASK
) |
220 ((upper_32_bits(addr
) & 0xff) << 4) |
222 entry
= cpu_to_le32(entry
);
223 rdev
->gart
.table
.ram
.ptr
[i
] = entry
;
227 int rs400_mc_wait_for_idle(struct radeon_device
*rdev
)
232 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
234 tmp
= RREG32(0x0150);
235 if (tmp
& (1 << 2)) {
243 void rs400_gpu_init(struct radeon_device
*rdev
)
245 /* FIXME: HDP same place on rs400 ? */
246 r100_hdp_reset(rdev
);
247 /* FIXME: is this correct ? */
248 r420_pipes_init(rdev
);
249 if (rs400_mc_wait_for_idle(rdev
)) {
250 printk(KERN_WARNING
"rs400: Failed to wait MC idle while "
251 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
255 void rs400_mc_init(struct radeon_device
*rdev
)
259 rs400_gart_adjust_size(rdev
);
260 rdev
->mc
.igp_sideport_enabled
= radeon_combios_sideport_present(rdev
);
261 /* DDR for all card after R300 & IGP */
262 rdev
->mc
.vram_is_ddr
= true;
263 rdev
->mc
.vram_width
= 128;
264 r100_vram_init_sizes(rdev
);
265 base
= (RREG32(RADEON_NB_TOM
) & 0xffff) << 16;
266 radeon_vram_location(rdev
, &rdev
->mc
, base
);
267 radeon_gtt_location(rdev
, &rdev
->mc
);
270 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
274 WREG32(RS480_NB_MC_INDEX
, reg
& 0xff);
275 r
= RREG32(RS480_NB_MC_DATA
);
276 WREG32(RS480_NB_MC_INDEX
, 0xff);
280 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
282 WREG32(RS480_NB_MC_INDEX
, ((reg
) & 0xff) | RS480_NB_MC_IND_WR_EN
);
283 WREG32(RS480_NB_MC_DATA
, (v
));
284 WREG32(RS480_NB_MC_INDEX
, 0xff);
287 #if defined(CONFIG_DEBUG_FS)
288 static int rs400_debugfs_gart_info(struct seq_file
*m
, void *data
)
290 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
291 struct drm_device
*dev
= node
->minor
->dev
;
292 struct radeon_device
*rdev
= dev
->dev_private
;
295 tmp
= RREG32(RADEON_HOST_PATH_CNTL
);
296 seq_printf(m
, "HOST_PATH_CNTL 0x%08x\n", tmp
);
297 tmp
= RREG32(RADEON_BUS_CNTL
);
298 seq_printf(m
, "BUS_CNTL 0x%08x\n", tmp
);
299 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
300 seq_printf(m
, "AIC_CTRL_SCRATCH 0x%08x\n", tmp
);
301 if (rdev
->family
== CHIP_RS690
|| (rdev
->family
== CHIP_RS740
)) {
302 tmp
= RREG32_MC(RS690_MCCFG_AGP_BASE
);
303 seq_printf(m
, "MCCFG_AGP_BASE 0x%08x\n", tmp
);
304 tmp
= RREG32_MC(RS690_MCCFG_AGP_BASE_2
);
305 seq_printf(m
, "MCCFG_AGP_BASE_2 0x%08x\n", tmp
);
306 tmp
= RREG32_MC(RS690_MCCFG_AGP_LOCATION
);
307 seq_printf(m
, "MCCFG_AGP_LOCATION 0x%08x\n", tmp
);
308 tmp
= RREG32_MC(0x100);
309 seq_printf(m
, "MCCFG_FB_LOCATION 0x%08x\n", tmp
);
311 seq_printf(m
, "HDP_FB_LOCATION 0x%08x\n", tmp
);
313 tmp
= RREG32(RADEON_AGP_BASE
);
314 seq_printf(m
, "AGP_BASE 0x%08x\n", tmp
);
315 tmp
= RREG32(RS480_AGP_BASE_2
);
316 seq_printf(m
, "AGP_BASE_2 0x%08x\n", tmp
);
317 tmp
= RREG32(RADEON_MC_AGP_LOCATION
);
318 seq_printf(m
, "MC_AGP_LOCATION 0x%08x\n", tmp
);
320 tmp
= RREG32_MC(RS480_GART_BASE
);
321 seq_printf(m
, "GART_BASE 0x%08x\n", tmp
);
322 tmp
= RREG32_MC(RS480_GART_FEATURE_ID
);
323 seq_printf(m
, "GART_FEATURE_ID 0x%08x\n", tmp
);
324 tmp
= RREG32_MC(RS480_AGP_MODE_CNTL
);
325 seq_printf(m
, "AGP_MODE_CONTROL 0x%08x\n", tmp
);
326 tmp
= RREG32_MC(RS480_MC_MISC_CNTL
);
327 seq_printf(m
, "MC_MISC_CNTL 0x%08x\n", tmp
);
328 tmp
= RREG32_MC(0x5F);
329 seq_printf(m
, "MC_MISC_UMA_CNTL 0x%08x\n", tmp
);
330 tmp
= RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
);
331 seq_printf(m
, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp
);
332 tmp
= RREG32_MC(RS480_GART_CACHE_CNTRL
);
333 seq_printf(m
, "GART_CACHE_CNTRL 0x%08x\n", tmp
);
334 tmp
= RREG32_MC(0x3B);
335 seq_printf(m
, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp
);
336 tmp
= RREG32_MC(0x3C);
337 seq_printf(m
, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp
);
338 tmp
= RREG32_MC(0x30);
339 seq_printf(m
, "GART_ERROR_0 0x%08x\n", tmp
);
340 tmp
= RREG32_MC(0x31);
341 seq_printf(m
, "GART_ERROR_1 0x%08x\n", tmp
);
342 tmp
= RREG32_MC(0x32);
343 seq_printf(m
, "GART_ERROR_2 0x%08x\n", tmp
);
344 tmp
= RREG32_MC(0x33);
345 seq_printf(m
, "GART_ERROR_3 0x%08x\n", tmp
);
346 tmp
= RREG32_MC(0x34);
347 seq_printf(m
, "GART_ERROR_4 0x%08x\n", tmp
);
348 tmp
= RREG32_MC(0x35);
349 seq_printf(m
, "GART_ERROR_5 0x%08x\n", tmp
);
350 tmp
= RREG32_MC(0x36);
351 seq_printf(m
, "GART_ERROR_6 0x%08x\n", tmp
);
352 tmp
= RREG32_MC(0x37);
353 seq_printf(m
, "GART_ERROR_7 0x%08x\n", tmp
);
357 static struct drm_info_list rs400_gart_info_list
[] = {
358 {"rs400_gart_info", rs400_debugfs_gart_info
, 0, NULL
},
362 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
)
364 #if defined(CONFIG_DEBUG_FS)
365 return radeon_debugfs_add_files(rdev
, rs400_gart_info_list
, 1);
371 void rs400_mc_program(struct radeon_device
*rdev
)
373 struct r100_mc_save save
;
375 /* Stops all mc clients */
376 r100_mc_stop(rdev
, &save
);
378 /* Wait for mc idle */
379 if (rs400_mc_wait_for_idle(rdev
))
380 dev_warn(rdev
->dev
, "rs400: Wait MC idle timeout before updating MC.\n");
381 WREG32(R_000148_MC_FB_LOCATION
,
382 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
383 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
385 r100_mc_resume(rdev
, &save
);
388 static int rs400_startup(struct radeon_device
*rdev
)
392 rs400_mc_program(rdev
);
394 r300_clock_startup(rdev
);
395 /* Initialize GPU configuration (# pipes, ...) */
396 rs400_gpu_init(rdev
);
397 r100_enable_bm(rdev
);
398 /* Initialize GART (initialize after TTM so we can allocate
399 * memory through TTM but finalize after TTM) */
400 r
= rs400_gart_enable(rdev
);
405 rdev
->config
.r300
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
407 r
= r100_cp_init(rdev
, 1024 * 1024);
409 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
412 r
= r100_wb_init(rdev
);
414 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
415 r
= r100_ib_init(rdev
);
417 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
423 int rs400_resume(struct radeon_device
*rdev
)
425 /* Make sur GART are not working */
426 rs400_gart_disable(rdev
);
427 /* Resume clock before doing reset */
428 r300_clock_startup(rdev
);
429 /* setup MC before calling post tables */
430 rs400_mc_program(rdev
);
431 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
432 if (radeon_gpu_reset(rdev
)) {
433 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
434 RREG32(R_000E40_RBBM_STATUS
),
435 RREG32(R_0007C0_CP_STAT
));
438 radeon_combios_asic_init(rdev
->ddev
);
439 /* Resume clock after posting */
440 r300_clock_startup(rdev
);
441 /* Initialize surface registers */
442 radeon_surface_init(rdev
);
443 return rs400_startup(rdev
);
446 int rs400_suspend(struct radeon_device
*rdev
)
448 r100_cp_disable(rdev
);
449 r100_wb_disable(rdev
);
450 r100_irq_disable(rdev
);
451 rs400_gart_disable(rdev
);
455 void rs400_fini(struct radeon_device
*rdev
)
460 radeon_gem_fini(rdev
);
461 rs400_gart_fini(rdev
);
462 radeon_irq_kms_fini(rdev
);
463 radeon_fence_driver_fini(rdev
);
464 radeon_bo_fini(rdev
);
465 radeon_atombios_fini(rdev
);
470 int rs400_init(struct radeon_device
*rdev
)
475 r100_vga_render_disable(rdev
);
476 /* Initialize scratch registers */
477 radeon_scratch_init(rdev
);
478 /* Initialize surface registers */
479 radeon_surface_init(rdev
);
480 /* TODO: disable VGA need to use VGA request */
482 if (!radeon_get_bios(rdev
)) {
483 if (ASIC_IS_AVIVO(rdev
))
486 if (rdev
->is_atom_bios
) {
487 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
490 r
= radeon_combios_init(rdev
);
494 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
495 if (radeon_gpu_reset(rdev
)) {
497 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
498 RREG32(R_000E40_RBBM_STATUS
),
499 RREG32(R_0007C0_CP_STAT
));
501 /* check if cards are posted or not */
502 if (radeon_boot_test_post_card(rdev
) == false)
505 /* Initialize clocks */
506 radeon_get_clock_info(rdev
->ddev
);
507 /* Initialize power management */
508 radeon_pm_init(rdev
);
509 /* initialize memory controller */
512 r
= radeon_fence_driver_init(rdev
);
515 r
= radeon_irq_kms_init(rdev
);
519 r
= radeon_bo_init(rdev
);
522 r
= rs400_gart_init(rdev
);
525 r300_set_reg_safe(rdev
);
526 rdev
->accel_working
= true;
527 r
= rs400_startup(rdev
);
529 /* Somethings want wront with the accel init stop accel */
530 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
534 rs400_gart_fini(rdev
);
535 radeon_irq_kms_fini(rdev
);
536 rdev
->accel_working
= false;