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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / rs690.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "atom.h"
32 #include "rs690d.h"
33
34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
35 {
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
43 return 0;
44 udelay(1);
45 }
46 return -1;
47 }
48
49 static void rs690_gpu_init(struct radeon_device *rdev)
50 {
51 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57 }
58
59 union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62 };
63
64 void rs690_pm_info(struct radeon_device *rdev)
65 {
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
67 union igp_info *info;
68 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
79 tmp.full = rfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock);
81 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
83 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock));
84 rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth);
85 break;
86 case 2:
87 tmp.full = rfixed_const(100);
88 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock);
89 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
90 rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock);
91 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
92 rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq);
93 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
94 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
95 break;
96 default:
97 tmp.full = rfixed_const(100);
98 /* We assume the slower possible clock ie worst case */
99 /* DDR 333Mhz */
100 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
101 /* FIXME: system clock ? */
102 rdev->pm.igp_system_mclk.full = rfixed_const(100);
103 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
104 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
105 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
106 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
107 break;
108 }
109 } else {
110 tmp.full = rfixed_const(100);
111 /* We assume the slower possible clock ie worst case */
112 /* DDR 333Mhz */
113 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
114 /* FIXME: system clock ? */
115 rdev->pm.igp_system_mclk.full = rfixed_const(100);
116 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
117 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
118 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
119 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
120 }
121 /* Compute various bandwidth */
122 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
123 tmp.full = rfixed_const(4);
124 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
125 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
126 * = ht_clk * ht_width / 5
127 */
128 tmp.full = rfixed_const(5);
129 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
130 rdev->pm.igp_ht_link_width);
131 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
132 if (tmp.full < rdev->pm.max_bandwidth.full) {
133 /* HT link is a limiting factor */
134 rdev->pm.max_bandwidth.full = tmp.full;
135 }
136 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
137 * = (sideport_clk * 14) / 10
138 */
139 tmp.full = rfixed_const(14);
140 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
141 tmp.full = rfixed_const(10);
142 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
143 }
144
145 void rs690_mc_init(struct radeon_device *rdev)
146 {
147 u64 base;
148
149 rs400_gart_adjust_size(rdev);
150 rdev->mc.vram_is_ddr = true;
151 rdev->mc.vram_width = 128;
152 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
153 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
154 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
155 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
156 rdev->mc.visible_vram_size = rdev->mc.aper_size;
157 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
158 base = G_000100_MC_FB_START(base) << 16;
159 rs690_pm_info(rdev);
160 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
161 radeon_vram_location(rdev, &rdev->mc, base);
162 radeon_gtt_location(rdev, &rdev->mc);
163 radeon_update_bandwidth_info(rdev);
164 }
165
166 void rs690_line_buffer_adjust(struct radeon_device *rdev,
167 struct drm_display_mode *mode1,
168 struct drm_display_mode *mode2)
169 {
170 u32 tmp;
171
172 /*
173 * Line Buffer Setup
174 * There is a single line buffer shared by both display controllers.
175 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
176 * the display controllers. The paritioning can either be done
177 * manually or via one of four preset allocations specified in bits 1:0:
178 * 0 - line buffer is divided in half and shared between crtc
179 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
180 * 2 - D1 gets the whole buffer
181 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
182 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
183 * allocation mode. In manual allocation mode, D1 always starts at 0,
184 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
185 */
186 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
187 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
188 /* auto */
189 if (mode1 && mode2) {
190 if (mode1->hdisplay > mode2->hdisplay) {
191 if (mode1->hdisplay > 2560)
192 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
193 else
194 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
195 } else if (mode2->hdisplay > mode1->hdisplay) {
196 if (mode2->hdisplay > 2560)
197 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
198 else
199 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
200 } else
201 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
202 } else if (mode1) {
203 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
204 } else if (mode2) {
205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
206 }
207 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
208 }
209
210 struct rs690_watermark {
211 u32 lb_request_fifo_depth;
212 fixed20_12 num_line_pair;
213 fixed20_12 estimated_width;
214 fixed20_12 worst_case_latency;
215 fixed20_12 consumption_rate;
216 fixed20_12 active_time;
217 fixed20_12 dbpp;
218 fixed20_12 priority_mark_max;
219 fixed20_12 priority_mark;
220 fixed20_12 sclk;
221 };
222
223 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
224 struct radeon_crtc *crtc,
225 struct rs690_watermark *wm)
226 {
227 struct drm_display_mode *mode = &crtc->base.mode;
228 fixed20_12 a, b, c;
229 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
230 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
231 /* FIXME: detect IGP with sideport memory, i don't think there is any
232 * such product available
233 */
234 bool sideport = false;
235
236 if (!crtc->base.enabled) {
237 /* FIXME: wouldn't it better to set priority mark to maximum */
238 wm->lb_request_fifo_depth = 4;
239 return;
240 }
241
242 if (crtc->vsc.full > rfixed_const(2))
243 wm->num_line_pair.full = rfixed_const(2);
244 else
245 wm->num_line_pair.full = rfixed_const(1);
246
247 b.full = rfixed_const(mode->crtc_hdisplay);
248 c.full = rfixed_const(256);
249 a.full = rfixed_div(b, c);
250 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
251 request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
252 if (a.full < rfixed_const(4)) {
253 wm->lb_request_fifo_depth = 4;
254 } else {
255 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
256 }
257
258 /* Determine consumption rate
259 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
260 * vtaps = number of vertical taps,
261 * vsc = vertical scaling ratio, defined as source/destination
262 * hsc = horizontal scaling ration, defined as source/destination
263 */
264 a.full = rfixed_const(mode->clock);
265 b.full = rfixed_const(1000);
266 a.full = rfixed_div(a, b);
267 pclk.full = rfixed_div(b, a);
268 if (crtc->rmx_type != RMX_OFF) {
269 b.full = rfixed_const(2);
270 if (crtc->vsc.full > b.full)
271 b.full = crtc->vsc.full;
272 b.full = rfixed_mul(b, crtc->hsc);
273 c.full = rfixed_const(2);
274 b.full = rfixed_div(b, c);
275 consumption_time.full = rfixed_div(pclk, b);
276 } else {
277 consumption_time.full = pclk.full;
278 }
279 a.full = rfixed_const(1);
280 wm->consumption_rate.full = rfixed_div(a, consumption_time);
281
282
283 /* Determine line time
284 * LineTime = total time for one line of displayhtotal
285 * LineTime = total number of horizontal pixels
286 * pclk = pixel clock period(ns)
287 */
288 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
289 line_time.full = rfixed_mul(a, pclk);
290
291 /* Determine active time
292 * ActiveTime = time of active region of display within one line,
293 * hactive = total number of horizontal active pixels
294 * htotal = total number of horizontal pixels
295 */
296 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
297 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
298 wm->active_time.full = rfixed_mul(line_time, b);
299 wm->active_time.full = rfixed_div(wm->active_time, a);
300
301 /* Maximun bandwidth is the minimun bandwidth of all component */
302 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
303 if (sideport) {
304 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
305 rdev->pm.sideport_bandwidth.full)
306 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
307 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
308 read_delay_latency.full = rfixed_div(read_delay_latency,
309 rdev->pm.igp_sideport_mclk);
310 } else {
311 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
312 rdev->pm.k8_bandwidth.full)
313 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
314 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
315 rdev->pm.ht_bandwidth.full)
316 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
317 read_delay_latency.full = rfixed_const(5000);
318 }
319
320 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
321 a.full = rfixed_const(16);
322 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
323 a.full = rfixed_const(1000);
324 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
325 /* Determine chunk time
326 * ChunkTime = the time it takes the DCP to send one chunk of data
327 * to the LB which consists of pipeline delay and inter chunk gap
328 * sclk = system clock(ns)
329 */
330 a.full = rfixed_const(256 * 13);
331 chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
332 a.full = rfixed_const(10);
333 chunk_time.full = rfixed_div(chunk_time, a);
334
335 /* Determine the worst case latency
336 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
337 * WorstCaseLatency = worst case time from urgent to when the MC starts
338 * to return data
339 * READ_DELAY_IDLE_MAX = constant of 1us
340 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
341 * which consists of pipeline delay and inter chunk gap
342 */
343 if (rfixed_trunc(wm->num_line_pair) > 1) {
344 a.full = rfixed_const(3);
345 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
346 wm->worst_case_latency.full += read_delay_latency.full;
347 } else {
348 a.full = rfixed_const(2);
349 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
350 wm->worst_case_latency.full += read_delay_latency.full;
351 }
352
353 /* Determine the tolerable latency
354 * TolerableLatency = Any given request has only 1 line time
355 * for the data to be returned
356 * LBRequestFifoDepth = Number of chunk requests the LB can
357 * put into the request FIFO for a display
358 * LineTime = total time for one line of display
359 * ChunkTime = the time it takes the DCP to send one chunk
360 * of data to the LB which consists of
361 * pipeline delay and inter chunk gap
362 */
363 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
364 tolerable_latency.full = line_time.full;
365 } else {
366 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
367 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
368 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
369 tolerable_latency.full = line_time.full - tolerable_latency.full;
370 }
371 /* We assume worst case 32bits (4 bytes) */
372 wm->dbpp.full = rfixed_const(4 * 8);
373
374 /* Determine the maximum priority mark
375 * width = viewport width in pixels
376 */
377 a.full = rfixed_const(16);
378 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
379 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
380 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
381
382 /* Determine estimated width */
383 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
384 estimated_width.full = rfixed_div(estimated_width, consumption_time);
385 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
386 wm->priority_mark.full = rfixed_const(10);
387 } else {
388 a.full = rfixed_const(16);
389 wm->priority_mark.full = rfixed_div(estimated_width, a);
390 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
391 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
392 }
393 }
394
395 void rs690_bandwidth_update(struct radeon_device *rdev)
396 {
397 struct drm_display_mode *mode0 = NULL;
398 struct drm_display_mode *mode1 = NULL;
399 struct rs690_watermark wm0;
400 struct rs690_watermark wm1;
401 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
402 fixed20_12 priority_mark02, priority_mark12, fill_rate;
403 fixed20_12 a, b;
404
405 radeon_update_display_priority(rdev);
406
407 if (rdev->mode_info.crtcs[0]->base.enabled)
408 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
409 if (rdev->mode_info.crtcs[1]->base.enabled)
410 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
411 /*
412 * Set display0/1 priority up in the memory controller for
413 * modes if the user specifies HIGH for displaypriority
414 * option.
415 */
416 if ((rdev->disp_priority == 2) &&
417 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
418 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
419 tmp &= C_000104_MC_DISP0R_INIT_LAT;
420 tmp &= C_000104_MC_DISP1R_INIT_LAT;
421 if (mode0)
422 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
423 if (mode1)
424 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
425 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
426 }
427 rs690_line_buffer_adjust(rdev, mode0, mode1);
428
429 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
430 WREG32(R_006C9C_DCP_CONTROL, 0);
431 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
432 WREG32(R_006C9C_DCP_CONTROL, 2);
433
434 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
435 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
436
437 tmp = (wm0.lb_request_fifo_depth - 1);
438 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
439 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
440
441 if (mode0 && mode1) {
442 if (rfixed_trunc(wm0.dbpp) > 64)
443 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
444 else
445 a.full = wm0.num_line_pair.full;
446 if (rfixed_trunc(wm1.dbpp) > 64)
447 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
448 else
449 b.full = wm1.num_line_pair.full;
450 a.full += b.full;
451 fill_rate.full = rfixed_div(wm0.sclk, a);
452 if (wm0.consumption_rate.full > fill_rate.full) {
453 b.full = wm0.consumption_rate.full - fill_rate.full;
454 b.full = rfixed_mul(b, wm0.active_time);
455 a.full = rfixed_mul(wm0.worst_case_latency,
456 wm0.consumption_rate);
457 a.full = a.full + b.full;
458 b.full = rfixed_const(16 * 1000);
459 priority_mark02.full = rfixed_div(a, b);
460 } else {
461 a.full = rfixed_mul(wm0.worst_case_latency,
462 wm0.consumption_rate);
463 b.full = rfixed_const(16 * 1000);
464 priority_mark02.full = rfixed_div(a, b);
465 }
466 if (wm1.consumption_rate.full > fill_rate.full) {
467 b.full = wm1.consumption_rate.full - fill_rate.full;
468 b.full = rfixed_mul(b, wm1.active_time);
469 a.full = rfixed_mul(wm1.worst_case_latency,
470 wm1.consumption_rate);
471 a.full = a.full + b.full;
472 b.full = rfixed_const(16 * 1000);
473 priority_mark12.full = rfixed_div(a, b);
474 } else {
475 a.full = rfixed_mul(wm1.worst_case_latency,
476 wm1.consumption_rate);
477 b.full = rfixed_const(16 * 1000);
478 priority_mark12.full = rfixed_div(a, b);
479 }
480 if (wm0.priority_mark.full > priority_mark02.full)
481 priority_mark02.full = wm0.priority_mark.full;
482 if (rfixed_trunc(priority_mark02) < 0)
483 priority_mark02.full = 0;
484 if (wm0.priority_mark_max.full > priority_mark02.full)
485 priority_mark02.full = wm0.priority_mark_max.full;
486 if (wm1.priority_mark.full > priority_mark12.full)
487 priority_mark12.full = wm1.priority_mark.full;
488 if (rfixed_trunc(priority_mark12) < 0)
489 priority_mark12.full = 0;
490 if (wm1.priority_mark_max.full > priority_mark12.full)
491 priority_mark12.full = wm1.priority_mark_max.full;
492 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
493 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
494 if (rdev->disp_priority == 2) {
495 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
496 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
497 }
498 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
499 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
500 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
501 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
502 } else if (mode0) {
503 if (rfixed_trunc(wm0.dbpp) > 64)
504 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
505 else
506 a.full = wm0.num_line_pair.full;
507 fill_rate.full = rfixed_div(wm0.sclk, a);
508 if (wm0.consumption_rate.full > fill_rate.full) {
509 b.full = wm0.consumption_rate.full - fill_rate.full;
510 b.full = rfixed_mul(b, wm0.active_time);
511 a.full = rfixed_mul(wm0.worst_case_latency,
512 wm0.consumption_rate);
513 a.full = a.full + b.full;
514 b.full = rfixed_const(16 * 1000);
515 priority_mark02.full = rfixed_div(a, b);
516 } else {
517 a.full = rfixed_mul(wm0.worst_case_latency,
518 wm0.consumption_rate);
519 b.full = rfixed_const(16 * 1000);
520 priority_mark02.full = rfixed_div(a, b);
521 }
522 if (wm0.priority_mark.full > priority_mark02.full)
523 priority_mark02.full = wm0.priority_mark.full;
524 if (rfixed_trunc(priority_mark02) < 0)
525 priority_mark02.full = 0;
526 if (wm0.priority_mark_max.full > priority_mark02.full)
527 priority_mark02.full = wm0.priority_mark_max.full;
528 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
529 if (rdev->disp_priority == 2)
530 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
531 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
532 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
533 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
534 S_006D48_D2MODE_PRIORITY_A_OFF(1));
535 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
536 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
537 } else {
538 if (rfixed_trunc(wm1.dbpp) > 64)
539 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
540 else
541 a.full = wm1.num_line_pair.full;
542 fill_rate.full = rfixed_div(wm1.sclk, a);
543 if (wm1.consumption_rate.full > fill_rate.full) {
544 b.full = wm1.consumption_rate.full - fill_rate.full;
545 b.full = rfixed_mul(b, wm1.active_time);
546 a.full = rfixed_mul(wm1.worst_case_latency,
547 wm1.consumption_rate);
548 a.full = a.full + b.full;
549 b.full = rfixed_const(16 * 1000);
550 priority_mark12.full = rfixed_div(a, b);
551 } else {
552 a.full = rfixed_mul(wm1.worst_case_latency,
553 wm1.consumption_rate);
554 b.full = rfixed_const(16 * 1000);
555 priority_mark12.full = rfixed_div(a, b);
556 }
557 if (wm1.priority_mark.full > priority_mark12.full)
558 priority_mark12.full = wm1.priority_mark.full;
559 if (rfixed_trunc(priority_mark12) < 0)
560 priority_mark12.full = 0;
561 if (wm1.priority_mark_max.full > priority_mark12.full)
562 priority_mark12.full = wm1.priority_mark_max.full;
563 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
564 if (rdev->disp_priority == 2)
565 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
567 S_006548_D1MODE_PRIORITY_A_OFF(1));
568 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
569 S_00654C_D1MODE_PRIORITY_B_OFF(1));
570 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
571 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
572 }
573 }
574
575 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
576 {
577 uint32_t r;
578
579 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
580 r = RREG32(R_00007C_MC_DATA);
581 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
582 return r;
583 }
584
585 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
586 {
587 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
588 S_000078_MC_IND_WR_EN(1));
589 WREG32(R_00007C_MC_DATA, v);
590 WREG32(R_000078_MC_INDEX, 0x7F);
591 }
592
593 void rs690_mc_program(struct radeon_device *rdev)
594 {
595 struct rv515_mc_save save;
596
597 /* Stops all mc clients */
598 rv515_mc_stop(rdev, &save);
599
600 /* Wait for mc idle */
601 if (rs690_mc_wait_for_idle(rdev))
602 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
603 /* Program MC, should be a 32bits limited address space */
604 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
605 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
606 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
607 WREG32(R_000134_HDP_FB_LOCATION,
608 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
609
610 rv515_mc_resume(rdev, &save);
611 }
612
613 static int rs690_startup(struct radeon_device *rdev)
614 {
615 int r;
616
617 rs690_mc_program(rdev);
618 /* Resume clock */
619 rv515_clock_startup(rdev);
620 /* Initialize GPU configuration (# pipes, ...) */
621 rs690_gpu_init(rdev);
622 /* Initialize GART (initialize after TTM so we can allocate
623 * memory through TTM but finalize after TTM) */
624 r = rs400_gart_enable(rdev);
625 if (r)
626 return r;
627 /* Enable IRQ */
628 rs600_irq_set(rdev);
629 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
630 /* 1M ring buffer */
631 r = r100_cp_init(rdev, 1024 * 1024);
632 if (r) {
633 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
634 return r;
635 }
636 r = r100_wb_init(rdev);
637 if (r)
638 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
639 r = r100_ib_init(rdev);
640 if (r) {
641 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
642 return r;
643 }
644 return 0;
645 }
646
647 int rs690_resume(struct radeon_device *rdev)
648 {
649 /* Make sur GART are not working */
650 rs400_gart_disable(rdev);
651 /* Resume clock before doing reset */
652 rv515_clock_startup(rdev);
653 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
654 if (radeon_asic_reset(rdev)) {
655 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
656 RREG32(R_000E40_RBBM_STATUS),
657 RREG32(R_0007C0_CP_STAT));
658 }
659 /* post */
660 atom_asic_init(rdev->mode_info.atom_context);
661 /* Resume clock after posting */
662 rv515_clock_startup(rdev);
663 /* Initialize surface registers */
664 radeon_surface_init(rdev);
665 return rs690_startup(rdev);
666 }
667
668 int rs690_suspend(struct radeon_device *rdev)
669 {
670 r100_cp_disable(rdev);
671 r100_wb_disable(rdev);
672 rs600_irq_disable(rdev);
673 rs400_gart_disable(rdev);
674 return 0;
675 }
676
677 void rs690_fini(struct radeon_device *rdev)
678 {
679 radeon_pm_fini(rdev);
680 r100_cp_fini(rdev);
681 r100_wb_fini(rdev);
682 r100_ib_fini(rdev);
683 radeon_gem_fini(rdev);
684 rs400_gart_fini(rdev);
685 radeon_irq_kms_fini(rdev);
686 radeon_fence_driver_fini(rdev);
687 radeon_bo_fini(rdev);
688 radeon_atombios_fini(rdev);
689 kfree(rdev->bios);
690 rdev->bios = NULL;
691 }
692
693 int rs690_init(struct radeon_device *rdev)
694 {
695 int r;
696
697 /* Disable VGA */
698 rv515_vga_render_disable(rdev);
699 /* Initialize scratch registers */
700 radeon_scratch_init(rdev);
701 /* Initialize surface registers */
702 radeon_surface_init(rdev);
703 /* TODO: disable VGA need to use VGA request */
704 /* BIOS*/
705 if (!radeon_get_bios(rdev)) {
706 if (ASIC_IS_AVIVO(rdev))
707 return -EINVAL;
708 }
709 if (rdev->is_atom_bios) {
710 r = radeon_atombios_init(rdev);
711 if (r)
712 return r;
713 } else {
714 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
715 return -EINVAL;
716 }
717 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
718 if (radeon_asic_reset(rdev)) {
719 dev_warn(rdev->dev,
720 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
721 RREG32(R_000E40_RBBM_STATUS),
722 RREG32(R_0007C0_CP_STAT));
723 }
724 /* check if cards are posted or not */
725 if (radeon_boot_test_post_card(rdev) == false)
726 return -EINVAL;
727
728 /* Initialize clocks */
729 radeon_get_clock_info(rdev->ddev);
730 /* Initialize power management */
731 radeon_pm_init(rdev);
732 /* initialize memory controller */
733 rs690_mc_init(rdev);
734 rv515_debugfs(rdev);
735 /* Fence driver */
736 r = radeon_fence_driver_init(rdev);
737 if (r)
738 return r;
739 r = radeon_irq_kms_init(rdev);
740 if (r)
741 return r;
742 /* Memory manager */
743 r = radeon_bo_init(rdev);
744 if (r)
745 return r;
746 r = rs400_gart_init(rdev);
747 if (r)
748 return r;
749 rs600_set_safe_registers(rdev);
750 rdev->accel_working = true;
751 r = rs690_startup(rdev);
752 if (r) {
753 /* Somethings want wront with the accel init stop accel */
754 dev_err(rdev->dev, "Disabling GPU acceleration\n");
755 r100_cp_fini(rdev);
756 r100_wb_fini(rdev);
757 r100_ib_fini(rdev);
758 rs400_gart_fini(rdev);
759 radeon_irq_kms_fini(rdev);
760 rdev->accel_working = false;
761 }
762 return 0;
763 }
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