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drm/radeon/kms: add dpm support for rv6xx (v3)
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / rs780_dpm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25 #include "drmP.h"
26 #include "radeon.h"
27 #include "rs780d.h"
28 #include "r600_dpm.h"
29 #include "rs780_dpm.h"
30 #include "atom.h"
31
32 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
33 {
34 struct igp_ps *ps = rps->ps_priv;
35
36 return ps;
37 }
38
39 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
40 {
41 struct igp_power_info *pi = rdev->pm.dpm.priv;
42
43 return pi;
44 }
45
46 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
47 {
48 struct igp_power_info *pi = rs780_get_pi(rdev);
49 struct radeon_mode_info *minfo = &rdev->mode_info;
50 struct drm_crtc *crtc;
51 struct radeon_crtc *radeon_crtc;
52 int i;
53
54 /* defaults */
55 pi->crtc_id = 0;
56 pi->refresh_rate = 60;
57
58 for (i = 0; i < rdev->num_crtc; i++) {
59 crtc = (struct drm_crtc *)minfo->crtcs[i];
60 if (crtc && crtc->enabled) {
61 radeon_crtc = to_radeon_crtc(crtc);
62 pi->crtc_id = radeon_crtc->crtc_id;
63 if (crtc->mode.htotal && crtc->mode.vtotal)
64 pi->refresh_rate =
65 (crtc->mode.clock * 1000) /
66 (crtc->mode.htotal * crtc->mode.vtotal);
67 break;
68 }
69 }
70 }
71
72 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
73
74 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev)
75 {
76 struct atom_clock_dividers dividers;
77 struct igp_ps *default_state = rs780_get_ps(rdev->pm.dpm.boot_ps);
78 int i, ret;
79
80 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
81 default_state->sclk_low, false, &dividers);
82 if (ret)
83 return ret;
84
85 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
86 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
87 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
88
89 if (dividers.enable_post_div)
90 r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
91 else
92 r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
93
94 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
95 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
96
97 r600_engine_clock_entry_enable(rdev, 0, true);
98 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
99 r600_engine_clock_entry_enable(rdev, i, false);
100
101 r600_enable_mclk_control(rdev, false);
102 r600_voltage_control_enable_pins(rdev, 0);
103
104 return 0;
105 }
106
107 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev)
108 {
109 int ret = 0;
110 int i;
111
112 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
113
114 r600_set_at(rdev, 0, 0, 0, 0);
115
116 r600_set_git(rdev, R600_GICST_DFLT);
117
118 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
119 r600_set_tc(rdev, i, 0, 0);
120
121 r600_select_td(rdev, R600_TD_DFLT);
122 r600_set_vrc(rdev, 0);
123
124 r600_set_tpu(rdev, R600_TPU_DFLT);
125 r600_set_tpc(rdev, R600_TPC_DFLT);
126
127 r600_set_sstu(rdev, R600_SSTU_DFLT);
128 r600_set_sst(rdev, R600_SST_DFLT);
129
130 r600_set_fctu(rdev, R600_FCTU_DFLT);
131 r600_set_fct(rdev, R600_FCT_DFLT);
132
133 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
134 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
135 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
136 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
137 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
138
139 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
140 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
141 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
142
143 ret = rs780_initialize_dpm_power_state(rdev);
144
145 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
146 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
147 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0);
148
149 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
150 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
151 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
152
153 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
154 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
155 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
156
157 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH);
158 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
159 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH);
160
161 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
162 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
163 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
164 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
165
166 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
167
168 r600_set_vrc(rdev, RS780_CGFTV_DFLT);
169
170 return ret;
171 }
172
173 static void rs780_start_dpm(struct radeon_device *rdev)
174 {
175 r600_enable_sclk_control(rdev, false);
176 r600_enable_mclk_control(rdev, false);
177
178 r600_dynamicpm_enable(rdev, true);
179
180 radeon_wait_for_vblank(rdev, 0);
181 radeon_wait_for_vblank(rdev, 1);
182
183 r600_enable_spll_bypass(rdev, true);
184 r600_wait_for_spll_change(rdev);
185 r600_enable_spll_bypass(rdev, false);
186 r600_wait_for_spll_change(rdev);
187
188 r600_enable_spll_bypass(rdev, true);
189 r600_wait_for_spll_change(rdev);
190 r600_enable_spll_bypass(rdev, false);
191 r600_wait_for_spll_change(rdev);
192
193 r600_enable_sclk_control(rdev, true);
194 }
195
196
197 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
198 {
199 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
200 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
201
202 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
203 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
204 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
205 }
206
207 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
208 {
209 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
210
211 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
212 ~STARTING_FEEDBACK_DIV_MASK);
213
214 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
215 ~FORCED_FEEDBACK_DIV_MASK);
216
217 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
218 }
219
220 static void rs780_voltage_scaling_init(struct radeon_device *rdev)
221 {
222 struct igp_power_info *pi = rs780_get_pi(rdev);
223 struct drm_device *dev = rdev->ddev;
224 u32 fv_throt_pwm_fb_div_range[3];
225 u32 fv_throt_pwm_range[4];
226
227 if (dev->pdev->device == 0x9614) {
228 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
229 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
230 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
231 } else if ((dev->pdev->device == 0x9714) ||
232 (dev->pdev->device == 0x9715)) {
233 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
234 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
235 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
236 } else {
237 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
238 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
239 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
240 }
241
242 if (pi->pwm_voltage_control) {
243 fv_throt_pwm_range[0] = pi->min_voltage;
244 fv_throt_pwm_range[1] = pi->min_voltage;
245 fv_throt_pwm_range[2] = pi->max_voltage;
246 fv_throt_pwm_range[3] = pi->max_voltage;
247 } else {
248 fv_throt_pwm_range[0] = pi->invert_pwm_required ?
249 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
250 fv_throt_pwm_range[1] = pi->invert_pwm_required ?
251 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
252 fv_throt_pwm_range[2] = pi->invert_pwm_required ?
253 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
254 fv_throt_pwm_range[3] = pi->invert_pwm_required ?
255 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
256 }
257
258 WREG32_P(FVTHROT_PWM_CTRL_REG0,
259 STARTING_PWM_HIGHTIME(pi->max_voltage),
260 ~STARTING_PWM_HIGHTIME_MASK);
261
262 WREG32_P(FVTHROT_PWM_CTRL_REG0,
263 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
264 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
265
266 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
267 ~FORCE_STARTING_PWM_HIGHTIME);
268
269 if (pi->invert_pwm_required)
270 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
271 else
272 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
273
274 rs780_voltage_scaling_enable(rdev, true);
275
276 WREG32(FVTHROT_PWM_CTRL_REG1,
277 (MIN_PWM_HIGHTIME(pi->min_voltage) |
278 MAX_PWM_HIGHTIME(pi->max_voltage)));
279
280 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
281 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
282 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
283 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
284
285 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
286 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
287 ~RANGE0_PWM_FEEDBACK_DIV_MASK);
288
289 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
290 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
291 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
292
293 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
294 (RANGE0_PWM(fv_throt_pwm_range[1]) |
295 RANGE1_PWM(fv_throt_pwm_range[2])));
296 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
297 (RANGE2_PWM(fv_throt_pwm_range[1]) |
298 RANGE3_PWM(fv_throt_pwm_range[2])));
299 }
300
301 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
302 {
303 if (enable)
304 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
305 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
306 else
307 WREG32_P(FVTHROT_CNTRL_REG, 0,
308 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
309 }
310
311 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
312 {
313 if (enable)
314 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
315 else
316 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
317 }
318
319 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
320 {
321 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
322 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
323 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
324 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
325 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
326
327 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
328 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
329 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
330 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
331 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
332 }
333
334 static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
335 {
336 WREG32_P(FVTHROT_FBDIV_REG2,
337 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
338 ~FB_DIV_TIMER_VAL_MASK);
339
340 WREG32_P(FVTHROT_CNTRL_REG,
341 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
342 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
343 }
344
345 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
346 {
347 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
348 }
349
350 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
351 {
352 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
353 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
354 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
355 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
356
357 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
358 }
359
360 static void rs780_program_at(struct radeon_device *rdev)
361 {
362 struct igp_power_info *pi = rs780_get_pi(rdev);
363
364 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
365 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
366 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
367 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
368 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
369 }
370
371 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
372 {
373 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
374 }
375
376 static void rs780_force_voltage_to_high(struct radeon_device *rdev)
377 {
378 struct igp_power_info *pi = rs780_get_pi(rdev);
379 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
380
381 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
382 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
383 return;
384
385 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
386
387 udelay(1);
388
389 WREG32_P(FVTHROT_PWM_CTRL_REG0,
390 STARTING_PWM_HIGHTIME(pi->max_voltage),
391 ~STARTING_PWM_HIGHTIME_MASK);
392
393 WREG32_P(FVTHROT_PWM_CTRL_REG0,
394 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
395
396 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
397 ~RANGE_PWM_FEEDBACK_DIV_EN);
398
399 udelay(1);
400
401 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
402 }
403
404 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev)
405 {
406 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
407 struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
408 struct igp_ps *old_state = rs780_get_ps(rdev->pm.dpm.current_ps);
409 int ret;
410
411 if ((new_state->sclk_high == old_state->sclk_high) &&
412 (new_state->sclk_low == old_state->sclk_low))
413 return 0;
414
415 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
416 new_state->sclk_low, false, &min_dividers);
417 if (ret)
418 return ret;
419
420 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
421 new_state->sclk_high, false, &max_dividers);
422 if (ret)
423 return ret;
424
425 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
426 old_state->sclk_high, false, &current_max_dividers);
427 if (ret)
428 return ret;
429
430 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
431
432 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(max_dividers.fb_div),
433 ~FORCED_FEEDBACK_DIV_MASK);
434 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(max_dividers.fb_div),
435 ~STARTING_FEEDBACK_DIV_MASK);
436 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
437
438 udelay(100);
439
440 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
441
442 if (max_dividers.fb_div > min_dividers.fb_div) {
443 WREG32_P(FVTHROT_FBDIV_REG0,
444 MIN_FEEDBACK_DIV(min_dividers.fb_div) |
445 MAX_FEEDBACK_DIV(max_dividers.fb_div),
446 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
447
448 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
449 }
450
451 return 0;
452 }
453
454 static void rs780_set_engine_clock_spc(struct radeon_device *rdev)
455 {
456 struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
457 struct igp_ps *old_state = rs780_get_ps(rdev->pm.dpm.current_ps);
458 struct igp_power_info *pi = rs780_get_pi(rdev);
459
460 if ((new_state->sclk_high == old_state->sclk_high) &&
461 (new_state->sclk_low == old_state->sclk_low))
462 return;
463
464 if (pi->crtc_id == 0)
465 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
466 else
467 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
468
469 }
470
471 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev)
472 {
473 struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
474 struct igp_ps *old_state = rs780_get_ps(rdev->pm.dpm.current_ps);
475
476 if ((new_state->sclk_high == old_state->sclk_high) &&
477 (new_state->sclk_low == old_state->sclk_low))
478 return;
479
480 rs780_clk_scaling_enable(rdev, true);
481 }
482
483 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
484 enum rs780_vddc_level vddc)
485 {
486 struct igp_power_info *pi = rs780_get_pi(rdev);
487
488 if (vddc == RS780_VDDC_LEVEL_HIGH)
489 return pi->max_voltage;
490 else if (vddc == RS780_VDDC_LEVEL_LOW)
491 return pi->min_voltage;
492 else
493 return pi->max_voltage;
494 }
495
496 static void rs780_enable_voltage_scaling(struct radeon_device *rdev)
497 {
498 struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
499 struct igp_power_info *pi = rs780_get_pi(rdev);
500 enum rs780_vddc_level vddc_high, vddc_low;
501
502 udelay(100);
503
504 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
505 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
506 return;
507
508 vddc_high = rs780_get_voltage_for_vddc_level(rdev,
509 new_state->max_voltage);
510 vddc_low = rs780_get_voltage_for_vddc_level(rdev,
511 new_state->min_voltage);
512
513 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
514
515 udelay(1);
516 if (vddc_high > vddc_low) {
517 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
518 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
519
520 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
521 } else if (vddc_high == vddc_low) {
522 if (pi->max_voltage != vddc_high) {
523 WREG32_P(FVTHROT_PWM_CTRL_REG0,
524 STARTING_PWM_HIGHTIME(vddc_high),
525 ~STARTING_PWM_HIGHTIME_MASK);
526
527 WREG32_P(FVTHROT_PWM_CTRL_REG0,
528 FORCE_STARTING_PWM_HIGHTIME,
529 ~FORCE_STARTING_PWM_HIGHTIME);
530 }
531 }
532
533 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
534 }
535
536 int rs780_dpm_enable(struct radeon_device *rdev)
537 {
538 struct igp_power_info *pi = rs780_get_pi(rdev);
539
540 rs780_get_pm_mode_parameters(rdev);
541 rs780_disable_vbios_powersaving(rdev);
542
543 if (r600_dynamicpm_enabled(rdev))
544 return -EINVAL;
545 if (rs780_initialize_dpm_parameters(rdev))
546 return -EINVAL;
547 rs780_start_dpm(rdev);
548
549 rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
550 rs780_preset_starting_fbdiv(rdev);
551 if (pi->voltage_control)
552 rs780_voltage_scaling_init(rdev);
553 rs780_clk_scaling_enable(rdev, true);
554 rs780_set_engine_clock_sc(rdev);
555 rs780_set_engine_clock_wfc(rdev);
556 rs780_program_at(rdev);
557 rs780_set_engine_clock_tdc(rdev);
558 rs780_set_engine_clock_ssc(rdev);
559
560 if (pi->gfx_clock_gating)
561 r600_gfx_clockgating_enable(rdev, true);
562
563 if (rdev->irq.installed && (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
564 r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
565 rdev->irq.dpm_thermal = true;
566 radeon_irq_set(rdev);
567 }
568
569 return 0;
570 }
571
572 void rs780_dpm_disable(struct radeon_device *rdev)
573 {
574 struct igp_power_info *pi = rs780_get_pi(rdev);
575
576 r600_dynamicpm_enable(rdev, false);
577
578 rs780_clk_scaling_enable(rdev, false);
579 rs780_voltage_scaling_enable(rdev, false);
580
581 if (pi->gfx_clock_gating)
582 r600_gfx_clockgating_enable(rdev, false);
583
584 if (rdev->irq.installed &&
585 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
586 rdev->irq.dpm_thermal = false;
587 radeon_irq_set(rdev);
588 }
589 }
590
591 int rs780_dpm_set_power_state(struct radeon_device *rdev)
592 {
593 struct igp_power_info *pi = rs780_get_pi(rdev);
594
595 rs780_get_pm_mode_parameters(rdev);
596
597 if (pi->voltage_control) {
598 rs780_force_voltage_to_high(rdev);
599 mdelay(5);
600 }
601
602 rs780_set_engine_clock_scaling(rdev);
603 rs780_set_engine_clock_spc(rdev);
604
605 rs780_activate_engine_clk_scaling(rdev);
606
607 if (pi->voltage_control)
608 rs780_enable_voltage_scaling(rdev);
609
610 return 0;
611 }
612
613 void rs780_dpm_setup_asic(struct radeon_device *rdev)
614 {
615
616 }
617
618 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
619 {
620 rs780_get_pm_mode_parameters(rdev);
621 rs780_program_at(rdev);
622 }
623
624 union igp_info {
625 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
626 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
627 };
628
629 union power_info {
630 struct _ATOM_POWERPLAY_INFO info;
631 struct _ATOM_POWERPLAY_INFO_V2 info_2;
632 struct _ATOM_POWERPLAY_INFO_V3 info_3;
633 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
634 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
635 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
636 };
637
638 union pplib_clock_info {
639 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
640 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
641 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
642 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
643 };
644
645 union pplib_power_state {
646 struct _ATOM_PPLIB_STATE v1;
647 struct _ATOM_PPLIB_STATE_V2 v2;
648 };
649
650 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
651 struct radeon_ps *rps,
652 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
653 u8 table_rev)
654 {
655 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
656 rps->class = le16_to_cpu(non_clock_info->usClassification);
657 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
658
659 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
660 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
661 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
662 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
663 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
664 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
665 } else {
666 rps->vclk = 0;
667 rps->dclk = 0;
668 }
669
670 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
671 rdev->pm.dpm.boot_ps = rps;
672 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
673 rdev->pm.dpm.uvd_ps = rps;
674 }
675
676 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
677 struct radeon_ps *rps,
678 union pplib_clock_info *clock_info)
679 {
680 struct igp_ps *ps = rs780_get_ps(rps);
681 u32 sclk;
682
683 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
684 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
685 ps->sclk_low = sclk;
686 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
687 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
688 ps->sclk_high = sclk;
689 switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
690 case ATOM_PPLIB_RS780_VOLTAGE_NONE:
691 default:
692 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
693 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
694 break;
695 case ATOM_PPLIB_RS780_VOLTAGE_LOW:
696 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
697 ps->max_voltage = RS780_VDDC_LEVEL_LOW;
698 break;
699 case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
700 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
701 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
702 break;
703 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
704 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
705 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
706 break;
707 }
708 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
709
710 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
711 ps->sclk_low = rdev->clock.default_sclk;
712 ps->sclk_high = rdev->clock.default_sclk;
713 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
714 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
715 }
716 }
717
718 static int rs780_parse_power_table(struct radeon_device *rdev)
719 {
720 struct radeon_mode_info *mode_info = &rdev->mode_info;
721 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
722 union pplib_power_state *power_state;
723 int i;
724 union pplib_clock_info *clock_info;
725 union power_info *power_info;
726 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
727 u16 data_offset;
728 u8 frev, crev;
729 struct igp_ps *ps;
730
731 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
732 &frev, &crev, &data_offset))
733 return -EINVAL;
734 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
735
736 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
737 power_info->pplib.ucNumStates, GFP_KERNEL);
738 if (!rdev->pm.dpm.ps)
739 return -ENOMEM;
740 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
741 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
742 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
743
744 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
745 power_state = (union pplib_power_state *)
746 (mode_info->atom_context->bios + data_offset +
747 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
748 i * power_info->pplib.ucStateEntrySize);
749 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
750 (mode_info->atom_context->bios + data_offset +
751 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
752 (power_state->v1.ucNonClockStateIndex *
753 power_info->pplib.ucNonClockSize));
754 if (power_info->pplib.ucStateEntrySize - 1) {
755 clock_info = (union pplib_clock_info *)
756 (mode_info->atom_context->bios + data_offset +
757 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
758 (power_state->v1.ucClockStateIndices[0] *
759 power_info->pplib.ucClockInfoSize));
760 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
761 if (ps == NULL) {
762 kfree(rdev->pm.dpm.ps);
763 return -ENOMEM;
764 }
765 rdev->pm.dpm.ps[i].ps_priv = ps;
766 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
767 non_clock_info,
768 power_info->pplib.ucNonClockSize);
769 rs780_parse_pplib_clock_info(rdev,
770 &rdev->pm.dpm.ps[i],
771 clock_info);
772 }
773 }
774 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
775 return 0;
776 }
777
778 int rs780_dpm_init(struct radeon_device *rdev)
779 {
780 struct igp_power_info *pi;
781 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
782 union igp_info *info;
783 u16 data_offset;
784 u8 frev, crev;
785 int ret;
786
787 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
788 if (pi == NULL)
789 return -ENOMEM;
790 rdev->pm.dpm.priv = pi;
791
792 ret = rs780_parse_power_table(rdev);
793 if (ret)
794 return ret;
795
796 pi->voltage_control = false;
797 pi->gfx_clock_gating = true;
798
799 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
800 &frev, &crev, &data_offset)) {
801 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
802
803 /* Get various system informations from bios */
804 switch (crev) {
805 case 1:
806 pi->num_of_cycles_in_period =
807 info->info.ucNumberOfCyclesInPeriod;
808 pi->num_of_cycles_in_period |=
809 info->info.ucNumberOfCyclesInPeriodHi << 8;
810 pi->invert_pwm_required =
811 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
812 pi->boot_voltage = info->info.ucStartingPWM_HighTime;
813 pi->max_voltage = info->info.ucMaxNBVoltage;
814 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
815 pi->min_voltage = info->info.ucMinNBVoltage;
816 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
817 pi->inter_voltage_low =
818 le16_to_cpu(info->info.usInterNBVoltageLow);
819 pi->inter_voltage_high =
820 le16_to_cpu(info->info.usInterNBVoltageHigh);
821 pi->voltage_control = true;
822 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
823 break;
824 case 2:
825 pi->num_of_cycles_in_period =
826 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
827 pi->invert_pwm_required =
828 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
829 pi->boot_voltage =
830 le16_to_cpu(info->info_2.usBootUpNBVoltage);
831 pi->max_voltage =
832 le16_to_cpu(info->info_2.usMaxNBVoltage);
833 pi->min_voltage =
834 le16_to_cpu(info->info_2.usMinNBVoltage);
835 pi->system_config =
836 le32_to_cpu(info->info_2.ulSystemConfig);
837 pi->pwm_voltage_control =
838 (pi->system_config & 0x4) ? true : false;
839 pi->voltage_control = true;
840 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
841 break;
842 default:
843 DRM_ERROR("No integrated system info for your GPU\n");
844 return -EINVAL;
845 }
846 if (pi->min_voltage > pi->max_voltage)
847 pi->voltage_control = false;
848 if (pi->pwm_voltage_control) {
849 if ((pi->num_of_cycles_in_period == 0) ||
850 (pi->max_voltage == 0) ||
851 (pi->min_voltage == 0))
852 pi->voltage_control = false;
853 } else {
854 if ((pi->num_of_cycles_in_period == 0) ||
855 (pi->max_voltage == 0))
856 pi->voltage_control = false;
857 }
858
859 return 0;
860 }
861 radeon_dpm_fini(rdev);
862 return -EINVAL;
863 }
864
865 void rs780_dpm_print_power_state(struct radeon_device *rdev,
866 struct radeon_ps *rps)
867 {
868 struct igp_ps *ps = rs780_get_ps(rps);
869
870 r600_dpm_print_class_info(rps->class, rps->class2);
871 r600_dpm_print_cap_info(rps->caps);
872 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
873 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n",
874 ps->sclk_low, ps->min_voltage);
875 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n",
876 ps->sclk_high, ps->max_voltage);
877 r600_dpm_print_ps_status(rdev, rps);
878 }
879
880 void rs780_dpm_fini(struct radeon_device *rdev)
881 {
882 int i;
883
884 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
885 kfree(rdev->pm.dpm.ps[i].ps_priv);
886 }
887 kfree(rdev->pm.dpm.ps);
888 kfree(rdev->pm.dpm.priv);
889 }
890
891 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
892 {
893 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
894
895 if (low)
896 return requested_state->sclk_low;
897 else
898 return requested_state->sclk_high;
899 }
900
901 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
902 {
903 struct igp_power_info *pi = rs780_get_pi(rdev);
904
905 return pi->bootup_uma_clk;
906 }
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